1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59f7917c00SJeff Kirsher 603069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6194cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6294cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 633069ee9bSVipul Pandya 64a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 65a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 66a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 67a6ec572bSAtul Gupta */ 68a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 69a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 70a6ec572bSAtul Gupta 71f7917c00SJeff Kirsher enum { 72f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 73f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 74f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 75f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 76a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 77098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 78f7917c00SJeff Kirsher }; 79f7917c00SJeff Kirsher 80f7917c00SJeff Kirsher enum { 81812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 82812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 83812034f1SHariprasad Shenai }; 84812034f1SHariprasad Shenai 85812034f1SHariprasad Shenai enum { 86f7917c00SJeff Kirsher MEM_EDC0, 87f7917c00SJeff Kirsher MEM_EDC1, 882422d9a3SSantosh Rastapur MEM_MC, 892422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 904db0401fSRahul Lakkireddy MEM_MC1, 914db0401fSRahul Lakkireddy MEM_HMA, 92f7917c00SJeff Kirsher }; 93f7917c00SJeff Kirsher 943069ee9bSVipul Pandya enum { 953eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 963eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 973069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 983069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 992422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1003eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1013eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1020abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1030abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1043069ee9bSVipul Pandya }; 1053069ee9bSVipul Pandya 106f7917c00SJeff Kirsher enum dev_master { 107f7917c00SJeff Kirsher MASTER_CANT, 108f7917c00SJeff Kirsher MASTER_MAY, 109f7917c00SJeff Kirsher MASTER_MUST 110f7917c00SJeff Kirsher }; 111f7917c00SJeff Kirsher 112f7917c00SJeff Kirsher enum dev_state { 113f7917c00SJeff Kirsher DEV_STATE_UNINIT, 114f7917c00SJeff Kirsher DEV_STATE_INIT, 115f7917c00SJeff Kirsher DEV_STATE_ERR 116f7917c00SJeff Kirsher }; 117f7917c00SJeff Kirsher 118c3168cabSGanesh Goudar enum cc_pause { 119f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 120f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 121f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124c3168cabSGanesh Goudar enum cc_fec { 1253bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1263bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1273bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1283bb4858fSGanesh Goudar }; 1293bb4858fSGanesh Goudar 130f7917c00SJeff Kirsher struct port_stats { 131f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 132f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 133f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 134f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 135f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 136f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 137f7917c00SJeff Kirsher 138f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 139f7917c00SJeff Kirsher u64 tx_frames_65_127; 140f7917c00SJeff Kirsher u64 tx_frames_128_255; 141f7917c00SJeff Kirsher u64 tx_frames_256_511; 142f7917c00SJeff Kirsher u64 tx_frames_512_1023; 143f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 144f7917c00SJeff Kirsher u64 tx_frames_1519_max; 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 147f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 148f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 153f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 154f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 155f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 156f7917c00SJeff Kirsher 157f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 158f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 159f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 160f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 161f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 162f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 163f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 164f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 165f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 166f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 167f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 168f7917c00SJeff Kirsher 169f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 170f7917c00SJeff Kirsher u64 rx_frames_65_127; 171f7917c00SJeff Kirsher u64 rx_frames_128_255; 172f7917c00SJeff Kirsher u64 rx_frames_256_511; 173f7917c00SJeff Kirsher u64 rx_frames_512_1023; 174f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 175f7917c00SJeff Kirsher u64 rx_frames_1519_max; 176f7917c00SJeff Kirsher 177f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 178f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 183f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 184f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 185f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 186f7917c00SJeff Kirsher 187f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 188f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 189f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 190f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 191f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 192f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 193f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 194f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 195f7917c00SJeff Kirsher }; 196f7917c00SJeff Kirsher 197f7917c00SJeff Kirsher struct lb_port_stats { 198f7917c00SJeff Kirsher u64 octets; 199f7917c00SJeff Kirsher u64 frames; 200f7917c00SJeff Kirsher u64 bcast_frames; 201f7917c00SJeff Kirsher u64 mcast_frames; 202f7917c00SJeff Kirsher u64 ucast_frames; 203f7917c00SJeff Kirsher u64 error_frames; 204f7917c00SJeff Kirsher 205f7917c00SJeff Kirsher u64 frames_64; 206f7917c00SJeff Kirsher u64 frames_65_127; 207f7917c00SJeff Kirsher u64 frames_128_255; 208f7917c00SJeff Kirsher u64 frames_256_511; 209f7917c00SJeff Kirsher u64 frames_512_1023; 210f7917c00SJeff Kirsher u64 frames_1024_1518; 211f7917c00SJeff Kirsher u64 frames_1519_max; 212f7917c00SJeff Kirsher 213f7917c00SJeff Kirsher u64 drop; 214f7917c00SJeff Kirsher 215f7917c00SJeff Kirsher u64 ovflow0; 216f7917c00SJeff Kirsher u64 ovflow1; 217f7917c00SJeff Kirsher u64 ovflow2; 218f7917c00SJeff Kirsher u64 ovflow3; 219f7917c00SJeff Kirsher u64 trunc0; 220f7917c00SJeff Kirsher u64 trunc1; 221f7917c00SJeff Kirsher u64 trunc2; 222f7917c00SJeff Kirsher u64 trunc3; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_tcp_stats { 226a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 227a4cfd929SHariprasad Shenai u64 tcp_in_segs; 228a4cfd929SHariprasad Shenai u64 tcp_out_segs; 229a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 230a4cfd929SHariprasad Shenai }; 231a4cfd929SHariprasad Shenai 232a4cfd929SHariprasad Shenai struct tp_usm_stats { 233a4cfd929SHariprasad Shenai u32 frames; 234a4cfd929SHariprasad Shenai u32 drops; 235a4cfd929SHariprasad Shenai u64 octets; 236f7917c00SJeff Kirsher }; 237f7917c00SJeff Kirsher 238a6222975SHariprasad Shenai struct tp_fcoe_stats { 239a6222975SHariprasad Shenai u32 frames_ddp; 240a6222975SHariprasad Shenai u32 frames_drop; 241a6222975SHariprasad Shenai u64 octets_ddp; 242f7917c00SJeff Kirsher }; 243f7917c00SJeff Kirsher 244f7917c00SJeff Kirsher struct tp_err_stats { 245a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 246a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 247a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 248a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 249a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 250a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 251a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 252a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 253a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 254a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 255a4cfd929SHariprasad Shenai }; 256a4cfd929SHariprasad Shenai 257a6222975SHariprasad Shenai struct tp_cpl_stats { 258a6222975SHariprasad Shenai u32 req[4]; 259a6222975SHariprasad Shenai u32 rsp[4]; 260a6222975SHariprasad Shenai }; 261a6222975SHariprasad Shenai 262a4cfd929SHariprasad Shenai struct tp_rdma_stats { 263a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 264a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 265f7917c00SJeff Kirsher }; 266f7917c00SJeff Kirsher 267e85c9a7aSHariprasad Shenai struct sge_params { 268e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 269e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 270e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 271e85c9a7aSHariprasad Shenai }; 272e85c9a7aSHariprasad Shenai 273f7917c00SJeff Kirsher struct tp_params { 274f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2752d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 276dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 277dca4faebSVipul Pandya /* channel map */ 278636f9d37SVipul Pandya 279636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 280636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 281dcf7b6f5SKumar Sanghvi 282dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 283dcf10ec7SRaju Rangoju u32 filter_mask; 284dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 285dcf7b6f5SKumar Sanghvi 2868eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2878eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2888eb9f2f9SArjun V */ 2898eb9f2f9SArjun V int rx_pkt_encap; 2908eb9f2f9SArjun V 291dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 292dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 293dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 294dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 295dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 296dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 297dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 298dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 299dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 300dcf7b6f5SKumar Sanghvi * present. 301dcf7b6f5SKumar Sanghvi */ 3020ba9a3b6SKumar Sanghvi int fcoe_shift; 303dcf7b6f5SKumar Sanghvi int port_shift; 3040ba9a3b6SKumar Sanghvi int vnic_shift; 3050ba9a3b6SKumar Sanghvi int vlan_shift; 3060ba9a3b6SKumar Sanghvi int tos_shift; 307dcf7b6f5SKumar Sanghvi int protocol_shift; 3080ba9a3b6SKumar Sanghvi int ethertype_shift; 3090ba9a3b6SKumar Sanghvi int macmatch_shift; 3100ba9a3b6SKumar Sanghvi int matchtype_shift; 3110ba9a3b6SKumar Sanghvi int frag_shift; 3120ba9a3b6SKumar Sanghvi 3130ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 314f7917c00SJeff Kirsher }; 315f7917c00SJeff Kirsher 316f7917c00SJeff Kirsher struct vpd_params { 317f7917c00SJeff Kirsher unsigned int cclk; 318f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 319f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 320f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 321a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 322098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 323f7917c00SJeff Kirsher }; 324f7917c00SJeff Kirsher 3250eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3260eaec62aSCasey Leedom */ 3270eaec62aSCasey Leedom struct pf_resources { 3280eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3290eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 3300eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 3310eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 3320eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 3330eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 3340eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 3350eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 3360eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 3370eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 3380eaec62aSCasey Leedom }; 3390eaec62aSCasey Leedom 340f7917c00SJeff Kirsher struct pci_params { 341baf50868SGanesh Goudar unsigned int vpd_cap_addr; 342f7917c00SJeff Kirsher unsigned char speed; 343f7917c00SJeff Kirsher unsigned char width; 344f7917c00SJeff Kirsher }; 345f7917c00SJeff Kirsher 34649aa284fSHariprasad Shenai struct devlog_params { 34749aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 34849aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 34949aa284fSHariprasad Shenai u32 size; /* size of log */ 35049aa284fSHariprasad Shenai }; 35149aa284fSHariprasad Shenai 3523ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3533ccc6cf7SHariprasad Shenai struct arch_specific_params { 3543ccc6cf7SHariprasad Shenai u8 nchan; 35544588560SHariprasad Shenai u8 pm_stats_cnt; 3562216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3573ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3583ccc6cf7SHariprasad Shenai u16 vfcount; 3593ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3603ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3613ccc6cf7SHariprasad Shenai }; 3623ccc6cf7SHariprasad Shenai 363f7917c00SJeff Kirsher struct adapter_params { 364e85c9a7aSHariprasad Shenai struct sge_params sge; 365f7917c00SJeff Kirsher struct tp_params tp; 366f7917c00SJeff Kirsher struct vpd_params vpd; 3670eaec62aSCasey Leedom struct pf_resources pfres; 368f7917c00SJeff Kirsher struct pci_params pci; 36949aa284fSHariprasad Shenai struct devlog_params devlog; 37049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 371f7917c00SJeff Kirsher 372f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 373f1ff24aaSHariprasad Shenai 374f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 375f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 376f7917c00SJeff Kirsher 377760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3780de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 379760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3800de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 381760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 382760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 383f7917c00SJeff Kirsher u8 api_vers[7]; 384f7917c00SJeff Kirsher 385f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 386f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 387f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 388f7917c00SJeff Kirsher 389f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 390f7917c00SJeff Kirsher unsigned char portvec; 391d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3923ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 393f7917c00SJeff Kirsher unsigned char offload; 39494cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 395ab0367eaSRahul Lakkireddy unsigned char ethofld; /* QoS support */ 396f7917c00SJeff Kirsher 3979a4da2cdSVipul Pandya unsigned char bypass; 3985c31254eSKumar Sanghvi unsigned char hash_filter; 3999a4da2cdSVipul Pandya 400f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 4011ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4024c2c5763SHariprasad Shenai 403b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4044c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4054c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 406086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 407c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4080ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 40902d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4108f46d467SArjun Vynipadath 4118f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4128f46d467SArjun Vynipadath * used by the Port 4138f46d467SArjun Vynipadath */ 4148f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 41543db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 416f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 417f7917c00SJeff Kirsher }; 418f7917c00SJeff Kirsher 419a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 420a3bfb617SHariprasad Shenai * and possible hangs. 421a3bfb617SHariprasad Shenai */ 422a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 423a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 424a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 425a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 426a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 427a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 428a3bfb617SHariprasad Shenai }; 429a3bfb617SHariprasad Shenai 4307f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4317f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4327f080c3fSHariprasad Shenai * error returns. 4337f080c3fSHariprasad Shenai */ 4347f080c3fSHariprasad Shenai struct mbox_cmd { 4357f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4367f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4377f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4387f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4397f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4407f080c3fSHariprasad Shenai }; 4417f080c3fSHariprasad Shenai 4427f080c3fSHariprasad Shenai struct mbox_cmd_log { 4437f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4447f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4457f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4467f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4477f080c3fSHariprasad Shenai }; 4487f080c3fSHariprasad Shenai 4497f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4507f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4517f080c3fSHariprasad Shenai */ 4527f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4537f080c3fSHariprasad Shenai unsigned int entry_idx) 4547f080c3fSHariprasad Shenai { 4557f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4567f080c3fSHariprasad Shenai } 4577f080c3fSHariprasad Shenai 45816e47624SHariprasad Shenai #include "t4fw_api.h" 45916e47624SHariprasad Shenai 46016e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 461b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 462b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 463b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 464b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 46516e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 46616e47624SHariprasad Shenai 46716e47624SHariprasad Shenai struct fw_info { 46816e47624SHariprasad Shenai u8 chip; 46916e47624SHariprasad Shenai char *fs_name; 47016e47624SHariprasad Shenai char *fw_mod_name; 47116e47624SHariprasad Shenai struct fw_hdr fw_hdr; 47216e47624SHariprasad Shenai }; 47316e47624SHariprasad Shenai 474f7917c00SJeff Kirsher struct trace_params { 475f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 476f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 477f7917c00SJeff Kirsher unsigned short snap_len; 478f7917c00SJeff Kirsher unsigned short min_len; 479f7917c00SJeff Kirsher unsigned char skip_ofst; 480f7917c00SJeff Kirsher unsigned char skip_len; 481f7917c00SJeff Kirsher unsigned char invert; 482f7917c00SJeff Kirsher unsigned char port; 483f7917c00SJeff Kirsher }; 484f7917c00SJeff Kirsher 485c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 486c3168cabSGanesh Goudar 487c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 488c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 489c3168cabSGanesh Goudar 490c3168cabSGanesh Goudar enum fw_caps { 491c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 492c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 493c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 494c3168cabSGanesh Goudar }; 495c3168cabSGanesh Goudar 496f7917c00SJeff Kirsher struct link_config { 497c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 498c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 499c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 500c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 501c3168cabSGanesh Goudar 502c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 503c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 504c3168cabSGanesh Goudar 505c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 506c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 507c3168cabSGanesh Goudar 508c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 509c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 510c3168cabSGanesh Goudar 511f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 512c3168cabSGanesh Goudar 513f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 514ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5158156b0baSGanesh Goudar 5168156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5178156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 518f7917c00SJeff Kirsher }; 519f7917c00SJeff Kirsher 520e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 521f7917c00SJeff Kirsher 522f7917c00SJeff Kirsher enum { 523f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 524f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 525f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 526f7917c00SJeff Kirsher }; 527f7917c00SJeff Kirsher 528f7917c00SJeff Kirsher enum { 529812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 530812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 531812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 532812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 533812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 534812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 535812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 536812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 537812034f1SHariprasad Shenai }; 538812034f1SHariprasad Shenai 539812034f1SHariprasad Shenai enum { 54068ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 54168ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 54268ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 54368ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 54468ddc82aSRahul Lakkireddy }; 54568ddc82aSRahul Lakkireddy 54668ddc82aSRahul Lakkireddy enum { 547cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 548cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5490fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 550f7917c00SJeff Kirsher }; 551f7917c00SJeff Kirsher 552d5fbda61SArjun Vynipadath enum { 553d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 554d5fbda61SArjun Vynipadath }; 555d5fbda61SArjun Vynipadath 556d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 557d5fbda61SArjun Vynipadath 558d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 559d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 560d5fbda61SArjun Vynipadath 561f7917c00SJeff Kirsher struct adapter; 562f7917c00SJeff Kirsher struct sge_rspq; 563f7917c00SJeff Kirsher 564688848b1SAnish Bhatt #include "cxgb4_dcb.h" 565688848b1SAnish Bhatt 56676fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 56776fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 56876fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 56976fed8a9SVarun Prakash 570f7917c00SJeff Kirsher struct port_info { 571f7917c00SJeff Kirsher struct adapter *adapter; 572f7917c00SJeff Kirsher u16 viid; 5733f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 574f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 575f7917c00SJeff Kirsher s8 mdio_addr; 57640e9de4bSHariprasad Shenai enum fw_port_type port_type; 577f7917c00SJeff Kirsher u8 mod_type; 578f7917c00SJeff Kirsher u8 port_id; 579f7917c00SJeff Kirsher u8 tx_chan; 580f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 581f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 582f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 583f7917c00SJeff Kirsher u8 rss_mode; 584f7917c00SJeff Kirsher struct link_config link_cfg; 585f7917c00SJeff Kirsher u16 *rss; 586a4cfd929SHariprasad Shenai struct port_stats stats_base; 587688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 588688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 589688848b1SAnish Bhatt #endif 59076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 59176fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 59276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5935e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5945e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 595a4569504SAtul Gupta bool ptp_enable; 596b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 597d5fbda61SArjun Vynipadath u32 eth_flags; 59802d805dcSSantosh Rastapur 59902d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 60002d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 60102d805dcSSantosh Rastapur */ 60202d805dcSSantosh Rastapur u8 vin; 60302d805dcSSantosh Rastapur u8 vivld; 60402d805dcSSantosh Rastapur u8 smt_idx; 60574dd5aa1SVishal Kulkarni u8 rx_cchan; 606f7917c00SJeff Kirsher }; 607f7917c00SJeff Kirsher 608f7917c00SJeff Kirsher struct dentry; 609f7917c00SJeff Kirsher struct work_struct; 610f7917c00SJeff Kirsher 611f7917c00SJeff Kirsher enum { /* adapter flags */ 61280f61f19SArjun Vynipadath CXGB4_FULL_INIT_DONE = (1 << 0), 61380f61f19SArjun Vynipadath CXGB4_DEV_ENABLED = (1 << 1), 61480f61f19SArjun Vynipadath CXGB4_USING_MSI = (1 << 2), 61580f61f19SArjun Vynipadath CXGB4_USING_MSIX = (1 << 3), 61680f61f19SArjun Vynipadath CXGB4_FW_OK = (1 << 4), 61780f61f19SArjun Vynipadath CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 61880f61f19SArjun Vynipadath CXGB4_USING_SOFT_PARAMS = (1 << 6), 61980f61f19SArjun Vynipadath CXGB4_MASTER_PF = (1 << 7), 62080f61f19SArjun Vynipadath CXGB4_FW_OFLD_CONN = (1 << 9), 62180f61f19SArjun Vynipadath CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 62280f61f19SArjun Vynipadath CXGB4_SHUTTING_DOWN = (1 << 11), 62380f61f19SArjun Vynipadath CXGB4_SGE_DBQ_TIMER = (1 << 12), 624f7917c00SJeff Kirsher }; 625f7917c00SJeff Kirsher 62694cdb8bbSHariprasad Shenai enum { 62794cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 628a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 62994cdb8bbSHariprasad Shenai }; 63094cdb8bbSHariprasad Shenai 631f7917c00SJeff Kirsher struct rx_sw_desc; 632f7917c00SJeff Kirsher 633f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 634f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 635f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 636f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 637f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 638f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 639f7917c00SJeff Kirsher unsigned long large_alloc_failed; 64070055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 64170055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 642f7917c00SJeff Kirsher unsigned long starving; 643f7917c00SJeff Kirsher /* RO fields */ 644f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 645f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 646f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 647f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 648f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 649df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 650df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 651f7917c00SJeff Kirsher }; 652f7917c00SJeff Kirsher 653f7917c00SJeff Kirsher /* A packet gather list */ 654f7917c00SJeff Kirsher struct pkt_gl { 6555e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 656e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 657f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 658f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 659f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 660f7917c00SJeff Kirsher }; 661f7917c00SJeff Kirsher 662f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 663f7917c00SJeff Kirsher const struct pkt_gl *gl); 6642337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6652337ba42SVarun Prakash /* LRO related declarations for ULD */ 6662337ba42SVarun Prakash struct t4_lro_mgr { 6672337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6682337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6692337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6702337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6712337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6722337ba42SVarun Prakash }; 673f7917c00SJeff Kirsher 674f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 675f7917c00SJeff Kirsher struct napi_struct napi; 676f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 677f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 678f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 679f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 680f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 681e553ec3fSHariprasad Shenai u8 adaptive_rx; 682f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 683f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 684f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 685f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 686f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 687f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 688f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 689f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 690df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 691df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 692f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 693f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 694f7917c00SJeff Kirsher struct adapter *adap; 695f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 696f7917c00SJeff Kirsher rspq_handler_t handler; 6972337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6982337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 699f7917c00SJeff Kirsher }; 700f7917c00SJeff Kirsher 701f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 702f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 703f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 704f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 705f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 706f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 707f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 708992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 709f7917c00SJeff Kirsher }; 710f7917c00SJeff Kirsher 711f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 712f7917c00SJeff Kirsher struct sge_rspq rspq; 713f7917c00SJeff Kirsher struct sge_fl fl; 714f7917c00SJeff Kirsher struct sge_eth_stats stats; 71576c3a552SRahul Lakkireddy struct msix_info *msix; 716f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 717f7917c00SJeff Kirsher 718f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 719f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 720f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 721f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 722f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 723f7917c00SJeff Kirsher }; 724f7917c00SJeff Kirsher 725f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 726f7917c00SJeff Kirsher struct sge_rspq rspq; 727f7917c00SJeff Kirsher struct sge_fl fl; 728f7917c00SJeff Kirsher struct sge_ofld_stats stats; 72976c3a552SRahul Lakkireddy struct msix_info *msix; 730f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 731f7917c00SJeff Kirsher 732f7917c00SJeff Kirsher struct tx_desc { 733f7917c00SJeff Kirsher __be64 flit[8]; 734f7917c00SJeff Kirsher }; 735f7917c00SJeff Kirsher 736f7917c00SJeff Kirsher struct tx_sw_desc; 737f7917c00SJeff Kirsher 738f7917c00SJeff Kirsher struct sge_txq { 739f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 740ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 741f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 742f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 743f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 744f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 745f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 746f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 747f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 748f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 749f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 750f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7513069ee9bSVipul Pandya spinlock_t db_lock; 7523069ee9bSVipul Pandya int db_disabled; 7533069ee9bSVipul Pandya unsigned short db_pidx; 75405eb2389SSteve Wise unsigned short db_pidx_inc; 755df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 756df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 757f7917c00SJeff Kirsher }; 758f7917c00SJeff Kirsher 759f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 760f7917c00SJeff Kirsher struct sge_txq q; 761f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 76210b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 76310b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 76410b00466SAnish Bhatt #endif 765d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 766d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 767f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 768f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 769f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 770f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 771f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 772f7917c00SJeff Kirsher 773ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 774f7917c00SJeff Kirsher struct sge_txq q; 775f7917c00SJeff Kirsher struct adapter *adap; 776f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 777f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 778126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 779f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 780f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 781f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 782f7917c00SJeff Kirsher 783f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 784f7917c00SJeff Kirsher struct sge_txq q; 785f7917c00SJeff Kirsher struct adapter *adap; 786f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 787f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 788f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 789f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 790f7917c00SJeff Kirsher 79194cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 79294cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 79394cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 79494cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 79594cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 79694cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 79794cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 79894cdb8bbSHariprasad Shenai }; 79994cdb8bbSHariprasad Shenai 800ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 801ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 802ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 803ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 804ab677ff4SHariprasad Shenai }; 805ab677ff4SHariprasad Shenai 806b1396c2bSRahul Lakkireddy enum sge_eosw_state { 807b1396c2bSRahul Lakkireddy CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 8080e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 8090e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 8104846d533SRahul Lakkireddy CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 8110e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 8120e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 813b1396c2bSRahul Lakkireddy }; 814b1396c2bSRahul Lakkireddy 815b1396c2bSRahul Lakkireddy struct sge_eosw_desc { 816b1396c2bSRahul Lakkireddy struct sk_buff *skb; /* SKB to free after getting completion */ 817b1396c2bSRahul Lakkireddy dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 818b1396c2bSRahul Lakkireddy }; 819b1396c2bSRahul Lakkireddy 820b1396c2bSRahul Lakkireddy struct sge_eosw_txq { 821b1396c2bSRahul Lakkireddy spinlock_t lock; /* Per queue lock to synchronize completions */ 822b1396c2bSRahul Lakkireddy enum sge_eosw_state state; /* Current ETHOFLD State */ 823b1396c2bSRahul Lakkireddy struct sge_eosw_desc *desc; /* Descriptor ring to hold packets */ 824b1396c2bSRahul Lakkireddy u32 ndesc; /* Number of descriptors */ 825b1396c2bSRahul Lakkireddy u32 pidx; /* Current Producer Index */ 826b1396c2bSRahul Lakkireddy u32 last_pidx; /* Last successfully transmitted Producer Index */ 827b1396c2bSRahul Lakkireddy u32 cidx; /* Current Consumer Index */ 828b1396c2bSRahul Lakkireddy u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 8290e395b3cSRahul Lakkireddy u32 flowc_idx; /* Descriptor containing a FLOWC request */ 830b1396c2bSRahul Lakkireddy u32 inuse; /* Number of packets held in ring */ 831b1396c2bSRahul Lakkireddy 832b1396c2bSRahul Lakkireddy u32 cred; /* Current available credits */ 833b1396c2bSRahul Lakkireddy u32 ncompl; /* # of completions posted */ 834b1396c2bSRahul Lakkireddy u32 last_compl; /* # of credits consumed since last completion req */ 835b1396c2bSRahul Lakkireddy 836b1396c2bSRahul Lakkireddy u32 eotid; /* Index into EOTID table in software */ 837b1396c2bSRahul Lakkireddy u32 hwtid; /* Hardware EOTID index */ 838b1396c2bSRahul Lakkireddy 839b1396c2bSRahul Lakkireddy u32 hwqid; /* Underlying hardware queue index */ 840b1396c2bSRahul Lakkireddy struct net_device *netdev; /* Pointer to netdevice */ 841b1396c2bSRahul Lakkireddy struct tasklet_struct qresume_tsk; /* Restarts the queue */ 8420e395b3cSRahul Lakkireddy struct completion completion; /* completion for FLOWC rendezvous */ 843b1396c2bSRahul Lakkireddy }; 844b1396c2bSRahul Lakkireddy 8452d0cb84dSRahul Lakkireddy struct sge_eohw_txq { 8462d0cb84dSRahul Lakkireddy spinlock_t lock; /* Per queue lock */ 8472d0cb84dSRahul Lakkireddy struct sge_txq q; /* HW Txq */ 8482d0cb84dSRahul Lakkireddy struct adapter *adap; /* Backpointer to adapter */ 8492d0cb84dSRahul Lakkireddy unsigned long tso; /* # of TSO requests */ 8502d0cb84dSRahul Lakkireddy unsigned long tx_cso; /* # of Tx checksum offloads */ 8512d0cb84dSRahul Lakkireddy unsigned long vlan_ins; /* # of Tx VLAN insertions */ 8522d0cb84dSRahul Lakkireddy unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 8532d0cb84dSRahul Lakkireddy }; 8542d0cb84dSRahul Lakkireddy 855f7917c00SJeff Kirsher struct sge { 856f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 857a4569504SAtul Gupta struct sge_eth_txq ptptxq; 858f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 859f7917c00SJeff Kirsher 860f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 861f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 86294cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 863ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 864f7917c00SJeff Kirsher 865f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 866f7917c00SJeff Kirsher spinlock_t intrq_lock; 867f7917c00SJeff Kirsher 8682d0cb84dSRahul Lakkireddy struct sge_eohw_txq *eohw_txq; 8692d0cb84dSRahul Lakkireddy struct sge_ofld_rxq *eohw_rxq; 8702d0cb84dSRahul Lakkireddy 871f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 872f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 873f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 8740fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 87594cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 8762d0cb84dSRahul Lakkireddy u16 eoqsets; /* # of ETHOFLD queues */ 8772d0cb84dSRahul Lakkireddy 878f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 879f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 880543a1b85SVishal Kulkarni u16 dbqtimer_tick; 881d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 88252367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 88352367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 88452367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 88552367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 88652367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 8870f4d201fSKumar Sanghvi 888a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 889f7917c00SJeff Kirsher unsigned int egr_start; 8904b8e27a8SHariprasad Shenai unsigned int egr_sz; 891f7917c00SJeff Kirsher unsigned int ingr_start; 8924b8e27a8SHariprasad Shenai unsigned int ingr_sz; 8934b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 8944b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 8954b8e27a8SHariprasad Shenai unsigned long *starving_fl; 8964b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 8975b377d11SHariprasad Shenai unsigned long *blocked_fl; 898f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 899f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 90076c3a552SRahul Lakkireddy 90176c3a552SRahul Lakkireddy int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 90276c3a552SRahul Lakkireddy int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 903f7917c00SJeff Kirsher }; 904f7917c00SJeff Kirsher 905f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 9060fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 907f7917c00SJeff Kirsher 908f7917c00SJeff Kirsher struct l2t_data; 909f7917c00SJeff Kirsher 9102422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 9112422d9a3SSantosh Rastapur 9127d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 9137d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 9147d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 9152422d9a3SSantosh Rastapur */ 9167d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 9172422d9a3SSantosh Rastapur 9182422d9a3SSantosh Rastapur #endif 9192422d9a3SSantosh Rastapur 920a4cfd929SHariprasad Shenai struct doorbell_stats { 921a4cfd929SHariprasad Shenai u32 db_drop; 922a4cfd929SHariprasad Shenai u32 db_empty; 923a4cfd929SHariprasad Shenai u32 db_full; 924a4cfd929SHariprasad Shenai }; 925a4cfd929SHariprasad Shenai 926fc08a01aSHariprasad Shenai struct hash_mac_addr { 927fc08a01aSHariprasad Shenai struct list_head list; 928fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 9293f8cfd0dSArjun Vynipadath unsigned int iface_mac; 930fc08a01aSHariprasad Shenai }; 931fc08a01aSHariprasad Shenai 93276c3a552SRahul Lakkireddy struct msix_bmap { 93394cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 93494cdb8bbSHariprasad Shenai unsigned int mapsize; 93594cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 93694cdb8bbSHariprasad Shenai }; 93794cdb8bbSHariprasad Shenai 93876c3a552SRahul Lakkireddy struct msix_info { 93994cdb8bbSHariprasad Shenai unsigned short vec; 94094cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 9410fbc81b3SHariprasad Shenai unsigned int idx; 942c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 94394cdb8bbSHariprasad Shenai }; 94494cdb8bbSHariprasad Shenai 945661dbeb9SHariprasad Shenai struct vf_info { 946661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 9478ea4fae9SGanesh Goudar unsigned int tx_rate; 948661dbeb9SHariprasad Shenai bool pf_set_mac; 9499d5fd927SGanesh Goudar u16 vlan; 9508b965f3fSArjun Vynipadath int link_state; 951661dbeb9SHariprasad Shenai }; 952661dbeb9SHariprasad Shenai 9538b4e6b3cSArjun Vynipadath enum { 9548b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 9558b4e6b3cSArjun Vynipadath }; 9568b4e6b3cSArjun Vynipadath 9578b4e6b3cSArjun Vynipadath struct hma_data { 9588b4e6b3cSArjun Vynipadath unsigned char flags; 9598b4e6b3cSArjun Vynipadath struct sg_table *sgt; 9608b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 9618b4e6b3cSArjun Vynipadath }; 9628b4e6b3cSArjun Vynipadath 9634055ae5eSHariprasad Shenai struct mbox_list { 9644055ae5eSHariprasad Shenai struct list_head list; 9654055ae5eSHariprasad Shenai }; 9664055ae5eSHariprasad Shenai 967e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 968b1871915SGanesh Goudar struct ch_thermal { 969b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 970b1871915SGanesh Goudar int trip_temp; 971b1871915SGanesh Goudar int trip_type; 972b1871915SGanesh Goudar }; 973b1871915SGanesh Goudar #endif 974b1871915SGanesh Goudar 97528b38705SRaju Rangoju struct mps_entries_ref { 97628b38705SRaju Rangoju struct list_head list; 97728b38705SRaju Rangoju u8 addr[ETH_ALEN]; 97828b38705SRaju Rangoju u8 mask[ETH_ALEN]; 97928b38705SRaju Rangoju u16 idx; 98028b38705SRaju Rangoju refcount_t refcnt; 98128b38705SRaju Rangoju }; 98228b38705SRaju Rangoju 983f7917c00SJeff Kirsher struct adapter { 984f7917c00SJeff Kirsher void __iomem *regs; 98522adfe0aSSantosh Rastapur void __iomem *bar2; 9860abfd152SHariprasad Shenai u32 t4_bar0; 987f7917c00SJeff Kirsher struct pci_dev *pdev; 988f7917c00SJeff Kirsher struct device *pdev_dev; 9890de72738SHariprasad Shenai const char *name; 9903069ee9bSVipul Pandya unsigned int mbox; 991b2612722SHariprasad Shenai unsigned int pf; 992f7917c00SJeff Kirsher unsigned int flags; 993e7b48a32SHariprasad Shenai unsigned int adap_idx; 9942422d9a3SSantosh Rastapur enum chip_type chip; 995d5fbda61SArjun Vynipadath u32 eth_flags; 996f7917c00SJeff Kirsher 997f7917c00SJeff Kirsher int msg_enable; 998846eac3fSGanesh Goudar __be16 vxlan_port; 999846eac3fSGanesh Goudar u8 vxlan_port_cnt; 1000c746fc0eSGanesh Goudar __be16 geneve_port; 1001c746fc0eSGanesh Goudar u8 geneve_port_cnt; 1002f7917c00SJeff Kirsher 1003f7917c00SJeff Kirsher struct adapter_params params; 1004f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 1005f7917c00SJeff Kirsher unsigned int swintr; 1006f7917c00SJeff Kirsher 100776c3a552SRahul Lakkireddy /* MSI-X Info for NIC and OFLD queues */ 100876c3a552SRahul Lakkireddy struct msix_info *msix_info; 100976c3a552SRahul Lakkireddy struct msix_bmap msix_bmap; 1010f7917c00SJeff Kirsher 1011a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 1012f7917c00SJeff Kirsher struct sge sge; 1013f7917c00SJeff Kirsher 1014f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 1015f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 1016f7917c00SJeff Kirsher 1017661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 1018661dbeb9SHariprasad Shenai u8 num_vfs; 1019661dbeb9SHariprasad Shenai 1020793dad94SVipul Pandya u32 filter_mode; 1021636f9d37SVipul Pandya unsigned int l2t_start; 1022636f9d37SVipul Pandya unsigned int l2t_end; 1023f7917c00SJeff Kirsher struct l2t_data *l2t; 1024b5a02f50SAnish Bhatt unsigned int clipt_start; 1025b5a02f50SAnish Bhatt unsigned int clipt_end; 1026b5a02f50SAnish Bhatt struct clip_tbl *clipt; 1027846eac3fSGanesh Goudar unsigned int rawf_start; 1028846eac3fSGanesh Goudar unsigned int rawf_cnt; 10293bdb376eSKumar Sanghvi struct smt_data *smt; 10300fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 1031f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 103294cdb8bbSHariprasad Shenai unsigned int num_uld; 10330fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 1034f7917c00SJeff Kirsher struct list_head list_node; 103501bcca68SVipul Pandya struct list_head rcu_node; 1036fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 103728b38705SRaju Rangoju struct list_head mps_ref; 103828b38705SRaju Rangoju spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1039f7917c00SJeff Kirsher 10407714cb9eSVarun Prakash void *iscsi_ppm; 10417714cb9eSVarun Prakash 1042f7917c00SJeff Kirsher struct tid_info tids; 1043f7917c00SJeff Kirsher void **tid_release_head; 1044f7917c00SJeff Kirsher spinlock_t tid_release_lock; 104529aaee65SAnish Bhatt struct workqueue_struct *workq; 1046f7917c00SJeff Kirsher struct work_struct tid_release_task; 1047881806bcSVipul Pandya struct work_struct db_full_task; 1048881806bcSVipul Pandya struct work_struct db_drop_task; 10498b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 1050f7917c00SJeff Kirsher bool tid_release_task_busy; 1051f7917c00SJeff Kirsher 10524055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 10534055ae5eSHariprasad Shenai spinlock_t mbox_lock; 10544055ae5eSHariprasad Shenai struct mbox_list mlist; 10554055ae5eSHariprasad Shenai 10567f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 10577f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 10587f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 10597f080c3fSHariprasad Shenai 10600fbc81b3SHariprasad Shenai struct mutex uld_mutex; 10610fbc81b3SHariprasad Shenai 1062f7917c00SJeff Kirsher struct dentry *debugfs_root; 1063621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1064621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 10658e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 10668e3d04fdSHariprasad Shenai * used for all 4 filters. 10678e3d04fdSHariprasad Shenai */ 1068f7917c00SJeff Kirsher 1069a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1070a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1071a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1072a4569504SAtul Gupta /* ptp lock */ 1073a4569504SAtul Gupta spinlock_t ptp_lock; 1074f7917c00SJeff Kirsher spinlock_t stats_lock; 1075fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1076d8931847SRahul Lakkireddy 1077d8931847SRahul Lakkireddy /* TC u32 offload */ 1078d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1079ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 108062488e4bSKumar Sanghvi 108162488e4bSKumar Sanghvi /* TC flower offload */ 1082a081e115SCasey Leedom bool tc_flower_initialized; 108379e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 108479e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1085e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 108679e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1087ad75b7d3SRahul Lakkireddy 1088ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1089ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 10908b4e6b3cSArjun Vynipadath 10918b4e6b3cSArjun Vynipadath /* HMA */ 10928b4e6b3cSArjun Vynipadath struct hma_data hma; 1093e4709475SRaju Rangoju 1094e4709475SRaju Rangoju struct srq_data *srq; 10951dde532dSRahul Lakkireddy 10961dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 10971dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1098e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1099b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1100b1871915SGanesh Goudar #endif 1101b1396c2bSRahul Lakkireddy 1102b1396c2bSRahul Lakkireddy /* TC MQPRIO offload */ 1103b1396c2bSRahul Lakkireddy struct cxgb4_tc_mqprio *tc_mqprio; 1104f7917c00SJeff Kirsher }; 1105f7917c00SJeff Kirsher 1106b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1107b72a32daSRahul Lakkireddy * programmed with various parameters. 1108b72a32daSRahul Lakkireddy */ 1109b72a32daSRahul Lakkireddy struct ch_sched_params { 1110b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 1111b72a32daSRahul Lakkireddy union { 1112b72a32daSRahul Lakkireddy struct { 1113b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 1114b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 1115b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 1116b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 1117b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 1118b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 1119b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 1120b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 1121b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 1122b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 1123b72a32daSRahul Lakkireddy } params; 1124b72a32daSRahul Lakkireddy } u; 1125b72a32daSRahul Lakkireddy }; 1126b72a32daSRahul Lakkireddy 112710a2604eSRahul Lakkireddy enum { 112810a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 112910a2604eSRahul Lakkireddy }; 113010a2604eSRahul Lakkireddy 113110a2604eSRahul Lakkireddy enum { 113210a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 113310a2604eSRahul Lakkireddy }; 113410a2604eSRahul Lakkireddy 113510a2604eSRahul Lakkireddy enum { 113610a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 11370e395b3cSRahul Lakkireddy SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 113810a2604eSRahul Lakkireddy }; 113910a2604eSRahul Lakkireddy 114010a2604eSRahul Lakkireddy enum { 114110a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 114210a2604eSRahul Lakkireddy }; 114310a2604eSRahul Lakkireddy 114410a2604eSRahul Lakkireddy enum { 114510a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 114610a2604eSRahul Lakkireddy }; 114710a2604eSRahul Lakkireddy 1148a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 1149a6ec572bSAtul Gupta struct sk_buff *skb; 1150a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 1151a6ec572bSAtul Gupta }; 1152a6ec572bSAtul Gupta 11536cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 11546cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 11556cede1f1SRahul Lakkireddy */ 11566cede1f1SRahul Lakkireddy struct ch_sched_queue { 11576cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 11586cede1f1SRahul Lakkireddy s8 class; /* class index */ 11596cede1f1SRahul Lakkireddy }; 11606cede1f1SRahul Lakkireddy 11610e395b3cSRahul Lakkireddy /* Support for "sched_flowc" command to allow one or more FLOWC 11620e395b3cSRahul Lakkireddy * to be bound to a TX Scheduling Class. 11630e395b3cSRahul Lakkireddy */ 11640e395b3cSRahul Lakkireddy struct ch_sched_flowc { 11650e395b3cSRahul Lakkireddy s32 tid; /* TID to bind */ 11660e395b3cSRahul Lakkireddy s8 class; /* class index */ 11670e395b3cSRahul Lakkireddy }; 11680e395b3cSRahul Lakkireddy 1169f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1170f2b7e78dSVipul Pandya */ 1171f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1172f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1173f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1174f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1175f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1176f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1177f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1178f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1179f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1180f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1181f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1182f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 118398f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1184f2b7e78dSVipul Pandya 1185f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1186f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1187f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1188f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1189f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1190f2b7e78dSVipul Pandya * matching rules are true. 1191f2b7e78dSVipul Pandya * 1192f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1193f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1194f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1195f2b7e78dSVipul Pandya * MPS match type) ... 1196f2b7e78dSVipul Pandya * 1197f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1198f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1199f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1200f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1201f2b7e78dSVipul Pandya */ 1202f2b7e78dSVipul Pandya struct ch_filter_tuple { 1203f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1204f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1205f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1206f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1207f2b7e78dSVipul Pandya * set of fields. 1208f2b7e78dSVipul Pandya */ 1209f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1210f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1211f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1212f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1213f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 121498f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1215f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1216f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1217f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1218f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1219f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1220f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1221f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1222f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1223f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1224f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 122598f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1226f2b7e78dSVipul Pandya 1227f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1228f2b7e78dSVipul Pandya * available for field rules. 1229f2b7e78dSVipul Pandya */ 1230f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1231f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1232f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1233f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1234f2b7e78dSVipul Pandya }; 1235f2b7e78dSVipul Pandya 1236f2b7e78dSVipul Pandya /* A filter ioctl command. 1237f2b7e78dSVipul Pandya */ 1238f2b7e78dSVipul Pandya struct ch_filter_specification { 1239f2b7e78dSVipul Pandya /* Administrative fields for filter. 1240f2b7e78dSVipul Pandya */ 1241f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1242f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1243f2b7e78dSVipul Pandya 1244f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1245f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1246f2b7e78dSVipul Pandya */ 1247f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 124812b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1249f2b7e78dSVipul Pandya 1250f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1251f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1252f2b7e78dSVipul Pandya * out as egress packets. 1253f2b7e78dSVipul Pandya */ 1254f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1255f2b7e78dSVipul Pandya 1256f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1257f2b7e78dSVipul Pandya 1258f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1259f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1260f2b7e78dSVipul Pandya 1261f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1262f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1263f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1264f2b7e78dSVipul Pandya 1265f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1266f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1267f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1268f2b7e78dSVipul Pandya */ 1269f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1270f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1271f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1272f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 12730ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1274f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1275f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1276f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1277f2b7e78dSVipul Pandya 12780ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 12790ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 12800ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 12810ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 12820ff90994SKumar Sanghvi 12830ff90994SKumar Sanghvi /* reservation for future additions */ 12840ff90994SKumar Sanghvi u8 rsvd[24]; 12850ff90994SKumar Sanghvi 1286f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1287f2b7e78dSVipul Pandya */ 1288f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1289f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1290f2b7e78dSVipul Pandya }; 1291f2b7e78dSVipul Pandya 1292f2b7e78dSVipul Pandya enum { 1293f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1294f2b7e78dSVipul Pandya FILTER_DROP, 1295f2b7e78dSVipul Pandya FILTER_SWITCH 1296f2b7e78dSVipul Pandya }; 1297f2b7e78dSVipul Pandya 1298f2b7e78dSVipul Pandya enum { 1299f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1300f2b7e78dSVipul Pandya VLAN_REMOVE, 1301f2b7e78dSVipul Pandya VLAN_INSERT, 1302f2b7e78dSVipul Pandya VLAN_REWRITE 1303f2b7e78dSVipul Pandya }; 1304f2b7e78dSVipul Pandya 1305557ccbf9SKumar Sanghvi enum { 130612b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 130712b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 130812b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 130912b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 131012b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 131112b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 131212b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 131312b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1314557ccbf9SKumar Sanghvi }; 1315557ccbf9SKumar Sanghvi 1316d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1317d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1318d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1319d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1320d57fd6caSRahul Lakkireddy * where the filter table is large. 1321d57fd6caSRahul Lakkireddy */ 1322d57fd6caSRahul Lakkireddy struct filter_entry { 1323d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1324d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1325d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1326d57fd6caSRahul Lakkireddy 1327d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1328578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1329d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 13303bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1331578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1332578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1333d57fd6caSRahul Lakkireddy 1334d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1335d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1336d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1337d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1338d57fd6caSRahul Lakkireddy */ 1339d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1340d57fd6caSRahul Lakkireddy }; 1341d57fd6caSRahul Lakkireddy 1342a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1343a4cfd929SHariprasad Shenai { 1344a4cfd929SHariprasad Shenai return adap->params.offload; 1345a4cfd929SHariprasad Shenai } 1346a4cfd929SHariprasad Shenai 13475c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 13485c31254eSKumar Sanghvi { 13495c31254eSKumar Sanghvi return adap->params.hash_filter; 13505c31254eSKumar Sanghvi } 13515c31254eSKumar Sanghvi 135294cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 135394cdb8bbSHariprasad Shenai { 135494cdb8bbSHariprasad Shenai return adap->params.crypto; 135594cdb8bbSHariprasad Shenai } 135694cdb8bbSHariprasad Shenai 13570fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 13580fbc81b3SHariprasad Shenai { 13590fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 13600fbc81b3SHariprasad Shenai } 13610fbc81b3SHariprasad Shenai 1362ab0367eaSRahul Lakkireddy static inline int is_ethofld(const struct adapter *adap) 1363ab0367eaSRahul Lakkireddy { 1364ab0367eaSRahul Lakkireddy return adap->params.ethofld; 1365ab0367eaSRahul Lakkireddy } 1366ab0367eaSRahul Lakkireddy 1367f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1368f7917c00SJeff Kirsher { 1369f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1370f7917c00SJeff Kirsher } 1371f7917c00SJeff Kirsher 1372f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1373f7917c00SJeff Kirsher { 1374f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1375f7917c00SJeff Kirsher } 1376f7917c00SJeff Kirsher 1377f7917c00SJeff Kirsher #ifndef readq 1378f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1379f7917c00SJeff Kirsher { 1380f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1381f7917c00SJeff Kirsher } 1382f7917c00SJeff Kirsher 1383f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1384f7917c00SJeff Kirsher { 1385f7917c00SJeff Kirsher writel(val, addr); 1386f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1387f7917c00SJeff Kirsher } 1388f7917c00SJeff Kirsher #endif 1389f7917c00SJeff Kirsher 1390f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1391f7917c00SJeff Kirsher { 1392f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1393f7917c00SJeff Kirsher } 1394f7917c00SJeff Kirsher 1395f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1396f7917c00SJeff Kirsher { 1397f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1398f7917c00SJeff Kirsher } 1399f7917c00SJeff Kirsher 1400f7917c00SJeff Kirsher /** 1401098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1402098ef6c2SHariprasad Shenai * @adapter: the adapter 1403098ef6c2SHariprasad Shenai * @port_idx: the port index 1404098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1405098ef6c2SHariprasad Shenai * 1406098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1407098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1408098ef6c2SHariprasad Shenai */ 1409098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1410098ef6c2SHariprasad Shenai u8 hw_addr[]) 1411098ef6c2SHariprasad Shenai { 1412098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1413098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1414098ef6c2SHariprasad Shenai } 1415098ef6c2SHariprasad Shenai 1416098ef6c2SHariprasad Shenai /** 1417f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1418f7917c00SJeff Kirsher * @dev: the netdev 1419f7917c00SJeff Kirsher * 1420f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1421f7917c00SJeff Kirsher */ 1422f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1423f7917c00SJeff Kirsher { 1424f7917c00SJeff Kirsher return netdev_priv(dev); 1425f7917c00SJeff Kirsher } 1426f7917c00SJeff Kirsher 1427f7917c00SJeff Kirsher /** 1428f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1429f7917c00SJeff Kirsher * @adap: the adapter 1430f7917c00SJeff Kirsher * @idx: the port index 1431f7917c00SJeff Kirsher * 1432f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1433f7917c00SJeff Kirsher */ 1434f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1435f7917c00SJeff Kirsher { 1436f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1437f7917c00SJeff Kirsher } 1438f7917c00SJeff Kirsher 1439f7917c00SJeff Kirsher /** 1440f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1441f7917c00SJeff Kirsher * @dev: the netdev 1442f7917c00SJeff Kirsher * 1443f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1444f7917c00SJeff Kirsher */ 1445f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1446f7917c00SJeff Kirsher { 1447f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1448f7917c00SJeff Kirsher } 1449f7917c00SJeff Kirsher 1450812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1451812034f1SHariprasad Shenai * - bits 0..9: chip version 1452812034f1SHariprasad Shenai * - bits 10..15: chip revision 1453812034f1SHariprasad Shenai * - bits 16..23: register dump version 1454812034f1SHariprasad Shenai */ 1455812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1456812034f1SHariprasad Shenai { 1457812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1458812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1459812034f1SHariprasad Shenai } 1460812034f1SHariprasad Shenai 1461812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1462812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1463812034f1SHariprasad Shenai const struct sge_rspq *q) 1464812034f1SHariprasad Shenai { 1465812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1466812034f1SHariprasad Shenai 1467812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1468812034f1SHariprasad Shenai } 1469812034f1SHariprasad Shenai 1470812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1471812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1472812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1473812034f1SHariprasad Shenai 14748156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1475f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1476f7917c00SJeff Kirsher 1477f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 14785fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1479f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1480d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1481f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1482f7917c00SJeff Kirsher const struct pkt_gl *gl); 1483f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1484f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1485f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1486f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 14872337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 14882337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1489f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1490f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1491d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1492f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1493f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1494f7917c00SJeff Kirsher unsigned int cmplqid); 14950fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 14960fbc81b3SHariprasad Shenai unsigned int cmplqid); 1497ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1498ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1499ab677ff4SHariprasad Shenai unsigned int uld_type); 15002d0cb84dSRahul Lakkireddy int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 15012d0cb84dSRahul Lakkireddy struct net_device *dev, u32 iqid); 15022d0cb84dSRahul Lakkireddy void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1503f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 150452367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1505f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1506f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1507d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1508d429005fSVishal Kulkarni int maxreclaim); 1509812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1510812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1511d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 15123069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1513f7917c00SJeff Kirsher 1514f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1515f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1516f7917c00SJeff Kirsher 15179a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 15189a4da2cdSVipul Pandya { 15199a4da2cdSVipul Pandya return adap->params.bypass; 15209a4da2cdSVipul Pandya } 15219a4da2cdSVipul Pandya 15229a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 15239a4da2cdSVipul Pandya { 15249a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 15259a4da2cdSVipul Pandya switch (device) { 15269a4da2cdSVipul Pandya case 0x440b: 15279a4da2cdSVipul Pandya case 0x440c: 15289a4da2cdSVipul Pandya return 1; 15299a4da2cdSVipul Pandya default: 15309a4da2cdSVipul Pandya return 0; 15319a4da2cdSVipul Pandya } 15329a4da2cdSVipul Pandya } 15339a4da2cdSVipul Pandya 153401b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 153501b69614SHariprasad Shenai { 153601b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 153701b69614SHariprasad Shenai switch (device) { 153801b69614SHariprasad Shenai case 0x4409: 153901b69614SHariprasad Shenai case 0x4486: 154001b69614SHariprasad Shenai return 1; 154101b69614SHariprasad Shenai 154201b69614SHariprasad Shenai default: 154301b69614SHariprasad Shenai return 0; 154401b69614SHariprasad Shenai } 154501b69614SHariprasad Shenai } 154601b69614SHariprasad Shenai 1547f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1548f7917c00SJeff Kirsher { 1549f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1550f7917c00SJeff Kirsher } 1551f7917c00SJeff Kirsher 1552f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1553f7917c00SJeff Kirsher unsigned int us) 1554f7917c00SJeff Kirsher { 1555f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1556f7917c00SJeff Kirsher } 1557f7917c00SJeff Kirsher 155852367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 155952367a76SVipul Pandya unsigned int ticks) 156052367a76SVipul Pandya { 156152367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 156252367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 156352367a76SVipul Pandya adapter->params.vpd.cclk); 156452367a76SVipul Pandya } 156552367a76SVipul Pandya 156608c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 156708c4901bSRahul Lakkireddy unsigned int ticks) 156808c4901bSRahul Lakkireddy { 156908c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 157008c4901bSRahul Lakkireddy } 157108c4901bSRahul Lakkireddy 1572f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1573f7917c00SJeff Kirsher u32 val); 1574f7917c00SJeff Kirsher 157501b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 157601b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1577f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1578f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1579f7917c00SJeff Kirsher 158001b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 158101b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 158201b69614SHariprasad Shenai int timeout) 158301b69614SHariprasad Shenai { 158401b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 158501b69614SHariprasad Shenai timeout); 158601b69614SHariprasad Shenai } 158701b69614SHariprasad Shenai 1588f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1589f7917c00SJeff Kirsher int size, void *rpl) 1590f7917c00SJeff Kirsher { 1591f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1592f7917c00SJeff Kirsher } 1593f7917c00SJeff Kirsher 1594f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1595f7917c00SJeff Kirsher int size, void *rpl) 1596f7917c00SJeff Kirsher { 1597f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1598f7917c00SJeff Kirsher } 1599f7917c00SJeff Kirsher 1600fc08a01aSHariprasad Shenai /** 1601fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1602fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1603fc08a01aSHariprasad Shenai * 1604fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1605fc08a01aSHariprasad Shenai * (hash) address matching. 1606fc08a01aSHariprasad Shenai */ 1607fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1608fc08a01aSHariprasad Shenai { 1609fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1610fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1611fc08a01aSHariprasad Shenai 1612fc08a01aSHariprasad Shenai a ^= b; 1613fc08a01aSHariprasad Shenai a ^= (a >> 12); 1614fc08a01aSHariprasad Shenai a ^= (a >> 6); 1615fc08a01aSHariprasad Shenai return a & 0x3f; 1616fc08a01aSHariprasad Shenai } 1617fc08a01aSHariprasad Shenai 161894cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 161994cdb8bbSHariprasad Shenai unsigned int cnt); 162094cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 162194cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 162294cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 162394cdb8bbSHariprasad Shenai { 162494cdb8bbSHariprasad Shenai q->adap = adap; 162594cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 162694cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 162794cdb8bbSHariprasad Shenai q->size = size; 162894cdb8bbSHariprasad Shenai } 162994cdb8bbSHariprasad Shenai 1630f56ec676SArjun Vynipadath /** 1631f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1632f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1633f56ec676SArjun Vynipadath * 1634f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1635f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1636f56ec676SArjun Vynipadath */ 1637f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1638f56ec676SArjun Vynipadath { 1639f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1640f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1641f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1642f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1643f56ec676SArjun Vynipadath } 1644f56ec676SArjun Vynipadath 164513ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 164613ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 164713ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1648f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1649f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1650f2b7e78dSVipul Pandya unsigned int start_idx); 16510abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1652f2b7e78dSVipul Pandya 1653f2b7e78dSVipul Pandya struct fw_filter_wr; 1654f2b7e78dSVipul Pandya 1655f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1656f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1657f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1658f7917c00SJeff Kirsher 16598203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 16608156b0baSGanesh Goudar 16619f764898SVishal Kulkarni fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 16629f764898SVishal Kulkarni struct link_config *lc); 16638156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 16648156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 16659f764898SVishal Kulkarni u8 sleep_ok, int timeout); 16668156b0baSGanesh Goudar 16678156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 16688156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 16698156b0baSGanesh Goudar { 16708156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 16718156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 16728156b0baSGanesh Goudar } 16738156b0baSGanesh Goudar 16748156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 16758156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 16768156b0baSGanesh Goudar { 16778156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 16788156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 16798156b0baSGanesh Goudar } 16808156b0baSGanesh Goudar 1681f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1682fc5ab020SHariprasad Shenai 1683b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1684b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1685b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1686b562fc37SHariprasad Shenai 16871a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 16881a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 16891a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 16901a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 16911a4330cdSRahul Lakkireddy int dir); 1692fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1693fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1694fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1695f01aa633SHariprasad Shenai void *buf, int dir); 1696fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1697fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1698fc5ab020SHariprasad Shenai { 1699fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1700fc5ab020SHariprasad Shenai } 1701fc5ab020SHariprasad Shenai 1702812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1703812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1704812034f1SHariprasad Shenai 1705940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1706f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1707098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1708098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 17090eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 171049216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 171149216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1712f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 171301b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 171401b69614SHariprasad Shenai int win, spinlock_t *lock, 171501b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 171601b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 171701b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 171849216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 171922c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 172022c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1721acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1722636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1723a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 17244da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 172516e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 17260de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 172716e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1728ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1729760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1730760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1731760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1732760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 173316e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 173416e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 173516e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1736f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 17373be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1738e85c9a7aSHariprasad Shenai 1739e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1740b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1741e85c9a7aSHariprasad Shenai unsigned int qid, 1742e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 174366cf188eSHariprasad S int user, 1744e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1745e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1746e85c9a7aSHariprasad Shenai 1747dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1748dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1749ae469b68SHariprasad Shenai 1750ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1751e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 17525ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1753dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1754c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1755c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1756c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1757f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1758f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1759f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1760f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1761f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1762f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1763f7917c00SJeff Kirsher unsigned int flags); 1764c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1765c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1766688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 17675ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 17685ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 17695ccf9d04SRahul Lakkireddy bool sleep_ok); 1770688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 17715ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1772688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 17735ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 17745ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 17755ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1776688ea5feSHariprasad Shenai 1777193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1778193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1779b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1780b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1781e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1782e5f0e43bSHariprasad Shenai size_t n); 1783c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1784c778af7dSHariprasad Shenai size_t n); 1785f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1786f1ff24aaSHariprasad Shenai unsigned int *valp); 1787f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1788f1ff24aaSHariprasad Shenai const unsigned int *valp); 1789f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 179019689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 179119689609SHariprasad Shenai unsigned int *pif_req_wrptr, 179219689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 179326fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 179474b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 179572aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1796f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1797a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1798a4cfd929SHariprasad Shenai struct port_stats *stats, 1799a4cfd929SHariprasad Shenai struct port_stats *offset); 180065046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1801f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1802bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1803636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1804636f9d37SVipul Pandya unsigned int mask, unsigned int val); 18052d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 18065ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 18075ccf9d04SRahul Lakkireddy bool sleep_ok); 18085ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 18095ccf9d04SRahul Lakkireddy bool sleep_ok); 18105ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 18115ccf9d04SRahul Lakkireddy bool sleep_ok); 18125ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 18135ccf9d04SRahul Lakkireddy bool sleep_ok); 1814f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 18155ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1816a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 18175ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1818f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1819f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1820f7917c00SJeff Kirsher 1821797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1822797ff0f5SHariprasad Shenai 18237864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1824f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1825f2b7e78dSVipul Pandya 1826f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1827f7917c00SJeff Kirsher const u8 *addr); 1828f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1829f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1830f7917c00SJeff Kirsher 1831f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1832f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1833f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1834f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1835f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1836636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1837636f9d37SVipul Pandya unsigned int cache_line_size); 1838636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1839f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1840f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1841f7917c00SJeff Kirsher u32 *val); 18428f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 18438f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 18448f46d467SArjun Vynipadath u32 *val); 184501b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1846f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 18478f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 184801b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1849688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1850688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 185101b69614SHariprasad Shenai const u32 *val, int timeout); 185201b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 185301b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1854688848b1SAnish Bhatt const u32 *val); 1855f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1856f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1857f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1858f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1859f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1860f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1861f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 186202d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 18634f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 18644f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 18654f3a0fcfSHariprasad Shenai unsigned int viid); 1866f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1867f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1868f7917c00SJeff Kirsher bool sleep_ok); 1869846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1870846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1871846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 187298f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 187398f3697fSKumar Sanghvi bool sleep_ok); 187498f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 187598f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 187698f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 187798f3697fSKumar Sanghvi bool sleep_ok); 1878846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1879846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1880846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1881f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1882f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1883f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1884fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1885fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1886fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1887f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 188802d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 1889f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1890f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1891688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1892688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1893e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1894e2f4f4e9SArjun Vynipadath struct port_info *pi, 1895e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1896f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1897f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1898f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1899f7917c00SJeff Kirsher unsigned int nblinks); 1900f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1901f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1902f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1903f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1904ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1905ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1906ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1907f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1908f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1909f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1910f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1911f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1912f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1913f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1914f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1915f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1916736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1917d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1918d429005fSVishal Kulkarni u16 *dbqtimers); 191923853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 19202061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1921c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1922c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1923f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1924881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1925881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 19268e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 19278e3d04fdSHariprasad Shenai int filter_index, int enable); 19288e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 19298e3d04fdSHariprasad Shenai int filter_index, int *enabled); 19308caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 19318caa1e84SVipul Pandya u32 addr, u32 val); 193208c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 193308c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 193408c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 19359e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 19369e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 19379e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 19389e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1939b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1940b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1941b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 194268bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1943a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1944a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1945a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1946a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1947a3bfb617SHariprasad Shenai int hz, int ticks); 1948858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1949858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 19505ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 19515ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 19524359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 19534359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 19545ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 19555ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 19565ccf9d04SRahul Lakkireddy 19570fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 19580fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 19590fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 19600fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1961f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1962f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1963f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 196494cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1965ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1966ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1967b1396c2bSRahul Lakkireddy void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 1968b1396c2bSRahul Lakkireddy u32 ndesc); 19690e395b3cSRahul Lakkireddy int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 1970b1396c2bSRahul Lakkireddy void cxgb4_ethofld_restart(unsigned long data); 19714846d533SRahul Lakkireddy int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 19724846d533SRahul Lakkireddy const struct pkt_gl *si); 1973ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1974a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1975a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1976a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1977a6ec572bSAtul Gupta dma_addr_t *addr); 1978a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1979a6ec572bSAtul Gupta void *pos); 1980a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1981a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1982a6ec572bSAtul Gupta const dma_addr_t *addr); 1983a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 19849d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 19859d5fd927SGanesh Goudar u16 vlan); 1986ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 1987b1871915SGanesh Goudar 1988b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 1989b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 1990c9765074SNirranjan Kirubaharan int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 1991c9765074SNirranjan Kirubaharan cpumask_var_t *aff_mask, int idx); 1992c9765074SNirranjan Kirubaharan void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 1993b1871915SGanesh Goudar 19942f0b9406SRaju Rangoju int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 19952f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 19962f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 19972f0b9406SRaju Rangoju 1998f9f329adSRaju Rangoju int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 1999f9f329adSRaju Rangoju bool free, unsigned int naddr, 2000f9f329adSRaju Rangoju const u8 **addr, u16 *idx, 2001f9f329adSRaju Rangoju u64 *hash, bool sleep_ok); 2002f9f329adSRaju Rangoju int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2003f9f329adSRaju Rangoju unsigned int naddr, const u8 **addr, bool sleep_ok); 200428b38705SRaju Rangoju int cxgb4_init_mps_ref_entries(struct adapter *adap); 200528b38705SRaju Rangoju void cxgb4_free_mps_ref_entries(struct adapter *adap); 200628b38705SRaju Rangoju int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 200728b38705SRaju Rangoju const u8 *addr, const u8 *mask, 200828b38705SRaju Rangoju unsigned int vni, unsigned int vni_mask, 200928b38705SRaju Rangoju u8 dip_hit, u8 lookup_type, bool sleep_ok); 201028b38705SRaju Rangoju int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 201128b38705SRaju Rangoju int idx, bool sleep_ok); 20125fab5158SRaju Rangoju int cxgb4_free_raw_mac_filt(struct adapter *adap, 20135fab5158SRaju Rangoju unsigned int viid, 20145fab5158SRaju Rangoju const u8 *addr, 20155fab5158SRaju Rangoju const u8 *mask, 20165fab5158SRaju Rangoju unsigned int idx, 20175fab5158SRaju Rangoju u8 lookup_type, 20185fab5158SRaju Rangoju u8 port_id, 20195fab5158SRaju Rangoju bool sleep_ok); 20205fab5158SRaju Rangoju int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 20215fab5158SRaju Rangoju unsigned int viid, 20225fab5158SRaju Rangoju const u8 *addr, 20235fab5158SRaju Rangoju const u8 *mask, 20245fab5158SRaju Rangoju unsigned int idx, 20255fab5158SRaju Rangoju u8 lookup_type, 20265fab5158SRaju Rangoju u8 port_id, 20275fab5158SRaju Rangoju bool sleep_ok); 20282f0b9406SRaju Rangoju int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 20292f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 20302f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 203176c3a552SRahul Lakkireddy int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 203276c3a552SRahul Lakkireddy void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2033b1396c2bSRahul Lakkireddy int cxgb_open(struct net_device *dev); 2034b1396c2bSRahul Lakkireddy int cxgb_close(struct net_device *dev); 20352d0cb84dSRahul Lakkireddy void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 20362d0cb84dSRahul Lakkireddy void cxgb4_quiesce_rx(struct sge_rspq *q); 2037f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 2038