1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59f7917c00SJeff Kirsher 603069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6194cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6294cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 633069ee9bSVipul Pandya 64a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 65a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 66a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 67a6ec572bSAtul Gupta */ 68a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 69a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 70a6ec572bSAtul Gupta 71f7917c00SJeff Kirsher enum { 72f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 73f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 74f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 75f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 76a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 77098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 78f7917c00SJeff Kirsher }; 79f7917c00SJeff Kirsher 80f7917c00SJeff Kirsher enum { 81812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 82812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 83812034f1SHariprasad Shenai }; 84812034f1SHariprasad Shenai 85812034f1SHariprasad Shenai enum { 86f7917c00SJeff Kirsher MEM_EDC0, 87f7917c00SJeff Kirsher MEM_EDC1, 882422d9a3SSantosh Rastapur MEM_MC, 892422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 904db0401fSRahul Lakkireddy MEM_MC1, 914db0401fSRahul Lakkireddy MEM_HMA, 92f7917c00SJeff Kirsher }; 93f7917c00SJeff Kirsher 943069ee9bSVipul Pandya enum { 953eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 963eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 973069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 983069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 992422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1003eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1013eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1020abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1030abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1043069ee9bSVipul Pandya }; 1053069ee9bSVipul Pandya 106f7917c00SJeff Kirsher enum dev_master { 107f7917c00SJeff Kirsher MASTER_CANT, 108f7917c00SJeff Kirsher MASTER_MAY, 109f7917c00SJeff Kirsher MASTER_MUST 110f7917c00SJeff Kirsher }; 111f7917c00SJeff Kirsher 112f7917c00SJeff Kirsher enum dev_state { 113f7917c00SJeff Kirsher DEV_STATE_UNINIT, 114f7917c00SJeff Kirsher DEV_STATE_INIT, 115f7917c00SJeff Kirsher DEV_STATE_ERR 116f7917c00SJeff Kirsher }; 117f7917c00SJeff Kirsher 118c3168cabSGanesh Goudar enum cc_pause { 119f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 120f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 121f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124c3168cabSGanesh Goudar enum cc_fec { 1253bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1263bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1273bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1283bb4858fSGanesh Goudar }; 1293bb4858fSGanesh Goudar 130f7917c00SJeff Kirsher struct port_stats { 131f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 132f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 133f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 134f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 135f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 136f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 137f7917c00SJeff Kirsher 138f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 139f7917c00SJeff Kirsher u64 tx_frames_65_127; 140f7917c00SJeff Kirsher u64 tx_frames_128_255; 141f7917c00SJeff Kirsher u64 tx_frames_256_511; 142f7917c00SJeff Kirsher u64 tx_frames_512_1023; 143f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 144f7917c00SJeff Kirsher u64 tx_frames_1519_max; 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 147f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 148f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 153f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 154f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 155f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 156f7917c00SJeff Kirsher 157f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 158f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 159f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 160f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 161f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 162f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 163f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 164f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 165f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 166f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 167f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 168f7917c00SJeff Kirsher 169f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 170f7917c00SJeff Kirsher u64 rx_frames_65_127; 171f7917c00SJeff Kirsher u64 rx_frames_128_255; 172f7917c00SJeff Kirsher u64 rx_frames_256_511; 173f7917c00SJeff Kirsher u64 rx_frames_512_1023; 174f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 175f7917c00SJeff Kirsher u64 rx_frames_1519_max; 176f7917c00SJeff Kirsher 177f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 178f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 183f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 184f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 185f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 186f7917c00SJeff Kirsher 187f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 188f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 189f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 190f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 191f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 192f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 193f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 194f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 195f7917c00SJeff Kirsher }; 196f7917c00SJeff Kirsher 197f7917c00SJeff Kirsher struct lb_port_stats { 198f7917c00SJeff Kirsher u64 octets; 199f7917c00SJeff Kirsher u64 frames; 200f7917c00SJeff Kirsher u64 bcast_frames; 201f7917c00SJeff Kirsher u64 mcast_frames; 202f7917c00SJeff Kirsher u64 ucast_frames; 203f7917c00SJeff Kirsher u64 error_frames; 204f7917c00SJeff Kirsher 205f7917c00SJeff Kirsher u64 frames_64; 206f7917c00SJeff Kirsher u64 frames_65_127; 207f7917c00SJeff Kirsher u64 frames_128_255; 208f7917c00SJeff Kirsher u64 frames_256_511; 209f7917c00SJeff Kirsher u64 frames_512_1023; 210f7917c00SJeff Kirsher u64 frames_1024_1518; 211f7917c00SJeff Kirsher u64 frames_1519_max; 212f7917c00SJeff Kirsher 213f7917c00SJeff Kirsher u64 drop; 214f7917c00SJeff Kirsher 215f7917c00SJeff Kirsher u64 ovflow0; 216f7917c00SJeff Kirsher u64 ovflow1; 217f7917c00SJeff Kirsher u64 ovflow2; 218f7917c00SJeff Kirsher u64 ovflow3; 219f7917c00SJeff Kirsher u64 trunc0; 220f7917c00SJeff Kirsher u64 trunc1; 221f7917c00SJeff Kirsher u64 trunc2; 222f7917c00SJeff Kirsher u64 trunc3; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_tcp_stats { 226a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 227a4cfd929SHariprasad Shenai u64 tcp_in_segs; 228a4cfd929SHariprasad Shenai u64 tcp_out_segs; 229a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 230a4cfd929SHariprasad Shenai }; 231a4cfd929SHariprasad Shenai 232a4cfd929SHariprasad Shenai struct tp_usm_stats { 233a4cfd929SHariprasad Shenai u32 frames; 234a4cfd929SHariprasad Shenai u32 drops; 235a4cfd929SHariprasad Shenai u64 octets; 236f7917c00SJeff Kirsher }; 237f7917c00SJeff Kirsher 238a6222975SHariprasad Shenai struct tp_fcoe_stats { 239a6222975SHariprasad Shenai u32 frames_ddp; 240a6222975SHariprasad Shenai u32 frames_drop; 241a6222975SHariprasad Shenai u64 octets_ddp; 242f7917c00SJeff Kirsher }; 243f7917c00SJeff Kirsher 244f7917c00SJeff Kirsher struct tp_err_stats { 245a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 246a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 247a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 248a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 249a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 250a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 251a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 252a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 253a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 254a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 255a4cfd929SHariprasad Shenai }; 256a4cfd929SHariprasad Shenai 257a6222975SHariprasad Shenai struct tp_cpl_stats { 258a6222975SHariprasad Shenai u32 req[4]; 259a6222975SHariprasad Shenai u32 rsp[4]; 260a6222975SHariprasad Shenai }; 261a6222975SHariprasad Shenai 262a4cfd929SHariprasad Shenai struct tp_rdma_stats { 263a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 264a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 265f7917c00SJeff Kirsher }; 266f7917c00SJeff Kirsher 267e85c9a7aSHariprasad Shenai struct sge_params { 268e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 269e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 270e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 271e85c9a7aSHariprasad Shenai }; 272e85c9a7aSHariprasad Shenai 273f7917c00SJeff Kirsher struct tp_params { 274f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2752d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 276dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 277dca4faebSVipul Pandya /* channel map */ 278636f9d37SVipul Pandya 279636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 280636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 281dcf7b6f5SKumar Sanghvi 282dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 283dcf10ec7SRaju Rangoju u32 filter_mask; 284dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 285dcf7b6f5SKumar Sanghvi 2868eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2878eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2888eb9f2f9SArjun V */ 2898eb9f2f9SArjun V int rx_pkt_encap; 2908eb9f2f9SArjun V 291dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 292dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 293dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 294dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 295dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 296dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 297dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 298dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 299dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 300dcf7b6f5SKumar Sanghvi * present. 301dcf7b6f5SKumar Sanghvi */ 3020ba9a3b6SKumar Sanghvi int fcoe_shift; 303dcf7b6f5SKumar Sanghvi int port_shift; 3040ba9a3b6SKumar Sanghvi int vnic_shift; 3050ba9a3b6SKumar Sanghvi int vlan_shift; 3060ba9a3b6SKumar Sanghvi int tos_shift; 307dcf7b6f5SKumar Sanghvi int protocol_shift; 3080ba9a3b6SKumar Sanghvi int ethertype_shift; 3090ba9a3b6SKumar Sanghvi int macmatch_shift; 3100ba9a3b6SKumar Sanghvi int matchtype_shift; 3110ba9a3b6SKumar Sanghvi int frag_shift; 3120ba9a3b6SKumar Sanghvi 3130ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 314f7917c00SJeff Kirsher }; 315f7917c00SJeff Kirsher 316f7917c00SJeff Kirsher struct vpd_params { 317f7917c00SJeff Kirsher unsigned int cclk; 318f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 319f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 320f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 321a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 322098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 323f7917c00SJeff Kirsher }; 324f7917c00SJeff Kirsher 3250eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3260eaec62aSCasey Leedom */ 3270eaec62aSCasey Leedom struct pf_resources { 3280eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3290eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 3300eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 3310eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 3320eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 3330eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 3340eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 3350eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 3360eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 3370eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 3380eaec62aSCasey Leedom }; 3390eaec62aSCasey Leedom 340f7917c00SJeff Kirsher struct pci_params { 341baf50868SGanesh Goudar unsigned int vpd_cap_addr; 342f7917c00SJeff Kirsher unsigned char speed; 343f7917c00SJeff Kirsher unsigned char width; 344f7917c00SJeff Kirsher }; 345f7917c00SJeff Kirsher 34649aa284fSHariprasad Shenai struct devlog_params { 34749aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 34849aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 34949aa284fSHariprasad Shenai u32 size; /* size of log */ 35049aa284fSHariprasad Shenai }; 35149aa284fSHariprasad Shenai 3523ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3533ccc6cf7SHariprasad Shenai struct arch_specific_params { 3543ccc6cf7SHariprasad Shenai u8 nchan; 35544588560SHariprasad Shenai u8 pm_stats_cnt; 3562216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3573ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3583ccc6cf7SHariprasad Shenai u16 vfcount; 3593ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3603ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3613ccc6cf7SHariprasad Shenai }; 3623ccc6cf7SHariprasad Shenai 363f7917c00SJeff Kirsher struct adapter_params { 364e85c9a7aSHariprasad Shenai struct sge_params sge; 365f7917c00SJeff Kirsher struct tp_params tp; 366f7917c00SJeff Kirsher struct vpd_params vpd; 3670eaec62aSCasey Leedom struct pf_resources pfres; 368f7917c00SJeff Kirsher struct pci_params pci; 36949aa284fSHariprasad Shenai struct devlog_params devlog; 37049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 371f7917c00SJeff Kirsher 372f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 373f1ff24aaSHariprasad Shenai 374f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 375f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 376f7917c00SJeff Kirsher 377760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3780de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 379760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3800de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 381760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 382760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 383f7917c00SJeff Kirsher u8 api_vers[7]; 384f7917c00SJeff Kirsher 385f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 386f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 387f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 388f7917c00SJeff Kirsher 389f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 390f7917c00SJeff Kirsher unsigned char portvec; 391d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3923ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 393f7917c00SJeff Kirsher unsigned char offload; 39494cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 395ab0367eaSRahul Lakkireddy unsigned char ethofld; /* QoS support */ 396f7917c00SJeff Kirsher 3979a4da2cdSVipul Pandya unsigned char bypass; 3985c31254eSKumar Sanghvi unsigned char hash_filter; 3999a4da2cdSVipul Pandya 400f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 4011ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4024c2c5763SHariprasad Shenai 403b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4044c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4054c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 406086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 407c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4080ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 40902d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4108f46d467SArjun Vynipadath 4118f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4128f46d467SArjun Vynipadath * used by the Port 4138f46d467SArjun Vynipadath */ 4148f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 41543db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 416f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 417f7917c00SJeff Kirsher }; 418f7917c00SJeff Kirsher 419a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 420a3bfb617SHariprasad Shenai * and possible hangs. 421a3bfb617SHariprasad Shenai */ 422a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 423a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 424a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 425a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 426a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 427a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 428a3bfb617SHariprasad Shenai }; 429a3bfb617SHariprasad Shenai 4307f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4317f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4327f080c3fSHariprasad Shenai * error returns. 4337f080c3fSHariprasad Shenai */ 4347f080c3fSHariprasad Shenai struct mbox_cmd { 4357f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4367f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4377f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4387f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4397f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4407f080c3fSHariprasad Shenai }; 4417f080c3fSHariprasad Shenai 4427f080c3fSHariprasad Shenai struct mbox_cmd_log { 4437f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4447f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4457f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4467f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4477f080c3fSHariprasad Shenai }; 4487f080c3fSHariprasad Shenai 4497f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4507f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4517f080c3fSHariprasad Shenai */ 4527f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4537f080c3fSHariprasad Shenai unsigned int entry_idx) 4547f080c3fSHariprasad Shenai { 4557f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4567f080c3fSHariprasad Shenai } 4577f080c3fSHariprasad Shenai 45816e47624SHariprasad Shenai #include "t4fw_api.h" 45916e47624SHariprasad Shenai 46016e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 461b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 462b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 463b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 464b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 46516e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 46616e47624SHariprasad Shenai 46716e47624SHariprasad Shenai struct fw_info { 46816e47624SHariprasad Shenai u8 chip; 46916e47624SHariprasad Shenai char *fs_name; 47016e47624SHariprasad Shenai char *fw_mod_name; 47116e47624SHariprasad Shenai struct fw_hdr fw_hdr; 47216e47624SHariprasad Shenai }; 47316e47624SHariprasad Shenai 474f7917c00SJeff Kirsher struct trace_params { 475f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 476f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 477f7917c00SJeff Kirsher unsigned short snap_len; 478f7917c00SJeff Kirsher unsigned short min_len; 479f7917c00SJeff Kirsher unsigned char skip_ofst; 480f7917c00SJeff Kirsher unsigned char skip_len; 481f7917c00SJeff Kirsher unsigned char invert; 482f7917c00SJeff Kirsher unsigned char port; 483f7917c00SJeff Kirsher }; 484f7917c00SJeff Kirsher 485c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 486c3168cabSGanesh Goudar 487c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 488c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 489c3168cabSGanesh Goudar 490c3168cabSGanesh Goudar enum fw_caps { 491c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 492c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 493c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 494c3168cabSGanesh Goudar }; 495c3168cabSGanesh Goudar 496f7917c00SJeff Kirsher struct link_config { 497c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 498c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 499c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 500c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 501c3168cabSGanesh Goudar 502c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 503c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 504c3168cabSGanesh Goudar 505c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 506c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 5070caeaf6aSRahul Lakkireddy enum cc_pause advertised_fc; /* actual advertised flow control */ 508c3168cabSGanesh Goudar 509c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 510c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 511c3168cabSGanesh Goudar 512f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 513c3168cabSGanesh Goudar 514f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 515ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5168156b0baSGanesh Goudar 5178156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5188156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 519f7917c00SJeff Kirsher }; 520f7917c00SJeff Kirsher 521e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 522f7917c00SJeff Kirsher 523f7917c00SJeff Kirsher enum { 524f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 525f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 526f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 527f7917c00SJeff Kirsher }; 528f7917c00SJeff Kirsher 529f7917c00SJeff Kirsher enum { 530812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 531812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 532812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 533812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 534812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 535812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 536812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 537812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 538812034f1SHariprasad Shenai }; 539812034f1SHariprasad Shenai 540812034f1SHariprasad Shenai enum { 54168ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 54268ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 54368ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 54468ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 54568ddc82aSRahul Lakkireddy }; 54668ddc82aSRahul Lakkireddy 54768ddc82aSRahul Lakkireddy enum { 548cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 549cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5500fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 551f7917c00SJeff Kirsher }; 552f7917c00SJeff Kirsher 553d5fbda61SArjun Vynipadath enum { 554d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 555d5fbda61SArjun Vynipadath }; 556d5fbda61SArjun Vynipadath 557d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 558d5fbda61SArjun Vynipadath 559d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 560d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 561d5fbda61SArjun Vynipadath 562f7917c00SJeff Kirsher struct adapter; 563f7917c00SJeff Kirsher struct sge_rspq; 564f7917c00SJeff Kirsher 565688848b1SAnish Bhatt #include "cxgb4_dcb.h" 566688848b1SAnish Bhatt 56776fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 56876fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 56976fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 57076fed8a9SVarun Prakash 571f7917c00SJeff Kirsher struct port_info { 572f7917c00SJeff Kirsher struct adapter *adapter; 573f7917c00SJeff Kirsher u16 viid; 5743f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 575f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 576f7917c00SJeff Kirsher s8 mdio_addr; 57740e9de4bSHariprasad Shenai enum fw_port_type port_type; 578f7917c00SJeff Kirsher u8 mod_type; 579f7917c00SJeff Kirsher u8 port_id; 580f7917c00SJeff Kirsher u8 tx_chan; 581f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 582f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 583f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 584f7917c00SJeff Kirsher u8 rss_mode; 585f7917c00SJeff Kirsher struct link_config link_cfg; 586f7917c00SJeff Kirsher u16 *rss; 587a4cfd929SHariprasad Shenai struct port_stats stats_base; 588688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 589688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 590688848b1SAnish Bhatt #endif 59176fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 59276fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 59376fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5945e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5955e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 596a4569504SAtul Gupta bool ptp_enable; 597b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 598d5fbda61SArjun Vynipadath u32 eth_flags; 59902d805dcSSantosh Rastapur 60002d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 60102d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 60202d805dcSSantosh Rastapur */ 60302d805dcSSantosh Rastapur u8 vin; 60402d805dcSSantosh Rastapur u8 vivld; 60502d805dcSSantosh Rastapur u8 smt_idx; 60674dd5aa1SVishal Kulkarni u8 rx_cchan; 6074ec4762dSRahul Lakkireddy 6084ec4762dSRahul Lakkireddy bool tc_block_shared; 609f7917c00SJeff Kirsher }; 610f7917c00SJeff Kirsher 611f7917c00SJeff Kirsher struct dentry; 612f7917c00SJeff Kirsher struct work_struct; 613f7917c00SJeff Kirsher 614f7917c00SJeff Kirsher enum { /* adapter flags */ 61580f61f19SArjun Vynipadath CXGB4_FULL_INIT_DONE = (1 << 0), 61680f61f19SArjun Vynipadath CXGB4_DEV_ENABLED = (1 << 1), 61780f61f19SArjun Vynipadath CXGB4_USING_MSI = (1 << 2), 61880f61f19SArjun Vynipadath CXGB4_USING_MSIX = (1 << 3), 61980f61f19SArjun Vynipadath CXGB4_FW_OK = (1 << 4), 62080f61f19SArjun Vynipadath CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 62180f61f19SArjun Vynipadath CXGB4_USING_SOFT_PARAMS = (1 << 6), 62280f61f19SArjun Vynipadath CXGB4_MASTER_PF = (1 << 7), 62380f61f19SArjun Vynipadath CXGB4_FW_OFLD_CONN = (1 << 9), 62480f61f19SArjun Vynipadath CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 62580f61f19SArjun Vynipadath CXGB4_SHUTTING_DOWN = (1 << 11), 62680f61f19SArjun Vynipadath CXGB4_SGE_DBQ_TIMER = (1 << 12), 627f7917c00SJeff Kirsher }; 628f7917c00SJeff Kirsher 62994cdb8bbSHariprasad Shenai enum { 63094cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 631a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 63294cdb8bbSHariprasad Shenai }; 63394cdb8bbSHariprasad Shenai 634f7917c00SJeff Kirsher struct rx_sw_desc; 635f7917c00SJeff Kirsher 636f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 637f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 638f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 639f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 640f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 641f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 642f7917c00SJeff Kirsher unsigned long large_alloc_failed; 64370055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 64470055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 645f7917c00SJeff Kirsher unsigned long starving; 646f7917c00SJeff Kirsher /* RO fields */ 647f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 648f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 649f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 650f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 651f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 652df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 653df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 654f7917c00SJeff Kirsher }; 655f7917c00SJeff Kirsher 656f7917c00SJeff Kirsher /* A packet gather list */ 657f7917c00SJeff Kirsher struct pkt_gl { 6585e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 659e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 660f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 661f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 662f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 663f7917c00SJeff Kirsher }; 664f7917c00SJeff Kirsher 665f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 666f7917c00SJeff Kirsher const struct pkt_gl *gl); 6672337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6682337ba42SVarun Prakash /* LRO related declarations for ULD */ 6692337ba42SVarun Prakash struct t4_lro_mgr { 6702337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6712337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6722337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6732337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6742337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6752337ba42SVarun Prakash }; 676f7917c00SJeff Kirsher 677f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 678f7917c00SJeff Kirsher struct napi_struct napi; 679f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 680f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 681f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 682f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 683f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 684e553ec3fSHariprasad Shenai u8 adaptive_rx; 685f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 686f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 687f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 688f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 689f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 690f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 691f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 692f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 693df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 694df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 695f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 696f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 697f7917c00SJeff Kirsher struct adapter *adap; 698f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 699f7917c00SJeff Kirsher rspq_handler_t handler; 7002337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 7012337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 702f7917c00SJeff Kirsher }; 703f7917c00SJeff Kirsher 704f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 705f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 706f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 707f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 708f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 709f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 710f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 711992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 712f7917c00SJeff Kirsher }; 713f7917c00SJeff Kirsher 714f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 715f7917c00SJeff Kirsher struct sge_rspq rspq; 716f7917c00SJeff Kirsher struct sge_fl fl; 717f7917c00SJeff Kirsher struct sge_eth_stats stats; 71876c3a552SRahul Lakkireddy struct msix_info *msix; 719f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 720f7917c00SJeff Kirsher 721f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 722f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 723f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 724f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 725f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 726f7917c00SJeff Kirsher }; 727f7917c00SJeff Kirsher 728f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 729f7917c00SJeff Kirsher struct sge_rspq rspq; 730f7917c00SJeff Kirsher struct sge_fl fl; 731f7917c00SJeff Kirsher struct sge_ofld_stats stats; 73276c3a552SRahul Lakkireddy struct msix_info *msix; 733f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 734f7917c00SJeff Kirsher 735f7917c00SJeff Kirsher struct tx_desc { 736f7917c00SJeff Kirsher __be64 flit[8]; 737f7917c00SJeff Kirsher }; 738f7917c00SJeff Kirsher 7390ed96b46SRahul Lakkireddy struct ulptx_sgl; 7400ed96b46SRahul Lakkireddy 7410ed96b46SRahul Lakkireddy struct tx_sw_desc { 7420ed96b46SRahul Lakkireddy struct sk_buff *skb; /* SKB to free after getting completion */ 7430ed96b46SRahul Lakkireddy dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 7440ed96b46SRahul Lakkireddy }; 745f7917c00SJeff Kirsher 746f7917c00SJeff Kirsher struct sge_txq { 747f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 748ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 749f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 750f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 751f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 752f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 753f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 754f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 755f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 756f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 757f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 758f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7593069ee9bSVipul Pandya spinlock_t db_lock; 7603069ee9bSVipul Pandya int db_disabled; 7613069ee9bSVipul Pandya unsigned short db_pidx; 76205eb2389SSteve Wise unsigned short db_pidx_inc; 763df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 764df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 765f7917c00SJeff Kirsher }; 766f7917c00SJeff Kirsher 767f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 768f7917c00SJeff Kirsher struct sge_txq q; 769f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 77010b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 77110b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 77210b00466SAnish Bhatt #endif 773d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 774d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 775f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 7761a2a14fbSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 777f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 778f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 779f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 780f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 781f7917c00SJeff Kirsher 782ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 783f7917c00SJeff Kirsher struct sge_txq q; 784f7917c00SJeff Kirsher struct adapter *adap; 785f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 786f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 787126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 788f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 789f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 790f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 791f7917c00SJeff Kirsher 792f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 793f7917c00SJeff Kirsher struct sge_txq q; 794f7917c00SJeff Kirsher struct adapter *adap; 795f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 796f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 797f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 798f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 799f7917c00SJeff Kirsher 80094cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 80194cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 80294cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 80394cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 80494cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 80594cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 80694cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 80794cdb8bbSHariprasad Shenai }; 80894cdb8bbSHariprasad Shenai 809ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 810ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 811ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 812ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 813ab677ff4SHariprasad Shenai }; 814ab677ff4SHariprasad Shenai 815b1396c2bSRahul Lakkireddy enum sge_eosw_state { 816b1396c2bSRahul Lakkireddy CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 8170e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 8180e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 8194846d533SRahul Lakkireddy CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 8200e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 8210e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 822b1396c2bSRahul Lakkireddy }; 823b1396c2bSRahul Lakkireddy 824b1396c2bSRahul Lakkireddy struct sge_eosw_txq { 825b1396c2bSRahul Lakkireddy spinlock_t lock; /* Per queue lock to synchronize completions */ 826b1396c2bSRahul Lakkireddy enum sge_eosw_state state; /* Current ETHOFLD State */ 8270ed96b46SRahul Lakkireddy struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 828b1396c2bSRahul Lakkireddy u32 ndesc; /* Number of descriptors */ 829b1396c2bSRahul Lakkireddy u32 pidx; /* Current Producer Index */ 830b1396c2bSRahul Lakkireddy u32 last_pidx; /* Last successfully transmitted Producer Index */ 831b1396c2bSRahul Lakkireddy u32 cidx; /* Current Consumer Index */ 832b1396c2bSRahul Lakkireddy u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 8330e395b3cSRahul Lakkireddy u32 flowc_idx; /* Descriptor containing a FLOWC request */ 834b1396c2bSRahul Lakkireddy u32 inuse; /* Number of packets held in ring */ 835b1396c2bSRahul Lakkireddy 836b1396c2bSRahul Lakkireddy u32 cred; /* Current available credits */ 837b1396c2bSRahul Lakkireddy u32 ncompl; /* # of completions posted */ 838b1396c2bSRahul Lakkireddy u32 last_compl; /* # of credits consumed since last completion req */ 839b1396c2bSRahul Lakkireddy 840b1396c2bSRahul Lakkireddy u32 eotid; /* Index into EOTID table in software */ 841b1396c2bSRahul Lakkireddy u32 hwtid; /* Hardware EOTID index */ 842b1396c2bSRahul Lakkireddy 843b1396c2bSRahul Lakkireddy u32 hwqid; /* Underlying hardware queue index */ 844b1396c2bSRahul Lakkireddy struct net_device *netdev; /* Pointer to netdevice */ 845b1396c2bSRahul Lakkireddy struct tasklet_struct qresume_tsk; /* Restarts the queue */ 8460e395b3cSRahul Lakkireddy struct completion completion; /* completion for FLOWC rendezvous */ 847b1396c2bSRahul Lakkireddy }; 848b1396c2bSRahul Lakkireddy 8492d0cb84dSRahul Lakkireddy struct sge_eohw_txq { 8502d0cb84dSRahul Lakkireddy spinlock_t lock; /* Per queue lock */ 8512d0cb84dSRahul Lakkireddy struct sge_txq q; /* HW Txq */ 8522d0cb84dSRahul Lakkireddy struct adapter *adap; /* Backpointer to adapter */ 8532d0cb84dSRahul Lakkireddy unsigned long tso; /* # of TSO requests */ 8548311f0beSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 8552d0cb84dSRahul Lakkireddy unsigned long tx_cso; /* # of Tx checksum offloads */ 8562d0cb84dSRahul Lakkireddy unsigned long vlan_ins; /* # of Tx VLAN insertions */ 8572d0cb84dSRahul Lakkireddy unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 8582d0cb84dSRahul Lakkireddy }; 8592d0cb84dSRahul Lakkireddy 860f7917c00SJeff Kirsher struct sge { 861f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 862a4569504SAtul Gupta struct sge_eth_txq ptptxq; 863f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 864f7917c00SJeff Kirsher 865f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 866f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 86794cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 868ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 869f7917c00SJeff Kirsher 870f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 871f7917c00SJeff Kirsher spinlock_t intrq_lock; 872f7917c00SJeff Kirsher 8732d0cb84dSRahul Lakkireddy struct sge_eohw_txq *eohw_txq; 8742d0cb84dSRahul Lakkireddy struct sge_ofld_rxq *eohw_rxq; 8752d0cb84dSRahul Lakkireddy 876f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 877f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 878f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 8790fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 88094cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 8812d0cb84dSRahul Lakkireddy u16 eoqsets; /* # of ETHOFLD queues */ 8822d0cb84dSRahul Lakkireddy 883f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 884f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 885543a1b85SVishal Kulkarni u16 dbqtimer_tick; 886d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 88752367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 88852367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 88952367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 89052367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 89152367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 8920f4d201fSKumar Sanghvi 893a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 894f7917c00SJeff Kirsher unsigned int egr_start; 8954b8e27a8SHariprasad Shenai unsigned int egr_sz; 896f7917c00SJeff Kirsher unsigned int ingr_start; 8974b8e27a8SHariprasad Shenai unsigned int ingr_sz; 8984b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 8994b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 9004b8e27a8SHariprasad Shenai unsigned long *starving_fl; 9014b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 9025b377d11SHariprasad Shenai unsigned long *blocked_fl; 903f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 904f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 90576c3a552SRahul Lakkireddy 90676c3a552SRahul Lakkireddy int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 90776c3a552SRahul Lakkireddy int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 908f7917c00SJeff Kirsher }; 909f7917c00SJeff Kirsher 910f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 9110fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 912f7917c00SJeff Kirsher 913f7917c00SJeff Kirsher struct l2t_data; 914f7917c00SJeff Kirsher 9152422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 9162422d9a3SSantosh Rastapur 9177d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 9187d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 9197d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 9202422d9a3SSantosh Rastapur */ 9217d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 9222422d9a3SSantosh Rastapur 9232422d9a3SSantosh Rastapur #endif 9242422d9a3SSantosh Rastapur 925a4cfd929SHariprasad Shenai struct doorbell_stats { 926a4cfd929SHariprasad Shenai u32 db_drop; 927a4cfd929SHariprasad Shenai u32 db_empty; 928a4cfd929SHariprasad Shenai u32 db_full; 929a4cfd929SHariprasad Shenai }; 930a4cfd929SHariprasad Shenai 931fc08a01aSHariprasad Shenai struct hash_mac_addr { 932fc08a01aSHariprasad Shenai struct list_head list; 933fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 9343f8cfd0dSArjun Vynipadath unsigned int iface_mac; 935fc08a01aSHariprasad Shenai }; 936fc08a01aSHariprasad Shenai 93776c3a552SRahul Lakkireddy struct msix_bmap { 93894cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 93994cdb8bbSHariprasad Shenai unsigned int mapsize; 94094cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 94194cdb8bbSHariprasad Shenai }; 94294cdb8bbSHariprasad Shenai 94376c3a552SRahul Lakkireddy struct msix_info { 94494cdb8bbSHariprasad Shenai unsigned short vec; 94594cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 9460fbc81b3SHariprasad Shenai unsigned int idx; 947c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 94894cdb8bbSHariprasad Shenai }; 94994cdb8bbSHariprasad Shenai 950661dbeb9SHariprasad Shenai struct vf_info { 951661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 9528ea4fae9SGanesh Goudar unsigned int tx_rate; 953661dbeb9SHariprasad Shenai bool pf_set_mac; 9549d5fd927SGanesh Goudar u16 vlan; 9558b965f3fSArjun Vynipadath int link_state; 956661dbeb9SHariprasad Shenai }; 957661dbeb9SHariprasad Shenai 9588b4e6b3cSArjun Vynipadath enum { 9598b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 9608b4e6b3cSArjun Vynipadath }; 9618b4e6b3cSArjun Vynipadath 9628b4e6b3cSArjun Vynipadath struct hma_data { 9638b4e6b3cSArjun Vynipadath unsigned char flags; 9648b4e6b3cSArjun Vynipadath struct sg_table *sgt; 9658b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 9668b4e6b3cSArjun Vynipadath }; 9678b4e6b3cSArjun Vynipadath 9684055ae5eSHariprasad Shenai struct mbox_list { 9694055ae5eSHariprasad Shenai struct list_head list; 9704055ae5eSHariprasad Shenai }; 9714055ae5eSHariprasad Shenai 972e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 973b1871915SGanesh Goudar struct ch_thermal { 974b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 975b1871915SGanesh Goudar int trip_temp; 976b1871915SGanesh Goudar int trip_type; 977b1871915SGanesh Goudar }; 978b1871915SGanesh Goudar #endif 979b1871915SGanesh Goudar 98028b38705SRaju Rangoju struct mps_entries_ref { 98128b38705SRaju Rangoju struct list_head list; 98228b38705SRaju Rangoju u8 addr[ETH_ALEN]; 98328b38705SRaju Rangoju u8 mask[ETH_ALEN]; 98428b38705SRaju Rangoju u16 idx; 98528b38705SRaju Rangoju refcount_t refcnt; 98628b38705SRaju Rangoju }; 98728b38705SRaju Rangoju 988f7917c00SJeff Kirsher struct adapter { 989f7917c00SJeff Kirsher void __iomem *regs; 99022adfe0aSSantosh Rastapur void __iomem *bar2; 9910abfd152SHariprasad Shenai u32 t4_bar0; 992f7917c00SJeff Kirsher struct pci_dev *pdev; 993f7917c00SJeff Kirsher struct device *pdev_dev; 9940de72738SHariprasad Shenai const char *name; 9953069ee9bSVipul Pandya unsigned int mbox; 996b2612722SHariprasad Shenai unsigned int pf; 997f7917c00SJeff Kirsher unsigned int flags; 998e7b48a32SHariprasad Shenai unsigned int adap_idx; 9992422d9a3SSantosh Rastapur enum chip_type chip; 1000d5fbda61SArjun Vynipadath u32 eth_flags; 1001f7917c00SJeff Kirsher 1002f7917c00SJeff Kirsher int msg_enable; 1003846eac3fSGanesh Goudar __be16 vxlan_port; 1004846eac3fSGanesh Goudar u8 vxlan_port_cnt; 1005c746fc0eSGanesh Goudar __be16 geneve_port; 1006c746fc0eSGanesh Goudar u8 geneve_port_cnt; 1007f7917c00SJeff Kirsher 1008f7917c00SJeff Kirsher struct adapter_params params; 1009f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 1010f7917c00SJeff Kirsher unsigned int swintr; 1011f7917c00SJeff Kirsher 101276c3a552SRahul Lakkireddy /* MSI-X Info for NIC and OFLD queues */ 101376c3a552SRahul Lakkireddy struct msix_info *msix_info; 101476c3a552SRahul Lakkireddy struct msix_bmap msix_bmap; 1015f7917c00SJeff Kirsher 1016a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 1017f7917c00SJeff Kirsher struct sge sge; 1018f7917c00SJeff Kirsher 1019f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 1020f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 1021f7917c00SJeff Kirsher 1022661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 1023661dbeb9SHariprasad Shenai u8 num_vfs; 1024661dbeb9SHariprasad Shenai 1025793dad94SVipul Pandya u32 filter_mode; 1026636f9d37SVipul Pandya unsigned int l2t_start; 1027636f9d37SVipul Pandya unsigned int l2t_end; 1028f7917c00SJeff Kirsher struct l2t_data *l2t; 1029b5a02f50SAnish Bhatt unsigned int clipt_start; 1030b5a02f50SAnish Bhatt unsigned int clipt_end; 1031b5a02f50SAnish Bhatt struct clip_tbl *clipt; 1032846eac3fSGanesh Goudar unsigned int rawf_start; 1033846eac3fSGanesh Goudar unsigned int rawf_cnt; 10343bdb376eSKumar Sanghvi struct smt_data *smt; 10350fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 1036f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 103794cdb8bbSHariprasad Shenai unsigned int num_uld; 10380fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 1039f7917c00SJeff Kirsher struct list_head list_node; 104001bcca68SVipul Pandya struct list_head rcu_node; 1041fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 104228b38705SRaju Rangoju struct list_head mps_ref; 104328b38705SRaju Rangoju spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1044f7917c00SJeff Kirsher 10457714cb9eSVarun Prakash void *iscsi_ppm; 10467714cb9eSVarun Prakash 1047f7917c00SJeff Kirsher struct tid_info tids; 1048f7917c00SJeff Kirsher void **tid_release_head; 1049f7917c00SJeff Kirsher spinlock_t tid_release_lock; 105029aaee65SAnish Bhatt struct workqueue_struct *workq; 1051f7917c00SJeff Kirsher struct work_struct tid_release_task; 1052881806bcSVipul Pandya struct work_struct db_full_task; 1053881806bcSVipul Pandya struct work_struct db_drop_task; 10548b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 1055f7917c00SJeff Kirsher bool tid_release_task_busy; 1056f7917c00SJeff Kirsher 10574055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 10584055ae5eSHariprasad Shenai spinlock_t mbox_lock; 10594055ae5eSHariprasad Shenai struct mbox_list mlist; 10604055ae5eSHariprasad Shenai 10617f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 10627f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 10637f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 10647f080c3fSHariprasad Shenai 10650fbc81b3SHariprasad Shenai struct mutex uld_mutex; 10660fbc81b3SHariprasad Shenai 1067f7917c00SJeff Kirsher struct dentry *debugfs_root; 1068621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1069621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 10708e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 10718e3d04fdSHariprasad Shenai * used for all 4 filters. 10728e3d04fdSHariprasad Shenai */ 1073f7917c00SJeff Kirsher 1074a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1075a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1076a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1077a4569504SAtul Gupta /* ptp lock */ 1078a4569504SAtul Gupta spinlock_t ptp_lock; 1079f7917c00SJeff Kirsher spinlock_t stats_lock; 1080fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1081d8931847SRahul Lakkireddy 1082d8931847SRahul Lakkireddy /* TC u32 offload */ 1083d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1084ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 108562488e4bSKumar Sanghvi 108662488e4bSKumar Sanghvi /* TC flower offload */ 1087a081e115SCasey Leedom bool tc_flower_initialized; 108879e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 108979e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1090e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 109179e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1092ad75b7d3SRahul Lakkireddy 1093ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1094ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 10958b4e6b3cSArjun Vynipadath 10968b4e6b3cSArjun Vynipadath /* HMA */ 10978b4e6b3cSArjun Vynipadath struct hma_data hma; 1098e4709475SRaju Rangoju 1099e4709475SRaju Rangoju struct srq_data *srq; 11001dde532dSRahul Lakkireddy 11011dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 11021dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1103e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1104b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1105b1871915SGanesh Goudar #endif 1106b1396c2bSRahul Lakkireddy 1107b1396c2bSRahul Lakkireddy /* TC MQPRIO offload */ 1108b1396c2bSRahul Lakkireddy struct cxgb4_tc_mqprio *tc_mqprio; 11094ec4762dSRahul Lakkireddy 11104ec4762dSRahul Lakkireddy /* TC MATCHALL classifier offload */ 11114ec4762dSRahul Lakkireddy struct cxgb4_tc_matchall *tc_matchall; 1112f7917c00SJeff Kirsher }; 1113f7917c00SJeff Kirsher 1114b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1115b72a32daSRahul Lakkireddy * programmed with various parameters. 1116b72a32daSRahul Lakkireddy */ 1117b72a32daSRahul Lakkireddy struct ch_sched_params { 1118b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 1119b72a32daSRahul Lakkireddy union { 1120b72a32daSRahul Lakkireddy struct { 1121b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 1122b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 1123b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 1124b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 1125b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 1126b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 1127b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 1128b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 1129b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 1130b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 1131b72a32daSRahul Lakkireddy } params; 1132b72a32daSRahul Lakkireddy } u; 1133b72a32daSRahul Lakkireddy }; 1134b72a32daSRahul Lakkireddy 113510a2604eSRahul Lakkireddy enum { 113610a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 113710a2604eSRahul Lakkireddy }; 113810a2604eSRahul Lakkireddy 113910a2604eSRahul Lakkireddy enum { 114010a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 11414ec4762dSRahul Lakkireddy SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 114210a2604eSRahul Lakkireddy }; 114310a2604eSRahul Lakkireddy 114410a2604eSRahul Lakkireddy enum { 114510a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 11460e395b3cSRahul Lakkireddy SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 114710a2604eSRahul Lakkireddy }; 114810a2604eSRahul Lakkireddy 114910a2604eSRahul Lakkireddy enum { 115010a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 115110a2604eSRahul Lakkireddy }; 115210a2604eSRahul Lakkireddy 115310a2604eSRahul Lakkireddy enum { 115410a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 115510a2604eSRahul Lakkireddy }; 115610a2604eSRahul Lakkireddy 11576cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 11586cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 11596cede1f1SRahul Lakkireddy */ 11606cede1f1SRahul Lakkireddy struct ch_sched_queue { 11616cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 11626cede1f1SRahul Lakkireddy s8 class; /* class index */ 11636cede1f1SRahul Lakkireddy }; 11646cede1f1SRahul Lakkireddy 11650e395b3cSRahul Lakkireddy /* Support for "sched_flowc" command to allow one or more FLOWC 11660e395b3cSRahul Lakkireddy * to be bound to a TX Scheduling Class. 11670e395b3cSRahul Lakkireddy */ 11680e395b3cSRahul Lakkireddy struct ch_sched_flowc { 11690e395b3cSRahul Lakkireddy s32 tid; /* TID to bind */ 11700e395b3cSRahul Lakkireddy s8 class; /* class index */ 11710e395b3cSRahul Lakkireddy }; 11720e395b3cSRahul Lakkireddy 1173f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1174f2b7e78dSVipul Pandya */ 1175f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1176f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1177f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1178f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1179f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1180f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1181f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1182f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1183f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1184f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1185f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1186f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 118798f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1188f2b7e78dSVipul Pandya 1189f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1190f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1191f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1192f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1193f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1194f2b7e78dSVipul Pandya * matching rules are true. 1195f2b7e78dSVipul Pandya * 1196f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1197f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1198f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1199f2b7e78dSVipul Pandya * MPS match type) ... 1200f2b7e78dSVipul Pandya * 1201f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1202f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1203f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1204f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1205f2b7e78dSVipul Pandya */ 1206f2b7e78dSVipul Pandya struct ch_filter_tuple { 1207f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1208f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1209f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1210f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1211f2b7e78dSVipul Pandya * set of fields. 1212f2b7e78dSVipul Pandya */ 1213f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1214f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1215f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1216f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1217f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 121898f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1219f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1220f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1221f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1222f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1223f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1224f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1225f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1226f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1227f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1228f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 122998f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1230f2b7e78dSVipul Pandya 1231f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1232f2b7e78dSVipul Pandya * available for field rules. 1233f2b7e78dSVipul Pandya */ 1234f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1235f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1236f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1237f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1238f2b7e78dSVipul Pandya }; 1239f2b7e78dSVipul Pandya 1240f2b7e78dSVipul Pandya /* A filter ioctl command. 1241f2b7e78dSVipul Pandya */ 1242f2b7e78dSVipul Pandya struct ch_filter_specification { 1243f2b7e78dSVipul Pandya /* Administrative fields for filter. 1244f2b7e78dSVipul Pandya */ 1245f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1246f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1247f2b7e78dSVipul Pandya 1248f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1249f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1250f2b7e78dSVipul Pandya */ 1251f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 125212b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1253f2b7e78dSVipul Pandya 1254f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1255f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1256f2b7e78dSVipul Pandya * out as egress packets. 1257f2b7e78dSVipul Pandya */ 1258f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1259f2b7e78dSVipul Pandya 1260f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1261f2b7e78dSVipul Pandya 1262f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1263f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1264f2b7e78dSVipul Pandya 1265f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1266f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1267f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1268f2b7e78dSVipul Pandya 1269f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1270f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1271f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1272f2b7e78dSVipul Pandya */ 1273f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1274f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1275f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1276f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 12770ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1278f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1279f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1280f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1281f2b7e78dSVipul Pandya 12820ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 12830ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 12840ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 12850ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 12860ff90994SKumar Sanghvi 128741ec03e5SRahul Lakkireddy u32 tc_prio; /* TC's filter priority index */ 128841ec03e5SRahul Lakkireddy u64 tc_cookie; /* Unique cookie identifying TC rules */ 128941ec03e5SRahul Lakkireddy 12900ff90994SKumar Sanghvi /* reservation for future additions */ 129141ec03e5SRahul Lakkireddy u8 rsvd[12]; 12920ff90994SKumar Sanghvi 1293f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1294f2b7e78dSVipul Pandya */ 1295f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1296f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1297f2b7e78dSVipul Pandya }; 1298f2b7e78dSVipul Pandya 1299f2b7e78dSVipul Pandya enum { 1300f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1301f2b7e78dSVipul Pandya FILTER_DROP, 1302f2b7e78dSVipul Pandya FILTER_SWITCH 1303f2b7e78dSVipul Pandya }; 1304f2b7e78dSVipul Pandya 1305f2b7e78dSVipul Pandya enum { 1306f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1307f2b7e78dSVipul Pandya VLAN_REMOVE, 1308f2b7e78dSVipul Pandya VLAN_INSERT, 1309f2b7e78dSVipul Pandya VLAN_REWRITE 1310f2b7e78dSVipul Pandya }; 1311f2b7e78dSVipul Pandya 1312557ccbf9SKumar Sanghvi enum { 131312b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 131412b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 131512b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 131612b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 131712b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 131812b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 131912b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 132012b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1321557ccbf9SKumar Sanghvi }; 1322557ccbf9SKumar Sanghvi 1323d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1324d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1325d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1326d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1327d57fd6caSRahul Lakkireddy * where the filter table is large. 1328d57fd6caSRahul Lakkireddy */ 1329d57fd6caSRahul Lakkireddy struct filter_entry { 1330d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1331d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1332d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1333d57fd6caSRahul Lakkireddy 1334d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1335578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1336d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 13373bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1338578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1339578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1340d57fd6caSRahul Lakkireddy 1341d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1342d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1343d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1344d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1345d57fd6caSRahul Lakkireddy */ 1346d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1347d57fd6caSRahul Lakkireddy }; 1348d57fd6caSRahul Lakkireddy 1349a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1350a4cfd929SHariprasad Shenai { 1351a4cfd929SHariprasad Shenai return adap->params.offload; 1352a4cfd929SHariprasad Shenai } 1353a4cfd929SHariprasad Shenai 13545c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 13555c31254eSKumar Sanghvi { 13565c31254eSKumar Sanghvi return adap->params.hash_filter; 13575c31254eSKumar Sanghvi } 13585c31254eSKumar Sanghvi 135994cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 136094cdb8bbSHariprasad Shenai { 136194cdb8bbSHariprasad Shenai return adap->params.crypto; 136294cdb8bbSHariprasad Shenai } 136394cdb8bbSHariprasad Shenai 13640fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 13650fbc81b3SHariprasad Shenai { 13660fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 13670fbc81b3SHariprasad Shenai } 13680fbc81b3SHariprasad Shenai 1369ab0367eaSRahul Lakkireddy static inline int is_ethofld(const struct adapter *adap) 1370ab0367eaSRahul Lakkireddy { 1371ab0367eaSRahul Lakkireddy return adap->params.ethofld; 1372ab0367eaSRahul Lakkireddy } 1373ab0367eaSRahul Lakkireddy 1374f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1375f7917c00SJeff Kirsher { 1376f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1377f7917c00SJeff Kirsher } 1378f7917c00SJeff Kirsher 1379f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1380f7917c00SJeff Kirsher { 1381f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1382f7917c00SJeff Kirsher } 1383f7917c00SJeff Kirsher 1384f7917c00SJeff Kirsher #ifndef readq 1385f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1386f7917c00SJeff Kirsher { 1387f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1388f7917c00SJeff Kirsher } 1389f7917c00SJeff Kirsher 1390f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1391f7917c00SJeff Kirsher { 1392f7917c00SJeff Kirsher writel(val, addr); 1393f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1394f7917c00SJeff Kirsher } 1395f7917c00SJeff Kirsher #endif 1396f7917c00SJeff Kirsher 1397f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1398f7917c00SJeff Kirsher { 1399f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1400f7917c00SJeff Kirsher } 1401f7917c00SJeff Kirsher 1402f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1403f7917c00SJeff Kirsher { 1404f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1405f7917c00SJeff Kirsher } 1406f7917c00SJeff Kirsher 1407f7917c00SJeff Kirsher /** 1408098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1409098ef6c2SHariprasad Shenai * @adapter: the adapter 1410098ef6c2SHariprasad Shenai * @port_idx: the port index 1411098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1412098ef6c2SHariprasad Shenai * 1413098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1414098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1415098ef6c2SHariprasad Shenai */ 1416098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1417098ef6c2SHariprasad Shenai u8 hw_addr[]) 1418098ef6c2SHariprasad Shenai { 1419098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1420098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1421098ef6c2SHariprasad Shenai } 1422098ef6c2SHariprasad Shenai 1423098ef6c2SHariprasad Shenai /** 1424f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1425f7917c00SJeff Kirsher * @dev: the netdev 1426f7917c00SJeff Kirsher * 1427f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1428f7917c00SJeff Kirsher */ 1429f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1430f7917c00SJeff Kirsher { 1431f7917c00SJeff Kirsher return netdev_priv(dev); 1432f7917c00SJeff Kirsher } 1433f7917c00SJeff Kirsher 1434f7917c00SJeff Kirsher /** 1435f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1436f7917c00SJeff Kirsher * @adap: the adapter 1437f7917c00SJeff Kirsher * @idx: the port index 1438f7917c00SJeff Kirsher * 1439f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1440f7917c00SJeff Kirsher */ 1441f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1442f7917c00SJeff Kirsher { 1443f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1444f7917c00SJeff Kirsher } 1445f7917c00SJeff Kirsher 1446f7917c00SJeff Kirsher /** 1447f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1448f7917c00SJeff Kirsher * @dev: the netdev 1449f7917c00SJeff Kirsher * 1450f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1451f7917c00SJeff Kirsher */ 1452f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1453f7917c00SJeff Kirsher { 1454f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1455f7917c00SJeff Kirsher } 1456f7917c00SJeff Kirsher 1457812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1458812034f1SHariprasad Shenai * - bits 0..9: chip version 1459812034f1SHariprasad Shenai * - bits 10..15: chip revision 1460812034f1SHariprasad Shenai * - bits 16..23: register dump version 1461812034f1SHariprasad Shenai */ 1462812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1463812034f1SHariprasad Shenai { 1464812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1465812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1466812034f1SHariprasad Shenai } 1467812034f1SHariprasad Shenai 1468812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1469812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1470812034f1SHariprasad Shenai const struct sge_rspq *q) 1471812034f1SHariprasad Shenai { 1472812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1473812034f1SHariprasad Shenai 1474812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1475812034f1SHariprasad Shenai } 1476812034f1SHariprasad Shenai 1477812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1478812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1479812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1480812034f1SHariprasad Shenai 14818156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1482f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1483f7917c00SJeff Kirsher 1484f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 14855fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1486f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1487d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1488f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1489f7917c00SJeff Kirsher const struct pkt_gl *gl); 1490f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1491f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1492f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1493f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 14942337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 14952337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1496f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1497f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1498d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1499f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1500f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1501f7917c00SJeff Kirsher unsigned int cmplqid); 15020fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 15030fbc81b3SHariprasad Shenai unsigned int cmplqid); 1504ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1505ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1506ab677ff4SHariprasad Shenai unsigned int uld_type); 15072d0cb84dSRahul Lakkireddy int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 15082d0cb84dSRahul Lakkireddy struct net_device *dev, u32 iqid); 15092d0cb84dSRahul Lakkireddy void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1510f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 151152367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1512f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1513f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1514d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1515d429005fSVishal Kulkarni int maxreclaim); 1516812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1517812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1518d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 15193069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1520f7917c00SJeff Kirsher 1521f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1522f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1523f7917c00SJeff Kirsher 15249a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 15259a4da2cdSVipul Pandya { 15269a4da2cdSVipul Pandya return adap->params.bypass; 15279a4da2cdSVipul Pandya } 15289a4da2cdSVipul Pandya 15299a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 15309a4da2cdSVipul Pandya { 15319a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 15329a4da2cdSVipul Pandya switch (device) { 15339a4da2cdSVipul Pandya case 0x440b: 15349a4da2cdSVipul Pandya case 0x440c: 15359a4da2cdSVipul Pandya return 1; 15369a4da2cdSVipul Pandya default: 15379a4da2cdSVipul Pandya return 0; 15389a4da2cdSVipul Pandya } 15399a4da2cdSVipul Pandya } 15409a4da2cdSVipul Pandya 154101b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 154201b69614SHariprasad Shenai { 154301b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 154401b69614SHariprasad Shenai switch (device) { 154501b69614SHariprasad Shenai case 0x4409: 154601b69614SHariprasad Shenai case 0x4486: 154701b69614SHariprasad Shenai return 1; 154801b69614SHariprasad Shenai 154901b69614SHariprasad Shenai default: 155001b69614SHariprasad Shenai return 0; 155101b69614SHariprasad Shenai } 155201b69614SHariprasad Shenai } 155301b69614SHariprasad Shenai 1554f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1555f7917c00SJeff Kirsher { 1556f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1557f7917c00SJeff Kirsher } 1558f7917c00SJeff Kirsher 1559f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1560f7917c00SJeff Kirsher unsigned int us) 1561f7917c00SJeff Kirsher { 1562f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1563f7917c00SJeff Kirsher } 1564f7917c00SJeff Kirsher 156552367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 156652367a76SVipul Pandya unsigned int ticks) 156752367a76SVipul Pandya { 156852367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 156952367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 157052367a76SVipul Pandya adapter->params.vpd.cclk); 157152367a76SVipul Pandya } 157252367a76SVipul Pandya 157308c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 157408c4901bSRahul Lakkireddy unsigned int ticks) 157508c4901bSRahul Lakkireddy { 157608c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 157708c4901bSRahul Lakkireddy } 157808c4901bSRahul Lakkireddy 1579f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1580f7917c00SJeff Kirsher u32 val); 1581f7917c00SJeff Kirsher 158201b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 158301b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1584f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1585f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1586f7917c00SJeff Kirsher 158701b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 158801b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 158901b69614SHariprasad Shenai int timeout) 159001b69614SHariprasad Shenai { 159101b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 159201b69614SHariprasad Shenai timeout); 159301b69614SHariprasad Shenai } 159401b69614SHariprasad Shenai 1595f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1596f7917c00SJeff Kirsher int size, void *rpl) 1597f7917c00SJeff Kirsher { 1598f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1599f7917c00SJeff Kirsher } 1600f7917c00SJeff Kirsher 1601f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1602f7917c00SJeff Kirsher int size, void *rpl) 1603f7917c00SJeff Kirsher { 1604f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1605f7917c00SJeff Kirsher } 1606f7917c00SJeff Kirsher 1607fc08a01aSHariprasad Shenai /** 1608fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1609fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1610fc08a01aSHariprasad Shenai * 1611fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1612fc08a01aSHariprasad Shenai * (hash) address matching. 1613fc08a01aSHariprasad Shenai */ 1614fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1615fc08a01aSHariprasad Shenai { 1616fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1617fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1618fc08a01aSHariprasad Shenai 1619fc08a01aSHariprasad Shenai a ^= b; 1620fc08a01aSHariprasad Shenai a ^= (a >> 12); 1621fc08a01aSHariprasad Shenai a ^= (a >> 6); 1622fc08a01aSHariprasad Shenai return a & 0x3f; 1623fc08a01aSHariprasad Shenai } 1624fc08a01aSHariprasad Shenai 162594cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 162694cdb8bbSHariprasad Shenai unsigned int cnt); 162794cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 162894cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 162994cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 163094cdb8bbSHariprasad Shenai { 163194cdb8bbSHariprasad Shenai q->adap = adap; 163294cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 163394cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 163494cdb8bbSHariprasad Shenai q->size = size; 163594cdb8bbSHariprasad Shenai } 163694cdb8bbSHariprasad Shenai 1637f56ec676SArjun Vynipadath /** 1638f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1639f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1640f56ec676SArjun Vynipadath * 1641f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1642f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1643f56ec676SArjun Vynipadath */ 1644f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1645f56ec676SArjun Vynipadath { 1646f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1647f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1648f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1649f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1650f56ec676SArjun Vynipadath } 1651f56ec676SArjun Vynipadath 165213ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 165313ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 165413ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1655f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1656f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1657f2b7e78dSVipul Pandya unsigned int start_idx); 16580abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1659f2b7e78dSVipul Pandya 1660f2b7e78dSVipul Pandya struct fw_filter_wr; 1661f2b7e78dSVipul Pandya 1662f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1663f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1664f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1665f7917c00SJeff Kirsher 16668203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 16678156b0baSGanesh Goudar 16689f764898SVishal Kulkarni fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 16699f764898SVishal Kulkarni struct link_config *lc); 16708156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 16718156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 16729f764898SVishal Kulkarni u8 sleep_ok, int timeout); 16738156b0baSGanesh Goudar 16748156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 16758156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 16768156b0baSGanesh Goudar { 16778156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 16788156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 16798156b0baSGanesh Goudar } 16808156b0baSGanesh Goudar 16818156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 16828156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 16838156b0baSGanesh Goudar { 16848156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 16858156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 16868156b0baSGanesh Goudar } 16878156b0baSGanesh Goudar 1688f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1689fc5ab020SHariprasad Shenai 1690b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1691b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1692b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1693b562fc37SHariprasad Shenai 16941a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 16951a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 16961a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 16971a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 16981a4330cdSRahul Lakkireddy int dir); 1699fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1700fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1701fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1702f01aa633SHariprasad Shenai void *buf, int dir); 1703fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1704fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1705fc5ab020SHariprasad Shenai { 1706fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1707fc5ab020SHariprasad Shenai } 1708fc5ab020SHariprasad Shenai 1709812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1710812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1711812034f1SHariprasad Shenai 1712940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1713f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1714098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1715098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 17160eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 171749216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 171849216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1719f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 172001b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 172101b69614SHariprasad Shenai int win, spinlock_t *lock, 172201b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 172301b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 172401b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 172549216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 172622c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 172722c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1728acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1729636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1730a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 17314da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 173216e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 17330de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 173416e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1735ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1736760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1737760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1738760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1739760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 174016e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 174116e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 174216e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1743f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 17443be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1745e85c9a7aSHariprasad Shenai 1746e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1747b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1748e85c9a7aSHariprasad Shenai unsigned int qid, 1749e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 175066cf188eSHariprasad S int user, 1751e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1752e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1753e85c9a7aSHariprasad Shenai 1754dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1755dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1756ae469b68SHariprasad Shenai 1757ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1758e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 17595ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1760dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1761c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1762c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1763c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1764f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1765f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1766f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1767f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1768f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1769f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1770f7917c00SJeff Kirsher unsigned int flags); 1771c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1772c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1773688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 17745ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 17755ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 17765ccf9d04SRahul Lakkireddy bool sleep_ok); 1777688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 17785ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1779688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 17805ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 17815ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 17825ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1783688ea5feSHariprasad Shenai 1784193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1785193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1786b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1787b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1788e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1789e5f0e43bSHariprasad Shenai size_t n); 1790c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1791c778af7dSHariprasad Shenai size_t n); 1792f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1793f1ff24aaSHariprasad Shenai unsigned int *valp); 1794f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1795f1ff24aaSHariprasad Shenai const unsigned int *valp); 1796f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 179719689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 179819689609SHariprasad Shenai unsigned int *pif_req_wrptr, 179919689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 180026fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 180174b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 180272aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1803f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1804a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1805a4cfd929SHariprasad Shenai struct port_stats *stats, 1806a4cfd929SHariprasad Shenai struct port_stats *offset); 180765046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1808f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1809bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1810636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1811636f9d37SVipul Pandya unsigned int mask, unsigned int val); 18122d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 18135ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 18145ccf9d04SRahul Lakkireddy bool sleep_ok); 18155ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 18165ccf9d04SRahul Lakkireddy bool sleep_ok); 18175ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 18185ccf9d04SRahul Lakkireddy bool sleep_ok); 18195ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 18205ccf9d04SRahul Lakkireddy bool sleep_ok); 1821f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 18225ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1823a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 18245ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1825f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1826f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1827f7917c00SJeff Kirsher 1828797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1829797ff0f5SHariprasad Shenai 18307864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1831f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1832f2b7e78dSVipul Pandya 1833f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1834f7917c00SJeff Kirsher const u8 *addr); 1835f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1836f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1837f7917c00SJeff Kirsher 1838f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1839f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1840f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1841f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1842f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1843636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1844636f9d37SVipul Pandya unsigned int cache_line_size); 1845636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1846f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1847f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1848f7917c00SJeff Kirsher u32 *val); 18498f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 18508f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 18518f46d467SArjun Vynipadath u32 *val); 185201b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1853f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 18548f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 185501b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1856688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1857688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 185801b69614SHariprasad Shenai const u32 *val, int timeout); 185901b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 186001b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1861688848b1SAnish Bhatt const u32 *val); 1862f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1863f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1864f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1865f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1866f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1867f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1868f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 186902d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 18704f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 18714f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 18724f3a0fcfSHariprasad Shenai unsigned int viid); 1873f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1874f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1875f7917c00SJeff Kirsher bool sleep_ok); 1876846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1877846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1878846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 187998f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 188098f3697fSKumar Sanghvi bool sleep_ok); 188198f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 188298f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 188398f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 188498f3697fSKumar Sanghvi bool sleep_ok); 1885846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1886846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1887846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1888f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1889f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1890f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1891fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1892fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1893fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1894f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 189502d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 1896f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1897f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1898688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1899688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1900e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1901e2f4f4e9SArjun Vynipadath struct port_info *pi, 1902e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1903f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1904f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1905f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1906f7917c00SJeff Kirsher unsigned int nblinks); 1907f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1908f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1909f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1910f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1911ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1912ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1913ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1914f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1915f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1916f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1917f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1918f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1919f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1920f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1921f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1922f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1923736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1924d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1925d429005fSVishal Kulkarni u16 *dbqtimers); 192623853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 19272061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1928c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1929c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1930f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1931881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1932881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 19338e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 19348e3d04fdSHariprasad Shenai int filter_index, int enable); 19358e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 19368e3d04fdSHariprasad Shenai int filter_index, int *enabled); 19378caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 19388caa1e84SVipul Pandya u32 addr, u32 val); 193908c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 194008c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 194108c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 19429e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 19439e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 19449e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 19459e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1946b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1947b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1948b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 194968bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1950a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1951a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1952a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1953a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1954a3bfb617SHariprasad Shenai int hz, int ticks); 1955858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1956858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 19575ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 19585ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 19594359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 19604359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 19615ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 19625ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 19635ccf9d04SRahul Lakkireddy 19640fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 19650fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 19660fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 19670fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1968f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1969f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1970f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 197194cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1972ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1973ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1974b1396c2bSRahul Lakkireddy void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 1975b1396c2bSRahul Lakkireddy u32 ndesc); 19760e395b3cSRahul Lakkireddy int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 1977b1396c2bSRahul Lakkireddy void cxgb4_ethofld_restart(unsigned long data); 19784846d533SRahul Lakkireddy int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 19794846d533SRahul Lakkireddy const struct pkt_gl *si); 1980ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1981a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1982a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1983a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1984a6ec572bSAtul Gupta dma_addr_t *addr); 1985a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1986a6ec572bSAtul Gupta void *pos); 1987a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1988a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1989a6ec572bSAtul Gupta const dma_addr_t *addr); 1990a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 19919d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 19929d5fd927SGanesh Goudar u16 vlan); 1993ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 1994b1871915SGanesh Goudar 1995b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 1996b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 1997c9765074SNirranjan Kirubaharan int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 1998c9765074SNirranjan Kirubaharan cpumask_var_t *aff_mask, int idx); 1999c9765074SNirranjan Kirubaharan void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2000b1871915SGanesh Goudar 20012f0b9406SRaju Rangoju int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 20022f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 20032f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 20042f0b9406SRaju Rangoju 2005f9f329adSRaju Rangoju int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2006f9f329adSRaju Rangoju bool free, unsigned int naddr, 2007f9f329adSRaju Rangoju const u8 **addr, u16 *idx, 2008f9f329adSRaju Rangoju u64 *hash, bool sleep_ok); 2009f9f329adSRaju Rangoju int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2010f9f329adSRaju Rangoju unsigned int naddr, const u8 **addr, bool sleep_ok); 201128b38705SRaju Rangoju int cxgb4_init_mps_ref_entries(struct adapter *adap); 201228b38705SRaju Rangoju void cxgb4_free_mps_ref_entries(struct adapter *adap); 201328b38705SRaju Rangoju int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 201428b38705SRaju Rangoju const u8 *addr, const u8 *mask, 201528b38705SRaju Rangoju unsigned int vni, unsigned int vni_mask, 201628b38705SRaju Rangoju u8 dip_hit, u8 lookup_type, bool sleep_ok); 201728b38705SRaju Rangoju int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 201828b38705SRaju Rangoju int idx, bool sleep_ok); 20195fab5158SRaju Rangoju int cxgb4_free_raw_mac_filt(struct adapter *adap, 20205fab5158SRaju Rangoju unsigned int viid, 20215fab5158SRaju Rangoju const u8 *addr, 20225fab5158SRaju Rangoju const u8 *mask, 20235fab5158SRaju Rangoju unsigned int idx, 20245fab5158SRaju Rangoju u8 lookup_type, 20255fab5158SRaju Rangoju u8 port_id, 20265fab5158SRaju Rangoju bool sleep_ok); 20275fab5158SRaju Rangoju int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 20285fab5158SRaju Rangoju unsigned int viid, 20295fab5158SRaju Rangoju const u8 *addr, 20305fab5158SRaju Rangoju const u8 *mask, 20315fab5158SRaju Rangoju unsigned int idx, 20325fab5158SRaju Rangoju u8 lookup_type, 20335fab5158SRaju Rangoju u8 port_id, 20345fab5158SRaju Rangoju bool sleep_ok); 20352f0b9406SRaju Rangoju int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 20362f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 20372f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 203876c3a552SRahul Lakkireddy int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 203976c3a552SRahul Lakkireddy void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2040b1396c2bSRahul Lakkireddy int cxgb_open(struct net_device *dev); 2041b1396c2bSRahul Lakkireddy int cxgb_close(struct net_device *dev); 20422d0cb84dSRahul Lakkireddy void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 20432d0cb84dSRahul Lakkireddy void cxgb4_quiesce_rx(struct sge_rspq *q); 2044f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 2045