1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 52a4569504SAtul Gupta #include <linux/ptp_classify.h> 53f7917c00SJeff Kirsher #include <asm/io.h> 5427999805SHariprasad S #include "t4_chip_type.h" 55f7917c00SJeff Kirsher #include "cxgb4_uld.h" 56f7917c00SJeff Kirsher 573069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5894cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5994cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 603069ee9bSVipul Pandya 61f7917c00SJeff Kirsher enum { 62f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 63f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 64f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 65f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 66a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 67098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 68f7917c00SJeff Kirsher }; 69f7917c00SJeff Kirsher 70f7917c00SJeff Kirsher enum { 71812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 72812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 73812034f1SHariprasad Shenai }; 74812034f1SHariprasad Shenai 75812034f1SHariprasad Shenai enum { 76f7917c00SJeff Kirsher MEM_EDC0, 77f7917c00SJeff Kirsher MEM_EDC1, 782422d9a3SSantosh Rastapur MEM_MC, 792422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 802422d9a3SSantosh Rastapur MEM_MC1 81f7917c00SJeff Kirsher }; 82f7917c00SJeff Kirsher 833069ee9bSVipul Pandya enum { 843eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 853eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 863069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 873069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 882422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 893eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 903eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 910abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 920abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 933069ee9bSVipul Pandya }; 943069ee9bSVipul Pandya 95f7917c00SJeff Kirsher enum dev_master { 96f7917c00SJeff Kirsher MASTER_CANT, 97f7917c00SJeff Kirsher MASTER_MAY, 98f7917c00SJeff Kirsher MASTER_MUST 99f7917c00SJeff Kirsher }; 100f7917c00SJeff Kirsher 101f7917c00SJeff Kirsher enum dev_state { 102f7917c00SJeff Kirsher DEV_STATE_UNINIT, 103f7917c00SJeff Kirsher DEV_STATE_INIT, 104f7917c00SJeff Kirsher DEV_STATE_ERR 105f7917c00SJeff Kirsher }; 106f7917c00SJeff Kirsher 107c3168cabSGanesh Goudar enum cc_pause { 108f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 109f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 110f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 111f7917c00SJeff Kirsher }; 112f7917c00SJeff Kirsher 113c3168cabSGanesh Goudar enum cc_fec { 1143bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1153bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1163bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1173bb4858fSGanesh Goudar }; 1183bb4858fSGanesh Goudar 119f7917c00SJeff Kirsher struct port_stats { 120f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 121f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 122f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 123f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 124f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 125f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 126f7917c00SJeff Kirsher 127f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 128f7917c00SJeff Kirsher u64 tx_frames_65_127; 129f7917c00SJeff Kirsher u64 tx_frames_128_255; 130f7917c00SJeff Kirsher u64 tx_frames_256_511; 131f7917c00SJeff Kirsher u64 tx_frames_512_1023; 132f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 133f7917c00SJeff Kirsher u64 tx_frames_1519_max; 134f7917c00SJeff Kirsher 135f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 136f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 137f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 138f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 139f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 140f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 141f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 142f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 143f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 144f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 147f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 148f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 149f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 150f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 151f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 152f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 153f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 154f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 155f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 156f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 157f7917c00SJeff Kirsher 158f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 159f7917c00SJeff Kirsher u64 rx_frames_65_127; 160f7917c00SJeff Kirsher u64 rx_frames_128_255; 161f7917c00SJeff Kirsher u64 rx_frames_256_511; 162f7917c00SJeff Kirsher u64 rx_frames_512_1023; 163f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 164f7917c00SJeff Kirsher u64 rx_frames_1519_max; 165f7917c00SJeff Kirsher 166f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 167f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 168f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 169f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 170f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 171f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 172f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 173f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 174f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 175f7917c00SJeff Kirsher 176f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 177f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 178f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 179f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 180f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 181f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 182f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 183f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 184f7917c00SJeff Kirsher }; 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher struct lb_port_stats { 187f7917c00SJeff Kirsher u64 octets; 188f7917c00SJeff Kirsher u64 frames; 189f7917c00SJeff Kirsher u64 bcast_frames; 190f7917c00SJeff Kirsher u64 mcast_frames; 191f7917c00SJeff Kirsher u64 ucast_frames; 192f7917c00SJeff Kirsher u64 error_frames; 193f7917c00SJeff Kirsher 194f7917c00SJeff Kirsher u64 frames_64; 195f7917c00SJeff Kirsher u64 frames_65_127; 196f7917c00SJeff Kirsher u64 frames_128_255; 197f7917c00SJeff Kirsher u64 frames_256_511; 198f7917c00SJeff Kirsher u64 frames_512_1023; 199f7917c00SJeff Kirsher u64 frames_1024_1518; 200f7917c00SJeff Kirsher u64 frames_1519_max; 201f7917c00SJeff Kirsher 202f7917c00SJeff Kirsher u64 drop; 203f7917c00SJeff Kirsher 204f7917c00SJeff Kirsher u64 ovflow0; 205f7917c00SJeff Kirsher u64 ovflow1; 206f7917c00SJeff Kirsher u64 ovflow2; 207f7917c00SJeff Kirsher u64 ovflow3; 208f7917c00SJeff Kirsher u64 trunc0; 209f7917c00SJeff Kirsher u64 trunc1; 210f7917c00SJeff Kirsher u64 trunc2; 211f7917c00SJeff Kirsher u64 trunc3; 212f7917c00SJeff Kirsher }; 213f7917c00SJeff Kirsher 214f7917c00SJeff Kirsher struct tp_tcp_stats { 215a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 216a4cfd929SHariprasad Shenai u64 tcp_in_segs; 217a4cfd929SHariprasad Shenai u64 tcp_out_segs; 218a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 219a4cfd929SHariprasad Shenai }; 220a4cfd929SHariprasad Shenai 221a4cfd929SHariprasad Shenai struct tp_usm_stats { 222a4cfd929SHariprasad Shenai u32 frames; 223a4cfd929SHariprasad Shenai u32 drops; 224a4cfd929SHariprasad Shenai u64 octets; 225f7917c00SJeff Kirsher }; 226f7917c00SJeff Kirsher 227a6222975SHariprasad Shenai struct tp_fcoe_stats { 228a6222975SHariprasad Shenai u32 frames_ddp; 229a6222975SHariprasad Shenai u32 frames_drop; 230a6222975SHariprasad Shenai u64 octets_ddp; 231f7917c00SJeff Kirsher }; 232f7917c00SJeff Kirsher 233f7917c00SJeff Kirsher struct tp_err_stats { 234a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 235a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 236a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 237a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 238a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 239a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 240a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 241a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 242a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 243a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 244a4cfd929SHariprasad Shenai }; 245a4cfd929SHariprasad Shenai 246a6222975SHariprasad Shenai struct tp_cpl_stats { 247a6222975SHariprasad Shenai u32 req[4]; 248a6222975SHariprasad Shenai u32 rsp[4]; 249a6222975SHariprasad Shenai }; 250a6222975SHariprasad Shenai 251a4cfd929SHariprasad Shenai struct tp_rdma_stats { 252a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 253a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 254f7917c00SJeff Kirsher }; 255f7917c00SJeff Kirsher 256e85c9a7aSHariprasad Shenai struct sge_params { 257e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 258e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 259e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 260e85c9a7aSHariprasad Shenai }; 261e85c9a7aSHariprasad Shenai 262f7917c00SJeff Kirsher struct tp_params { 263f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2642d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 265dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 266dca4faebSVipul Pandya /* channel map */ 267636f9d37SVipul Pandya 268636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 269636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 270dcf7b6f5SKumar Sanghvi 271dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 272dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 273dcf7b6f5SKumar Sanghvi 2748eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2758eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2768eb9f2f9SArjun V */ 2778eb9f2f9SArjun V int rx_pkt_encap; 2788eb9f2f9SArjun V 279dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 280dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 281dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 282dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 283dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 284dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 285dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 286dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 287dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 288dcf7b6f5SKumar Sanghvi * present. 289dcf7b6f5SKumar Sanghvi */ 2900ba9a3b6SKumar Sanghvi int fcoe_shift; 291dcf7b6f5SKumar Sanghvi int port_shift; 2920ba9a3b6SKumar Sanghvi int vnic_shift; 2930ba9a3b6SKumar Sanghvi int vlan_shift; 2940ba9a3b6SKumar Sanghvi int tos_shift; 295dcf7b6f5SKumar Sanghvi int protocol_shift; 2960ba9a3b6SKumar Sanghvi int ethertype_shift; 2970ba9a3b6SKumar Sanghvi int macmatch_shift; 2980ba9a3b6SKumar Sanghvi int matchtype_shift; 2990ba9a3b6SKumar Sanghvi int frag_shift; 3000ba9a3b6SKumar Sanghvi 3010ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 302f7917c00SJeff Kirsher }; 303f7917c00SJeff Kirsher 304f7917c00SJeff Kirsher struct vpd_params { 305f7917c00SJeff Kirsher unsigned int cclk; 306f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 307f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 308f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 309a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 310098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 311f7917c00SJeff Kirsher }; 312f7917c00SJeff Kirsher 313f7917c00SJeff Kirsher struct pci_params { 314f7917c00SJeff Kirsher unsigned char speed; 315f7917c00SJeff Kirsher unsigned char width; 316f7917c00SJeff Kirsher }; 317f7917c00SJeff Kirsher 31849aa284fSHariprasad Shenai struct devlog_params { 31949aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 32049aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 32149aa284fSHariprasad Shenai u32 size; /* size of log */ 32249aa284fSHariprasad Shenai }; 32349aa284fSHariprasad Shenai 3243ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3253ccc6cf7SHariprasad Shenai struct arch_specific_params { 3263ccc6cf7SHariprasad Shenai u8 nchan; 32744588560SHariprasad Shenai u8 pm_stats_cnt; 3282216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3293ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3303ccc6cf7SHariprasad Shenai u16 vfcount; 3313ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3323ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3333ccc6cf7SHariprasad Shenai }; 3343ccc6cf7SHariprasad Shenai 335f7917c00SJeff Kirsher struct adapter_params { 336e85c9a7aSHariprasad Shenai struct sge_params sge; 337f7917c00SJeff Kirsher struct tp_params tp; 338f7917c00SJeff Kirsher struct vpd_params vpd; 339f7917c00SJeff Kirsher struct pci_params pci; 34049aa284fSHariprasad Shenai struct devlog_params devlog; 34149aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 342f7917c00SJeff Kirsher 343f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 344f1ff24aaSHariprasad Shenai 345f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 346f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 347f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 348f7917c00SJeff Kirsher 349760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3500de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 351760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3520de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 353760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 354760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 355f7917c00SJeff Kirsher u8 api_vers[7]; 356f7917c00SJeff Kirsher 357f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 358f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 359f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 360f7917c00SJeff Kirsher 361f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 362f7917c00SJeff Kirsher unsigned char portvec; 363d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3643ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 365f7917c00SJeff Kirsher unsigned char offload; 36694cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 367f7917c00SJeff Kirsher 3689a4da2cdSVipul Pandya unsigned char bypass; 3699a4da2cdSVipul Pandya 370f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3711ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3724c2c5763SHariprasad Shenai 373b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3744c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3754c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 376086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 377c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 3780ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 3798f46d467SArjun Vynipadath 3808f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 3818f46d467SArjun Vynipadath * used by the Port 3828f46d467SArjun Vynipadath */ 3838f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 384f7917c00SJeff Kirsher }; 385f7917c00SJeff Kirsher 386a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 387a3bfb617SHariprasad Shenai * and possible hangs. 388a3bfb617SHariprasad Shenai */ 389a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 390a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 391a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 392a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 393a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 394a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 395a3bfb617SHariprasad Shenai }; 396a3bfb617SHariprasad Shenai 3977f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 3987f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 3997f080c3fSHariprasad Shenai * error returns. 4007f080c3fSHariprasad Shenai */ 4017f080c3fSHariprasad Shenai struct mbox_cmd { 4027f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4037f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4047f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4057f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4067f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4077f080c3fSHariprasad Shenai }; 4087f080c3fSHariprasad Shenai 4097f080c3fSHariprasad Shenai struct mbox_cmd_log { 4107f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4117f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4127f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4137f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4147f080c3fSHariprasad Shenai }; 4157f080c3fSHariprasad Shenai 4167f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4177f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4187f080c3fSHariprasad Shenai */ 4197f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4207f080c3fSHariprasad Shenai unsigned int entry_idx) 4217f080c3fSHariprasad Shenai { 4227f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4237f080c3fSHariprasad Shenai } 4247f080c3fSHariprasad Shenai 42516e47624SHariprasad Shenai #include "t4fw_api.h" 42616e47624SHariprasad Shenai 42716e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 428b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 429b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 430b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 431b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 43216e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 43316e47624SHariprasad Shenai 43416e47624SHariprasad Shenai struct fw_info { 43516e47624SHariprasad Shenai u8 chip; 43616e47624SHariprasad Shenai char *fs_name; 43716e47624SHariprasad Shenai char *fw_mod_name; 43816e47624SHariprasad Shenai struct fw_hdr fw_hdr; 43916e47624SHariprasad Shenai }; 44016e47624SHariprasad Shenai 441f7917c00SJeff Kirsher struct trace_params { 442f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 443f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 444f7917c00SJeff Kirsher unsigned short snap_len; 445f7917c00SJeff Kirsher unsigned short min_len; 446f7917c00SJeff Kirsher unsigned char skip_ofst; 447f7917c00SJeff Kirsher unsigned char skip_len; 448f7917c00SJeff Kirsher unsigned char invert; 449f7917c00SJeff Kirsher unsigned char port; 450f7917c00SJeff Kirsher }; 451f7917c00SJeff Kirsher 452c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 453c3168cabSGanesh Goudar 454c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 455c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 456c3168cabSGanesh Goudar 457c3168cabSGanesh Goudar enum fw_caps { 458c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 459c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 460c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 461c3168cabSGanesh Goudar }; 462c3168cabSGanesh Goudar 463f7917c00SJeff Kirsher struct link_config { 464c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 465c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 466c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 467c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 468c3168cabSGanesh Goudar 469c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 470c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 471c3168cabSGanesh Goudar 472c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 473c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 474c3168cabSGanesh Goudar 475c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 476c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 477c3168cabSGanesh Goudar 478f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 479c3168cabSGanesh Goudar 480f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 481ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 482f7917c00SJeff Kirsher }; 483f7917c00SJeff Kirsher 484e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 485f7917c00SJeff Kirsher 486f7917c00SJeff Kirsher enum { 487f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 488f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 489f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 490f7917c00SJeff Kirsher }; 491f7917c00SJeff Kirsher 492f7917c00SJeff Kirsher enum { 493812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 494812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 495812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 496812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 497812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 498812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 499812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 500812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 501812034f1SHariprasad Shenai }; 502812034f1SHariprasad Shenai 503812034f1SHariprasad Shenai enum { 504cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 505cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5060fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 507f7917c00SJeff Kirsher }; 508f7917c00SJeff Kirsher 509f7917c00SJeff Kirsher struct adapter; 510f7917c00SJeff Kirsher struct sge_rspq; 511f7917c00SJeff Kirsher 512688848b1SAnish Bhatt #include "cxgb4_dcb.h" 513688848b1SAnish Bhatt 51476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 51576fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 51676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 51776fed8a9SVarun Prakash 518f7917c00SJeff Kirsher struct port_info { 519f7917c00SJeff Kirsher struct adapter *adapter; 520f7917c00SJeff Kirsher u16 viid; 521f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 522f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 523f7917c00SJeff Kirsher s8 mdio_addr; 52440e9de4bSHariprasad Shenai enum fw_port_type port_type; 525f7917c00SJeff Kirsher u8 mod_type; 526f7917c00SJeff Kirsher u8 port_id; 527f7917c00SJeff Kirsher u8 tx_chan; 528f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 529f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 530f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 531f7917c00SJeff Kirsher u8 rss_mode; 532f7917c00SJeff Kirsher struct link_config link_cfg; 533f7917c00SJeff Kirsher u16 *rss; 534a4cfd929SHariprasad Shenai struct port_stats stats_base; 535688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 536688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 537688848b1SAnish Bhatt #endif 53876fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 53976fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 54076fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5415e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5425e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 543a4569504SAtul Gupta bool ptp_enable; 544b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 545f7917c00SJeff Kirsher }; 546f7917c00SJeff Kirsher 547f7917c00SJeff Kirsher struct dentry; 548f7917c00SJeff Kirsher struct work_struct; 549f7917c00SJeff Kirsher 550f7917c00SJeff Kirsher enum { /* adapter flags */ 551f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 552144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 553144be3d9SGavin Shan USING_MSI = (1 << 2), 554144be3d9SGavin Shan USING_MSIX = (1 << 3), 555f7917c00SJeff Kirsher FW_OK = (1 << 4), 55613ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 55752367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 55852367a76SVipul Pandya MASTER_PF = (1 << 7), 55952367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 560b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 561e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 562f7917c00SJeff Kirsher }; 563f7917c00SJeff Kirsher 56494cdb8bbSHariprasad Shenai enum { 56594cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 56694cdb8bbSHariprasad Shenai }; 56794cdb8bbSHariprasad Shenai 568f7917c00SJeff Kirsher struct rx_sw_desc; 569f7917c00SJeff Kirsher 570f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 571f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 572f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 573f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 574f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 575f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 576f7917c00SJeff Kirsher unsigned long large_alloc_failed; 57770055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 57870055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 579f7917c00SJeff Kirsher unsigned long starving; 580f7917c00SJeff Kirsher /* RO fields */ 581f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 582f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 583f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 584f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 585f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 586df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 587df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 588f7917c00SJeff Kirsher }; 589f7917c00SJeff Kirsher 590f7917c00SJeff Kirsher /* A packet gather list */ 591f7917c00SJeff Kirsher struct pkt_gl { 5925e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 593e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 594f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 595f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 596f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 597f7917c00SJeff Kirsher }; 598f7917c00SJeff Kirsher 599f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 600f7917c00SJeff Kirsher const struct pkt_gl *gl); 6012337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6022337ba42SVarun Prakash /* LRO related declarations for ULD */ 6032337ba42SVarun Prakash struct t4_lro_mgr { 6042337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6052337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6062337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6072337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6082337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6092337ba42SVarun Prakash }; 610f7917c00SJeff Kirsher 611f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 612f7917c00SJeff Kirsher struct napi_struct napi; 613f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 614f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 615f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 616f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 617f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 618e553ec3fSHariprasad Shenai u8 adaptive_rx; 619f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 620f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 621f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 622f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 623f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 624f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 625f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 626f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 627df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 628df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 629f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 630f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 631f7917c00SJeff Kirsher struct adapter *adap; 632f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 633f7917c00SJeff Kirsher rspq_handler_t handler; 6342337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6352337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 636f7917c00SJeff Kirsher }; 637f7917c00SJeff Kirsher 638f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 639f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 640f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 641f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 642f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 643f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 644f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 645f7917c00SJeff Kirsher }; 646f7917c00SJeff Kirsher 647f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 648f7917c00SJeff Kirsher struct sge_rspq rspq; 649f7917c00SJeff Kirsher struct sge_fl fl; 650f7917c00SJeff Kirsher struct sge_eth_stats stats; 651f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 652f7917c00SJeff Kirsher 653f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 654f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 655f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 656f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 657f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 658f7917c00SJeff Kirsher }; 659f7917c00SJeff Kirsher 660f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 661f7917c00SJeff Kirsher struct sge_rspq rspq; 662f7917c00SJeff Kirsher struct sge_fl fl; 663f7917c00SJeff Kirsher struct sge_ofld_stats stats; 664f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 665f7917c00SJeff Kirsher 666f7917c00SJeff Kirsher struct tx_desc { 667f7917c00SJeff Kirsher __be64 flit[8]; 668f7917c00SJeff Kirsher }; 669f7917c00SJeff Kirsher 670f7917c00SJeff Kirsher struct tx_sw_desc; 671f7917c00SJeff Kirsher 672f7917c00SJeff Kirsher struct sge_txq { 673f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 674ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 675f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 676f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 677f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 678f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 679f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 680f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 681f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 682f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 683f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 684f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6853069ee9bSVipul Pandya spinlock_t db_lock; 6863069ee9bSVipul Pandya int db_disabled; 6873069ee9bSVipul Pandya unsigned short db_pidx; 68805eb2389SSteve Wise unsigned short db_pidx_inc; 689df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 690df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 691f7917c00SJeff Kirsher }; 692f7917c00SJeff Kirsher 693f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 694f7917c00SJeff Kirsher struct sge_txq q; 695f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 69610b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 69710b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 69810b00466SAnish Bhatt #endif 699f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 700f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 701f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 702f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 703f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 704f7917c00SJeff Kirsher 705ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 706f7917c00SJeff Kirsher struct sge_txq q; 707f7917c00SJeff Kirsher struct adapter *adap; 708f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 709f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 710126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 711f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 712f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 713f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 714f7917c00SJeff Kirsher 715f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 716f7917c00SJeff Kirsher struct sge_txq q; 717f7917c00SJeff Kirsher struct adapter *adap; 718f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 719f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 720f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 721f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 722f7917c00SJeff Kirsher 72394cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 72494cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 72594cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 72694cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 72794cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 72894cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 72994cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 73094cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 73194cdb8bbSHariprasad Shenai }; 73294cdb8bbSHariprasad Shenai 733ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 734ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 735ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 736ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 737ab677ff4SHariprasad Shenai }; 738ab677ff4SHariprasad Shenai 739f7917c00SJeff Kirsher struct sge { 740f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 741a4569504SAtul Gupta struct sge_eth_txq ptptxq; 742f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 743f7917c00SJeff Kirsher 744f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 745f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 74694cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 747ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 748f7917c00SJeff Kirsher 749f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 750f7917c00SJeff Kirsher spinlock_t intrq_lock; 751f7917c00SJeff Kirsher 752f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 753f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 754f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7550fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 75694cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 757f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 758f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 75952367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 76052367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 76152367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 76252367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 76352367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7640f4d201fSKumar Sanghvi 765a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 766f7917c00SJeff Kirsher unsigned int egr_start; 7674b8e27a8SHariprasad Shenai unsigned int egr_sz; 768f7917c00SJeff Kirsher unsigned int ingr_start; 7694b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7704b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7714b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7724b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7734b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7745b377d11SHariprasad Shenai unsigned long *blocked_fl; 775f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 776f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 777f7917c00SJeff Kirsher }; 778f7917c00SJeff Kirsher 779f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7800fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 781f7917c00SJeff Kirsher 782f7917c00SJeff Kirsher struct l2t_data; 783f7917c00SJeff Kirsher 7842422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7852422d9a3SSantosh Rastapur 7867d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7877d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7887d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7892422d9a3SSantosh Rastapur */ 7907d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7912422d9a3SSantosh Rastapur 7922422d9a3SSantosh Rastapur #endif 7932422d9a3SSantosh Rastapur 794a4cfd929SHariprasad Shenai struct doorbell_stats { 795a4cfd929SHariprasad Shenai u32 db_drop; 796a4cfd929SHariprasad Shenai u32 db_empty; 797a4cfd929SHariprasad Shenai u32 db_full; 798a4cfd929SHariprasad Shenai }; 799a4cfd929SHariprasad Shenai 800fc08a01aSHariprasad Shenai struct hash_mac_addr { 801fc08a01aSHariprasad Shenai struct list_head list; 802fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 803fc08a01aSHariprasad Shenai }; 804fc08a01aSHariprasad Shenai 80594cdb8bbSHariprasad Shenai struct uld_msix_bmap { 80694cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 80794cdb8bbSHariprasad Shenai unsigned int mapsize; 80894cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 80994cdb8bbSHariprasad Shenai }; 81094cdb8bbSHariprasad Shenai 81194cdb8bbSHariprasad Shenai struct uld_msix_info { 81294cdb8bbSHariprasad Shenai unsigned short vec; 81394cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8140fbc81b3SHariprasad Shenai unsigned int idx; 81594cdb8bbSHariprasad Shenai }; 81694cdb8bbSHariprasad Shenai 817661dbeb9SHariprasad Shenai struct vf_info { 818661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8198ea4fae9SGanesh Goudar unsigned int tx_rate; 820661dbeb9SHariprasad Shenai bool pf_set_mac; 821661dbeb9SHariprasad Shenai }; 822661dbeb9SHariprasad Shenai 8234055ae5eSHariprasad Shenai struct mbox_list { 8244055ae5eSHariprasad Shenai struct list_head list; 8254055ae5eSHariprasad Shenai }; 8264055ae5eSHariprasad Shenai 827f7917c00SJeff Kirsher struct adapter { 828f7917c00SJeff Kirsher void __iomem *regs; 82922adfe0aSSantosh Rastapur void __iomem *bar2; 8300abfd152SHariprasad Shenai u32 t4_bar0; 831f7917c00SJeff Kirsher struct pci_dev *pdev; 832f7917c00SJeff Kirsher struct device *pdev_dev; 8330de72738SHariprasad Shenai const char *name; 8343069ee9bSVipul Pandya unsigned int mbox; 835b2612722SHariprasad Shenai unsigned int pf; 836f7917c00SJeff Kirsher unsigned int flags; 837e7b48a32SHariprasad Shenai unsigned int adap_idx; 8382422d9a3SSantosh Rastapur enum chip_type chip; 839f7917c00SJeff Kirsher 840f7917c00SJeff Kirsher int msg_enable; 841f7917c00SJeff Kirsher 842f7917c00SJeff Kirsher struct adapter_params params; 843f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 844f7917c00SJeff Kirsher unsigned int swintr; 845f7917c00SJeff Kirsher 846f7917c00SJeff Kirsher struct { 847f7917c00SJeff Kirsher unsigned short vec; 848f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 849f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 85094cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 85194cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8520fbc81b3SHariprasad Shenai int msi_idx; 853f7917c00SJeff Kirsher 854a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 855f7917c00SJeff Kirsher struct sge sge; 856f7917c00SJeff Kirsher 857f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 858f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 859f7917c00SJeff Kirsher 860661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 861661dbeb9SHariprasad Shenai u8 num_vfs; 862661dbeb9SHariprasad Shenai 863793dad94SVipul Pandya u32 filter_mode; 864636f9d37SVipul Pandya unsigned int l2t_start; 865636f9d37SVipul Pandya unsigned int l2t_end; 866f7917c00SJeff Kirsher struct l2t_data *l2t; 867b5a02f50SAnish Bhatt unsigned int clipt_start; 868b5a02f50SAnish Bhatt unsigned int clipt_end; 869b5a02f50SAnish Bhatt struct clip_tbl *clipt; 8703bdb376eSKumar Sanghvi struct smt_data *smt; 8710fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 872f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 87394cdb8bbSHariprasad Shenai unsigned int num_uld; 8740fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 875f7917c00SJeff Kirsher struct list_head list_node; 87601bcca68SVipul Pandya struct list_head rcu_node; 877fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 878f7917c00SJeff Kirsher 8797714cb9eSVarun Prakash void *iscsi_ppm; 8807714cb9eSVarun Prakash 881f7917c00SJeff Kirsher struct tid_info tids; 882f7917c00SJeff Kirsher void **tid_release_head; 883f7917c00SJeff Kirsher spinlock_t tid_release_lock; 88429aaee65SAnish Bhatt struct workqueue_struct *workq; 885f7917c00SJeff Kirsher struct work_struct tid_release_task; 886881806bcSVipul Pandya struct work_struct db_full_task; 887881806bcSVipul Pandya struct work_struct db_drop_task; 888f7917c00SJeff Kirsher bool tid_release_task_busy; 889f7917c00SJeff Kirsher 8904055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 8914055ae5eSHariprasad Shenai spinlock_t mbox_lock; 8924055ae5eSHariprasad Shenai struct mbox_list mlist; 8934055ae5eSHariprasad Shenai 8947f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 8957f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 8967f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 8977f080c3fSHariprasad Shenai 8980fbc81b3SHariprasad Shenai struct mutex uld_mutex; 8990fbc81b3SHariprasad Shenai 900f7917c00SJeff Kirsher struct dentry *debugfs_root; 901621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 902621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 9038e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 9048e3d04fdSHariprasad Shenai * used for all 4 filters. 9058e3d04fdSHariprasad Shenai */ 906f7917c00SJeff Kirsher 907a4569504SAtul Gupta struct ptp_clock *ptp_clock; 908a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 909a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 910a4569504SAtul Gupta /* ptp lock */ 911a4569504SAtul Gupta spinlock_t ptp_lock; 912f7917c00SJeff Kirsher spinlock_t stats_lock; 913fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 914d8931847SRahul Lakkireddy 915d8931847SRahul Lakkireddy /* TC u32 offload */ 916d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 917ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 91862488e4bSKumar Sanghvi 91962488e4bSKumar Sanghvi /* TC flower offload */ 92062488e4bSKumar Sanghvi DECLARE_HASHTABLE(flower_anymatch_tbl, 9); 921e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 922ad75b7d3SRahul Lakkireddy 923ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 924ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 925f7917c00SJeff Kirsher }; 926f7917c00SJeff Kirsher 927b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 928b72a32daSRahul Lakkireddy * programmed with various parameters. 929b72a32daSRahul Lakkireddy */ 930b72a32daSRahul Lakkireddy struct ch_sched_params { 931b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 932b72a32daSRahul Lakkireddy union { 933b72a32daSRahul Lakkireddy struct { 934b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 935b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 936b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 937b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 938b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 939b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 940b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 941b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 942b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 943b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 944b72a32daSRahul Lakkireddy } params; 945b72a32daSRahul Lakkireddy } u; 946b72a32daSRahul Lakkireddy }; 947b72a32daSRahul Lakkireddy 94810a2604eSRahul Lakkireddy enum { 94910a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 95010a2604eSRahul Lakkireddy }; 95110a2604eSRahul Lakkireddy 95210a2604eSRahul Lakkireddy enum { 95310a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 95410a2604eSRahul Lakkireddy }; 95510a2604eSRahul Lakkireddy 95610a2604eSRahul Lakkireddy enum { 95710a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 95810a2604eSRahul Lakkireddy }; 95910a2604eSRahul Lakkireddy 96010a2604eSRahul Lakkireddy enum { 96110a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 96210a2604eSRahul Lakkireddy }; 96310a2604eSRahul Lakkireddy 96410a2604eSRahul Lakkireddy enum { 96510a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 96610a2604eSRahul Lakkireddy }; 96710a2604eSRahul Lakkireddy 9686cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 9696cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 9706cede1f1SRahul Lakkireddy */ 9716cede1f1SRahul Lakkireddy struct ch_sched_queue { 9726cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 9736cede1f1SRahul Lakkireddy s8 class; /* class index */ 9746cede1f1SRahul Lakkireddy }; 9756cede1f1SRahul Lakkireddy 976f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 977f2b7e78dSVipul Pandya */ 978f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 979f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 980f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 981f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 982f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 983f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 984f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 985f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 986f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 987f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 988f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 989f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 990f2b7e78dSVipul Pandya 991f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 992f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 993f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 994f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 995f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 996f2b7e78dSVipul Pandya * matching rules are true. 997f2b7e78dSVipul Pandya * 998f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 999f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1000f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1001f2b7e78dSVipul Pandya * MPS match type) ... 1002f2b7e78dSVipul Pandya * 1003f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1004f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1005f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1006f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1007f2b7e78dSVipul Pandya */ 1008f2b7e78dSVipul Pandya struct ch_filter_tuple { 1009f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1010f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1011f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1012f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1013f2b7e78dSVipul Pandya * set of fields. 1014f2b7e78dSVipul Pandya */ 1015f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1016f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1017f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1018f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1019f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 1020f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1021f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1022f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1023f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1024f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1025f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1026f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1027f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1028f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1029f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1030f2b7e78dSVipul Pandya 1031f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1032f2b7e78dSVipul Pandya * available for field rules. 1033f2b7e78dSVipul Pandya */ 1034f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1035f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1036f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1037f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1038f2b7e78dSVipul Pandya }; 1039f2b7e78dSVipul Pandya 1040f2b7e78dSVipul Pandya /* A filter ioctl command. 1041f2b7e78dSVipul Pandya */ 1042f2b7e78dSVipul Pandya struct ch_filter_specification { 1043f2b7e78dSVipul Pandya /* Administrative fields for filter. 1044f2b7e78dSVipul Pandya */ 1045f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1046f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1047f2b7e78dSVipul Pandya 1048f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1049f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1050f2b7e78dSVipul Pandya */ 1051f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1052f2b7e78dSVipul Pandya 1053f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1054f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1055f2b7e78dSVipul Pandya * out as egress packets. 1056f2b7e78dSVipul Pandya */ 1057f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1058f2b7e78dSVipul Pandya 1059f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1060f2b7e78dSVipul Pandya 1061f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1062f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1063f2b7e78dSVipul Pandya 1064f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1065f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1066f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1067f2b7e78dSVipul Pandya 1068f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1069f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1070f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1071f2b7e78dSVipul Pandya */ 1072f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1073f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1074f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1075f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 10760ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1077f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1078f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1079f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1080f2b7e78dSVipul Pandya 10810ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 10820ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 10830ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 10840ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 10850ff90994SKumar Sanghvi 10860ff90994SKumar Sanghvi /* reservation for future additions */ 10870ff90994SKumar Sanghvi u8 rsvd[24]; 10880ff90994SKumar Sanghvi 1089f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1090f2b7e78dSVipul Pandya */ 1091f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1092f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1093f2b7e78dSVipul Pandya }; 1094f2b7e78dSVipul Pandya 1095f2b7e78dSVipul Pandya enum { 1096f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1097f2b7e78dSVipul Pandya FILTER_DROP, 1098f2b7e78dSVipul Pandya FILTER_SWITCH 1099f2b7e78dSVipul Pandya }; 1100f2b7e78dSVipul Pandya 1101f2b7e78dSVipul Pandya enum { 1102f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1103f2b7e78dSVipul Pandya VLAN_REMOVE, 1104f2b7e78dSVipul Pandya VLAN_INSERT, 1105f2b7e78dSVipul Pandya VLAN_REWRITE 1106f2b7e78dSVipul Pandya }; 1107f2b7e78dSVipul Pandya 1108557ccbf9SKumar Sanghvi enum { 1109557ccbf9SKumar Sanghvi NAT_MODE_ALL = 7, /* NAT on entire 4-tuple */ 1110557ccbf9SKumar Sanghvi }; 1111557ccbf9SKumar Sanghvi 1112d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1113d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1114d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1115d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1116d57fd6caSRahul Lakkireddy * where the filter table is large. 1117d57fd6caSRahul Lakkireddy */ 1118d57fd6caSRahul Lakkireddy struct filter_entry { 1119d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1120d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1121d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1122d57fd6caSRahul Lakkireddy 1123d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1124578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1125d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 11263bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1127578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1128578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1129d57fd6caSRahul Lakkireddy 1130d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1131d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1132d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1133d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1134d57fd6caSRahul Lakkireddy */ 1135d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1136d57fd6caSRahul Lakkireddy }; 1137d57fd6caSRahul Lakkireddy 1138a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1139a4cfd929SHariprasad Shenai { 1140a4cfd929SHariprasad Shenai return adap->params.offload; 1141a4cfd929SHariprasad Shenai } 1142a4cfd929SHariprasad Shenai 114394cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 114494cdb8bbSHariprasad Shenai { 114594cdb8bbSHariprasad Shenai return adap->params.crypto; 114694cdb8bbSHariprasad Shenai } 114794cdb8bbSHariprasad Shenai 11480fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 11490fbc81b3SHariprasad Shenai { 11500fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 11510fbc81b3SHariprasad Shenai } 11520fbc81b3SHariprasad Shenai 1153f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1154f7917c00SJeff Kirsher { 1155f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1156f7917c00SJeff Kirsher } 1157f7917c00SJeff Kirsher 1158f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1159f7917c00SJeff Kirsher { 1160f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1161f7917c00SJeff Kirsher } 1162f7917c00SJeff Kirsher 1163f7917c00SJeff Kirsher #ifndef readq 1164f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1165f7917c00SJeff Kirsher { 1166f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1167f7917c00SJeff Kirsher } 1168f7917c00SJeff Kirsher 1169f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1170f7917c00SJeff Kirsher { 1171f7917c00SJeff Kirsher writel(val, addr); 1172f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1173f7917c00SJeff Kirsher } 1174f7917c00SJeff Kirsher #endif 1175f7917c00SJeff Kirsher 1176f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1177f7917c00SJeff Kirsher { 1178f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1179f7917c00SJeff Kirsher } 1180f7917c00SJeff Kirsher 1181f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1182f7917c00SJeff Kirsher { 1183f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1184f7917c00SJeff Kirsher } 1185f7917c00SJeff Kirsher 1186f7917c00SJeff Kirsher /** 1187098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1188098ef6c2SHariprasad Shenai * @adapter: the adapter 1189098ef6c2SHariprasad Shenai * @port_idx: the port index 1190098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1191098ef6c2SHariprasad Shenai * 1192098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1193098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1194098ef6c2SHariprasad Shenai */ 1195098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1196098ef6c2SHariprasad Shenai u8 hw_addr[]) 1197098ef6c2SHariprasad Shenai { 1198098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1199098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1200098ef6c2SHariprasad Shenai } 1201098ef6c2SHariprasad Shenai 1202098ef6c2SHariprasad Shenai /** 1203f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1204f7917c00SJeff Kirsher * @dev: the netdev 1205f7917c00SJeff Kirsher * 1206f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1207f7917c00SJeff Kirsher */ 1208f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1209f7917c00SJeff Kirsher { 1210f7917c00SJeff Kirsher return netdev_priv(dev); 1211f7917c00SJeff Kirsher } 1212f7917c00SJeff Kirsher 1213f7917c00SJeff Kirsher /** 1214f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1215f7917c00SJeff Kirsher * @adap: the adapter 1216f7917c00SJeff Kirsher * @idx: the port index 1217f7917c00SJeff Kirsher * 1218f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1219f7917c00SJeff Kirsher */ 1220f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1221f7917c00SJeff Kirsher { 1222f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1223f7917c00SJeff Kirsher } 1224f7917c00SJeff Kirsher 1225f7917c00SJeff Kirsher /** 1226f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1227f7917c00SJeff Kirsher * @dev: the netdev 1228f7917c00SJeff Kirsher * 1229f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1230f7917c00SJeff Kirsher */ 1231f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1232f7917c00SJeff Kirsher { 1233f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1234f7917c00SJeff Kirsher } 1235f7917c00SJeff Kirsher 1236812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1237812034f1SHariprasad Shenai * - bits 0..9: chip version 1238812034f1SHariprasad Shenai * - bits 10..15: chip revision 1239812034f1SHariprasad Shenai * - bits 16..23: register dump version 1240812034f1SHariprasad Shenai */ 1241812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1242812034f1SHariprasad Shenai { 1243812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1244812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1245812034f1SHariprasad Shenai } 1246812034f1SHariprasad Shenai 1247812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1248812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1249812034f1SHariprasad Shenai const struct sge_rspq *q) 1250812034f1SHariprasad Shenai { 1251812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1252812034f1SHariprasad Shenai 1253812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1254812034f1SHariprasad Shenai } 1255812034f1SHariprasad Shenai 1256812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1257812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1258812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1259812034f1SHariprasad Shenai 1260f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1261f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1262f7917c00SJeff Kirsher 1263f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 12645fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1265f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1266f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1267f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1268f7917c00SJeff Kirsher const struct pkt_gl *gl); 1269f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1270f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1271f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1272f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 12732337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 12742337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1275f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1276f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1277f7917c00SJeff Kirsher unsigned int iqid); 1278f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1279f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1280f7917c00SJeff Kirsher unsigned int cmplqid); 12810fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 12820fbc81b3SHariprasad Shenai unsigned int cmplqid); 1283ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1284ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1285ab677ff4SHariprasad Shenai unsigned int uld_type); 1286f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 128752367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1288f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1289f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1290812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1291812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 12923069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1293f7917c00SJeff Kirsher 1294f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1295f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1296f7917c00SJeff Kirsher 12979a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 12989a4da2cdSVipul Pandya { 12999a4da2cdSVipul Pandya return adap->params.bypass; 13009a4da2cdSVipul Pandya } 13019a4da2cdSVipul Pandya 13029a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 13039a4da2cdSVipul Pandya { 13049a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 13059a4da2cdSVipul Pandya switch (device) { 13069a4da2cdSVipul Pandya case 0x440b: 13079a4da2cdSVipul Pandya case 0x440c: 13089a4da2cdSVipul Pandya return 1; 13099a4da2cdSVipul Pandya default: 13109a4da2cdSVipul Pandya return 0; 13119a4da2cdSVipul Pandya } 13129a4da2cdSVipul Pandya } 13139a4da2cdSVipul Pandya 131401b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 131501b69614SHariprasad Shenai { 131601b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 131701b69614SHariprasad Shenai switch (device) { 131801b69614SHariprasad Shenai case 0x4409: 131901b69614SHariprasad Shenai case 0x4486: 132001b69614SHariprasad Shenai return 1; 132101b69614SHariprasad Shenai 132201b69614SHariprasad Shenai default: 132301b69614SHariprasad Shenai return 0; 132401b69614SHariprasad Shenai } 132501b69614SHariprasad Shenai } 132601b69614SHariprasad Shenai 1327f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1328f7917c00SJeff Kirsher { 1329f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1330f7917c00SJeff Kirsher } 1331f7917c00SJeff Kirsher 1332f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1333f7917c00SJeff Kirsher unsigned int us) 1334f7917c00SJeff Kirsher { 1335f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1336f7917c00SJeff Kirsher } 1337f7917c00SJeff Kirsher 133852367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 133952367a76SVipul Pandya unsigned int ticks) 134052367a76SVipul Pandya { 134152367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 134252367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 134352367a76SVipul Pandya adapter->params.vpd.cclk); 134452367a76SVipul Pandya } 134552367a76SVipul Pandya 134608c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 134708c4901bSRahul Lakkireddy unsigned int ticks) 134808c4901bSRahul Lakkireddy { 134908c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 135008c4901bSRahul Lakkireddy } 135108c4901bSRahul Lakkireddy 1352f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1353f7917c00SJeff Kirsher u32 val); 1354f7917c00SJeff Kirsher 135501b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 135601b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1357f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1358f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1359f7917c00SJeff Kirsher 136001b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 136101b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 136201b69614SHariprasad Shenai int timeout) 136301b69614SHariprasad Shenai { 136401b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 136501b69614SHariprasad Shenai timeout); 136601b69614SHariprasad Shenai } 136701b69614SHariprasad Shenai 1368f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1369f7917c00SJeff Kirsher int size, void *rpl) 1370f7917c00SJeff Kirsher { 1371f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1372f7917c00SJeff Kirsher } 1373f7917c00SJeff Kirsher 1374f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1375f7917c00SJeff Kirsher int size, void *rpl) 1376f7917c00SJeff Kirsher { 1377f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1378f7917c00SJeff Kirsher } 1379f7917c00SJeff Kirsher 1380fc08a01aSHariprasad Shenai /** 1381fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1382fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1383fc08a01aSHariprasad Shenai * 1384fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1385fc08a01aSHariprasad Shenai * (hash) address matching. 1386fc08a01aSHariprasad Shenai */ 1387fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1388fc08a01aSHariprasad Shenai { 1389fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1390fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1391fc08a01aSHariprasad Shenai 1392fc08a01aSHariprasad Shenai a ^= b; 1393fc08a01aSHariprasad Shenai a ^= (a >> 12); 1394fc08a01aSHariprasad Shenai a ^= (a >> 6); 1395fc08a01aSHariprasad Shenai return a & 0x3f; 1396fc08a01aSHariprasad Shenai } 1397fc08a01aSHariprasad Shenai 139894cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 139994cdb8bbSHariprasad Shenai unsigned int cnt); 140094cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 140194cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 140294cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 140394cdb8bbSHariprasad Shenai { 140494cdb8bbSHariprasad Shenai q->adap = adap; 140594cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 140694cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 140794cdb8bbSHariprasad Shenai q->size = size; 140894cdb8bbSHariprasad Shenai } 140994cdb8bbSHariprasad Shenai 141013ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 141113ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 141213ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1413f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1414f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1415f2b7e78dSVipul Pandya unsigned int start_idx); 14160abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1417f2b7e78dSVipul Pandya 1418f2b7e78dSVipul Pandya struct fw_filter_wr; 1419f2b7e78dSVipul Pandya 1420f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1421f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1422f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1423f7917c00SJeff Kirsher 14248203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 14254036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1426f7917c00SJeff Kirsher struct link_config *lc); 1427f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1428fc5ab020SHariprasad Shenai 1429b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1430b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1431b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1432b562fc37SHariprasad Shenai 1433fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1434fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1435fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1436f01aa633SHariprasad Shenai void *buf, int dir); 1437fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1438fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1439fc5ab020SHariprasad Shenai { 1440fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1441fc5ab020SHariprasad Shenai } 1442fc5ab020SHariprasad Shenai 1443812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1444812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1445812034f1SHariprasad Shenai 1446f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1447098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1448098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 144949216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 145049216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1451f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 145201b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 145301b69614SHariprasad Shenai int win, spinlock_t *lock, 145401b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 145501b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 145601b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 145749216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 145822c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 145922c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1460acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1461636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1462a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 14634da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 146416e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 14650de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 146616e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1467ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1468760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1469760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1470760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1471760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 147216e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 147316e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 147416e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1475f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 14763be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1477e85c9a7aSHariprasad Shenai 1478e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1479b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1480e85c9a7aSHariprasad Shenai unsigned int qid, 1481e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 148266cf188eSHariprasad S int user, 1483e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1484e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1485e85c9a7aSHariprasad Shenai 1486dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1487dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1488ae469b68SHariprasad Shenai 1489ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1490e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 14915ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1492dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1493c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1494c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1495c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1496f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1497f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1498f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1499f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1500f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1501f7917c00SJeff Kirsher unsigned int flags); 1502c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1503c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1504688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 15055ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 15065ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 15075ccf9d04SRahul Lakkireddy bool sleep_ok); 1508688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 15095ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1510688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 15115ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 15125ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 15135ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1514688ea5feSHariprasad Shenai 1515193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1516193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1517b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1518b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1519e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1520e5f0e43bSHariprasad Shenai size_t n); 1521c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1522c778af7dSHariprasad Shenai size_t n); 1523f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1524f1ff24aaSHariprasad Shenai unsigned int *valp); 1525f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1526f1ff24aaSHariprasad Shenai const unsigned int *valp); 1527f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 152819689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 152919689609SHariprasad Shenai unsigned int *pif_req_wrptr, 153019689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 153126fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 153274b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 153372aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1534f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1535a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1536a4cfd929SHariprasad Shenai struct port_stats *stats, 1537a4cfd929SHariprasad Shenai struct port_stats *offset); 153865046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1539f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1540bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1541636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1542636f9d37SVipul Pandya unsigned int mask, unsigned int val); 15432d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 15445ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 15455ccf9d04SRahul Lakkireddy bool sleep_ok); 15465ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 15475ccf9d04SRahul Lakkireddy bool sleep_ok); 15485ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 15495ccf9d04SRahul Lakkireddy bool sleep_ok); 15505ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 15515ccf9d04SRahul Lakkireddy bool sleep_ok); 1552f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 15535ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1554a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 15555ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1556f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1557f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1558f7917c00SJeff Kirsher 1559797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1560797ff0f5SHariprasad Shenai 15617864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1562f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1563f2b7e78dSVipul Pandya 1564f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1565f7917c00SJeff Kirsher const u8 *addr); 1566f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1567f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1568f7917c00SJeff Kirsher 1569f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1570f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1571f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1572f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1573f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1574636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1575636f9d37SVipul Pandya unsigned int cache_line_size); 1576636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1577f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1578f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1579f7917c00SJeff Kirsher u32 *val); 15808f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 15818f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 15828f46d467SArjun Vynipadath u32 *val); 158301b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1584f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 15858f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 158601b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1587688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1588688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 158901b69614SHariprasad Shenai const u32 *val, int timeout); 159001b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 159101b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1592688848b1SAnish Bhatt const u32 *val); 1593f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1594f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1595f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1596f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1597f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1598f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1599f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1600f7917c00SJeff Kirsher unsigned int *rss_size); 16014f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 16024f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 16034f3a0fcfSHariprasad Shenai unsigned int viid); 1604f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1605f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1606f7917c00SJeff Kirsher bool sleep_ok); 1607f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1608f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1609f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1610fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1611fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1612fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1613f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1614f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1615f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1616f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1617688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1618688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1619f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1620f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1621f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1622f7917c00SJeff Kirsher unsigned int nblinks); 1623f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1624f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1625f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1626f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1627ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1628ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1629ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1630f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1631f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1632f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1633f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1634f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1635f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1636f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1637f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1638f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 16395d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 164023853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 16412061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1642c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1643c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1644f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1645881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1646881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 16478e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 16488e3d04fdSHariprasad Shenai int filter_index, int enable); 16498e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 16508e3d04fdSHariprasad Shenai int filter_index, int *enabled); 16518caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 16528caa1e84SVipul Pandya u32 addr, u32 val); 165308c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 165408c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 165508c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1656b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1657b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1658b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 165968bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1660a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1661a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1662a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1663a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1664a3bfb617SHariprasad Shenai int hz, int ticks); 1665858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1666858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 16675ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 16685ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 16694359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 16704359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 16715ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 16725ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 16735ccf9d04SRahul Lakkireddy 16740fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 16750fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 16760fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 16770fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 167894cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1679ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1680ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1681ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1682f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1683