1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 50f7917c00SJeff Kirsher #include <asm/io.h> 51f7917c00SJeff Kirsher #include "cxgb4_uld.h" 52f7917c00SJeff Kirsher 533069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 543069ee9bSVipul Pandya 55f7917c00SJeff Kirsher enum { 56f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 57f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 58f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 59f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 60a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 61098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 62f7917c00SJeff Kirsher }; 63f7917c00SJeff Kirsher 64f7917c00SJeff Kirsher enum { 65812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 66812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 67812034f1SHariprasad Shenai }; 68812034f1SHariprasad Shenai 69812034f1SHariprasad Shenai enum { 70f7917c00SJeff Kirsher MEM_EDC0, 71f7917c00SJeff Kirsher MEM_EDC1, 722422d9a3SSantosh Rastapur MEM_MC, 732422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 742422d9a3SSantosh Rastapur MEM_MC1 75f7917c00SJeff Kirsher }; 76f7917c00SJeff Kirsher 773069ee9bSVipul Pandya enum { 783eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 793eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 803069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 813069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 822422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 833eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 843eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 850abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 860abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 873069ee9bSVipul Pandya }; 883069ee9bSVipul Pandya 89f7917c00SJeff Kirsher enum dev_master { 90f7917c00SJeff Kirsher MASTER_CANT, 91f7917c00SJeff Kirsher MASTER_MAY, 92f7917c00SJeff Kirsher MASTER_MUST 93f7917c00SJeff Kirsher }; 94f7917c00SJeff Kirsher 95f7917c00SJeff Kirsher enum dev_state { 96f7917c00SJeff Kirsher DEV_STATE_UNINIT, 97f7917c00SJeff Kirsher DEV_STATE_INIT, 98f7917c00SJeff Kirsher DEV_STATE_ERR 99f7917c00SJeff Kirsher }; 100f7917c00SJeff Kirsher 101f7917c00SJeff Kirsher enum { 102f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 103f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 104f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 105f7917c00SJeff Kirsher }; 106f7917c00SJeff Kirsher 107f7917c00SJeff Kirsher struct port_stats { 108f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 109f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 110f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 111f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 112f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 113f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 114f7917c00SJeff Kirsher 115f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 116f7917c00SJeff Kirsher u64 tx_frames_65_127; 117f7917c00SJeff Kirsher u64 tx_frames_128_255; 118f7917c00SJeff Kirsher u64 tx_frames_256_511; 119f7917c00SJeff Kirsher u64 tx_frames_512_1023; 120f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 121f7917c00SJeff Kirsher u64 tx_frames_1519_max; 122f7917c00SJeff Kirsher 123f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 124f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 125f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 126f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 127f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 128f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 129f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 131f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 132f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 133f7917c00SJeff Kirsher 134f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 135f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 136f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 137f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 138f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 139f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 140f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 141f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 142f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 143f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 144f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 147f7917c00SJeff Kirsher u64 rx_frames_65_127; 148f7917c00SJeff Kirsher u64 rx_frames_128_255; 149f7917c00SJeff Kirsher u64 rx_frames_256_511; 150f7917c00SJeff Kirsher u64 rx_frames_512_1023; 151f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 152f7917c00SJeff Kirsher u64 rx_frames_1519_max; 153f7917c00SJeff Kirsher 154f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 155f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 156f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 157f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 158f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 159f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 161f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 162f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 163f7917c00SJeff Kirsher 164f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 165f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 166f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 167f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 168f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 169f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 170f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 171f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 172f7917c00SJeff Kirsher }; 173f7917c00SJeff Kirsher 174f7917c00SJeff Kirsher struct lb_port_stats { 175f7917c00SJeff Kirsher u64 octets; 176f7917c00SJeff Kirsher u64 frames; 177f7917c00SJeff Kirsher u64 bcast_frames; 178f7917c00SJeff Kirsher u64 mcast_frames; 179f7917c00SJeff Kirsher u64 ucast_frames; 180f7917c00SJeff Kirsher u64 error_frames; 181f7917c00SJeff Kirsher 182f7917c00SJeff Kirsher u64 frames_64; 183f7917c00SJeff Kirsher u64 frames_65_127; 184f7917c00SJeff Kirsher u64 frames_128_255; 185f7917c00SJeff Kirsher u64 frames_256_511; 186f7917c00SJeff Kirsher u64 frames_512_1023; 187f7917c00SJeff Kirsher u64 frames_1024_1518; 188f7917c00SJeff Kirsher u64 frames_1519_max; 189f7917c00SJeff Kirsher 190f7917c00SJeff Kirsher u64 drop; 191f7917c00SJeff Kirsher 192f7917c00SJeff Kirsher u64 ovflow0; 193f7917c00SJeff Kirsher u64 ovflow1; 194f7917c00SJeff Kirsher u64 ovflow2; 195f7917c00SJeff Kirsher u64 ovflow3; 196f7917c00SJeff Kirsher u64 trunc0; 197f7917c00SJeff Kirsher u64 trunc1; 198f7917c00SJeff Kirsher u64 trunc2; 199f7917c00SJeff Kirsher u64 trunc3; 200f7917c00SJeff Kirsher }; 201f7917c00SJeff Kirsher 202f7917c00SJeff Kirsher struct tp_tcp_stats { 203a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 204a4cfd929SHariprasad Shenai u64 tcp_in_segs; 205a4cfd929SHariprasad Shenai u64 tcp_out_segs; 206a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 207a4cfd929SHariprasad Shenai }; 208a4cfd929SHariprasad Shenai 209a4cfd929SHariprasad Shenai struct tp_usm_stats { 210a4cfd929SHariprasad Shenai u32 frames; 211a4cfd929SHariprasad Shenai u32 drops; 212a4cfd929SHariprasad Shenai u64 octets; 213f7917c00SJeff Kirsher }; 214f7917c00SJeff Kirsher 215a6222975SHariprasad Shenai struct tp_fcoe_stats { 216a6222975SHariprasad Shenai u32 frames_ddp; 217a6222975SHariprasad Shenai u32 frames_drop; 218a6222975SHariprasad Shenai u64 octets_ddp; 219f7917c00SJeff Kirsher }; 220f7917c00SJeff Kirsher 221f7917c00SJeff Kirsher struct tp_err_stats { 222a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 223a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 224a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 225a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 226a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 227a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 228a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 229a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 230a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 231a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 232a4cfd929SHariprasad Shenai }; 233a4cfd929SHariprasad Shenai 234a6222975SHariprasad Shenai struct tp_cpl_stats { 235a6222975SHariprasad Shenai u32 req[4]; 236a6222975SHariprasad Shenai u32 rsp[4]; 237a6222975SHariprasad Shenai }; 238a6222975SHariprasad Shenai 239a4cfd929SHariprasad Shenai struct tp_rdma_stats { 240a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 241a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 242f7917c00SJeff Kirsher }; 243f7917c00SJeff Kirsher 244e85c9a7aSHariprasad Shenai struct sge_params { 245e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 246e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 247e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 248e85c9a7aSHariprasad Shenai }; 249e85c9a7aSHariprasad Shenai 250f7917c00SJeff Kirsher struct tp_params { 251f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2522d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 253dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 254dca4faebSVipul Pandya /* channel map */ 255636f9d37SVipul Pandya 256636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 257636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 258dcf7b6f5SKumar Sanghvi 259dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 260dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 261dcf7b6f5SKumar Sanghvi 262dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 263dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 264dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 265dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 266dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 267dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 268dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 269dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 270dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 271dcf7b6f5SKumar Sanghvi * present. 272dcf7b6f5SKumar Sanghvi */ 273dcf7b6f5SKumar Sanghvi int vlan_shift; 274dcf7b6f5SKumar Sanghvi int vnic_shift; 275dcf7b6f5SKumar Sanghvi int port_shift; 276dcf7b6f5SKumar Sanghvi int protocol_shift; 277f7917c00SJeff Kirsher }; 278f7917c00SJeff Kirsher 279f7917c00SJeff Kirsher struct vpd_params { 280f7917c00SJeff Kirsher unsigned int cclk; 281f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 282f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 283f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 284a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 285098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 286f7917c00SJeff Kirsher }; 287f7917c00SJeff Kirsher 288f7917c00SJeff Kirsher struct pci_params { 289f7917c00SJeff Kirsher unsigned char speed; 290f7917c00SJeff Kirsher unsigned char width; 291f7917c00SJeff Kirsher }; 292f7917c00SJeff Kirsher 293d14807ddSHariprasad Shenai #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 294d14807ddSHariprasad Shenai #define CHELSIO_CHIP_FPGA 0x100 295d14807ddSHariprasad Shenai #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 296d14807ddSHariprasad Shenai #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 297d14807ddSHariprasad Shenai 298d14807ddSHariprasad Shenai #define CHELSIO_T4 0x4 299d14807ddSHariprasad Shenai #define CHELSIO_T5 0x5 300ab4b583bSHariprasad Shenai #define CHELSIO_T6 0x6 301d14807ddSHariprasad Shenai 302d14807ddSHariprasad Shenai enum chip_type { 303d14807ddSHariprasad Shenai T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 304d14807ddSHariprasad Shenai T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 305d14807ddSHariprasad Shenai T4_FIRST_REV = T4_A1, 306d14807ddSHariprasad Shenai T4_LAST_REV = T4_A2, 307d14807ddSHariprasad Shenai 308d14807ddSHariprasad Shenai T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 309d14807ddSHariprasad Shenai T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 310d14807ddSHariprasad Shenai T5_FIRST_REV = T5_A0, 311d14807ddSHariprasad Shenai T5_LAST_REV = T5_A1, 312ab4b583bSHariprasad Shenai 313ab4b583bSHariprasad Shenai T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0), 314ab4b583bSHariprasad Shenai T6_FIRST_REV = T6_A0, 315ab4b583bSHariprasad Shenai T6_LAST_REV = T6_A0, 316d14807ddSHariprasad Shenai }; 317d14807ddSHariprasad Shenai 31849aa284fSHariprasad Shenai struct devlog_params { 31949aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 32049aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 32149aa284fSHariprasad Shenai u32 size; /* size of log */ 32249aa284fSHariprasad Shenai }; 32349aa284fSHariprasad Shenai 3243ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3253ccc6cf7SHariprasad Shenai struct arch_specific_params { 3263ccc6cf7SHariprasad Shenai u8 nchan; 3273ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3283ccc6cf7SHariprasad Shenai u16 vfcount; 3293ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3303ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3313ccc6cf7SHariprasad Shenai }; 3323ccc6cf7SHariprasad Shenai 333f7917c00SJeff Kirsher struct adapter_params { 334e85c9a7aSHariprasad Shenai struct sge_params sge; 335f7917c00SJeff Kirsher struct tp_params tp; 336f7917c00SJeff Kirsher struct vpd_params vpd; 337f7917c00SJeff Kirsher struct pci_params pci; 33849aa284fSHariprasad Shenai struct devlog_params devlog; 33949aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 340f7917c00SJeff Kirsher 341f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 342f1ff24aaSHariprasad Shenai 343f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 344f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 345f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 346f7917c00SJeff Kirsher 347f7917c00SJeff Kirsher unsigned int fw_vers; 348f7917c00SJeff Kirsher unsigned int tp_vers; 349f7917c00SJeff Kirsher u8 api_vers[7]; 350f7917c00SJeff Kirsher 351f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 352f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 353f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 354f7917c00SJeff Kirsher 355f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 356f7917c00SJeff Kirsher unsigned char portvec; 357d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3583ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 359f7917c00SJeff Kirsher unsigned char offload; 360f7917c00SJeff Kirsher 3619a4da2cdSVipul Pandya unsigned char bypass; 3629a4da2cdSVipul Pandya 363f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3641ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3654c2c5763SHariprasad Shenai 3664c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3674c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 368f7917c00SJeff Kirsher }; 369f7917c00SJeff Kirsher 370a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 371a3bfb617SHariprasad Shenai * and possible hangs. 372a3bfb617SHariprasad Shenai */ 373a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 374a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 375a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 376a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 377a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 378a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 379a3bfb617SHariprasad Shenai }; 380a3bfb617SHariprasad Shenai 38116e47624SHariprasad Shenai #include "t4fw_api.h" 38216e47624SHariprasad Shenai 38316e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 384b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 385b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 386b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 387b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 38816e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 38916e47624SHariprasad Shenai 39016e47624SHariprasad Shenai struct fw_info { 39116e47624SHariprasad Shenai u8 chip; 39216e47624SHariprasad Shenai char *fs_name; 39316e47624SHariprasad Shenai char *fw_mod_name; 39416e47624SHariprasad Shenai struct fw_hdr fw_hdr; 39516e47624SHariprasad Shenai }; 39616e47624SHariprasad Shenai 39716e47624SHariprasad Shenai 398f7917c00SJeff Kirsher struct trace_params { 399f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 400f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 401f7917c00SJeff Kirsher unsigned short snap_len; 402f7917c00SJeff Kirsher unsigned short min_len; 403f7917c00SJeff Kirsher unsigned char skip_ofst; 404f7917c00SJeff Kirsher unsigned char skip_len; 405f7917c00SJeff Kirsher unsigned char invert; 406f7917c00SJeff Kirsher unsigned char port; 407f7917c00SJeff Kirsher }; 408f7917c00SJeff Kirsher 409f7917c00SJeff Kirsher struct link_config { 410f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 411f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 412f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 413f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 414f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 415f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 416f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 417f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 418f7917c00SJeff Kirsher }; 419f7917c00SJeff Kirsher 420e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 421f7917c00SJeff Kirsher 422f7917c00SJeff Kirsher enum { 423f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 424f7917c00SJeff Kirsher MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 425f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 426f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 427f36e58e5SHariprasad Shenai MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 428cf38be6dSHariprasad Shenai MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 429f7917c00SJeff Kirsher }; 430f7917c00SJeff Kirsher 431f7917c00SJeff Kirsher enum { 432812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 433812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 434812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 435812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 436812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 437812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 438812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 439812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 440812034f1SHariprasad Shenai }; 441812034f1SHariprasad Shenai 442812034f1SHariprasad Shenai enum { 443cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 444cf38be6dSHariprasad Shenai /* forwarded interrupts */ 445cf38be6dSHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 446cf38be6dSHariprasad Shenai + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 447f7917c00SJeff Kirsher }; 448f7917c00SJeff Kirsher 449f7917c00SJeff Kirsher struct adapter; 450f7917c00SJeff Kirsher struct sge_rspq; 451f7917c00SJeff Kirsher 452688848b1SAnish Bhatt #include "cxgb4_dcb.h" 453688848b1SAnish Bhatt 45476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 45576fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 45676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 45776fed8a9SVarun Prakash 458f7917c00SJeff Kirsher struct port_info { 459f7917c00SJeff Kirsher struct adapter *adapter; 460f7917c00SJeff Kirsher u16 viid; 461f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 462f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 463f7917c00SJeff Kirsher s8 mdio_addr; 46440e9de4bSHariprasad Shenai enum fw_port_type port_type; 465f7917c00SJeff Kirsher u8 mod_type; 466f7917c00SJeff Kirsher u8 port_id; 467f7917c00SJeff Kirsher u8 tx_chan; 468f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 469f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 470f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 471f7917c00SJeff Kirsher u8 rss_mode; 472f7917c00SJeff Kirsher struct link_config link_cfg; 473f7917c00SJeff Kirsher u16 *rss; 474a4cfd929SHariprasad Shenai struct port_stats stats_base; 475688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 476688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 477688848b1SAnish Bhatt #endif 47876fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 47976fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 48076fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 481f7917c00SJeff Kirsher }; 482f7917c00SJeff Kirsher 483f7917c00SJeff Kirsher struct dentry; 484f7917c00SJeff Kirsher struct work_struct; 485f7917c00SJeff Kirsher 486f7917c00SJeff Kirsher enum { /* adapter flags */ 487f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 488144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 489144be3d9SGavin Shan USING_MSI = (1 << 2), 490144be3d9SGavin Shan USING_MSIX = (1 << 3), 491f7917c00SJeff Kirsher FW_OK = (1 << 4), 49213ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 49352367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 49452367a76SVipul Pandya MASTER_PF = (1 << 7), 49552367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 496f7917c00SJeff Kirsher }; 497f7917c00SJeff Kirsher 498f7917c00SJeff Kirsher struct rx_sw_desc; 499f7917c00SJeff Kirsher 500f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 501f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 502f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 503f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 504f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 505f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 506f7917c00SJeff Kirsher unsigned long large_alloc_failed; 507f7917c00SJeff Kirsher unsigned long starving; 508f7917c00SJeff Kirsher /* RO fields */ 509f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 510f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 511f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 512f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 513f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 514df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 515df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 516f7917c00SJeff Kirsher }; 517f7917c00SJeff Kirsher 518f7917c00SJeff Kirsher /* A packet gather list */ 519f7917c00SJeff Kirsher struct pkt_gl { 520e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 521f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 522f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 523f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 524f7917c00SJeff Kirsher }; 525f7917c00SJeff Kirsher 526f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 527f7917c00SJeff Kirsher const struct pkt_gl *gl); 528f7917c00SJeff Kirsher 529f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 530f7917c00SJeff Kirsher struct napi_struct napi; 531f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 532f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 533f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 534f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 535f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 536e553ec3fSHariprasad Shenai u8 adaptive_rx; 537f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 538f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 539f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 540f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 541f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 542f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 543f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 544f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 545df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 546df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 547f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 548f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 549f7917c00SJeff Kirsher struct adapter *adap; 550f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 551f7917c00SJeff Kirsher rspq_handler_t handler; 5523a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5533a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5543a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5553a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5563a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5573a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5583a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5593a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5603a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5613a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5623a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 5633a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5643a336cb1SHariprasad Shenai unsigned int bpoll_state; 5653a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 5663a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 5673a336cb1SHariprasad Shenai 568f7917c00SJeff Kirsher }; 569f7917c00SJeff Kirsher 570f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 571f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 572f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 573f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 574f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 575f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 576f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 577f7917c00SJeff Kirsher }; 578f7917c00SJeff Kirsher 579f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 580f7917c00SJeff Kirsher struct sge_rspq rspq; 581f7917c00SJeff Kirsher struct sge_fl fl; 582f7917c00SJeff Kirsher struct sge_eth_stats stats; 583f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 584f7917c00SJeff Kirsher 585f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 586f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 587f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 588f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 589f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 590f7917c00SJeff Kirsher }; 591f7917c00SJeff Kirsher 592f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 593f7917c00SJeff Kirsher struct sge_rspq rspq; 594f7917c00SJeff Kirsher struct sge_fl fl; 595f7917c00SJeff Kirsher struct sge_ofld_stats stats; 596f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 597f7917c00SJeff Kirsher 598f7917c00SJeff Kirsher struct tx_desc { 599f7917c00SJeff Kirsher __be64 flit[8]; 600f7917c00SJeff Kirsher }; 601f7917c00SJeff Kirsher 602f7917c00SJeff Kirsher struct tx_sw_desc; 603f7917c00SJeff Kirsher 604f7917c00SJeff Kirsher struct sge_txq { 605f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 606f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 607f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 608f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 609f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 610f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 611f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 612f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 613f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 614f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 615f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6163069ee9bSVipul Pandya spinlock_t db_lock; 6173069ee9bSVipul Pandya int db_disabled; 6183069ee9bSVipul Pandya unsigned short db_pidx; 61905eb2389SSteve Wise unsigned short db_pidx_inc; 620df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 621df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 622f7917c00SJeff Kirsher }; 623f7917c00SJeff Kirsher 624f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 625f7917c00SJeff Kirsher struct sge_txq q; 626f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 62710b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 62810b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 62910b00466SAnish Bhatt #endif 630f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 631f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 632f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 633f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 634f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 635f7917c00SJeff Kirsher 636f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 637f7917c00SJeff Kirsher struct sge_txq q; 638f7917c00SJeff Kirsher struct adapter *adap; 639f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 640f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 641f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 642f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 643f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 644f7917c00SJeff Kirsher 645f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 646f7917c00SJeff Kirsher struct sge_txq q; 647f7917c00SJeff Kirsher struct adapter *adap; 648f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 649f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 650f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 651f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 652f7917c00SJeff Kirsher 653f7917c00SJeff Kirsher struct sge { 654f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 655f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 656f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 657f7917c00SJeff Kirsher 658f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 659f7917c00SJeff Kirsher struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 660f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 661cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 662f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 663f7917c00SJeff Kirsher 664f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 665f7917c00SJeff Kirsher spinlock_t intrq_lock; 666f7917c00SJeff Kirsher 667f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 668f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 669f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 670f7917c00SJeff Kirsher u16 ofldqsets; /* # of active offload queue sets */ 671f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 672cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 673f7917c00SJeff Kirsher u16 ofld_rxq[MAX_OFLD_QSETS]; 674f36e58e5SHariprasad Shenai u16 rdma_rxq[MAX_RDMA_QUEUES]; 675f36e58e5SHariprasad Shenai u16 rdma_ciq[MAX_RDMA_CIQS]; 676f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 677f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 67852367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 67952367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 68052367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 68152367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 68252367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 6830f4d201fSKumar Sanghvi 684a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 685f7917c00SJeff Kirsher unsigned int egr_start; 6864b8e27a8SHariprasad Shenai unsigned int egr_sz; 687f7917c00SJeff Kirsher unsigned int ingr_start; 6884b8e27a8SHariprasad Shenai unsigned int ingr_sz; 6894b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 6904b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 6914b8e27a8SHariprasad Shenai unsigned long *starving_fl; 6924b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 6935b377d11SHariprasad Shenai unsigned long *blocked_fl; 694f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 695f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 696f7917c00SJeff Kirsher }; 697f7917c00SJeff Kirsher 698f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 699f7917c00SJeff Kirsher #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 700f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 701cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 702f7917c00SJeff Kirsher 703f7917c00SJeff Kirsher struct l2t_data; 704f7917c00SJeff Kirsher 7052422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7062422d9a3SSantosh Rastapur 7077d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7087d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7097d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7102422d9a3SSantosh Rastapur */ 7117d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7122422d9a3SSantosh Rastapur 7132422d9a3SSantosh Rastapur #endif 7142422d9a3SSantosh Rastapur 715a4cfd929SHariprasad Shenai struct doorbell_stats { 716a4cfd929SHariprasad Shenai u32 db_drop; 717a4cfd929SHariprasad Shenai u32 db_empty; 718a4cfd929SHariprasad Shenai u32 db_full; 719a4cfd929SHariprasad Shenai }; 720a4cfd929SHariprasad Shenai 721f7917c00SJeff Kirsher struct adapter { 722f7917c00SJeff Kirsher void __iomem *regs; 72322adfe0aSSantosh Rastapur void __iomem *bar2; 7240abfd152SHariprasad Shenai u32 t4_bar0; 725f7917c00SJeff Kirsher struct pci_dev *pdev; 726f7917c00SJeff Kirsher struct device *pdev_dev; 7273069ee9bSVipul Pandya unsigned int mbox; 728b2612722SHariprasad Shenai unsigned int pf; 729f7917c00SJeff Kirsher unsigned int flags; 7302422d9a3SSantosh Rastapur enum chip_type chip; 731f7917c00SJeff Kirsher 732f7917c00SJeff Kirsher int msg_enable; 733f7917c00SJeff Kirsher 734f7917c00SJeff Kirsher struct adapter_params params; 735f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 736f7917c00SJeff Kirsher unsigned int swintr; 737f7917c00SJeff Kirsher 738f7917c00SJeff Kirsher struct { 739f7917c00SJeff Kirsher unsigned short vec; 740f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 741f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 742f7917c00SJeff Kirsher 743a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 744f7917c00SJeff Kirsher struct sge sge; 745f7917c00SJeff Kirsher 746f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 747f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 748f7917c00SJeff Kirsher 749793dad94SVipul Pandya u32 filter_mode; 750636f9d37SVipul Pandya unsigned int l2t_start; 751636f9d37SVipul Pandya unsigned int l2t_end; 752f7917c00SJeff Kirsher struct l2t_data *l2t; 753b5a02f50SAnish Bhatt unsigned int clipt_start; 754b5a02f50SAnish Bhatt unsigned int clipt_end; 755b5a02f50SAnish Bhatt struct clip_tbl *clipt; 756f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 757f7917c00SJeff Kirsher struct list_head list_node; 75801bcca68SVipul Pandya struct list_head rcu_node; 759f7917c00SJeff Kirsher 760f7917c00SJeff Kirsher struct tid_info tids; 761f7917c00SJeff Kirsher void **tid_release_head; 762f7917c00SJeff Kirsher spinlock_t tid_release_lock; 76329aaee65SAnish Bhatt struct workqueue_struct *workq; 764f7917c00SJeff Kirsher struct work_struct tid_release_task; 765881806bcSVipul Pandya struct work_struct db_full_task; 766881806bcSVipul Pandya struct work_struct db_drop_task; 767f7917c00SJeff Kirsher bool tid_release_task_busy; 768f7917c00SJeff Kirsher 769f7917c00SJeff Kirsher struct dentry *debugfs_root; 7700b2c2a93SHariprasad Shenai u32 use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 771f7917c00SJeff Kirsher 772f7917c00SJeff Kirsher spinlock_t stats_lock; 773fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 774f7917c00SJeff Kirsher }; 775f7917c00SJeff Kirsher 776f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 777f2b7e78dSVipul Pandya */ 778f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 779f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 780f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 781f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 782f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 783f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 784f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 785f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 786f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 787f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 788f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 789f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 790f2b7e78dSVipul Pandya 791f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 792f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 793f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 794f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 795f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 796f2b7e78dSVipul Pandya * matching rules are true. 797f2b7e78dSVipul Pandya * 798f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 799f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 800f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 801f2b7e78dSVipul Pandya * MPS match type) ... 802f2b7e78dSVipul Pandya * 803f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 804f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 805f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 806f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 807f2b7e78dSVipul Pandya */ 808f2b7e78dSVipul Pandya struct ch_filter_tuple { 809f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 810f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 811f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 812f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 813f2b7e78dSVipul Pandya * set of fields. 814f2b7e78dSVipul Pandya */ 815f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 816f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 817f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 818f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 819f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 820f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 821f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 822f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 823f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 824f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 825f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 826f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 827f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 828f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 829f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 830f2b7e78dSVipul Pandya 831f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 832f2b7e78dSVipul Pandya * available for field rules. 833f2b7e78dSVipul Pandya */ 834f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 835f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 836f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 837f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 838f2b7e78dSVipul Pandya }; 839f2b7e78dSVipul Pandya 840f2b7e78dSVipul Pandya /* A filter ioctl command. 841f2b7e78dSVipul Pandya */ 842f2b7e78dSVipul Pandya struct ch_filter_specification { 843f2b7e78dSVipul Pandya /* Administrative fields for filter. 844f2b7e78dSVipul Pandya */ 845f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 846f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 847f2b7e78dSVipul Pandya 848f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 849f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 850f2b7e78dSVipul Pandya */ 851f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 852f2b7e78dSVipul Pandya 853f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 854f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 855f2b7e78dSVipul Pandya * out as egress packets. 856f2b7e78dSVipul Pandya */ 857f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 858f2b7e78dSVipul Pandya 859f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 860f2b7e78dSVipul Pandya 861f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 862f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 863f2b7e78dSVipul Pandya 864f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 865f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 866f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 867f2b7e78dSVipul Pandya 868f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 869f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 870f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 871f2b7e78dSVipul Pandya */ 872f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 873f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 874f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 875f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 876f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 877f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 878f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 879f2b7e78dSVipul Pandya 880f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 881f2b7e78dSVipul Pandya */ 882f2b7e78dSVipul Pandya struct ch_filter_tuple val; 883f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 884f2b7e78dSVipul Pandya }; 885f2b7e78dSVipul Pandya 886f2b7e78dSVipul Pandya enum { 887f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 888f2b7e78dSVipul Pandya FILTER_DROP, 889f2b7e78dSVipul Pandya FILTER_SWITCH 890f2b7e78dSVipul Pandya }; 891f2b7e78dSVipul Pandya 892f2b7e78dSVipul Pandya enum { 893f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 894f2b7e78dSVipul Pandya VLAN_REMOVE, 895f2b7e78dSVipul Pandya VLAN_INSERT, 896f2b7e78dSVipul Pandya VLAN_REWRITE 897f2b7e78dSVipul Pandya }; 898f2b7e78dSVipul Pandya 899a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 900a4cfd929SHariprasad Shenai { 901a4cfd929SHariprasad Shenai return adap->params.offload; 902a4cfd929SHariprasad Shenai } 903a4cfd929SHariprasad Shenai 904ab4b583bSHariprasad Shenai static inline int is_t6(enum chip_type chip) 905ab4b583bSHariprasad Shenai { 906ab4b583bSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6; 907ab4b583bSHariprasad Shenai } 908ab4b583bSHariprasad Shenai 9092422d9a3SSantosh Rastapur static inline int is_t5(enum chip_type chip) 9102422d9a3SSantosh Rastapur { 911d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 9122422d9a3SSantosh Rastapur } 9132422d9a3SSantosh Rastapur 9142422d9a3SSantosh Rastapur static inline int is_t4(enum chip_type chip) 9152422d9a3SSantosh Rastapur { 916d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 9172422d9a3SSantosh Rastapur } 9182422d9a3SSantosh Rastapur 919f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 920f7917c00SJeff Kirsher { 921f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 922f7917c00SJeff Kirsher } 923f7917c00SJeff Kirsher 924f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 925f7917c00SJeff Kirsher { 926f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 927f7917c00SJeff Kirsher } 928f7917c00SJeff Kirsher 929f7917c00SJeff Kirsher #ifndef readq 930f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 931f7917c00SJeff Kirsher { 932f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 933f7917c00SJeff Kirsher } 934f7917c00SJeff Kirsher 935f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 936f7917c00SJeff Kirsher { 937f7917c00SJeff Kirsher writel(val, addr); 938f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 939f7917c00SJeff Kirsher } 940f7917c00SJeff Kirsher #endif 941f7917c00SJeff Kirsher 942f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 943f7917c00SJeff Kirsher { 944f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 945f7917c00SJeff Kirsher } 946f7917c00SJeff Kirsher 947f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 948f7917c00SJeff Kirsher { 949f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 950f7917c00SJeff Kirsher } 951f7917c00SJeff Kirsher 952f7917c00SJeff Kirsher /** 953098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 954098ef6c2SHariprasad Shenai * @adapter: the adapter 955098ef6c2SHariprasad Shenai * @port_idx: the port index 956098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 957098ef6c2SHariprasad Shenai * 958098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 959098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 960098ef6c2SHariprasad Shenai */ 961098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 962098ef6c2SHariprasad Shenai u8 hw_addr[]) 963098ef6c2SHariprasad Shenai { 964098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 965098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 966098ef6c2SHariprasad Shenai } 967098ef6c2SHariprasad Shenai 968098ef6c2SHariprasad Shenai /** 969f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 970f7917c00SJeff Kirsher * @dev: the netdev 971f7917c00SJeff Kirsher * 972f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 973f7917c00SJeff Kirsher */ 974f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 975f7917c00SJeff Kirsher { 976f7917c00SJeff Kirsher return netdev_priv(dev); 977f7917c00SJeff Kirsher } 978f7917c00SJeff Kirsher 979f7917c00SJeff Kirsher /** 980f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 981f7917c00SJeff Kirsher * @adap: the adapter 982f7917c00SJeff Kirsher * @idx: the port index 983f7917c00SJeff Kirsher * 984f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 985f7917c00SJeff Kirsher */ 986f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 987f7917c00SJeff Kirsher { 988f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 989f7917c00SJeff Kirsher } 990f7917c00SJeff Kirsher 991f7917c00SJeff Kirsher /** 992f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 993f7917c00SJeff Kirsher * @dev: the netdev 994f7917c00SJeff Kirsher * 995f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 996f7917c00SJeff Kirsher */ 997f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 998f7917c00SJeff Kirsher { 999f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1000f7917c00SJeff Kirsher } 1001f7917c00SJeff Kirsher 10023a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 10033a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 10043a336cb1SHariprasad Shenai { 10053a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 10063a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10073a336cb1SHariprasad Shenai } 10083a336cb1SHariprasad Shenai 10093a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 10103a336cb1SHariprasad Shenai { 10113a336cb1SHariprasad Shenai bool rc = true; 10123a336cb1SHariprasad Shenai 10133a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 10143a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 10153a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 10163a336cb1SHariprasad Shenai rc = false; 10173a336cb1SHariprasad Shenai } else { 10183a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 10193a336cb1SHariprasad Shenai } 10203a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 10213a336cb1SHariprasad Shenai return rc; 10223a336cb1SHariprasad Shenai } 10233a336cb1SHariprasad Shenai 10243a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10253a336cb1SHariprasad Shenai { 10263a336cb1SHariprasad Shenai bool rc = false; 10273a336cb1SHariprasad Shenai 10283a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 10293a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 10303a336cb1SHariprasad Shenai rc = true; 10313a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10323a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 10333a336cb1SHariprasad Shenai return rc; 10343a336cb1SHariprasad Shenai } 10353a336cb1SHariprasad Shenai 10363a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10373a336cb1SHariprasad Shenai { 10383a336cb1SHariprasad Shenai bool rc = true; 10393a336cb1SHariprasad Shenai 10403a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 10413a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 10423a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 10433a336cb1SHariprasad Shenai rc = false; 10443a336cb1SHariprasad Shenai } else { 10453a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 10463a336cb1SHariprasad Shenai } 10473a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 10483a336cb1SHariprasad Shenai return rc; 10493a336cb1SHariprasad Shenai } 10503a336cb1SHariprasad Shenai 10513a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10523a336cb1SHariprasad Shenai { 10533a336cb1SHariprasad Shenai bool rc = false; 10543a336cb1SHariprasad Shenai 10553a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 10563a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 10573a336cb1SHariprasad Shenai rc = true; 10583a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10593a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 10603a336cb1SHariprasad Shenai return rc; 10613a336cb1SHariprasad Shenai } 10623a336cb1SHariprasad Shenai 10633a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10643a336cb1SHariprasad Shenai { 10653a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 10663a336cb1SHariprasad Shenai } 10673a336cb1SHariprasad Shenai #else 10683a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 10693a336cb1SHariprasad Shenai { 10703a336cb1SHariprasad Shenai } 10713a336cb1SHariprasad Shenai 10723a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 10733a336cb1SHariprasad Shenai { 10743a336cb1SHariprasad Shenai return true; 10753a336cb1SHariprasad Shenai } 10763a336cb1SHariprasad Shenai 10773a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10783a336cb1SHariprasad Shenai { 10793a336cb1SHariprasad Shenai return false; 10803a336cb1SHariprasad Shenai } 10813a336cb1SHariprasad Shenai 10823a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10833a336cb1SHariprasad Shenai { 10843a336cb1SHariprasad Shenai return false; 10853a336cb1SHariprasad Shenai } 10863a336cb1SHariprasad Shenai 10873a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10883a336cb1SHariprasad Shenai { 10893a336cb1SHariprasad Shenai return false; 10903a336cb1SHariprasad Shenai } 10913a336cb1SHariprasad Shenai 10923a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10933a336cb1SHariprasad Shenai { 10943a336cb1SHariprasad Shenai return false; 10953a336cb1SHariprasad Shenai } 10963a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 10973a336cb1SHariprasad Shenai 1098812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1099812034f1SHariprasad Shenai * - bits 0..9: chip version 1100812034f1SHariprasad Shenai * - bits 10..15: chip revision 1101812034f1SHariprasad Shenai * - bits 16..23: register dump version 1102812034f1SHariprasad Shenai */ 1103812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1104812034f1SHariprasad Shenai { 1105812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1106812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1107812034f1SHariprasad Shenai } 1108812034f1SHariprasad Shenai 1109812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1110812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1111812034f1SHariprasad Shenai const struct sge_rspq *q) 1112812034f1SHariprasad Shenai { 1113812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1114812034f1SHariprasad Shenai 1115812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1116812034f1SHariprasad Shenai } 1117812034f1SHariprasad Shenai 1118812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1119812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1120812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1121812034f1SHariprasad Shenai 1122f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1123f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1124f7917c00SJeff Kirsher 1125f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1126f7917c00SJeff Kirsher 1127f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 11285fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1129f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1130f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1131f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1132f7917c00SJeff Kirsher const struct pkt_gl *gl); 1133f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1134f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1135f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1136f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 1137145ef8a5SHariprasad Shenai struct sge_fl *fl, rspq_handler_t hnd, int cong); 1138f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1139f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1140f7917c00SJeff Kirsher unsigned int iqid); 1141f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1142f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1143f7917c00SJeff Kirsher unsigned int cmplqid); 1144f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1145f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1146f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 114752367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1148f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1149f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 11503a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1151812034f1SHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1152812034f1SHariprasad Shenai unsigned int cnt); 1153812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1154812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 11553069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1156f7917c00SJeff Kirsher 1157f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1158f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1159f7917c00SJeff Kirsher 11609a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 11619a4da2cdSVipul Pandya { 11629a4da2cdSVipul Pandya return adap->params.bypass; 11639a4da2cdSVipul Pandya } 11649a4da2cdSVipul Pandya 11659a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 11669a4da2cdSVipul Pandya { 11679a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 11689a4da2cdSVipul Pandya switch (device) { 11699a4da2cdSVipul Pandya case 0x440b: 11709a4da2cdSVipul Pandya case 0x440c: 11719a4da2cdSVipul Pandya return 1; 11729a4da2cdSVipul Pandya default: 11739a4da2cdSVipul Pandya return 0; 11749a4da2cdSVipul Pandya } 11759a4da2cdSVipul Pandya } 11769a4da2cdSVipul Pandya 117701b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 117801b69614SHariprasad Shenai { 117901b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 118001b69614SHariprasad Shenai switch (device) { 118101b69614SHariprasad Shenai case 0x4409: 118201b69614SHariprasad Shenai case 0x4486: 118301b69614SHariprasad Shenai return 1; 118401b69614SHariprasad Shenai 118501b69614SHariprasad Shenai default: 118601b69614SHariprasad Shenai return 0; 118701b69614SHariprasad Shenai } 118801b69614SHariprasad Shenai } 118901b69614SHariprasad Shenai 1190f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1191f7917c00SJeff Kirsher { 1192f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1193f7917c00SJeff Kirsher } 1194f7917c00SJeff Kirsher 1195f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1196f7917c00SJeff Kirsher unsigned int us) 1197f7917c00SJeff Kirsher { 1198f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1199f7917c00SJeff Kirsher } 1200f7917c00SJeff Kirsher 120152367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 120252367a76SVipul Pandya unsigned int ticks) 120352367a76SVipul Pandya { 120452367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 120552367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 120652367a76SVipul Pandya adapter->params.vpd.cclk); 120752367a76SVipul Pandya } 120852367a76SVipul Pandya 1209f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1210f7917c00SJeff Kirsher u32 val); 1211f7917c00SJeff Kirsher 121201b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 121301b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1214f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1215f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1216f7917c00SJeff Kirsher 121701b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 121801b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 121901b69614SHariprasad Shenai int timeout) 122001b69614SHariprasad Shenai { 122101b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 122201b69614SHariprasad Shenai timeout); 122301b69614SHariprasad Shenai } 122401b69614SHariprasad Shenai 1225f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1226f7917c00SJeff Kirsher int size, void *rpl) 1227f7917c00SJeff Kirsher { 1228f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1229f7917c00SJeff Kirsher } 1230f7917c00SJeff Kirsher 1231f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1232f7917c00SJeff Kirsher int size, void *rpl) 1233f7917c00SJeff Kirsher { 1234f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1235f7917c00SJeff Kirsher } 1236f7917c00SJeff Kirsher 123713ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 123813ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 123913ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1240f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1241f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1242f2b7e78dSVipul Pandya unsigned int start_idx); 12430abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1244f2b7e78dSVipul Pandya 1245f2b7e78dSVipul Pandya struct fw_filter_wr; 1246f2b7e78dSVipul Pandya 1247f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1248f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1249f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1250f7917c00SJeff Kirsher 12518203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 12524036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1253f7917c00SJeff Kirsher struct link_config *lc); 1254f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1255fc5ab020SHariprasad Shenai 1256b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1257b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1258b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1259b562fc37SHariprasad Shenai 1260fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1261fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1262fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1263f01aa633SHariprasad Shenai void *buf, int dir); 1264fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1265fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1266fc5ab020SHariprasad Shenai { 1267fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1268fc5ab020SHariprasad Shenai } 1269fc5ab020SHariprasad Shenai 1270812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1271812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1272812034f1SHariprasad Shenai 1273f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1274098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1275098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 127649216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 127749216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1278f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 127901b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 128001b69614SHariprasad Shenai int win, spinlock_t *lock, 128101b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 128201b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 128301b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 128449216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 128522c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 128622c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1287636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 128816e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 128916e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1290ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 129116e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 129216e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 129316e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1294f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1295e85c9a7aSHariprasad Shenai 1296e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1297b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1298e85c9a7aSHariprasad Shenai unsigned int qid, 1299e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 130066cf188eSHariprasad S int user, 1301e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1302e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1303e85c9a7aSHariprasad Shenai 1304dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1305dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1306ae469b68SHariprasad Shenai 1307ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1308e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1309dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1310dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1311c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1312f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1313f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1314f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1315f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1316f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1317f7917c00SJeff Kirsher unsigned int flags); 1318c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1319c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1320688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1321688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1322688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1323688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1324688ea5feSHariprasad Shenai u32 *valp); 1325688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1326688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1327688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1328688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1329688ea5feSHariprasad Shenai 1330145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1331b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1332b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1333e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1334e5f0e43bSHariprasad Shenai size_t n); 1335c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1336c778af7dSHariprasad Shenai size_t n); 1337f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1338f1ff24aaSHariprasad Shenai unsigned int *valp); 1339f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1340f1ff24aaSHariprasad Shenai const unsigned int *valp); 1341f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 134219689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 134319689609SHariprasad Shenai unsigned int *pif_req_wrptr, 134419689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 134526fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 134674b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 134772aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1348f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1349a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1350a4cfd929SHariprasad Shenai struct port_stats *stats, 1351a4cfd929SHariprasad Shenai struct port_stats *offset); 135265046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1353f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1354bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1355636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1356636f9d37SVipul Pandya unsigned int mask, unsigned int val); 13572d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1358a4cfd929SHariprasad Shenai void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1359a6222975SHariprasad Shenai void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1360a4cfd929SHariprasad Shenai void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1361a4cfd929SHariprasad Shenai void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1362f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1363f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1364a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1365a6222975SHariprasad Shenai struct tp_fcoe_stats *st); 1366f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1367f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1368f7917c00SJeff Kirsher 1369797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1370797ff0f5SHariprasad Shenai 13717864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1372f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1373f2b7e78dSVipul Pandya 1374f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1375f7917c00SJeff Kirsher const u8 *addr); 1376f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1377f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1378f7917c00SJeff Kirsher 1379f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1380f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1381f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1382f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1383f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1384636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1385636f9d37SVipul Pandya unsigned int cache_line_size); 1386636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1387f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1388f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1389f7917c00SJeff Kirsher u32 *val); 139001b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1391f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 139201b69614SHariprasad Shenai u32 *val, int rw); 139301b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1394688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1395688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 139601b69614SHariprasad Shenai const u32 *val, int timeout); 139701b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 139801b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1399688848b1SAnish Bhatt const u32 *val); 1400f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1401f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1402f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1403f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1404f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1405f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1406f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1407f7917c00SJeff Kirsher unsigned int *rss_size); 14084f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 14094f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 14104f3a0fcfSHariprasad Shenai unsigned int viid); 1411f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1412f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1413f7917c00SJeff Kirsher bool sleep_ok); 1414f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1415f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1416f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1417f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1418f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1419f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1420f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1421688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1422688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1423f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1424f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1425f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1426f7917c00SJeff Kirsher unsigned int nblinks); 1427f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1428f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1429f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1430f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1431f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1432f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1433f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1434f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1435f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1436f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1437f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1438f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1439f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 14405d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1441f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1442881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1443881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 14448caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 14458caa1e84SVipul Pandya u32 addr, u32 val); 144668bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1447fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1448a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1449a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1450a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1451a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1452a3bfb617SHariprasad Shenai int hz, int ticks); 1453f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1454