1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #include <linux/sort.h> 19 20 #include "t4_regs.h" 21 #include "cxgb4.h" 22 #include "cudbg_if.h" 23 #include "cudbg_lib_common.h" 24 #include "cudbg_entity.h" 25 #include "cudbg_lib.h" 26 27 static void cudbg_write_and_release_buff(struct cudbg_buffer *pin_buff, 28 struct cudbg_buffer *dbg_buff) 29 { 30 cudbg_update_buff(pin_buff, dbg_buff); 31 cudbg_put_buff(pin_buff, dbg_buff); 32 } 33 34 static int is_fw_attached(struct cudbg_init *pdbg_init) 35 { 36 struct adapter *padap = pdbg_init->adap; 37 38 if (!(padap->flags & FW_OK) || padap->use_bd) 39 return 0; 40 41 return 1; 42 } 43 44 /* This function will add additional padding bytes into debug_buffer to make it 45 * 4 byte aligned. 46 */ 47 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff, 48 struct cudbg_entity_hdr *entity_hdr) 49 { 50 u8 zero_buf[4] = {0}; 51 u8 padding, remain; 52 53 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4; 54 padding = 4 - remain; 55 if (remain) { 56 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf, 57 padding); 58 dbg_buff->offset += padding; 59 entity_hdr->num_pad = padding; 60 } 61 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset; 62 } 63 64 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i) 65 { 66 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf; 67 68 return (struct cudbg_entity_hdr *) 69 ((char *)outbuf + cudbg_hdr->hdr_len + 70 (sizeof(struct cudbg_entity_hdr) * (i - 1))); 71 } 72 73 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len, 74 void *dest) 75 { 76 int vaddr, rc; 77 78 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE); 79 if (vaddr < 0) 80 return vaddr; 81 82 rc = pci_read_vpd(padap->pdev, vaddr, len, dest); 83 if (rc < 0) 84 return rc; 85 86 return 0; 87 } 88 89 static int cudbg_mem_desc_cmp(const void *a, const void *b) 90 { 91 return ((const struct cudbg_mem_desc *)a)->base - 92 ((const struct cudbg_mem_desc *)b)->base; 93 } 94 95 int cudbg_fill_meminfo(struct adapter *padap, 96 struct cudbg_meminfo *meminfo_buff) 97 { 98 struct cudbg_mem_desc *md; 99 u32 lo, hi, used, alloc; 100 int n, i; 101 102 memset(meminfo_buff->avail, 0, 103 ARRAY_SIZE(meminfo_buff->avail) * 104 sizeof(struct cudbg_mem_desc)); 105 memset(meminfo_buff->mem, 0, 106 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc)); 107 md = meminfo_buff->mem; 108 109 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) { 110 meminfo_buff->mem[i].limit = 0; 111 meminfo_buff->mem[i].idx = i; 112 } 113 114 /* Find and sort the populated memory ranges */ 115 i = 0; 116 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A); 117 if (lo & EDRAM0_ENABLE_F) { 118 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A); 119 meminfo_buff->avail[i].base = 120 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi)); 121 meminfo_buff->avail[i].limit = 122 meminfo_buff->avail[i].base + 123 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi)); 124 meminfo_buff->avail[i].idx = 0; 125 i++; 126 } 127 128 if (lo & EDRAM1_ENABLE_F) { 129 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A); 130 meminfo_buff->avail[i].base = 131 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi)); 132 meminfo_buff->avail[i].limit = 133 meminfo_buff->avail[i].base + 134 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi)); 135 meminfo_buff->avail[i].idx = 1; 136 i++; 137 } 138 139 if (is_t5(padap->params.chip)) { 140 if (lo & EXT_MEM0_ENABLE_F) { 141 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A); 142 meminfo_buff->avail[i].base = 143 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 144 meminfo_buff->avail[i].limit = 145 meminfo_buff->avail[i].base + 146 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 147 meminfo_buff->avail[i].idx = 3; 148 i++; 149 } 150 151 if (lo & EXT_MEM1_ENABLE_F) { 152 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 153 meminfo_buff->avail[i].base = 154 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 155 meminfo_buff->avail[i].limit = 156 meminfo_buff->avail[i].base + 157 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 158 meminfo_buff->avail[i].idx = 4; 159 i++; 160 } 161 } else { 162 if (lo & EXT_MEM_ENABLE_F) { 163 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A); 164 meminfo_buff->avail[i].base = 165 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 166 meminfo_buff->avail[i].limit = 167 meminfo_buff->avail[i].base + 168 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 169 meminfo_buff->avail[i].idx = 2; 170 i++; 171 } 172 173 if (lo & HMA_MUX_F) { 174 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 175 meminfo_buff->avail[i].base = 176 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 177 meminfo_buff->avail[i].limit = 178 meminfo_buff->avail[i].base + 179 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 180 meminfo_buff->avail[i].idx = 5; 181 i++; 182 } 183 } 184 185 if (!i) /* no memory available */ 186 return CUDBG_STATUS_ENTITY_NOT_FOUND; 187 188 meminfo_buff->avail_c = i; 189 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc), 190 cudbg_mem_desc_cmp, NULL); 191 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); 192 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); 193 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); 194 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A); 195 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A); 196 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A); 197 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A); 198 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A); 199 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A); 200 201 /* the next few have explicit upper bounds */ 202 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A); 203 md->limit = md->base - 1 + 204 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) * 205 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A)); 206 md++; 207 208 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A); 209 md->limit = md->base - 1 + 210 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) * 211 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A)); 212 md++; 213 214 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) { 215 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) { 216 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4; 217 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 218 } else { 219 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 220 md->base = t4_read_reg(padap, 221 LE_DB_HASH_TBL_BASE_ADDR_A); 222 } 223 md->limit = 0; 224 } else { 225 md->base = 0; 226 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 227 } 228 md++; 229 230 #define ulp_region(reg) do { \ 231 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ 232 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\ 233 } while (0) 234 235 ulp_region(RX_ISCSI); 236 ulp_region(RX_TDDP); 237 ulp_region(TX_TPT); 238 ulp_region(RX_STAG); 239 ulp_region(RX_RQ); 240 ulp_region(RX_RQUDP); 241 ulp_region(RX_PBL); 242 ulp_region(TX_PBL); 243 #undef ulp_region 244 md->base = 0; 245 md->idx = ARRAY_SIZE(cudbg_region); 246 if (!is_t4(padap->params.chip)) { 247 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A); 248 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A); 249 u32 size = 0; 250 251 if (is_t5(padap->params.chip)) { 252 if (sge_ctrl & VFIFO_ENABLE_F) 253 size = DBVFIFO_SIZE_G(fifo_size); 254 } else { 255 size = T6_DBVFIFO_SIZE_G(fifo_size); 256 } 257 258 if (size) { 259 md->base = BASEADDR_G(t4_read_reg(padap, 260 SGE_DBVFIFO_BADDR_A)); 261 md->limit = md->base + (size << 2) - 1; 262 } 263 } 264 265 md++; 266 267 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A); 268 md->limit = 0; 269 md++; 270 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A); 271 md->limit = 0; 272 md++; 273 274 md->base = padap->vres.ocq.start; 275 if (padap->vres.ocq.size) 276 md->limit = md->base + padap->vres.ocq.size - 1; 277 else 278 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 279 md++; 280 281 /* add any address-space holes, there can be up to 3 */ 282 for (n = 0; n < i - 1; n++) 283 if (meminfo_buff->avail[n].limit < 284 meminfo_buff->avail[n + 1].base) 285 (md++)->base = meminfo_buff->avail[n].limit; 286 287 if (meminfo_buff->avail[n].limit) 288 (md++)->base = meminfo_buff->avail[n].limit; 289 290 n = md - meminfo_buff->mem; 291 meminfo_buff->mem_c = n; 292 293 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc), 294 cudbg_mem_desc_cmp, NULL); 295 296 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A); 297 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1; 298 meminfo_buff->up_ram_lo = lo; 299 meminfo_buff->up_ram_hi = hi; 300 301 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A); 302 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1; 303 meminfo_buff->up_extmem2_lo = lo; 304 meminfo_buff->up_extmem2_hi = hi; 305 306 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A); 307 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo); 308 meminfo_buff->rx_pages_data[1] = 309 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10; 310 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1; 311 312 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A); 313 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A); 314 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo); 315 meminfo_buff->tx_pages_data[1] = 316 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10); 317 meminfo_buff->tx_pages_data[2] = 318 hi >= (1 << 20) ? 'M' : 'K'; 319 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo); 320 321 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A); 322 323 for (i = 0; i < 4; i++) { 324 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 325 lo = t4_read_reg(padap, 326 MPS_RX_MAC_BG_PG_CNT0_A + i * 4); 327 else 328 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4); 329 if (is_t5(padap->params.chip)) { 330 used = T5_USED_G(lo); 331 alloc = T5_ALLOC_G(lo); 332 } else { 333 used = USED_G(lo); 334 alloc = ALLOC_G(lo); 335 } 336 meminfo_buff->port_used[i] = used; 337 meminfo_buff->port_alloc[i] = alloc; 338 } 339 340 for (i = 0; i < padap->params.arch.nchan; i++) { 341 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 342 lo = t4_read_reg(padap, 343 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4); 344 else 345 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4); 346 if (is_t5(padap->params.chip)) { 347 used = T5_USED_G(lo); 348 alloc = T5_ALLOC_G(lo); 349 } else { 350 used = USED_G(lo); 351 alloc = ALLOC_G(lo); 352 } 353 meminfo_buff->loopback_used[i] = used; 354 meminfo_buff->loopback_alloc[i] = alloc; 355 } 356 357 return 0; 358 } 359 360 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init, 361 struct cudbg_buffer *dbg_buff, 362 struct cudbg_error *cudbg_err) 363 { 364 struct adapter *padap = pdbg_init->adap; 365 struct cudbg_buffer temp_buff = { 0 }; 366 u32 buf_size = 0; 367 int rc = 0; 368 369 if (is_t4(padap->params.chip)) 370 buf_size = T4_REGMAP_SIZE; 371 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip)) 372 buf_size = T5_REGMAP_SIZE; 373 374 rc = cudbg_get_buff(dbg_buff, buf_size, &temp_buff); 375 if (rc) 376 return rc; 377 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size); 378 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 379 return rc; 380 } 381 382 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init, 383 struct cudbg_buffer *dbg_buff, 384 struct cudbg_error *cudbg_err) 385 { 386 struct adapter *padap = pdbg_init->adap; 387 struct cudbg_buffer temp_buff = { 0 }; 388 struct devlog_params *dparams; 389 int rc = 0; 390 391 rc = t4_init_devlog_params(padap); 392 if (rc < 0) { 393 cudbg_err->sys_err = rc; 394 return rc; 395 } 396 397 dparams = &padap->params.devlog; 398 rc = cudbg_get_buff(dbg_buff, dparams->size, &temp_buff); 399 if (rc) 400 return rc; 401 402 /* Collect FW devlog */ 403 if (dparams->start != 0) { 404 spin_lock(&padap->win0_lock); 405 rc = t4_memory_rw(padap, padap->params.drv_memwin, 406 dparams->memtype, dparams->start, 407 dparams->size, 408 (__be32 *)(char *)temp_buff.data, 409 1); 410 spin_unlock(&padap->win0_lock); 411 if (rc) { 412 cudbg_err->sys_err = rc; 413 cudbg_put_buff(&temp_buff, dbg_buff); 414 return rc; 415 } 416 } 417 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 418 return rc; 419 } 420 421 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init, 422 struct cudbg_buffer *dbg_buff, 423 struct cudbg_error *cudbg_err) 424 { 425 struct adapter *padap = pdbg_init->adap; 426 struct cudbg_buffer temp_buff = { 0 }; 427 int size, rc; 428 u32 cfg = 0; 429 430 if (is_t6(padap->params.chip)) { 431 size = padap->params.cim_la_size / 10 + 1; 432 size *= 11 * sizeof(u32); 433 } else { 434 size = padap->params.cim_la_size / 8; 435 size *= 8 * sizeof(u32); 436 } 437 438 size += sizeof(cfg); 439 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 440 if (rc) 441 return rc; 442 443 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 444 if (rc) { 445 cudbg_err->sys_err = rc; 446 cudbg_put_buff(&temp_buff, dbg_buff); 447 return rc; 448 } 449 450 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg)); 451 rc = t4_cim_read_la(padap, 452 (u32 *)((char *)temp_buff.data + sizeof(cfg)), 453 NULL); 454 if (rc < 0) { 455 cudbg_err->sys_err = rc; 456 cudbg_put_buff(&temp_buff, dbg_buff); 457 return rc; 458 } 459 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 460 return rc; 461 } 462 463 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init, 464 struct cudbg_buffer *dbg_buff, 465 struct cudbg_error *cudbg_err) 466 { 467 struct adapter *padap = pdbg_init->adap; 468 struct cudbg_buffer temp_buff = { 0 }; 469 int size, rc; 470 471 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); 472 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 473 if (rc) 474 return rc; 475 476 t4_cim_read_ma_la(padap, 477 (u32 *)temp_buff.data, 478 (u32 *)((char *)temp_buff.data + 479 5 * CIM_MALA_SIZE)); 480 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 481 return rc; 482 } 483 484 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init, 485 struct cudbg_buffer *dbg_buff, 486 struct cudbg_error *cudbg_err) 487 { 488 struct adapter *padap = pdbg_init->adap; 489 struct cudbg_buffer temp_buff = { 0 }; 490 struct cudbg_cim_qcfg *cim_qcfg_data; 491 int rc; 492 493 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_cim_qcfg), 494 &temp_buff); 495 if (rc) 496 return rc; 497 498 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data; 499 cim_qcfg_data->chip = padap->params.chip; 500 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A, 501 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat); 502 if (rc) { 503 cudbg_err->sys_err = rc; 504 cudbg_put_buff(&temp_buff, dbg_buff); 505 return rc; 506 } 507 508 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A, 509 ARRAY_SIZE(cim_qcfg_data->obq_wr), 510 cim_qcfg_data->obq_wr); 511 if (rc) { 512 cudbg_err->sys_err = rc; 513 cudbg_put_buff(&temp_buff, dbg_buff); 514 return rc; 515 } 516 517 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size, 518 cim_qcfg_data->thres); 519 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 520 return rc; 521 } 522 523 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init, 524 struct cudbg_buffer *dbg_buff, 525 struct cudbg_error *cudbg_err, int qid) 526 { 527 struct adapter *padap = pdbg_init->adap; 528 struct cudbg_buffer temp_buff = { 0 }; 529 int no_of_read_words, rc = 0; 530 u32 qsize; 531 532 /* collect CIM IBQ */ 533 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32); 534 rc = cudbg_get_buff(dbg_buff, qsize, &temp_buff); 535 if (rc) 536 return rc; 537 538 /* t4_read_cim_ibq will return no. of read words or error */ 539 no_of_read_words = t4_read_cim_ibq(padap, qid, 540 (u32 *)temp_buff.data, qsize); 541 /* no_of_read_words is less than or equal to 0 means error */ 542 if (no_of_read_words <= 0) { 543 if (!no_of_read_words) 544 rc = CUDBG_SYSTEM_ERROR; 545 else 546 rc = no_of_read_words; 547 cudbg_err->sys_err = rc; 548 cudbg_put_buff(&temp_buff, dbg_buff); 549 return rc; 550 } 551 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 552 return rc; 553 } 554 555 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init, 556 struct cudbg_buffer *dbg_buff, 557 struct cudbg_error *cudbg_err) 558 { 559 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0); 560 } 561 562 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init, 563 struct cudbg_buffer *dbg_buff, 564 struct cudbg_error *cudbg_err) 565 { 566 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1); 567 } 568 569 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init, 570 struct cudbg_buffer *dbg_buff, 571 struct cudbg_error *cudbg_err) 572 { 573 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2); 574 } 575 576 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init, 577 struct cudbg_buffer *dbg_buff, 578 struct cudbg_error *cudbg_err) 579 { 580 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3); 581 } 582 583 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init, 584 struct cudbg_buffer *dbg_buff, 585 struct cudbg_error *cudbg_err) 586 { 587 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4); 588 } 589 590 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init, 591 struct cudbg_buffer *dbg_buff, 592 struct cudbg_error *cudbg_err) 593 { 594 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5); 595 } 596 597 u32 cudbg_cim_obq_size(struct adapter *padap, int qid) 598 { 599 u32 value; 600 601 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 602 QUENUMSELECT_V(qid)); 603 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A); 604 value = CIMQSIZE_G(value) * 64; /* size in number of words */ 605 return value * sizeof(u32); 606 } 607 608 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init, 609 struct cudbg_buffer *dbg_buff, 610 struct cudbg_error *cudbg_err, int qid) 611 { 612 struct adapter *padap = pdbg_init->adap; 613 struct cudbg_buffer temp_buff = { 0 }; 614 int no_of_read_words, rc = 0; 615 u32 qsize; 616 617 /* collect CIM OBQ */ 618 qsize = cudbg_cim_obq_size(padap, qid); 619 rc = cudbg_get_buff(dbg_buff, qsize, &temp_buff); 620 if (rc) 621 return rc; 622 623 /* t4_read_cim_obq will return no. of read words or error */ 624 no_of_read_words = t4_read_cim_obq(padap, qid, 625 (u32 *)temp_buff.data, qsize); 626 /* no_of_read_words is less than or equal to 0 means error */ 627 if (no_of_read_words <= 0) { 628 if (!no_of_read_words) 629 rc = CUDBG_SYSTEM_ERROR; 630 else 631 rc = no_of_read_words; 632 cudbg_err->sys_err = rc; 633 cudbg_put_buff(&temp_buff, dbg_buff); 634 return rc; 635 } 636 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 637 return rc; 638 } 639 640 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init, 641 struct cudbg_buffer *dbg_buff, 642 struct cudbg_error *cudbg_err) 643 { 644 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0); 645 } 646 647 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init, 648 struct cudbg_buffer *dbg_buff, 649 struct cudbg_error *cudbg_err) 650 { 651 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1); 652 } 653 654 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init, 655 struct cudbg_buffer *dbg_buff, 656 struct cudbg_error *cudbg_err) 657 { 658 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2); 659 } 660 661 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init, 662 struct cudbg_buffer *dbg_buff, 663 struct cudbg_error *cudbg_err) 664 { 665 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3); 666 } 667 668 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init, 669 struct cudbg_buffer *dbg_buff, 670 struct cudbg_error *cudbg_err) 671 { 672 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4); 673 } 674 675 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init, 676 struct cudbg_buffer *dbg_buff, 677 struct cudbg_error *cudbg_err) 678 { 679 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5); 680 } 681 682 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init, 683 struct cudbg_buffer *dbg_buff, 684 struct cudbg_error *cudbg_err) 685 { 686 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6); 687 } 688 689 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init, 690 struct cudbg_buffer *dbg_buff, 691 struct cudbg_error *cudbg_err) 692 { 693 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7); 694 } 695 696 static int cudbg_meminfo_get_mem_index(struct adapter *padap, 697 struct cudbg_meminfo *mem_info, 698 u8 mem_type, u8 *idx) 699 { 700 u8 i, flag; 701 702 switch (mem_type) { 703 case MEM_EDC0: 704 flag = EDC0_FLAG; 705 break; 706 case MEM_EDC1: 707 flag = EDC1_FLAG; 708 break; 709 case MEM_MC0: 710 /* Some T5 cards have both MC0 and MC1. */ 711 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG; 712 break; 713 case MEM_MC1: 714 flag = MC1_FLAG; 715 break; 716 case MEM_HMA: 717 flag = HMA_FLAG; 718 break; 719 default: 720 return CUDBG_STATUS_ENTITY_NOT_FOUND; 721 } 722 723 for (i = 0; i < mem_info->avail_c; i++) { 724 if (mem_info->avail[i].idx == flag) { 725 *idx = i; 726 return 0; 727 } 728 } 729 730 return CUDBG_STATUS_ENTITY_NOT_FOUND; 731 } 732 733 /* Fetch the @region_name's start and end from @meminfo. */ 734 static int cudbg_get_mem_region(struct adapter *padap, 735 struct cudbg_meminfo *meminfo, 736 u8 mem_type, const char *region_name, 737 struct cudbg_mem_desc *mem_desc) 738 { 739 u8 mc, found = 0; 740 u32 i, idx = 0; 741 int rc; 742 743 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc); 744 if (rc) 745 return rc; 746 747 for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) { 748 if (!strcmp(cudbg_region[i], region_name)) { 749 found = 1; 750 idx = i; 751 break; 752 } 753 } 754 if (!found) 755 return -EINVAL; 756 757 found = 0; 758 for (i = 0; i < meminfo->mem_c; i++) { 759 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region)) 760 continue; /* Skip holes */ 761 762 if (!(meminfo->mem[i].limit)) 763 meminfo->mem[i].limit = 764 i < meminfo->mem_c - 1 ? 765 meminfo->mem[i + 1].base - 1 : ~0; 766 767 if (meminfo->mem[i].idx == idx) { 768 /* Check if the region exists in @mem_type memory */ 769 if (meminfo->mem[i].base < meminfo->avail[mc].base && 770 meminfo->mem[i].limit < meminfo->avail[mc].base) 771 return -EINVAL; 772 773 if (meminfo->mem[i].base > meminfo->avail[mc].limit) 774 return -EINVAL; 775 776 memcpy(mem_desc, &meminfo->mem[i], 777 sizeof(struct cudbg_mem_desc)); 778 found = 1; 779 break; 780 } 781 } 782 if (!found) 783 return -EINVAL; 784 785 return 0; 786 } 787 788 /* Fetch and update the start and end of the requested memory region w.r.t 0 789 * in the corresponding EDC/MC/HMA. 790 */ 791 static int cudbg_get_mem_relative(struct adapter *padap, 792 struct cudbg_meminfo *meminfo, 793 u8 mem_type, u32 *out_base, u32 *out_end) 794 { 795 u8 mc_idx; 796 int rc; 797 798 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx); 799 if (rc) 800 return rc; 801 802 if (*out_base < meminfo->avail[mc_idx].base) 803 *out_base = 0; 804 else 805 *out_base -= meminfo->avail[mc_idx].base; 806 807 if (*out_end > meminfo->avail[mc_idx].limit) 808 *out_end = meminfo->avail[mc_idx].limit; 809 else 810 *out_end -= meminfo->avail[mc_idx].base; 811 812 return 0; 813 } 814 815 /* Get TX and RX Payload region */ 816 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type, 817 const char *region_name, 818 struct cudbg_region_info *payload) 819 { 820 struct cudbg_mem_desc mem_desc = { 0 }; 821 struct cudbg_meminfo meminfo; 822 int rc; 823 824 rc = cudbg_fill_meminfo(padap, &meminfo); 825 if (rc) 826 return rc; 827 828 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name, 829 &mem_desc); 830 if (rc) { 831 payload->exist = false; 832 return 0; 833 } 834 835 payload->exist = true; 836 payload->start = mem_desc.base; 837 payload->end = mem_desc.limit; 838 839 return cudbg_get_mem_relative(padap, &meminfo, mem_type, 840 &payload->start, &payload->end); 841 } 842 843 #define CUDBG_YIELD_ITERATION 256 844 845 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init, 846 struct cudbg_buffer *dbg_buff, u8 mem_type, 847 unsigned long tot_len, 848 struct cudbg_error *cudbg_err) 849 { 850 static const char * const region_name[] = { "Tx payload:", 851 "Rx payload:" }; 852 unsigned long bytes, bytes_left, bytes_read = 0; 853 struct adapter *padap = pdbg_init->adap; 854 struct cudbg_buffer temp_buff = { 0 }; 855 struct cudbg_region_info payload[2]; 856 u32 yield_count = 0; 857 int rc = 0; 858 u8 i; 859 860 /* Get TX/RX Payload region range if they exist */ 861 memset(payload, 0, sizeof(payload)); 862 for (i = 0; i < ARRAY_SIZE(region_name); i++) { 863 rc = cudbg_get_payload_range(padap, mem_type, region_name[i], 864 &payload[i]); 865 if (rc) 866 return rc; 867 868 if (payload[i].exist) { 869 /* Align start and end to avoid wrap around */ 870 payload[i].start = roundup(payload[i].start, 871 CUDBG_CHUNK_SIZE); 872 payload[i].end = rounddown(payload[i].end, 873 CUDBG_CHUNK_SIZE); 874 } 875 } 876 877 bytes_left = tot_len; 878 while (bytes_left > 0) { 879 /* As MC size is huge and read through PIO access, this 880 * loop will hold cpu for a longer time. OS may think that 881 * the process is hanged and will generate CPU stall traces. 882 * So yield the cpu regularly. 883 */ 884 yield_count++; 885 if (!(yield_count % CUDBG_YIELD_ITERATION)) 886 schedule(); 887 888 bytes = min_t(unsigned long, bytes_left, 889 (unsigned long)CUDBG_CHUNK_SIZE); 890 rc = cudbg_get_buff(dbg_buff, bytes, &temp_buff); 891 if (rc) 892 return rc; 893 894 for (i = 0; i < ARRAY_SIZE(payload); i++) 895 if (payload[i].exist && 896 bytes_read >= payload[i].start && 897 bytes_read + bytes <= payload[i].end) 898 /* TX and RX Payload regions can't overlap */ 899 goto skip_read; 900 901 spin_lock(&padap->win0_lock); 902 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type, 903 bytes_read, bytes, 904 (__be32 *)temp_buff.data, 905 1); 906 spin_unlock(&padap->win0_lock); 907 if (rc) { 908 cudbg_err->sys_err = rc; 909 cudbg_put_buff(&temp_buff, dbg_buff); 910 return rc; 911 } 912 913 skip_read: 914 bytes_left -= bytes; 915 bytes_read += bytes; 916 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 917 } 918 return rc; 919 } 920 921 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init, 922 struct cudbg_error *cudbg_err) 923 { 924 struct adapter *padap = pdbg_init->adap; 925 int rc; 926 927 if (is_fw_attached(pdbg_init)) { 928 /* Flush uP dcache before reading edcX/mcX */ 929 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH); 930 if (rc) 931 cudbg_err->sys_warn = rc; 932 } 933 } 934 935 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init, 936 struct cudbg_buffer *dbg_buff, 937 struct cudbg_error *cudbg_err, 938 u8 mem_type) 939 { 940 struct adapter *padap = pdbg_init->adap; 941 struct cudbg_meminfo mem_info; 942 unsigned long size; 943 u8 mc_idx; 944 int rc; 945 946 memset(&mem_info, 0, sizeof(struct cudbg_meminfo)); 947 rc = cudbg_fill_meminfo(padap, &mem_info); 948 if (rc) 949 return rc; 950 951 cudbg_t4_fwcache(pdbg_init, cudbg_err); 952 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx); 953 if (rc) 954 return rc; 955 956 size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base; 957 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size, 958 cudbg_err); 959 } 960 961 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init, 962 struct cudbg_buffer *dbg_buff, 963 struct cudbg_error *cudbg_err) 964 { 965 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 966 MEM_EDC0); 967 } 968 969 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init, 970 struct cudbg_buffer *dbg_buff, 971 struct cudbg_error *cudbg_err) 972 { 973 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 974 MEM_EDC1); 975 } 976 977 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init, 978 struct cudbg_buffer *dbg_buff, 979 struct cudbg_error *cudbg_err) 980 { 981 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 982 MEM_MC0); 983 } 984 985 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init, 986 struct cudbg_buffer *dbg_buff, 987 struct cudbg_error *cudbg_err) 988 { 989 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 990 MEM_MC1); 991 } 992 993 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init, 994 struct cudbg_buffer *dbg_buff, 995 struct cudbg_error *cudbg_err) 996 { 997 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 998 MEM_HMA); 999 } 1000 1001 int cudbg_collect_rss(struct cudbg_init *pdbg_init, 1002 struct cudbg_buffer *dbg_buff, 1003 struct cudbg_error *cudbg_err) 1004 { 1005 struct adapter *padap = pdbg_init->adap; 1006 struct cudbg_buffer temp_buff = { 0 }; 1007 int rc, nentries; 1008 1009 nentries = t4_chip_rss_size(padap); 1010 rc = cudbg_get_buff(dbg_buff, nentries * sizeof(u16), &temp_buff); 1011 if (rc) 1012 return rc; 1013 1014 rc = t4_read_rss(padap, (u16 *)temp_buff.data); 1015 if (rc) { 1016 cudbg_err->sys_err = rc; 1017 cudbg_put_buff(&temp_buff, dbg_buff); 1018 return rc; 1019 } 1020 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1021 return rc; 1022 } 1023 1024 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init, 1025 struct cudbg_buffer *dbg_buff, 1026 struct cudbg_error *cudbg_err) 1027 { 1028 struct adapter *padap = pdbg_init->adap; 1029 struct cudbg_buffer temp_buff = { 0 }; 1030 struct cudbg_rss_vf_conf *vfconf; 1031 int vf, rc, vf_count; 1032 1033 vf_count = padap->params.arch.vfcount; 1034 rc = cudbg_get_buff(dbg_buff, 1035 vf_count * sizeof(struct cudbg_rss_vf_conf), 1036 &temp_buff); 1037 if (rc) 1038 return rc; 1039 1040 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data; 1041 for (vf = 0; vf < vf_count; vf++) 1042 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl, 1043 &vfconf[vf].rss_vf_vfh, true); 1044 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1045 return rc; 1046 } 1047 1048 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init, 1049 struct cudbg_buffer *dbg_buff, 1050 struct cudbg_error *cudbg_err) 1051 { 1052 struct adapter *padap = pdbg_init->adap; 1053 struct cudbg_buffer temp_buff = { 0 }; 1054 int rc; 1055 1056 rc = cudbg_get_buff(dbg_buff, NMTUS * sizeof(u16), &temp_buff); 1057 if (rc) 1058 return rc; 1059 1060 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL); 1061 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1062 return rc; 1063 } 1064 1065 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init, 1066 struct cudbg_buffer *dbg_buff, 1067 struct cudbg_error *cudbg_err) 1068 { 1069 struct adapter *padap = pdbg_init->adap; 1070 struct cudbg_buffer temp_buff = { 0 }; 1071 struct cudbg_pm_stats *pm_stats_buff; 1072 int rc; 1073 1074 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pm_stats), 1075 &temp_buff); 1076 if (rc) 1077 return rc; 1078 1079 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data; 1080 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc); 1081 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc); 1082 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1083 return rc; 1084 } 1085 1086 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init, 1087 struct cudbg_buffer *dbg_buff, 1088 struct cudbg_error *cudbg_err) 1089 { 1090 struct adapter *padap = pdbg_init->adap; 1091 struct cudbg_buffer temp_buff = { 0 }; 1092 struct cudbg_hw_sched *hw_sched_buff; 1093 int i, rc = 0; 1094 1095 if (!padap->params.vpd.cclk) 1096 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1097 1098 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_hw_sched), 1099 &temp_buff); 1100 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data; 1101 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A); 1102 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A)); 1103 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab); 1104 for (i = 0; i < NTX_SCHED; ++i) 1105 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i], 1106 &hw_sched_buff->ipg[i], true); 1107 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1108 return rc; 1109 } 1110 1111 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init, 1112 struct cudbg_buffer *dbg_buff, 1113 struct cudbg_error *cudbg_err) 1114 { 1115 struct adapter *padap = pdbg_init->adap; 1116 struct cudbg_buffer temp_buff = { 0 }; 1117 struct ireg_buf *ch_tp_pio; 1118 int i, rc, n = 0; 1119 u32 size; 1120 1121 if (is_t5(padap->params.chip)) 1122 n = sizeof(t5_tp_pio_array) + 1123 sizeof(t5_tp_tm_pio_array) + 1124 sizeof(t5_tp_mib_index_array); 1125 else 1126 n = sizeof(t6_tp_pio_array) + 1127 sizeof(t6_tp_tm_pio_array) + 1128 sizeof(t6_tp_mib_index_array); 1129 1130 n = n / (IREG_NUM_ELEM * sizeof(u32)); 1131 size = sizeof(struct ireg_buf) * n; 1132 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1133 if (rc) 1134 return rc; 1135 1136 ch_tp_pio = (struct ireg_buf *)temp_buff.data; 1137 1138 /* TP_PIO */ 1139 if (is_t5(padap->params.chip)) 1140 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1141 else if (is_t6(padap->params.chip)) 1142 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1143 1144 for (i = 0; i < n; i++) { 1145 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1146 u32 *buff = ch_tp_pio->outbuf; 1147 1148 if (is_t5(padap->params.chip)) { 1149 tp_pio->ireg_addr = t5_tp_pio_array[i][0]; 1150 tp_pio->ireg_data = t5_tp_pio_array[i][1]; 1151 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2]; 1152 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3]; 1153 } else if (is_t6(padap->params.chip)) { 1154 tp_pio->ireg_addr = t6_tp_pio_array[i][0]; 1155 tp_pio->ireg_data = t6_tp_pio_array[i][1]; 1156 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2]; 1157 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3]; 1158 } 1159 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range, 1160 tp_pio->ireg_local_offset, true); 1161 ch_tp_pio++; 1162 } 1163 1164 /* TP_TM_PIO */ 1165 if (is_t5(padap->params.chip)) 1166 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1167 else if (is_t6(padap->params.chip)) 1168 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1169 1170 for (i = 0; i < n; i++) { 1171 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1172 u32 *buff = ch_tp_pio->outbuf; 1173 1174 if (is_t5(padap->params.chip)) { 1175 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0]; 1176 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1]; 1177 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2]; 1178 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3]; 1179 } else if (is_t6(padap->params.chip)) { 1180 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0]; 1181 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1]; 1182 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2]; 1183 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3]; 1184 } 1185 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range, 1186 tp_pio->ireg_local_offset, true); 1187 ch_tp_pio++; 1188 } 1189 1190 /* TP_MIB_INDEX */ 1191 if (is_t5(padap->params.chip)) 1192 n = sizeof(t5_tp_mib_index_array) / 1193 (IREG_NUM_ELEM * sizeof(u32)); 1194 else if (is_t6(padap->params.chip)) 1195 n = sizeof(t6_tp_mib_index_array) / 1196 (IREG_NUM_ELEM * sizeof(u32)); 1197 1198 for (i = 0; i < n ; i++) { 1199 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1200 u32 *buff = ch_tp_pio->outbuf; 1201 1202 if (is_t5(padap->params.chip)) { 1203 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0]; 1204 tp_pio->ireg_data = t5_tp_mib_index_array[i][1]; 1205 tp_pio->ireg_local_offset = 1206 t5_tp_mib_index_array[i][2]; 1207 tp_pio->ireg_offset_range = 1208 t5_tp_mib_index_array[i][3]; 1209 } else if (is_t6(padap->params.chip)) { 1210 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0]; 1211 tp_pio->ireg_data = t6_tp_mib_index_array[i][1]; 1212 tp_pio->ireg_local_offset = 1213 t6_tp_mib_index_array[i][2]; 1214 tp_pio->ireg_offset_range = 1215 t6_tp_mib_index_array[i][3]; 1216 } 1217 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range, 1218 tp_pio->ireg_local_offset, true); 1219 ch_tp_pio++; 1220 } 1221 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1222 return rc; 1223 } 1224 1225 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init, 1226 struct cudbg_buffer *dbg_buff, 1227 struct cudbg_error *cudbg_err) 1228 { 1229 struct adapter *padap = pdbg_init->adap; 1230 struct cudbg_buffer temp_buff = { 0 }; 1231 struct ireg_buf *ch_sge_dbg; 1232 int i, rc; 1233 1234 rc = cudbg_get_buff(dbg_buff, sizeof(*ch_sge_dbg) * 2, &temp_buff); 1235 if (rc) 1236 return rc; 1237 1238 ch_sge_dbg = (struct ireg_buf *)temp_buff.data; 1239 for (i = 0; i < 2; i++) { 1240 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio; 1241 u32 *buff = ch_sge_dbg->outbuf; 1242 1243 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0]; 1244 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1]; 1245 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2]; 1246 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3]; 1247 t4_read_indirect(padap, 1248 sge_pio->ireg_addr, 1249 sge_pio->ireg_data, 1250 buff, 1251 sge_pio->ireg_offset_range, 1252 sge_pio->ireg_local_offset); 1253 ch_sge_dbg++; 1254 } 1255 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1256 return rc; 1257 } 1258 1259 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init, 1260 struct cudbg_buffer *dbg_buff, 1261 struct cudbg_error *cudbg_err) 1262 { 1263 struct adapter *padap = pdbg_init->adap; 1264 struct cudbg_buffer temp_buff = { 0 }; 1265 struct cudbg_ulprx_la *ulprx_la_buff; 1266 int rc; 1267 1268 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_ulprx_la), 1269 &temp_buff); 1270 if (rc) 1271 return rc; 1272 1273 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data; 1274 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data); 1275 ulprx_la_buff->size = ULPRX_LA_SIZE; 1276 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1277 return rc; 1278 } 1279 1280 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init, 1281 struct cudbg_buffer *dbg_buff, 1282 struct cudbg_error *cudbg_err) 1283 { 1284 struct adapter *padap = pdbg_init->adap; 1285 struct cudbg_buffer temp_buff = { 0 }; 1286 struct cudbg_tp_la *tp_la_buff; 1287 int size, rc; 1288 1289 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); 1290 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1291 if (rc) 1292 return rc; 1293 1294 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data; 1295 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A)); 1296 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL); 1297 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1298 return rc; 1299 } 1300 1301 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init, 1302 struct cudbg_buffer *dbg_buff, 1303 struct cudbg_error *cudbg_err) 1304 { 1305 struct adapter *padap = pdbg_init->adap; 1306 struct cudbg_buffer temp_buff = { 0 }; 1307 struct cudbg_meminfo *meminfo_buff; 1308 int rc; 1309 1310 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_meminfo), &temp_buff); 1311 if (rc) 1312 return rc; 1313 1314 meminfo_buff = (struct cudbg_meminfo *)temp_buff.data; 1315 rc = cudbg_fill_meminfo(padap, meminfo_buff); 1316 if (rc) { 1317 cudbg_err->sys_err = rc; 1318 cudbg_put_buff(&temp_buff, dbg_buff); 1319 return rc; 1320 } 1321 1322 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1323 return rc; 1324 } 1325 1326 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init, 1327 struct cudbg_buffer *dbg_buff, 1328 struct cudbg_error *cudbg_err) 1329 { 1330 struct cudbg_cim_pif_la *cim_pif_la_buff; 1331 struct adapter *padap = pdbg_init->adap; 1332 struct cudbg_buffer temp_buff = { 0 }; 1333 int size, rc; 1334 1335 size = sizeof(struct cudbg_cim_pif_la) + 1336 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); 1337 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1338 if (rc) 1339 return rc; 1340 1341 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data; 1342 cim_pif_la_buff->size = CIM_PIFLA_SIZE; 1343 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data, 1344 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE, 1345 NULL, NULL); 1346 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1347 return rc; 1348 } 1349 1350 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init, 1351 struct cudbg_buffer *dbg_buff, 1352 struct cudbg_error *cudbg_err) 1353 { 1354 struct adapter *padap = pdbg_init->adap; 1355 struct cudbg_buffer temp_buff = { 0 }; 1356 struct cudbg_clk_info *clk_info_buff; 1357 u64 tp_tick_us; 1358 int rc; 1359 1360 if (!padap->params.vpd.cclk) 1361 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1362 1363 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_clk_info), 1364 &temp_buff); 1365 if (rc) 1366 return rc; 1367 1368 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data; 1369 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */ 1370 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A); 1371 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res); 1372 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res); 1373 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000; 1374 1375 clk_info_buff->dack_timer = 1376 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 * 1377 t4_read_reg(padap, TP_DACK_TIMER_A); 1378 clk_info_buff->retransmit_min = 1379 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A); 1380 clk_info_buff->retransmit_max = 1381 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A); 1382 clk_info_buff->persist_timer_min = 1383 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A); 1384 clk_info_buff->persist_timer_max = 1385 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A); 1386 clk_info_buff->keepalive_idle_timer = 1387 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A); 1388 clk_info_buff->keepalive_interval = 1389 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A); 1390 clk_info_buff->initial_srtt = 1391 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A)); 1392 clk_info_buff->finwait2_timer = 1393 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A); 1394 1395 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1396 return rc; 1397 } 1398 1399 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init, 1400 struct cudbg_buffer *dbg_buff, 1401 struct cudbg_error *cudbg_err) 1402 { 1403 struct adapter *padap = pdbg_init->adap; 1404 struct cudbg_buffer temp_buff = { 0 }; 1405 struct ireg_buf *ch_pcie; 1406 int i, rc, n; 1407 u32 size; 1408 1409 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1410 size = sizeof(struct ireg_buf) * n * 2; 1411 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1412 if (rc) 1413 return rc; 1414 1415 ch_pcie = (struct ireg_buf *)temp_buff.data; 1416 /* PCIE_PDBG */ 1417 for (i = 0; i < n; i++) { 1418 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1419 u32 *buff = ch_pcie->outbuf; 1420 1421 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0]; 1422 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1]; 1423 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2]; 1424 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3]; 1425 t4_read_indirect(padap, 1426 pcie_pio->ireg_addr, 1427 pcie_pio->ireg_data, 1428 buff, 1429 pcie_pio->ireg_offset_range, 1430 pcie_pio->ireg_local_offset); 1431 ch_pcie++; 1432 } 1433 1434 /* PCIE_CDBG */ 1435 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1436 for (i = 0; i < n; i++) { 1437 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1438 u32 *buff = ch_pcie->outbuf; 1439 1440 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0]; 1441 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1]; 1442 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2]; 1443 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3]; 1444 t4_read_indirect(padap, 1445 pcie_pio->ireg_addr, 1446 pcie_pio->ireg_data, 1447 buff, 1448 pcie_pio->ireg_offset_range, 1449 pcie_pio->ireg_local_offset); 1450 ch_pcie++; 1451 } 1452 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1453 return rc; 1454 } 1455 1456 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init, 1457 struct cudbg_buffer *dbg_buff, 1458 struct cudbg_error *cudbg_err) 1459 { 1460 struct adapter *padap = pdbg_init->adap; 1461 struct cudbg_buffer temp_buff = { 0 }; 1462 struct ireg_buf *ch_pm; 1463 int i, rc, n; 1464 u32 size; 1465 1466 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1467 size = sizeof(struct ireg_buf) * n * 2; 1468 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1469 if (rc) 1470 return rc; 1471 1472 ch_pm = (struct ireg_buf *)temp_buff.data; 1473 /* PM_RX */ 1474 for (i = 0; i < n; i++) { 1475 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1476 u32 *buff = ch_pm->outbuf; 1477 1478 pm_pio->ireg_addr = t5_pm_rx_array[i][0]; 1479 pm_pio->ireg_data = t5_pm_rx_array[i][1]; 1480 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2]; 1481 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3]; 1482 t4_read_indirect(padap, 1483 pm_pio->ireg_addr, 1484 pm_pio->ireg_data, 1485 buff, 1486 pm_pio->ireg_offset_range, 1487 pm_pio->ireg_local_offset); 1488 ch_pm++; 1489 } 1490 1491 /* PM_TX */ 1492 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1493 for (i = 0; i < n; i++) { 1494 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1495 u32 *buff = ch_pm->outbuf; 1496 1497 pm_pio->ireg_addr = t5_pm_tx_array[i][0]; 1498 pm_pio->ireg_data = t5_pm_tx_array[i][1]; 1499 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2]; 1500 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3]; 1501 t4_read_indirect(padap, 1502 pm_pio->ireg_addr, 1503 pm_pio->ireg_data, 1504 buff, 1505 pm_pio->ireg_offset_range, 1506 pm_pio->ireg_local_offset); 1507 ch_pm++; 1508 } 1509 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1510 return rc; 1511 } 1512 1513 int cudbg_collect_tid(struct cudbg_init *pdbg_init, 1514 struct cudbg_buffer *dbg_buff, 1515 struct cudbg_error *cudbg_err) 1516 { 1517 struct adapter *padap = pdbg_init->adap; 1518 struct cudbg_tid_info_region_rev1 *tid1; 1519 struct cudbg_buffer temp_buff = { 0 }; 1520 struct cudbg_tid_info_region *tid; 1521 u32 para[2], val[2]; 1522 int rc; 1523 1524 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_tid_info_region_rev1), 1525 &temp_buff); 1526 if (rc) 1527 return rc; 1528 1529 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data; 1530 tid = &tid1->tid; 1531 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE; 1532 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV; 1533 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) - 1534 sizeof(struct cudbg_ver_hdr); 1535 1536 #define FW_PARAM_PFVF_A(param) \ 1537 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 1538 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 1539 FW_PARAMS_PARAM_Y_V(0) | \ 1540 FW_PARAMS_PARAM_Z_V(0)) 1541 1542 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START); 1543 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END); 1544 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val); 1545 if (rc < 0) { 1546 cudbg_err->sys_err = rc; 1547 cudbg_put_buff(&temp_buff, dbg_buff); 1548 return rc; 1549 } 1550 tid->uotid_base = val[0]; 1551 tid->nuotids = val[1] - val[0] + 1; 1552 1553 if (is_t5(padap->params.chip)) { 1554 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4; 1555 } else if (is_t6(padap->params.chip)) { 1556 tid1->tid_start = 1557 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A); 1558 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A); 1559 1560 para[0] = FW_PARAM_PFVF_A(HPFILTER_START); 1561 para[1] = FW_PARAM_PFVF_A(HPFILTER_END); 1562 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, 1563 para, val); 1564 if (rc < 0) { 1565 cudbg_err->sys_err = rc; 1566 cudbg_put_buff(&temp_buff, dbg_buff); 1567 return rc; 1568 } 1569 tid->hpftid_base = val[0]; 1570 tid->nhpftids = val[1] - val[0] + 1; 1571 } 1572 1573 tid->ntids = padap->tids.ntids; 1574 tid->nstids = padap->tids.nstids; 1575 tid->stid_base = padap->tids.stid_base; 1576 tid->hash_base = padap->tids.hash_base; 1577 1578 tid->natids = padap->tids.natids; 1579 tid->nftids = padap->tids.nftids; 1580 tid->ftid_base = padap->tids.ftid_base; 1581 tid->aftid_base = padap->tids.aftid_base; 1582 tid->aftid_end = padap->tids.aftid_end; 1583 1584 tid->sftid_base = padap->tids.sftid_base; 1585 tid->nsftids = padap->tids.nsftids; 1586 1587 tid->flags = padap->flags; 1588 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A); 1589 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A); 1590 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A); 1591 1592 #undef FW_PARAM_PFVF_A 1593 1594 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1595 return rc; 1596 } 1597 1598 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init, 1599 struct cudbg_buffer *dbg_buff, 1600 struct cudbg_error *cudbg_err) 1601 { 1602 struct adapter *padap = pdbg_init->adap; 1603 struct cudbg_buffer temp_buff = { 0 }; 1604 u32 size, *value, j; 1605 int i, rc, n; 1606 1607 size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS; 1608 n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32)); 1609 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1610 if (rc) 1611 return rc; 1612 1613 value = (u32 *)temp_buff.data; 1614 for (i = 0; i < n; i++) { 1615 for (j = t5_pcie_config_array[i][0]; 1616 j <= t5_pcie_config_array[i][1]; j += 4) { 1617 t4_hw_pci_read_cfg4(padap, j, value); 1618 value++; 1619 } 1620 } 1621 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1622 return rc; 1623 } 1624 1625 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type) 1626 { 1627 int index, bit, bit_pos = 0; 1628 1629 switch (type) { 1630 case CTXT_EGRESS: 1631 bit_pos = 176; 1632 break; 1633 case CTXT_INGRESS: 1634 bit_pos = 141; 1635 break; 1636 case CTXT_FLM: 1637 bit_pos = 89; 1638 break; 1639 } 1640 index = bit_pos / 32; 1641 bit = bit_pos % 32; 1642 return buf[index] & (1U << bit); 1643 } 1644 1645 static int cudbg_get_ctxt_region_info(struct adapter *padap, 1646 struct cudbg_region_info *ctx_info, 1647 u8 *mem_type) 1648 { 1649 struct cudbg_mem_desc mem_desc; 1650 struct cudbg_meminfo meminfo; 1651 u32 i, j, value, found; 1652 u8 flq; 1653 int rc; 1654 1655 rc = cudbg_fill_meminfo(padap, &meminfo); 1656 if (rc) 1657 return rc; 1658 1659 /* Get EGRESS and INGRESS context region size */ 1660 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) { 1661 found = 0; 1662 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc)); 1663 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) { 1664 rc = cudbg_get_mem_region(padap, &meminfo, j, 1665 cudbg_region[i], 1666 &mem_desc); 1667 if (!rc) { 1668 found = 1; 1669 rc = cudbg_get_mem_relative(padap, &meminfo, j, 1670 &mem_desc.base, 1671 &mem_desc.limit); 1672 if (rc) { 1673 ctx_info[i].exist = false; 1674 break; 1675 } 1676 ctx_info[i].exist = true; 1677 ctx_info[i].start = mem_desc.base; 1678 ctx_info[i].end = mem_desc.limit; 1679 mem_type[i] = j; 1680 break; 1681 } 1682 } 1683 if (!found) 1684 ctx_info[i].exist = false; 1685 } 1686 1687 /* Get FLM and CNM max qid. */ 1688 value = t4_read_reg(padap, SGE_FLM_CFG_A); 1689 1690 /* Get number of data freelist queues */ 1691 flq = HDRSTARTFLQ_G(value); 1692 ctx_info[CTXT_FLM].exist = true; 1693 ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE; 1694 1695 /* The number of CONM contexts are same as number of freelist 1696 * queues. 1697 */ 1698 ctx_info[CTXT_CNM].exist = true; 1699 ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end; 1700 1701 return 0; 1702 } 1703 1704 int cudbg_dump_context_size(struct adapter *padap) 1705 { 1706 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} }; 1707 u8 mem_type[CTXT_INGRESS + 1] = { 0 }; 1708 u32 i, size = 0; 1709 int rc; 1710 1711 /* Get max valid qid for each type of queue */ 1712 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); 1713 if (rc) 1714 return rc; 1715 1716 for (i = 0; i < CTXT_CNM; i++) { 1717 if (!region_info[i].exist) { 1718 if (i == CTXT_EGRESS || i == CTXT_INGRESS) 1719 size += CUDBG_LOWMEM_MAX_CTXT_QIDS * 1720 SGE_CTXT_SIZE; 1721 continue; 1722 } 1723 1724 size += (region_info[i].end - region_info[i].start + 1) / 1725 SGE_CTXT_SIZE; 1726 } 1727 return size * sizeof(struct cudbg_ch_cntxt); 1728 } 1729 1730 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid, 1731 enum ctxt_type ctype, u32 *data) 1732 { 1733 struct adapter *padap = pdbg_init->adap; 1734 int rc = -1; 1735 1736 /* Under heavy traffic, the SGE Queue contexts registers will be 1737 * frequently accessed by firmware. 1738 * 1739 * To avoid conflicts with firmware, always ask firmware to fetch 1740 * the SGE Queue contexts via mailbox. On failure, fallback to 1741 * accessing hardware registers directly. 1742 */ 1743 if (is_fw_attached(pdbg_init)) 1744 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data); 1745 if (rc) 1746 t4_sge_ctxt_rd_bd(padap, cid, ctype, data); 1747 } 1748 1749 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid, 1750 u8 ctxt_type, 1751 struct cudbg_ch_cntxt **out_buff) 1752 { 1753 struct cudbg_ch_cntxt *buff = *out_buff; 1754 int rc; 1755 u32 j; 1756 1757 for (j = 0; j < max_qid; j++) { 1758 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data); 1759 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type); 1760 if (!rc) 1761 continue; 1762 1763 buff->cntxt_type = ctxt_type; 1764 buff->cntxt_id = j; 1765 buff++; 1766 if (ctxt_type == CTXT_FLM) { 1767 cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data); 1768 buff->cntxt_type = CTXT_CNM; 1769 buff->cntxt_id = j; 1770 buff++; 1771 } 1772 } 1773 1774 *out_buff = buff; 1775 } 1776 1777 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init, 1778 struct cudbg_buffer *dbg_buff, 1779 struct cudbg_error *cudbg_err) 1780 { 1781 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} }; 1782 struct adapter *padap = pdbg_init->adap; 1783 u32 j, size, max_ctx_size, max_ctx_qid; 1784 u8 mem_type[CTXT_INGRESS + 1] = { 0 }; 1785 struct cudbg_buffer temp_buff = { 0 }; 1786 struct cudbg_ch_cntxt *buff; 1787 u64 *dst_off, *src_off; 1788 u8 *ctx_buf; 1789 u8 i, k; 1790 int rc; 1791 1792 /* Get max valid qid for each type of queue */ 1793 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); 1794 if (rc) 1795 return rc; 1796 1797 rc = cudbg_dump_context_size(padap); 1798 if (rc <= 0) 1799 return CUDBG_STATUS_ENTITY_NOT_FOUND; 1800 1801 size = rc; 1802 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1803 if (rc) 1804 return rc; 1805 1806 /* Get buffer with enough space to read the biggest context 1807 * region in memory. 1808 */ 1809 max_ctx_size = max(region_info[CTXT_EGRESS].end - 1810 region_info[CTXT_EGRESS].start + 1, 1811 region_info[CTXT_INGRESS].end - 1812 region_info[CTXT_INGRESS].start + 1); 1813 1814 ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL); 1815 if (!ctx_buf) { 1816 cudbg_put_buff(&temp_buff, dbg_buff); 1817 return -ENOMEM; 1818 } 1819 1820 buff = (struct cudbg_ch_cntxt *)temp_buff.data; 1821 1822 /* Collect EGRESS and INGRESS context data. 1823 * In case of failures, fallback to collecting via FW or 1824 * backdoor access. 1825 */ 1826 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) { 1827 if (!region_info[i].exist) { 1828 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS; 1829 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i, 1830 &buff); 1831 continue; 1832 } 1833 1834 max_ctx_size = region_info[i].end - region_info[i].start + 1; 1835 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE; 1836 1837 t4_sge_ctxt_flush(padap, padap->mbox, i); 1838 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i], 1839 region_info[i].start, max_ctx_size, 1840 (__be32 *)ctx_buf, 1); 1841 if (rc) { 1842 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS; 1843 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i, 1844 &buff); 1845 continue; 1846 } 1847 1848 for (j = 0; j < max_ctx_qid; j++) { 1849 src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE); 1850 dst_off = (u64 *)buff->data; 1851 1852 /* The data is stored in 64-bit cpu order. Convert it 1853 * to big endian before parsing. 1854 */ 1855 for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++) 1856 dst_off[k] = cpu_to_be64(src_off[k]); 1857 1858 rc = cudbg_sge_ctxt_check_valid(buff->data, i); 1859 if (!rc) 1860 continue; 1861 1862 buff->cntxt_type = i; 1863 buff->cntxt_id = j; 1864 buff++; 1865 } 1866 } 1867 1868 kvfree(ctx_buf); 1869 1870 /* Collect FREELIST and CONGESTION MANAGER contexts */ 1871 max_ctx_size = region_info[CTXT_FLM].end - 1872 region_info[CTXT_FLM].start + 1; 1873 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE; 1874 /* Since FLM and CONM are 1-to-1 mapped, the below function 1875 * will fetch both FLM and CONM contexts. 1876 */ 1877 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff); 1878 1879 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1880 return rc; 1881 } 1882 1883 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 1884 { 1885 *mask = x | y; 1886 y = (__force u64)cpu_to_be64(y); 1887 memcpy(addr, (char *)&y + 2, ETH_ALEN); 1888 } 1889 1890 static void cudbg_mps_rpl_backdoor(struct adapter *padap, 1891 struct fw_ldst_mps_rplc *mps_rplc) 1892 { 1893 if (is_t5(padap->params.chip)) { 1894 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 1895 MPS_VF_RPLCT_MAP3_A)); 1896 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 1897 MPS_VF_RPLCT_MAP2_A)); 1898 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 1899 MPS_VF_RPLCT_MAP1_A)); 1900 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 1901 MPS_VF_RPLCT_MAP0_A)); 1902 } else { 1903 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 1904 MPS_VF_RPLCT_MAP7_A)); 1905 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 1906 MPS_VF_RPLCT_MAP6_A)); 1907 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 1908 MPS_VF_RPLCT_MAP5_A)); 1909 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 1910 MPS_VF_RPLCT_MAP4_A)); 1911 } 1912 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A)); 1913 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A)); 1914 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A)); 1915 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A)); 1916 } 1917 1918 static int cudbg_collect_tcam_index(struct adapter *padap, 1919 struct cudbg_mps_tcam *tcam, u32 idx) 1920 { 1921 u64 tcamy, tcamx, val; 1922 u32 ctl, data2; 1923 int rc = 0; 1924 1925 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) { 1926 /* CtlReqID - 1: use Host Driver Requester ID 1927 * CtlCmdType - 0: Read, 1: Write 1928 * CtlTcamSel - 0: TCAM0, 1: TCAM1 1929 * CtlXYBitSel- 0: Y bit, 1: X bit 1930 */ 1931 1932 /* Read tcamy */ 1933 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 1934 if (idx < 256) 1935 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 1936 else 1937 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1); 1938 1939 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1940 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 1941 tcamy = DMACH_G(val) << 32; 1942 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 1943 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 1944 tcam->lookup_type = DATALKPTYPE_G(data2); 1945 1946 /* 0 - Outer header, 1 - Inner header 1947 * [71:48] bit locations are overloaded for 1948 * outer vs. inner lookup types. 1949 */ 1950 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 1951 /* Inner header VNI */ 1952 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 1953 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val); 1954 tcam->dip_hit = data2 & DATADIPHIT_F; 1955 } else { 1956 tcam->vlan_vld = data2 & DATAVIDH2_F; 1957 tcam->ivlan = VIDL_G(val); 1958 } 1959 1960 tcam->port_num = DATAPORTNUM_G(data2); 1961 1962 /* Read tcamx. Change the control param */ 1963 ctl |= CTLXYBITSEL_V(1); 1964 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1965 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 1966 tcamx = DMACH_G(val) << 32; 1967 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 1968 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 1969 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 1970 /* Inner header VNI mask */ 1971 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 1972 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val); 1973 } 1974 } else { 1975 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx)); 1976 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx)); 1977 } 1978 1979 /* If no entry, return */ 1980 if (tcamx & tcamy) 1981 return rc; 1982 1983 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx)); 1984 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx)); 1985 1986 if (is_t5(padap->params.chip)) 1987 tcam->repli = (tcam->cls_lo & REPLICATE_F); 1988 else if (is_t6(padap->params.chip)) 1989 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F); 1990 1991 if (tcam->repli) { 1992 struct fw_ldst_cmd ldst_cmd; 1993 struct fw_ldst_mps_rplc mps_rplc; 1994 1995 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 1996 ldst_cmd.op_to_addrspace = 1997 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 1998 FW_CMD_REQUEST_F | FW_CMD_READ_F | 1999 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS)); 2000 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 2001 ldst_cmd.u.mps.rplc.fid_idx = 2002 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 2003 FW_LDST_CMD_IDX_V(idx)); 2004 2005 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd, sizeof(ldst_cmd), 2006 &ldst_cmd); 2007 if (rc) 2008 cudbg_mps_rpl_backdoor(padap, &mps_rplc); 2009 else 2010 mps_rplc = ldst_cmd.u.mps.rplc; 2011 2012 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0); 2013 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32); 2014 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64); 2015 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96); 2016 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) { 2017 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128); 2018 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160); 2019 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192); 2020 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224); 2021 } 2022 } 2023 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask); 2024 tcam->idx = idx; 2025 tcam->rplc_size = padap->params.arch.mps_rplc_size; 2026 return rc; 2027 } 2028 2029 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init, 2030 struct cudbg_buffer *dbg_buff, 2031 struct cudbg_error *cudbg_err) 2032 { 2033 struct adapter *padap = pdbg_init->adap; 2034 struct cudbg_buffer temp_buff = { 0 }; 2035 u32 size = 0, i, n, total_size = 0; 2036 struct cudbg_mps_tcam *tcam; 2037 int rc; 2038 2039 n = padap->params.arch.mps_tcam_size; 2040 size = sizeof(struct cudbg_mps_tcam) * n; 2041 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2042 if (rc) 2043 return rc; 2044 2045 tcam = (struct cudbg_mps_tcam *)temp_buff.data; 2046 for (i = 0; i < n; i++) { 2047 rc = cudbg_collect_tcam_index(padap, tcam, i); 2048 if (rc) { 2049 cudbg_err->sys_err = rc; 2050 cudbg_put_buff(&temp_buff, dbg_buff); 2051 return rc; 2052 } 2053 total_size += sizeof(struct cudbg_mps_tcam); 2054 tcam++; 2055 } 2056 2057 if (!total_size) { 2058 rc = CUDBG_SYSTEM_ERROR; 2059 cudbg_err->sys_err = rc; 2060 cudbg_put_buff(&temp_buff, dbg_buff); 2061 return rc; 2062 } 2063 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2064 return rc; 2065 } 2066 2067 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init, 2068 struct cudbg_buffer *dbg_buff, 2069 struct cudbg_error *cudbg_err) 2070 { 2071 struct adapter *padap = pdbg_init->adap; 2072 struct cudbg_buffer temp_buff = { 0 }; 2073 char vpd_str[CUDBG_VPD_VER_LEN + 1]; 2074 u32 scfg_vers, vpd_vers, fw_vers; 2075 struct cudbg_vpd_data *vpd_data; 2076 struct vpd_params vpd = { 0 }; 2077 int rc, ret; 2078 2079 rc = t4_get_raw_vpd_params(padap, &vpd); 2080 if (rc) 2081 return rc; 2082 2083 rc = t4_get_fw_version(padap, &fw_vers); 2084 if (rc) 2085 return rc; 2086 2087 /* Serial Configuration Version is located beyond the PF's vpd size. 2088 * Temporarily give access to entire EEPROM to get it. 2089 */ 2090 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE); 2091 if (rc < 0) 2092 return rc; 2093 2094 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN, 2095 &scfg_vers); 2096 2097 /* Restore back to original PF's vpd size */ 2098 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE); 2099 if (rc < 0) 2100 return rc; 2101 2102 if (ret) 2103 return ret; 2104 2105 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN, 2106 vpd_str); 2107 if (rc) 2108 return rc; 2109 2110 vpd_str[CUDBG_VPD_VER_LEN] = '\0'; 2111 rc = kstrtouint(vpd_str, 0, &vpd_vers); 2112 if (rc) 2113 return rc; 2114 2115 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_vpd_data), 2116 &temp_buff); 2117 if (rc) 2118 return rc; 2119 2120 vpd_data = (struct cudbg_vpd_data *)temp_buff.data; 2121 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1); 2122 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1); 2123 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1); 2124 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1); 2125 vpd_data->scfg_vers = scfg_vers; 2126 vpd_data->vpd_vers = vpd_vers; 2127 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers); 2128 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers); 2129 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers); 2130 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers); 2131 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2132 return rc; 2133 } 2134 2135 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid, 2136 struct cudbg_tid_data *tid_data) 2137 { 2138 struct adapter *padap = pdbg_init->adap; 2139 int i, cmd_retry = 8; 2140 u32 val; 2141 2142 /* Fill REQ_DATA regs with 0's */ 2143 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++) 2144 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0); 2145 2146 /* Write DBIG command */ 2147 val = DBGICMD_V(4) | DBGITID_V(tid); 2148 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val); 2149 tid_data->dbig_cmd = val; 2150 2151 val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */ 2152 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val); 2153 tid_data->dbig_conf = val; 2154 2155 /* Poll the DBGICMDBUSY bit */ 2156 val = 1; 2157 while (val) { 2158 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A); 2159 val = val & DBGICMDBUSY_F; 2160 cmd_retry--; 2161 if (!cmd_retry) 2162 return CUDBG_SYSTEM_ERROR; 2163 } 2164 2165 /* Check RESP status */ 2166 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A); 2167 tid_data->dbig_rsp_stat = val; 2168 if (!(val & 1)) 2169 return CUDBG_SYSTEM_ERROR; 2170 2171 /* Read RESP data */ 2172 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++) 2173 tid_data->data[i] = t4_read_reg(padap, 2174 LE_DB_DBGI_RSP_DATA_A + 2175 (i << 2)); 2176 tid_data->tid = tid; 2177 return 0; 2178 } 2179 2180 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region) 2181 { 2182 int type = LE_ET_UNKNOWN; 2183 2184 if (tid < tcam_region.server_start) 2185 type = LE_ET_TCAM_CON; 2186 else if (tid < tcam_region.filter_start) 2187 type = LE_ET_TCAM_SERVER; 2188 else if (tid < tcam_region.clip_start) 2189 type = LE_ET_TCAM_FILTER; 2190 else if (tid < tcam_region.routing_start) 2191 type = LE_ET_TCAM_CLIP; 2192 else if (tid < tcam_region.tid_hash_base) 2193 type = LE_ET_TCAM_ROUTING; 2194 else if (tid < tcam_region.max_tid) 2195 type = LE_ET_HASH_CON; 2196 else 2197 type = LE_ET_INVALID_TID; 2198 2199 return type; 2200 } 2201 2202 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data, 2203 struct cudbg_tcam tcam_region) 2204 { 2205 int ipv6 = 0; 2206 int le_type; 2207 2208 le_type = cudbg_get_le_type(tid_data->tid, tcam_region); 2209 if (tid_data->tid & 1) 2210 return 0; 2211 2212 if (le_type == LE_ET_HASH_CON) { 2213 ipv6 = tid_data->data[16] & 0x8000; 2214 } else if (le_type == LE_ET_TCAM_CON) { 2215 ipv6 = tid_data->data[16] & 0x8000; 2216 if (ipv6) 2217 ipv6 = tid_data->data[9] == 0x00C00000; 2218 } else { 2219 ipv6 = 0; 2220 } 2221 return ipv6; 2222 } 2223 2224 void cudbg_fill_le_tcam_info(struct adapter *padap, 2225 struct cudbg_tcam *tcam_region) 2226 { 2227 u32 value; 2228 2229 /* Get the LE regions */ 2230 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */ 2231 tcam_region->tid_hash_base = value; 2232 2233 /* Get routing table index */ 2234 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A); 2235 tcam_region->routing_start = value; 2236 2237 /*Get clip table index */ 2238 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A); 2239 tcam_region->clip_start = value; 2240 2241 /* Get filter table index */ 2242 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A); 2243 tcam_region->filter_start = value; 2244 2245 /* Get server table index */ 2246 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A); 2247 tcam_region->server_start = value; 2248 2249 /* Check whether hash is enabled and calculate the max tids */ 2250 value = t4_read_reg(padap, LE_DB_CONFIG_A); 2251 if ((value >> HASHEN_S) & 1) { 2252 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A); 2253 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { 2254 tcam_region->max_tid = (value & 0xFFFFF) + 2255 tcam_region->tid_hash_base; 2256 } else { 2257 value = HASHTIDSIZE_G(value); 2258 value = 1 << value; 2259 tcam_region->max_tid = value + 2260 tcam_region->tid_hash_base; 2261 } 2262 } else { /* hash not enabled */ 2263 tcam_region->max_tid = CUDBG_MAX_TCAM_TID; 2264 } 2265 } 2266 2267 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init, 2268 struct cudbg_buffer *dbg_buff, 2269 struct cudbg_error *cudbg_err) 2270 { 2271 struct adapter *padap = pdbg_init->adap; 2272 struct cudbg_buffer temp_buff = { 0 }; 2273 struct cudbg_tcam tcam_region = { 0 }; 2274 struct cudbg_tid_data *tid_data; 2275 u32 bytes = 0; 2276 int rc, size; 2277 u32 i; 2278 2279 cudbg_fill_le_tcam_info(padap, &tcam_region); 2280 2281 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid; 2282 size += sizeof(struct cudbg_tcam); 2283 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2284 if (rc) 2285 return rc; 2286 2287 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam)); 2288 bytes = sizeof(struct cudbg_tcam); 2289 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes); 2290 /* read all tid */ 2291 for (i = 0; i < tcam_region.max_tid; ) { 2292 rc = cudbg_read_tid(pdbg_init, i, tid_data); 2293 if (rc) { 2294 cudbg_err->sys_err = rc; 2295 cudbg_put_buff(&temp_buff, dbg_buff); 2296 return rc; 2297 } 2298 2299 /* ipv6 takes two tids */ 2300 cudbg_is_ipv6_entry(tid_data, tcam_region) ? i += 2 : i++; 2301 2302 tid_data++; 2303 bytes += sizeof(struct cudbg_tid_data); 2304 } 2305 2306 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2307 return rc; 2308 } 2309 2310 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init, 2311 struct cudbg_buffer *dbg_buff, 2312 struct cudbg_error *cudbg_err) 2313 { 2314 struct adapter *padap = pdbg_init->adap; 2315 struct cudbg_buffer temp_buff = { 0 }; 2316 u32 size; 2317 int rc; 2318 2319 size = sizeof(u16) * NMTUS * NCCTRL_WIN; 2320 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2321 if (rc) 2322 return rc; 2323 2324 t4_read_cong_tbl(padap, (void *)temp_buff.data); 2325 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2326 return rc; 2327 } 2328 2329 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init, 2330 struct cudbg_buffer *dbg_buff, 2331 struct cudbg_error *cudbg_err) 2332 { 2333 struct adapter *padap = pdbg_init->adap; 2334 struct cudbg_buffer temp_buff = { 0 }; 2335 struct ireg_buf *ma_indr; 2336 int i, rc, n; 2337 u32 size, j; 2338 2339 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2340 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2341 2342 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2343 size = sizeof(struct ireg_buf) * n * 2; 2344 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2345 if (rc) 2346 return rc; 2347 2348 ma_indr = (struct ireg_buf *)temp_buff.data; 2349 for (i = 0; i < n; i++) { 2350 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2351 u32 *buff = ma_indr->outbuf; 2352 2353 ma_fli->ireg_addr = t6_ma_ireg_array[i][0]; 2354 ma_fli->ireg_data = t6_ma_ireg_array[i][1]; 2355 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2]; 2356 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3]; 2357 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data, 2358 buff, ma_fli->ireg_offset_range, 2359 ma_fli->ireg_local_offset); 2360 ma_indr++; 2361 } 2362 2363 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32)); 2364 for (i = 0; i < n; i++) { 2365 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2366 u32 *buff = ma_indr->outbuf; 2367 2368 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0]; 2369 ma_fli->ireg_data = t6_ma_ireg_array2[i][1]; 2370 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2]; 2371 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) { 2372 t4_read_indirect(padap, ma_fli->ireg_addr, 2373 ma_fli->ireg_data, buff, 1, 2374 ma_fli->ireg_local_offset); 2375 buff++; 2376 ma_fli->ireg_local_offset += 0x20; 2377 } 2378 ma_indr++; 2379 } 2380 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2381 return rc; 2382 } 2383 2384 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init, 2385 struct cudbg_buffer *dbg_buff, 2386 struct cudbg_error *cudbg_err) 2387 { 2388 struct adapter *padap = pdbg_init->adap; 2389 struct cudbg_buffer temp_buff = { 0 }; 2390 struct cudbg_ulptx_la *ulptx_la_buff; 2391 u32 i, j; 2392 int rc; 2393 2394 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_ulptx_la), 2395 &temp_buff); 2396 if (rc) 2397 return rc; 2398 2399 ulptx_la_buff = (struct cudbg_ulptx_la *)temp_buff.data; 2400 for (i = 0; i < CUDBG_NUM_ULPTX; i++) { 2401 ulptx_la_buff->rdptr[i] = t4_read_reg(padap, 2402 ULP_TX_LA_RDPTR_0_A + 2403 0x10 * i); 2404 ulptx_la_buff->wrptr[i] = t4_read_reg(padap, 2405 ULP_TX_LA_WRPTR_0_A + 2406 0x10 * i); 2407 ulptx_la_buff->rddata[i] = t4_read_reg(padap, 2408 ULP_TX_LA_RDDATA_0_A + 2409 0x10 * i); 2410 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++) 2411 ulptx_la_buff->rd_data[i][j] = 2412 t4_read_reg(padap, 2413 ULP_TX_LA_RDDATA_0_A + 0x10 * i); 2414 } 2415 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2416 return rc; 2417 } 2418 2419 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init, 2420 struct cudbg_buffer *dbg_buff, 2421 struct cudbg_error *cudbg_err) 2422 { 2423 struct adapter *padap = pdbg_init->adap; 2424 struct cudbg_buffer temp_buff = { 0 }; 2425 struct ireg_buf *up_cim; 2426 int i, rc, n; 2427 u32 size; 2428 2429 n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2430 size = sizeof(struct ireg_buf) * n; 2431 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2432 if (rc) 2433 return rc; 2434 2435 up_cim = (struct ireg_buf *)temp_buff.data; 2436 for (i = 0; i < n; i++) { 2437 struct ireg_field *up_cim_reg = &up_cim->tp_pio; 2438 u32 *buff = up_cim->outbuf; 2439 2440 if (is_t5(padap->params.chip)) { 2441 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0]; 2442 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1]; 2443 up_cim_reg->ireg_local_offset = 2444 t5_up_cim_reg_array[i][2]; 2445 up_cim_reg->ireg_offset_range = 2446 t5_up_cim_reg_array[i][3]; 2447 } else if (is_t6(padap->params.chip)) { 2448 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0]; 2449 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1]; 2450 up_cim_reg->ireg_local_offset = 2451 t6_up_cim_reg_array[i][2]; 2452 up_cim_reg->ireg_offset_range = 2453 t6_up_cim_reg_array[i][3]; 2454 } 2455 2456 rc = t4_cim_read(padap, up_cim_reg->ireg_local_offset, 2457 up_cim_reg->ireg_offset_range, buff); 2458 if (rc) { 2459 cudbg_put_buff(&temp_buff, dbg_buff); 2460 return rc; 2461 } 2462 up_cim++; 2463 } 2464 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2465 return rc; 2466 } 2467 2468 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init, 2469 struct cudbg_buffer *dbg_buff, 2470 struct cudbg_error *cudbg_err) 2471 { 2472 struct adapter *padap = pdbg_init->adap; 2473 struct cudbg_buffer temp_buff = { 0 }; 2474 struct cudbg_pbt_tables *pbt; 2475 int i, rc; 2476 u32 addr; 2477 2478 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pbt_tables), 2479 &temp_buff); 2480 if (rc) 2481 return rc; 2482 2483 pbt = (struct cudbg_pbt_tables *)temp_buff.data; 2484 /* PBT dynamic entries */ 2485 addr = CUDBG_CHAC_PBT_ADDR; 2486 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) { 2487 rc = t4_cim_read(padap, addr + (i * 4), 1, 2488 &pbt->pbt_dynamic[i]); 2489 if (rc) { 2490 cudbg_err->sys_err = rc; 2491 cudbg_put_buff(&temp_buff, dbg_buff); 2492 return rc; 2493 } 2494 } 2495 2496 /* PBT static entries */ 2497 /* static entries start when bit 6 is set */ 2498 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6); 2499 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) { 2500 rc = t4_cim_read(padap, addr + (i * 4), 1, 2501 &pbt->pbt_static[i]); 2502 if (rc) { 2503 cudbg_err->sys_err = rc; 2504 cudbg_put_buff(&temp_buff, dbg_buff); 2505 return rc; 2506 } 2507 } 2508 2509 /* LRF entries */ 2510 addr = CUDBG_CHAC_PBT_LRF; 2511 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) { 2512 rc = t4_cim_read(padap, addr + (i * 4), 1, 2513 &pbt->lrf_table[i]); 2514 if (rc) { 2515 cudbg_err->sys_err = rc; 2516 cudbg_put_buff(&temp_buff, dbg_buff); 2517 return rc; 2518 } 2519 } 2520 2521 /* PBT data entries */ 2522 addr = CUDBG_CHAC_PBT_DATA; 2523 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) { 2524 rc = t4_cim_read(padap, addr + (i * 4), 1, 2525 &pbt->pbt_data[i]); 2526 if (rc) { 2527 cudbg_err->sys_err = rc; 2528 cudbg_put_buff(&temp_buff, dbg_buff); 2529 return rc; 2530 } 2531 } 2532 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2533 return rc; 2534 } 2535 2536 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init, 2537 struct cudbg_buffer *dbg_buff, 2538 struct cudbg_error *cudbg_err) 2539 { 2540 struct adapter *padap = pdbg_init->adap; 2541 struct cudbg_mbox_log *mboxlog = NULL; 2542 struct cudbg_buffer temp_buff = { 0 }; 2543 struct mbox_cmd_log *log = NULL; 2544 struct mbox_cmd *entry; 2545 unsigned int entry_idx; 2546 u16 mbox_cmds; 2547 int i, k, rc; 2548 u64 flit; 2549 u32 size; 2550 2551 log = padap->mbox_log; 2552 mbox_cmds = padap->mbox_log->size; 2553 size = sizeof(struct cudbg_mbox_log) * mbox_cmds; 2554 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2555 if (rc) 2556 return rc; 2557 2558 mboxlog = (struct cudbg_mbox_log *)temp_buff.data; 2559 for (k = 0; k < mbox_cmds; k++) { 2560 entry_idx = log->cursor + k; 2561 if (entry_idx >= log->size) 2562 entry_idx -= log->size; 2563 2564 entry = mbox_cmd_log_entry(log, entry_idx); 2565 /* skip over unused entries */ 2566 if (entry->timestamp == 0) 2567 continue; 2568 2569 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd)); 2570 for (i = 0; i < MBOX_LEN / 8; i++) { 2571 flit = entry->cmd[i]; 2572 mboxlog->hi[i] = (u32)(flit >> 32); 2573 mboxlog->lo[i] = (u32)flit; 2574 } 2575 mboxlog++; 2576 } 2577 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2578 return rc; 2579 } 2580 2581 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init, 2582 struct cudbg_buffer *dbg_buff, 2583 struct cudbg_error *cudbg_err) 2584 { 2585 struct adapter *padap = pdbg_init->adap; 2586 struct cudbg_buffer temp_buff = { 0 }; 2587 struct ireg_buf *hma_indr; 2588 int i, rc, n; 2589 u32 size; 2590 2591 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2592 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2593 2594 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2595 size = sizeof(struct ireg_buf) * n; 2596 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2597 if (rc) 2598 return rc; 2599 2600 hma_indr = (struct ireg_buf *)temp_buff.data; 2601 for (i = 0; i < n; i++) { 2602 struct ireg_field *hma_fli = &hma_indr->tp_pio; 2603 u32 *buff = hma_indr->outbuf; 2604 2605 hma_fli->ireg_addr = t6_hma_ireg_array[i][0]; 2606 hma_fli->ireg_data = t6_hma_ireg_array[i][1]; 2607 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2]; 2608 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3]; 2609 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data, 2610 buff, hma_fli->ireg_offset_range, 2611 hma_fli->ireg_local_offset); 2612 hma_indr++; 2613 } 2614 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2615 return rc; 2616 } 2617