1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #include <linux/sort.h> 19 20 #include "t4_regs.h" 21 #include "cxgb4.h" 22 #include "cudbg_if.h" 23 #include "cudbg_lib_common.h" 24 #include "cudbg_entity.h" 25 #include "cudbg_lib.h" 26 27 static void cudbg_write_and_release_buff(struct cudbg_buffer *pin_buff, 28 struct cudbg_buffer *dbg_buff) 29 { 30 cudbg_update_buff(pin_buff, dbg_buff); 31 cudbg_put_buff(pin_buff, dbg_buff); 32 } 33 34 static int is_fw_attached(struct cudbg_init *pdbg_init) 35 { 36 struct adapter *padap = pdbg_init->adap; 37 38 if (!(padap->flags & FW_OK) || padap->use_bd) 39 return 0; 40 41 return 1; 42 } 43 44 /* This function will add additional padding bytes into debug_buffer to make it 45 * 4 byte aligned. 46 */ 47 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff, 48 struct cudbg_entity_hdr *entity_hdr) 49 { 50 u8 zero_buf[4] = {0}; 51 u8 padding, remain; 52 53 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4; 54 padding = 4 - remain; 55 if (remain) { 56 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf, 57 padding); 58 dbg_buff->offset += padding; 59 entity_hdr->num_pad = padding; 60 } 61 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset; 62 } 63 64 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i) 65 { 66 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf; 67 68 return (struct cudbg_entity_hdr *) 69 ((char *)outbuf + cudbg_hdr->hdr_len + 70 (sizeof(struct cudbg_entity_hdr) * (i - 1))); 71 } 72 73 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len, 74 void *dest) 75 { 76 int vaddr, rc; 77 78 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE); 79 if (vaddr < 0) 80 return vaddr; 81 82 rc = pci_read_vpd(padap->pdev, vaddr, len, dest); 83 if (rc < 0) 84 return rc; 85 86 return 0; 87 } 88 89 static int cudbg_mem_desc_cmp(const void *a, const void *b) 90 { 91 return ((const struct cudbg_mem_desc *)a)->base - 92 ((const struct cudbg_mem_desc *)b)->base; 93 } 94 95 int cudbg_fill_meminfo(struct adapter *padap, 96 struct cudbg_meminfo *meminfo_buff) 97 { 98 struct cudbg_mem_desc *md; 99 u32 lo, hi, used, alloc; 100 int n, i; 101 102 memset(meminfo_buff->avail, 0, 103 ARRAY_SIZE(meminfo_buff->avail) * 104 sizeof(struct cudbg_mem_desc)); 105 memset(meminfo_buff->mem, 0, 106 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc)); 107 md = meminfo_buff->mem; 108 109 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) { 110 meminfo_buff->mem[i].limit = 0; 111 meminfo_buff->mem[i].idx = i; 112 } 113 114 /* Find and sort the populated memory ranges */ 115 i = 0; 116 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A); 117 if (lo & EDRAM0_ENABLE_F) { 118 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A); 119 meminfo_buff->avail[i].base = 120 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi)); 121 meminfo_buff->avail[i].limit = 122 meminfo_buff->avail[i].base + 123 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi)); 124 meminfo_buff->avail[i].idx = 0; 125 i++; 126 } 127 128 if (lo & EDRAM1_ENABLE_F) { 129 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A); 130 meminfo_buff->avail[i].base = 131 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi)); 132 meminfo_buff->avail[i].limit = 133 meminfo_buff->avail[i].base + 134 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi)); 135 meminfo_buff->avail[i].idx = 1; 136 i++; 137 } 138 139 if (is_t5(padap->params.chip)) { 140 if (lo & EXT_MEM0_ENABLE_F) { 141 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A); 142 meminfo_buff->avail[i].base = 143 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 144 meminfo_buff->avail[i].limit = 145 meminfo_buff->avail[i].base + 146 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 147 meminfo_buff->avail[i].idx = 3; 148 i++; 149 } 150 151 if (lo & EXT_MEM1_ENABLE_F) { 152 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 153 meminfo_buff->avail[i].base = 154 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 155 meminfo_buff->avail[i].limit = 156 meminfo_buff->avail[i].base + 157 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 158 meminfo_buff->avail[i].idx = 4; 159 i++; 160 } 161 } else { 162 if (lo & EXT_MEM_ENABLE_F) { 163 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A); 164 meminfo_buff->avail[i].base = 165 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 166 meminfo_buff->avail[i].limit = 167 meminfo_buff->avail[i].base + 168 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 169 meminfo_buff->avail[i].idx = 2; 170 i++; 171 } 172 173 if (lo & HMA_MUX_F) { 174 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 175 meminfo_buff->avail[i].base = 176 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 177 meminfo_buff->avail[i].limit = 178 meminfo_buff->avail[i].base + 179 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 180 meminfo_buff->avail[i].idx = 5; 181 i++; 182 } 183 } 184 185 if (!i) /* no memory available */ 186 return CUDBG_STATUS_ENTITY_NOT_FOUND; 187 188 meminfo_buff->avail_c = i; 189 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc), 190 cudbg_mem_desc_cmp, NULL); 191 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); 192 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); 193 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); 194 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A); 195 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A); 196 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A); 197 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A); 198 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A); 199 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A); 200 201 /* the next few have explicit upper bounds */ 202 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A); 203 md->limit = md->base - 1 + 204 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) * 205 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A)); 206 md++; 207 208 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A); 209 md->limit = md->base - 1 + 210 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) * 211 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A)); 212 md++; 213 214 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) { 215 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) { 216 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4; 217 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 218 } else { 219 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 220 md->base = t4_read_reg(padap, 221 LE_DB_HASH_TBL_BASE_ADDR_A); 222 } 223 md->limit = 0; 224 } else { 225 md->base = 0; 226 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 227 } 228 md++; 229 230 #define ulp_region(reg) do { \ 231 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ 232 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\ 233 } while (0) 234 235 ulp_region(RX_ISCSI); 236 ulp_region(RX_TDDP); 237 ulp_region(TX_TPT); 238 ulp_region(RX_STAG); 239 ulp_region(RX_RQ); 240 ulp_region(RX_RQUDP); 241 ulp_region(RX_PBL); 242 ulp_region(TX_PBL); 243 #undef ulp_region 244 md->base = 0; 245 md->idx = ARRAY_SIZE(cudbg_region); 246 if (!is_t4(padap->params.chip)) { 247 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A); 248 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A); 249 u32 size = 0; 250 251 if (is_t5(padap->params.chip)) { 252 if (sge_ctrl & VFIFO_ENABLE_F) 253 size = DBVFIFO_SIZE_G(fifo_size); 254 } else { 255 size = T6_DBVFIFO_SIZE_G(fifo_size); 256 } 257 258 if (size) { 259 md->base = BASEADDR_G(t4_read_reg(padap, 260 SGE_DBVFIFO_BADDR_A)); 261 md->limit = md->base + (size << 2) - 1; 262 } 263 } 264 265 md++; 266 267 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A); 268 md->limit = 0; 269 md++; 270 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A); 271 md->limit = 0; 272 md++; 273 274 md->base = padap->vres.ocq.start; 275 if (padap->vres.ocq.size) 276 md->limit = md->base + padap->vres.ocq.size - 1; 277 else 278 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 279 md++; 280 281 /* add any address-space holes, there can be up to 3 */ 282 for (n = 0; n < i - 1; n++) 283 if (meminfo_buff->avail[n].limit < 284 meminfo_buff->avail[n + 1].base) 285 (md++)->base = meminfo_buff->avail[n].limit; 286 287 if (meminfo_buff->avail[n].limit) 288 (md++)->base = meminfo_buff->avail[n].limit; 289 290 n = md - meminfo_buff->mem; 291 meminfo_buff->mem_c = n; 292 293 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc), 294 cudbg_mem_desc_cmp, NULL); 295 296 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A); 297 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1; 298 meminfo_buff->up_ram_lo = lo; 299 meminfo_buff->up_ram_hi = hi; 300 301 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A); 302 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1; 303 meminfo_buff->up_extmem2_lo = lo; 304 meminfo_buff->up_extmem2_hi = hi; 305 306 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A); 307 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo); 308 meminfo_buff->rx_pages_data[1] = 309 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10; 310 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1; 311 312 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A); 313 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A); 314 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo); 315 meminfo_buff->tx_pages_data[1] = 316 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10); 317 meminfo_buff->tx_pages_data[2] = 318 hi >= (1 << 20) ? 'M' : 'K'; 319 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo); 320 321 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A); 322 323 for (i = 0; i < 4; i++) { 324 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 325 lo = t4_read_reg(padap, 326 MPS_RX_MAC_BG_PG_CNT0_A + i * 4); 327 else 328 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4); 329 if (is_t5(padap->params.chip)) { 330 used = T5_USED_G(lo); 331 alloc = T5_ALLOC_G(lo); 332 } else { 333 used = USED_G(lo); 334 alloc = ALLOC_G(lo); 335 } 336 meminfo_buff->port_used[i] = used; 337 meminfo_buff->port_alloc[i] = alloc; 338 } 339 340 for (i = 0; i < padap->params.arch.nchan; i++) { 341 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 342 lo = t4_read_reg(padap, 343 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4); 344 else 345 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4); 346 if (is_t5(padap->params.chip)) { 347 used = T5_USED_G(lo); 348 alloc = T5_ALLOC_G(lo); 349 } else { 350 used = USED_G(lo); 351 alloc = ALLOC_G(lo); 352 } 353 meminfo_buff->loopback_used[i] = used; 354 meminfo_buff->loopback_alloc[i] = alloc; 355 } 356 357 return 0; 358 } 359 360 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init, 361 struct cudbg_buffer *dbg_buff, 362 struct cudbg_error *cudbg_err) 363 { 364 struct adapter *padap = pdbg_init->adap; 365 struct cudbg_buffer temp_buff = { 0 }; 366 u32 buf_size = 0; 367 int rc = 0; 368 369 if (is_t4(padap->params.chip)) 370 buf_size = T4_REGMAP_SIZE; 371 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip)) 372 buf_size = T5_REGMAP_SIZE; 373 374 rc = cudbg_get_buff(dbg_buff, buf_size, &temp_buff); 375 if (rc) 376 return rc; 377 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size); 378 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 379 return rc; 380 } 381 382 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init, 383 struct cudbg_buffer *dbg_buff, 384 struct cudbg_error *cudbg_err) 385 { 386 struct adapter *padap = pdbg_init->adap; 387 struct cudbg_buffer temp_buff = { 0 }; 388 struct devlog_params *dparams; 389 int rc = 0; 390 391 rc = t4_init_devlog_params(padap); 392 if (rc < 0) { 393 cudbg_err->sys_err = rc; 394 return rc; 395 } 396 397 dparams = &padap->params.devlog; 398 rc = cudbg_get_buff(dbg_buff, dparams->size, &temp_buff); 399 if (rc) 400 return rc; 401 402 /* Collect FW devlog */ 403 if (dparams->start != 0) { 404 spin_lock(&padap->win0_lock); 405 rc = t4_memory_rw(padap, padap->params.drv_memwin, 406 dparams->memtype, dparams->start, 407 dparams->size, 408 (__be32 *)(char *)temp_buff.data, 409 1); 410 spin_unlock(&padap->win0_lock); 411 if (rc) { 412 cudbg_err->sys_err = rc; 413 cudbg_put_buff(&temp_buff, dbg_buff); 414 return rc; 415 } 416 } 417 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 418 return rc; 419 } 420 421 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init, 422 struct cudbg_buffer *dbg_buff, 423 struct cudbg_error *cudbg_err) 424 { 425 struct adapter *padap = pdbg_init->adap; 426 struct cudbg_buffer temp_buff = { 0 }; 427 int size, rc; 428 u32 cfg = 0; 429 430 if (is_t6(padap->params.chip)) { 431 size = padap->params.cim_la_size / 10 + 1; 432 size *= 11 * sizeof(u32); 433 } else { 434 size = padap->params.cim_la_size / 8; 435 size *= 8 * sizeof(u32); 436 } 437 438 size += sizeof(cfg); 439 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 440 if (rc) 441 return rc; 442 443 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 444 if (rc) { 445 cudbg_err->sys_err = rc; 446 cudbg_put_buff(&temp_buff, dbg_buff); 447 return rc; 448 } 449 450 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg)); 451 rc = t4_cim_read_la(padap, 452 (u32 *)((char *)temp_buff.data + sizeof(cfg)), 453 NULL); 454 if (rc < 0) { 455 cudbg_err->sys_err = rc; 456 cudbg_put_buff(&temp_buff, dbg_buff); 457 return rc; 458 } 459 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 460 return rc; 461 } 462 463 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init, 464 struct cudbg_buffer *dbg_buff, 465 struct cudbg_error *cudbg_err) 466 { 467 struct adapter *padap = pdbg_init->adap; 468 struct cudbg_buffer temp_buff = { 0 }; 469 int size, rc; 470 471 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); 472 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 473 if (rc) 474 return rc; 475 476 t4_cim_read_ma_la(padap, 477 (u32 *)temp_buff.data, 478 (u32 *)((char *)temp_buff.data + 479 5 * CIM_MALA_SIZE)); 480 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 481 return rc; 482 } 483 484 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init, 485 struct cudbg_buffer *dbg_buff, 486 struct cudbg_error *cudbg_err) 487 { 488 struct adapter *padap = pdbg_init->adap; 489 struct cudbg_buffer temp_buff = { 0 }; 490 struct cudbg_cim_qcfg *cim_qcfg_data; 491 int rc; 492 493 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_cim_qcfg), 494 &temp_buff); 495 if (rc) 496 return rc; 497 498 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data; 499 cim_qcfg_data->chip = padap->params.chip; 500 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A, 501 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat); 502 if (rc) { 503 cudbg_err->sys_err = rc; 504 cudbg_put_buff(&temp_buff, dbg_buff); 505 return rc; 506 } 507 508 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A, 509 ARRAY_SIZE(cim_qcfg_data->obq_wr), 510 cim_qcfg_data->obq_wr); 511 if (rc) { 512 cudbg_err->sys_err = rc; 513 cudbg_put_buff(&temp_buff, dbg_buff); 514 return rc; 515 } 516 517 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size, 518 cim_qcfg_data->thres); 519 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 520 return rc; 521 } 522 523 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init, 524 struct cudbg_buffer *dbg_buff, 525 struct cudbg_error *cudbg_err, int qid) 526 { 527 struct adapter *padap = pdbg_init->adap; 528 struct cudbg_buffer temp_buff = { 0 }; 529 int no_of_read_words, rc = 0; 530 u32 qsize; 531 532 /* collect CIM IBQ */ 533 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32); 534 rc = cudbg_get_buff(dbg_buff, qsize, &temp_buff); 535 if (rc) 536 return rc; 537 538 /* t4_read_cim_ibq will return no. of read words or error */ 539 no_of_read_words = t4_read_cim_ibq(padap, qid, 540 (u32 *)temp_buff.data, qsize); 541 /* no_of_read_words is less than or equal to 0 means error */ 542 if (no_of_read_words <= 0) { 543 if (!no_of_read_words) 544 rc = CUDBG_SYSTEM_ERROR; 545 else 546 rc = no_of_read_words; 547 cudbg_err->sys_err = rc; 548 cudbg_put_buff(&temp_buff, dbg_buff); 549 return rc; 550 } 551 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 552 return rc; 553 } 554 555 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init, 556 struct cudbg_buffer *dbg_buff, 557 struct cudbg_error *cudbg_err) 558 { 559 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0); 560 } 561 562 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init, 563 struct cudbg_buffer *dbg_buff, 564 struct cudbg_error *cudbg_err) 565 { 566 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1); 567 } 568 569 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init, 570 struct cudbg_buffer *dbg_buff, 571 struct cudbg_error *cudbg_err) 572 { 573 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2); 574 } 575 576 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init, 577 struct cudbg_buffer *dbg_buff, 578 struct cudbg_error *cudbg_err) 579 { 580 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3); 581 } 582 583 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init, 584 struct cudbg_buffer *dbg_buff, 585 struct cudbg_error *cudbg_err) 586 { 587 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4); 588 } 589 590 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init, 591 struct cudbg_buffer *dbg_buff, 592 struct cudbg_error *cudbg_err) 593 { 594 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5); 595 } 596 597 u32 cudbg_cim_obq_size(struct adapter *padap, int qid) 598 { 599 u32 value; 600 601 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 602 QUENUMSELECT_V(qid)); 603 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A); 604 value = CIMQSIZE_G(value) * 64; /* size in number of words */ 605 return value * sizeof(u32); 606 } 607 608 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init, 609 struct cudbg_buffer *dbg_buff, 610 struct cudbg_error *cudbg_err, int qid) 611 { 612 struct adapter *padap = pdbg_init->adap; 613 struct cudbg_buffer temp_buff = { 0 }; 614 int no_of_read_words, rc = 0; 615 u32 qsize; 616 617 /* collect CIM OBQ */ 618 qsize = cudbg_cim_obq_size(padap, qid); 619 rc = cudbg_get_buff(dbg_buff, qsize, &temp_buff); 620 if (rc) 621 return rc; 622 623 /* t4_read_cim_obq will return no. of read words or error */ 624 no_of_read_words = t4_read_cim_obq(padap, qid, 625 (u32 *)temp_buff.data, qsize); 626 /* no_of_read_words is less than or equal to 0 means error */ 627 if (no_of_read_words <= 0) { 628 if (!no_of_read_words) 629 rc = CUDBG_SYSTEM_ERROR; 630 else 631 rc = no_of_read_words; 632 cudbg_err->sys_err = rc; 633 cudbg_put_buff(&temp_buff, dbg_buff); 634 return rc; 635 } 636 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 637 return rc; 638 } 639 640 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init, 641 struct cudbg_buffer *dbg_buff, 642 struct cudbg_error *cudbg_err) 643 { 644 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0); 645 } 646 647 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init, 648 struct cudbg_buffer *dbg_buff, 649 struct cudbg_error *cudbg_err) 650 { 651 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1); 652 } 653 654 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init, 655 struct cudbg_buffer *dbg_buff, 656 struct cudbg_error *cudbg_err) 657 { 658 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2); 659 } 660 661 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init, 662 struct cudbg_buffer *dbg_buff, 663 struct cudbg_error *cudbg_err) 664 { 665 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3); 666 } 667 668 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init, 669 struct cudbg_buffer *dbg_buff, 670 struct cudbg_error *cudbg_err) 671 { 672 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4); 673 } 674 675 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init, 676 struct cudbg_buffer *dbg_buff, 677 struct cudbg_error *cudbg_err) 678 { 679 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5); 680 } 681 682 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init, 683 struct cudbg_buffer *dbg_buff, 684 struct cudbg_error *cudbg_err) 685 { 686 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6); 687 } 688 689 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init, 690 struct cudbg_buffer *dbg_buff, 691 struct cudbg_error *cudbg_err) 692 { 693 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7); 694 } 695 696 static int cudbg_meminfo_get_mem_index(struct adapter *padap, 697 struct cudbg_meminfo *mem_info, 698 u8 mem_type, u8 *idx) 699 { 700 u8 i, flag; 701 702 switch (mem_type) { 703 case MEM_EDC0: 704 flag = EDC0_FLAG; 705 break; 706 case MEM_EDC1: 707 flag = EDC1_FLAG; 708 break; 709 case MEM_MC0: 710 /* Some T5 cards have both MC0 and MC1. */ 711 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG; 712 break; 713 case MEM_MC1: 714 flag = MC1_FLAG; 715 break; 716 case MEM_HMA: 717 flag = HMA_FLAG; 718 break; 719 default: 720 return CUDBG_STATUS_ENTITY_NOT_FOUND; 721 } 722 723 for (i = 0; i < mem_info->avail_c; i++) { 724 if (mem_info->avail[i].idx == flag) { 725 *idx = i; 726 return 0; 727 } 728 } 729 730 return CUDBG_STATUS_ENTITY_NOT_FOUND; 731 } 732 733 /* Fetch the @region_name's start and end from @meminfo. */ 734 static int cudbg_get_mem_region(struct adapter *padap, 735 struct cudbg_meminfo *meminfo, 736 u8 mem_type, const char *region_name, 737 struct cudbg_mem_desc *mem_desc) 738 { 739 u8 mc, found = 0; 740 u32 i, idx = 0; 741 int rc; 742 743 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc); 744 if (rc) 745 return rc; 746 747 for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) { 748 if (!strcmp(cudbg_region[i], region_name)) { 749 found = 1; 750 idx = i; 751 break; 752 } 753 } 754 if (!found) 755 return -EINVAL; 756 757 found = 0; 758 for (i = 0; i < meminfo->mem_c; i++) { 759 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region)) 760 continue; /* Skip holes */ 761 762 if (!(meminfo->mem[i].limit)) 763 meminfo->mem[i].limit = 764 i < meminfo->mem_c - 1 ? 765 meminfo->mem[i + 1].base - 1 : ~0; 766 767 if (meminfo->mem[i].idx == idx) { 768 /* Check if the region exists in @mem_type memory */ 769 if (meminfo->mem[i].base < meminfo->avail[mc].base && 770 meminfo->mem[i].limit < meminfo->avail[mc].base) 771 return -EINVAL; 772 773 if (meminfo->mem[i].base > meminfo->avail[mc].limit) 774 return -EINVAL; 775 776 memcpy(mem_desc, &meminfo->mem[i], 777 sizeof(struct cudbg_mem_desc)); 778 found = 1; 779 break; 780 } 781 } 782 if (!found) 783 return -EINVAL; 784 785 return 0; 786 } 787 788 /* Fetch and update the start and end of the requested memory region w.r.t 0 789 * in the corresponding EDC/MC/HMA. 790 */ 791 static int cudbg_get_mem_relative(struct adapter *padap, 792 struct cudbg_meminfo *meminfo, 793 u8 mem_type, u32 *out_base, u32 *out_end) 794 { 795 u8 mc_idx; 796 int rc; 797 798 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx); 799 if (rc) 800 return rc; 801 802 if (*out_base < meminfo->avail[mc_idx].base) 803 *out_base = 0; 804 else 805 *out_base -= meminfo->avail[mc_idx].base; 806 807 if (*out_end > meminfo->avail[mc_idx].limit) 808 *out_end = meminfo->avail[mc_idx].limit; 809 else 810 *out_end -= meminfo->avail[mc_idx].base; 811 812 return 0; 813 } 814 815 /* Get TX and RX Payload region */ 816 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type, 817 const char *region_name, 818 struct cudbg_region_info *payload) 819 { 820 struct cudbg_mem_desc mem_desc = { 0 }; 821 struct cudbg_meminfo meminfo; 822 int rc; 823 824 rc = cudbg_fill_meminfo(padap, &meminfo); 825 if (rc) 826 return rc; 827 828 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name, 829 &mem_desc); 830 if (rc) { 831 payload->exist = false; 832 return 0; 833 } 834 835 payload->exist = true; 836 payload->start = mem_desc.base; 837 payload->end = mem_desc.limit; 838 839 return cudbg_get_mem_relative(padap, &meminfo, mem_type, 840 &payload->start, &payload->end); 841 } 842 843 #define CUDBG_YIELD_ITERATION 256 844 845 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init, 846 struct cudbg_buffer *dbg_buff, u8 mem_type, 847 unsigned long tot_len, 848 struct cudbg_error *cudbg_err) 849 { 850 static const char * const region_name[] = { "Tx payload:", 851 "Rx payload:" }; 852 unsigned long bytes, bytes_left, bytes_read = 0; 853 struct adapter *padap = pdbg_init->adap; 854 struct cudbg_buffer temp_buff = { 0 }; 855 struct cudbg_region_info payload[2]; 856 u32 yield_count = 0; 857 int rc = 0; 858 u8 i; 859 860 /* Get TX/RX Payload region range if they exist */ 861 memset(payload, 0, sizeof(payload)); 862 for (i = 0; i < ARRAY_SIZE(region_name); i++) { 863 rc = cudbg_get_payload_range(padap, mem_type, region_name[i], 864 &payload[i]); 865 if (rc) 866 return rc; 867 868 if (payload[i].exist) { 869 /* Align start and end to avoid wrap around */ 870 payload[i].start = roundup(payload[i].start, 871 CUDBG_CHUNK_SIZE); 872 payload[i].end = rounddown(payload[i].end, 873 CUDBG_CHUNK_SIZE); 874 } 875 } 876 877 bytes_left = tot_len; 878 while (bytes_left > 0) { 879 /* As MC size is huge and read through PIO access, this 880 * loop will hold cpu for a longer time. OS may think that 881 * the process is hanged and will generate CPU stall traces. 882 * So yield the cpu regularly. 883 */ 884 yield_count++; 885 if (!(yield_count % CUDBG_YIELD_ITERATION)) 886 schedule(); 887 888 bytes = min_t(unsigned long, bytes_left, 889 (unsigned long)CUDBG_CHUNK_SIZE); 890 rc = cudbg_get_buff(dbg_buff, bytes, &temp_buff); 891 if (rc) 892 return rc; 893 894 for (i = 0; i < ARRAY_SIZE(payload); i++) 895 if (payload[i].exist && 896 bytes_read >= payload[i].start && 897 bytes_read + bytes <= payload[i].end) 898 /* TX and RX Payload regions can't overlap */ 899 goto skip_read; 900 901 spin_lock(&padap->win0_lock); 902 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type, 903 bytes_read, bytes, 904 (__be32 *)temp_buff.data, 905 1); 906 spin_unlock(&padap->win0_lock); 907 if (rc) { 908 cudbg_err->sys_err = rc; 909 cudbg_put_buff(&temp_buff, dbg_buff); 910 return rc; 911 } 912 913 skip_read: 914 bytes_left -= bytes; 915 bytes_read += bytes; 916 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 917 } 918 return rc; 919 } 920 921 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init, 922 struct cudbg_error *cudbg_err) 923 { 924 struct adapter *padap = pdbg_init->adap; 925 int rc; 926 927 if (is_fw_attached(pdbg_init)) { 928 /* Flush uP dcache before reading edcX/mcX */ 929 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH); 930 if (rc) 931 cudbg_err->sys_warn = rc; 932 } 933 } 934 935 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init, 936 struct cudbg_buffer *dbg_buff, 937 struct cudbg_error *cudbg_err, 938 u8 mem_type) 939 { 940 struct adapter *padap = pdbg_init->adap; 941 struct cudbg_meminfo mem_info; 942 unsigned long size; 943 u8 mc_idx; 944 int rc; 945 946 memset(&mem_info, 0, sizeof(struct cudbg_meminfo)); 947 rc = cudbg_fill_meminfo(padap, &mem_info); 948 if (rc) 949 return rc; 950 951 cudbg_t4_fwcache(pdbg_init, cudbg_err); 952 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx); 953 if (rc) 954 return rc; 955 956 size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base; 957 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size, 958 cudbg_err); 959 } 960 961 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init, 962 struct cudbg_buffer *dbg_buff, 963 struct cudbg_error *cudbg_err) 964 { 965 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 966 MEM_EDC0); 967 } 968 969 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init, 970 struct cudbg_buffer *dbg_buff, 971 struct cudbg_error *cudbg_err) 972 { 973 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 974 MEM_EDC1); 975 } 976 977 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init, 978 struct cudbg_buffer *dbg_buff, 979 struct cudbg_error *cudbg_err) 980 { 981 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 982 MEM_MC0); 983 } 984 985 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init, 986 struct cudbg_buffer *dbg_buff, 987 struct cudbg_error *cudbg_err) 988 { 989 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 990 MEM_MC1); 991 } 992 993 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init, 994 struct cudbg_buffer *dbg_buff, 995 struct cudbg_error *cudbg_err) 996 { 997 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 998 MEM_HMA); 999 } 1000 1001 int cudbg_collect_rss(struct cudbg_init *pdbg_init, 1002 struct cudbg_buffer *dbg_buff, 1003 struct cudbg_error *cudbg_err) 1004 { 1005 struct adapter *padap = pdbg_init->adap; 1006 struct cudbg_buffer temp_buff = { 0 }; 1007 int rc; 1008 1009 rc = cudbg_get_buff(dbg_buff, RSS_NENTRIES * sizeof(u16), &temp_buff); 1010 if (rc) 1011 return rc; 1012 1013 rc = t4_read_rss(padap, (u16 *)temp_buff.data); 1014 if (rc) { 1015 cudbg_err->sys_err = rc; 1016 cudbg_put_buff(&temp_buff, dbg_buff); 1017 return rc; 1018 } 1019 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1020 return rc; 1021 } 1022 1023 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init, 1024 struct cudbg_buffer *dbg_buff, 1025 struct cudbg_error *cudbg_err) 1026 { 1027 struct adapter *padap = pdbg_init->adap; 1028 struct cudbg_buffer temp_buff = { 0 }; 1029 struct cudbg_rss_vf_conf *vfconf; 1030 int vf, rc, vf_count; 1031 1032 vf_count = padap->params.arch.vfcount; 1033 rc = cudbg_get_buff(dbg_buff, 1034 vf_count * sizeof(struct cudbg_rss_vf_conf), 1035 &temp_buff); 1036 if (rc) 1037 return rc; 1038 1039 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data; 1040 for (vf = 0; vf < vf_count; vf++) 1041 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl, 1042 &vfconf[vf].rss_vf_vfh, true); 1043 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1044 return rc; 1045 } 1046 1047 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init, 1048 struct cudbg_buffer *dbg_buff, 1049 struct cudbg_error *cudbg_err) 1050 { 1051 struct adapter *padap = pdbg_init->adap; 1052 struct cudbg_buffer temp_buff = { 0 }; 1053 int rc; 1054 1055 rc = cudbg_get_buff(dbg_buff, NMTUS * sizeof(u16), &temp_buff); 1056 if (rc) 1057 return rc; 1058 1059 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL); 1060 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1061 return rc; 1062 } 1063 1064 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init, 1065 struct cudbg_buffer *dbg_buff, 1066 struct cudbg_error *cudbg_err) 1067 { 1068 struct adapter *padap = pdbg_init->adap; 1069 struct cudbg_buffer temp_buff = { 0 }; 1070 struct cudbg_pm_stats *pm_stats_buff; 1071 int rc; 1072 1073 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pm_stats), 1074 &temp_buff); 1075 if (rc) 1076 return rc; 1077 1078 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data; 1079 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc); 1080 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc); 1081 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1082 return rc; 1083 } 1084 1085 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init, 1086 struct cudbg_buffer *dbg_buff, 1087 struct cudbg_error *cudbg_err) 1088 { 1089 struct adapter *padap = pdbg_init->adap; 1090 struct cudbg_buffer temp_buff = { 0 }; 1091 struct cudbg_hw_sched *hw_sched_buff; 1092 int i, rc = 0; 1093 1094 if (!padap->params.vpd.cclk) 1095 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1096 1097 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_hw_sched), 1098 &temp_buff); 1099 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data; 1100 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A); 1101 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A)); 1102 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab); 1103 for (i = 0; i < NTX_SCHED; ++i) 1104 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i], 1105 &hw_sched_buff->ipg[i], true); 1106 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1107 return rc; 1108 } 1109 1110 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init, 1111 struct cudbg_buffer *dbg_buff, 1112 struct cudbg_error *cudbg_err) 1113 { 1114 struct adapter *padap = pdbg_init->adap; 1115 struct cudbg_buffer temp_buff = { 0 }; 1116 struct ireg_buf *ch_tp_pio; 1117 int i, rc, n = 0; 1118 u32 size; 1119 1120 if (is_t5(padap->params.chip)) 1121 n = sizeof(t5_tp_pio_array) + 1122 sizeof(t5_tp_tm_pio_array) + 1123 sizeof(t5_tp_mib_index_array); 1124 else 1125 n = sizeof(t6_tp_pio_array) + 1126 sizeof(t6_tp_tm_pio_array) + 1127 sizeof(t6_tp_mib_index_array); 1128 1129 n = n / (IREG_NUM_ELEM * sizeof(u32)); 1130 size = sizeof(struct ireg_buf) * n; 1131 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1132 if (rc) 1133 return rc; 1134 1135 ch_tp_pio = (struct ireg_buf *)temp_buff.data; 1136 1137 /* TP_PIO */ 1138 if (is_t5(padap->params.chip)) 1139 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1140 else if (is_t6(padap->params.chip)) 1141 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1142 1143 for (i = 0; i < n; i++) { 1144 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1145 u32 *buff = ch_tp_pio->outbuf; 1146 1147 if (is_t5(padap->params.chip)) { 1148 tp_pio->ireg_addr = t5_tp_pio_array[i][0]; 1149 tp_pio->ireg_data = t5_tp_pio_array[i][1]; 1150 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2]; 1151 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3]; 1152 } else if (is_t6(padap->params.chip)) { 1153 tp_pio->ireg_addr = t6_tp_pio_array[i][0]; 1154 tp_pio->ireg_data = t6_tp_pio_array[i][1]; 1155 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2]; 1156 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3]; 1157 } 1158 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range, 1159 tp_pio->ireg_local_offset, true); 1160 ch_tp_pio++; 1161 } 1162 1163 /* TP_TM_PIO */ 1164 if (is_t5(padap->params.chip)) 1165 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1166 else if (is_t6(padap->params.chip)) 1167 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1168 1169 for (i = 0; i < n; i++) { 1170 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1171 u32 *buff = ch_tp_pio->outbuf; 1172 1173 if (is_t5(padap->params.chip)) { 1174 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0]; 1175 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1]; 1176 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2]; 1177 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3]; 1178 } else if (is_t6(padap->params.chip)) { 1179 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0]; 1180 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1]; 1181 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2]; 1182 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3]; 1183 } 1184 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range, 1185 tp_pio->ireg_local_offset, true); 1186 ch_tp_pio++; 1187 } 1188 1189 /* TP_MIB_INDEX */ 1190 if (is_t5(padap->params.chip)) 1191 n = sizeof(t5_tp_mib_index_array) / 1192 (IREG_NUM_ELEM * sizeof(u32)); 1193 else if (is_t6(padap->params.chip)) 1194 n = sizeof(t6_tp_mib_index_array) / 1195 (IREG_NUM_ELEM * sizeof(u32)); 1196 1197 for (i = 0; i < n ; i++) { 1198 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1199 u32 *buff = ch_tp_pio->outbuf; 1200 1201 if (is_t5(padap->params.chip)) { 1202 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0]; 1203 tp_pio->ireg_data = t5_tp_mib_index_array[i][1]; 1204 tp_pio->ireg_local_offset = 1205 t5_tp_mib_index_array[i][2]; 1206 tp_pio->ireg_offset_range = 1207 t5_tp_mib_index_array[i][3]; 1208 } else if (is_t6(padap->params.chip)) { 1209 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0]; 1210 tp_pio->ireg_data = t6_tp_mib_index_array[i][1]; 1211 tp_pio->ireg_local_offset = 1212 t6_tp_mib_index_array[i][2]; 1213 tp_pio->ireg_offset_range = 1214 t6_tp_mib_index_array[i][3]; 1215 } 1216 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range, 1217 tp_pio->ireg_local_offset, true); 1218 ch_tp_pio++; 1219 } 1220 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1221 return rc; 1222 } 1223 1224 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init, 1225 struct cudbg_buffer *dbg_buff, 1226 struct cudbg_error *cudbg_err) 1227 { 1228 struct adapter *padap = pdbg_init->adap; 1229 struct cudbg_buffer temp_buff = { 0 }; 1230 struct ireg_buf *ch_sge_dbg; 1231 int i, rc; 1232 1233 rc = cudbg_get_buff(dbg_buff, sizeof(*ch_sge_dbg) * 2, &temp_buff); 1234 if (rc) 1235 return rc; 1236 1237 ch_sge_dbg = (struct ireg_buf *)temp_buff.data; 1238 for (i = 0; i < 2; i++) { 1239 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio; 1240 u32 *buff = ch_sge_dbg->outbuf; 1241 1242 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0]; 1243 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1]; 1244 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2]; 1245 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3]; 1246 t4_read_indirect(padap, 1247 sge_pio->ireg_addr, 1248 sge_pio->ireg_data, 1249 buff, 1250 sge_pio->ireg_offset_range, 1251 sge_pio->ireg_local_offset); 1252 ch_sge_dbg++; 1253 } 1254 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1255 return rc; 1256 } 1257 1258 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init, 1259 struct cudbg_buffer *dbg_buff, 1260 struct cudbg_error *cudbg_err) 1261 { 1262 struct adapter *padap = pdbg_init->adap; 1263 struct cudbg_buffer temp_buff = { 0 }; 1264 struct cudbg_ulprx_la *ulprx_la_buff; 1265 int rc; 1266 1267 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_ulprx_la), 1268 &temp_buff); 1269 if (rc) 1270 return rc; 1271 1272 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data; 1273 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data); 1274 ulprx_la_buff->size = ULPRX_LA_SIZE; 1275 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1276 return rc; 1277 } 1278 1279 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init, 1280 struct cudbg_buffer *dbg_buff, 1281 struct cudbg_error *cudbg_err) 1282 { 1283 struct adapter *padap = pdbg_init->adap; 1284 struct cudbg_buffer temp_buff = { 0 }; 1285 struct cudbg_tp_la *tp_la_buff; 1286 int size, rc; 1287 1288 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); 1289 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1290 if (rc) 1291 return rc; 1292 1293 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data; 1294 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A)); 1295 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL); 1296 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1297 return rc; 1298 } 1299 1300 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init, 1301 struct cudbg_buffer *dbg_buff, 1302 struct cudbg_error *cudbg_err) 1303 { 1304 struct adapter *padap = pdbg_init->adap; 1305 struct cudbg_buffer temp_buff = { 0 }; 1306 struct cudbg_meminfo *meminfo_buff; 1307 int rc; 1308 1309 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_meminfo), &temp_buff); 1310 if (rc) 1311 return rc; 1312 1313 meminfo_buff = (struct cudbg_meminfo *)temp_buff.data; 1314 rc = cudbg_fill_meminfo(padap, meminfo_buff); 1315 if (rc) { 1316 cudbg_err->sys_err = rc; 1317 cudbg_put_buff(&temp_buff, dbg_buff); 1318 return rc; 1319 } 1320 1321 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1322 return rc; 1323 } 1324 1325 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init, 1326 struct cudbg_buffer *dbg_buff, 1327 struct cudbg_error *cudbg_err) 1328 { 1329 struct cudbg_cim_pif_la *cim_pif_la_buff; 1330 struct adapter *padap = pdbg_init->adap; 1331 struct cudbg_buffer temp_buff = { 0 }; 1332 int size, rc; 1333 1334 size = sizeof(struct cudbg_cim_pif_la) + 1335 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); 1336 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1337 if (rc) 1338 return rc; 1339 1340 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data; 1341 cim_pif_la_buff->size = CIM_PIFLA_SIZE; 1342 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data, 1343 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE, 1344 NULL, NULL); 1345 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1346 return rc; 1347 } 1348 1349 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init, 1350 struct cudbg_buffer *dbg_buff, 1351 struct cudbg_error *cudbg_err) 1352 { 1353 struct adapter *padap = pdbg_init->adap; 1354 struct cudbg_buffer temp_buff = { 0 }; 1355 struct cudbg_clk_info *clk_info_buff; 1356 u64 tp_tick_us; 1357 int rc; 1358 1359 if (!padap->params.vpd.cclk) 1360 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1361 1362 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_clk_info), 1363 &temp_buff); 1364 if (rc) 1365 return rc; 1366 1367 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data; 1368 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */ 1369 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A); 1370 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res); 1371 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res); 1372 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000; 1373 1374 clk_info_buff->dack_timer = 1375 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 * 1376 t4_read_reg(padap, TP_DACK_TIMER_A); 1377 clk_info_buff->retransmit_min = 1378 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A); 1379 clk_info_buff->retransmit_max = 1380 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A); 1381 clk_info_buff->persist_timer_min = 1382 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A); 1383 clk_info_buff->persist_timer_max = 1384 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A); 1385 clk_info_buff->keepalive_idle_timer = 1386 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A); 1387 clk_info_buff->keepalive_interval = 1388 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A); 1389 clk_info_buff->initial_srtt = 1390 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A)); 1391 clk_info_buff->finwait2_timer = 1392 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A); 1393 1394 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1395 return rc; 1396 } 1397 1398 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init, 1399 struct cudbg_buffer *dbg_buff, 1400 struct cudbg_error *cudbg_err) 1401 { 1402 struct adapter *padap = pdbg_init->adap; 1403 struct cudbg_buffer temp_buff = { 0 }; 1404 struct ireg_buf *ch_pcie; 1405 int i, rc, n; 1406 u32 size; 1407 1408 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1409 size = sizeof(struct ireg_buf) * n * 2; 1410 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1411 if (rc) 1412 return rc; 1413 1414 ch_pcie = (struct ireg_buf *)temp_buff.data; 1415 /* PCIE_PDBG */ 1416 for (i = 0; i < n; i++) { 1417 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1418 u32 *buff = ch_pcie->outbuf; 1419 1420 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0]; 1421 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1]; 1422 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2]; 1423 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3]; 1424 t4_read_indirect(padap, 1425 pcie_pio->ireg_addr, 1426 pcie_pio->ireg_data, 1427 buff, 1428 pcie_pio->ireg_offset_range, 1429 pcie_pio->ireg_local_offset); 1430 ch_pcie++; 1431 } 1432 1433 /* PCIE_CDBG */ 1434 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1435 for (i = 0; i < n; i++) { 1436 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1437 u32 *buff = ch_pcie->outbuf; 1438 1439 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0]; 1440 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1]; 1441 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2]; 1442 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3]; 1443 t4_read_indirect(padap, 1444 pcie_pio->ireg_addr, 1445 pcie_pio->ireg_data, 1446 buff, 1447 pcie_pio->ireg_offset_range, 1448 pcie_pio->ireg_local_offset); 1449 ch_pcie++; 1450 } 1451 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1452 return rc; 1453 } 1454 1455 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init, 1456 struct cudbg_buffer *dbg_buff, 1457 struct cudbg_error *cudbg_err) 1458 { 1459 struct adapter *padap = pdbg_init->adap; 1460 struct cudbg_buffer temp_buff = { 0 }; 1461 struct ireg_buf *ch_pm; 1462 int i, rc, n; 1463 u32 size; 1464 1465 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1466 size = sizeof(struct ireg_buf) * n * 2; 1467 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1468 if (rc) 1469 return rc; 1470 1471 ch_pm = (struct ireg_buf *)temp_buff.data; 1472 /* PM_RX */ 1473 for (i = 0; i < n; i++) { 1474 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1475 u32 *buff = ch_pm->outbuf; 1476 1477 pm_pio->ireg_addr = t5_pm_rx_array[i][0]; 1478 pm_pio->ireg_data = t5_pm_rx_array[i][1]; 1479 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2]; 1480 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3]; 1481 t4_read_indirect(padap, 1482 pm_pio->ireg_addr, 1483 pm_pio->ireg_data, 1484 buff, 1485 pm_pio->ireg_offset_range, 1486 pm_pio->ireg_local_offset); 1487 ch_pm++; 1488 } 1489 1490 /* PM_TX */ 1491 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1492 for (i = 0; i < n; i++) { 1493 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1494 u32 *buff = ch_pm->outbuf; 1495 1496 pm_pio->ireg_addr = t5_pm_tx_array[i][0]; 1497 pm_pio->ireg_data = t5_pm_tx_array[i][1]; 1498 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2]; 1499 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3]; 1500 t4_read_indirect(padap, 1501 pm_pio->ireg_addr, 1502 pm_pio->ireg_data, 1503 buff, 1504 pm_pio->ireg_offset_range, 1505 pm_pio->ireg_local_offset); 1506 ch_pm++; 1507 } 1508 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1509 return rc; 1510 } 1511 1512 int cudbg_collect_tid(struct cudbg_init *pdbg_init, 1513 struct cudbg_buffer *dbg_buff, 1514 struct cudbg_error *cudbg_err) 1515 { 1516 struct adapter *padap = pdbg_init->adap; 1517 struct cudbg_tid_info_region_rev1 *tid1; 1518 struct cudbg_buffer temp_buff = { 0 }; 1519 struct cudbg_tid_info_region *tid; 1520 u32 para[2], val[2]; 1521 int rc; 1522 1523 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_tid_info_region_rev1), 1524 &temp_buff); 1525 if (rc) 1526 return rc; 1527 1528 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data; 1529 tid = &tid1->tid; 1530 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE; 1531 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV; 1532 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) - 1533 sizeof(struct cudbg_ver_hdr); 1534 1535 #define FW_PARAM_PFVF_A(param) \ 1536 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 1537 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 1538 FW_PARAMS_PARAM_Y_V(0) | \ 1539 FW_PARAMS_PARAM_Z_V(0)) 1540 1541 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START); 1542 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END); 1543 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val); 1544 if (rc < 0) { 1545 cudbg_err->sys_err = rc; 1546 cudbg_put_buff(&temp_buff, dbg_buff); 1547 return rc; 1548 } 1549 tid->uotid_base = val[0]; 1550 tid->nuotids = val[1] - val[0] + 1; 1551 1552 if (is_t5(padap->params.chip)) { 1553 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4; 1554 } else if (is_t6(padap->params.chip)) { 1555 tid1->tid_start = 1556 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A); 1557 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A); 1558 1559 para[0] = FW_PARAM_PFVF_A(HPFILTER_START); 1560 para[1] = FW_PARAM_PFVF_A(HPFILTER_END); 1561 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, 1562 para, val); 1563 if (rc < 0) { 1564 cudbg_err->sys_err = rc; 1565 cudbg_put_buff(&temp_buff, dbg_buff); 1566 return rc; 1567 } 1568 tid->hpftid_base = val[0]; 1569 tid->nhpftids = val[1] - val[0] + 1; 1570 } 1571 1572 tid->ntids = padap->tids.ntids; 1573 tid->nstids = padap->tids.nstids; 1574 tid->stid_base = padap->tids.stid_base; 1575 tid->hash_base = padap->tids.hash_base; 1576 1577 tid->natids = padap->tids.natids; 1578 tid->nftids = padap->tids.nftids; 1579 tid->ftid_base = padap->tids.ftid_base; 1580 tid->aftid_base = padap->tids.aftid_base; 1581 tid->aftid_end = padap->tids.aftid_end; 1582 1583 tid->sftid_base = padap->tids.sftid_base; 1584 tid->nsftids = padap->tids.nsftids; 1585 1586 tid->flags = padap->flags; 1587 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A); 1588 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A); 1589 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A); 1590 1591 #undef FW_PARAM_PFVF_A 1592 1593 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1594 return rc; 1595 } 1596 1597 int cudbg_dump_context_size(struct adapter *padap) 1598 { 1599 u32 value, size; 1600 u8 flq; 1601 1602 value = t4_read_reg(padap, SGE_FLM_CFG_A); 1603 1604 /* Get number of data freelist queues */ 1605 flq = HDRSTARTFLQ_G(value); 1606 size = CUDBG_MAX_FL_QIDS >> flq; 1607 1608 /* Add extra space for congestion manager contexts. 1609 * The number of CONM contexts are same as number of freelist 1610 * queues. 1611 */ 1612 size += size; 1613 return size * sizeof(struct cudbg_ch_cntxt); 1614 } 1615 1616 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid, 1617 enum ctxt_type ctype, u32 *data) 1618 { 1619 struct adapter *padap = pdbg_init->adap; 1620 int rc = -1; 1621 1622 /* Under heavy traffic, the SGE Queue contexts registers will be 1623 * frequently accessed by firmware. 1624 * 1625 * To avoid conflicts with firmware, always ask firmware to fetch 1626 * the SGE Queue contexts via mailbox. On failure, fallback to 1627 * accessing hardware registers directly. 1628 */ 1629 if (is_fw_attached(pdbg_init)) 1630 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data); 1631 if (rc) 1632 t4_sge_ctxt_rd_bd(padap, cid, ctype, data); 1633 } 1634 1635 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init, 1636 struct cudbg_buffer *dbg_buff, 1637 struct cudbg_error *cudbg_err) 1638 { 1639 struct adapter *padap = pdbg_init->adap; 1640 struct cudbg_buffer temp_buff = { 0 }; 1641 struct cudbg_ch_cntxt *buff; 1642 u32 size, i = 0; 1643 int rc; 1644 1645 rc = cudbg_dump_context_size(padap); 1646 if (rc <= 0) 1647 return CUDBG_STATUS_ENTITY_NOT_FOUND; 1648 1649 size = rc; 1650 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1651 if (rc) 1652 return rc; 1653 1654 buff = (struct cudbg_ch_cntxt *)temp_buff.data; 1655 while (size > 0) { 1656 buff->cntxt_type = CTXT_FLM; 1657 buff->cntxt_id = i; 1658 cudbg_read_sge_ctxt(pdbg_init, i, CTXT_FLM, buff->data); 1659 buff++; 1660 size -= sizeof(struct cudbg_ch_cntxt); 1661 1662 buff->cntxt_type = CTXT_CNM; 1663 buff->cntxt_id = i; 1664 cudbg_read_sge_ctxt(pdbg_init, i, CTXT_CNM, buff->data); 1665 buff++; 1666 size -= sizeof(struct cudbg_ch_cntxt); 1667 1668 i++; 1669 } 1670 1671 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1672 return rc; 1673 } 1674 1675 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 1676 { 1677 *mask = x | y; 1678 y = (__force u64)cpu_to_be64(y); 1679 memcpy(addr, (char *)&y + 2, ETH_ALEN); 1680 } 1681 1682 static void cudbg_mps_rpl_backdoor(struct adapter *padap, 1683 struct fw_ldst_mps_rplc *mps_rplc) 1684 { 1685 if (is_t5(padap->params.chip)) { 1686 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 1687 MPS_VF_RPLCT_MAP3_A)); 1688 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 1689 MPS_VF_RPLCT_MAP2_A)); 1690 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 1691 MPS_VF_RPLCT_MAP1_A)); 1692 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 1693 MPS_VF_RPLCT_MAP0_A)); 1694 } else { 1695 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 1696 MPS_VF_RPLCT_MAP7_A)); 1697 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 1698 MPS_VF_RPLCT_MAP6_A)); 1699 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 1700 MPS_VF_RPLCT_MAP5_A)); 1701 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 1702 MPS_VF_RPLCT_MAP4_A)); 1703 } 1704 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A)); 1705 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A)); 1706 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A)); 1707 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A)); 1708 } 1709 1710 static int cudbg_collect_tcam_index(struct adapter *padap, 1711 struct cudbg_mps_tcam *tcam, u32 idx) 1712 { 1713 u64 tcamy, tcamx, val; 1714 u32 ctl, data2; 1715 int rc = 0; 1716 1717 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) { 1718 /* CtlReqID - 1: use Host Driver Requester ID 1719 * CtlCmdType - 0: Read, 1: Write 1720 * CtlTcamSel - 0: TCAM0, 1: TCAM1 1721 * CtlXYBitSel- 0: Y bit, 1: X bit 1722 */ 1723 1724 /* Read tcamy */ 1725 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 1726 if (idx < 256) 1727 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 1728 else 1729 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1); 1730 1731 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1732 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 1733 tcamy = DMACH_G(val) << 32; 1734 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 1735 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 1736 tcam->lookup_type = DATALKPTYPE_G(data2); 1737 1738 /* 0 - Outer header, 1 - Inner header 1739 * [71:48] bit locations are overloaded for 1740 * outer vs. inner lookup types. 1741 */ 1742 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 1743 /* Inner header VNI */ 1744 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 1745 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val); 1746 tcam->dip_hit = data2 & DATADIPHIT_F; 1747 } else { 1748 tcam->vlan_vld = data2 & DATAVIDH2_F; 1749 tcam->ivlan = VIDL_G(val); 1750 } 1751 1752 tcam->port_num = DATAPORTNUM_G(data2); 1753 1754 /* Read tcamx. Change the control param */ 1755 ctl |= CTLXYBITSEL_V(1); 1756 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1757 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 1758 tcamx = DMACH_G(val) << 32; 1759 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 1760 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 1761 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 1762 /* Inner header VNI mask */ 1763 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 1764 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val); 1765 } 1766 } else { 1767 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx)); 1768 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx)); 1769 } 1770 1771 /* If no entry, return */ 1772 if (tcamx & tcamy) 1773 return rc; 1774 1775 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx)); 1776 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx)); 1777 1778 if (is_t5(padap->params.chip)) 1779 tcam->repli = (tcam->cls_lo & REPLICATE_F); 1780 else if (is_t6(padap->params.chip)) 1781 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F); 1782 1783 if (tcam->repli) { 1784 struct fw_ldst_cmd ldst_cmd; 1785 struct fw_ldst_mps_rplc mps_rplc; 1786 1787 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 1788 ldst_cmd.op_to_addrspace = 1789 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 1790 FW_CMD_REQUEST_F | FW_CMD_READ_F | 1791 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS)); 1792 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 1793 ldst_cmd.u.mps.rplc.fid_idx = 1794 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 1795 FW_LDST_CMD_IDX_V(idx)); 1796 1797 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd, sizeof(ldst_cmd), 1798 &ldst_cmd); 1799 if (rc) 1800 cudbg_mps_rpl_backdoor(padap, &mps_rplc); 1801 else 1802 mps_rplc = ldst_cmd.u.mps.rplc; 1803 1804 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0); 1805 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32); 1806 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64); 1807 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96); 1808 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) { 1809 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128); 1810 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160); 1811 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192); 1812 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224); 1813 } 1814 } 1815 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask); 1816 tcam->idx = idx; 1817 tcam->rplc_size = padap->params.arch.mps_rplc_size; 1818 return rc; 1819 } 1820 1821 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init, 1822 struct cudbg_buffer *dbg_buff, 1823 struct cudbg_error *cudbg_err) 1824 { 1825 struct adapter *padap = pdbg_init->adap; 1826 struct cudbg_buffer temp_buff = { 0 }; 1827 u32 size = 0, i, n, total_size = 0; 1828 struct cudbg_mps_tcam *tcam; 1829 int rc; 1830 1831 n = padap->params.arch.mps_tcam_size; 1832 size = sizeof(struct cudbg_mps_tcam) * n; 1833 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 1834 if (rc) 1835 return rc; 1836 1837 tcam = (struct cudbg_mps_tcam *)temp_buff.data; 1838 for (i = 0; i < n; i++) { 1839 rc = cudbg_collect_tcam_index(padap, tcam, i); 1840 if (rc) { 1841 cudbg_err->sys_err = rc; 1842 cudbg_put_buff(&temp_buff, dbg_buff); 1843 return rc; 1844 } 1845 total_size += sizeof(struct cudbg_mps_tcam); 1846 tcam++; 1847 } 1848 1849 if (!total_size) { 1850 rc = CUDBG_SYSTEM_ERROR; 1851 cudbg_err->sys_err = rc; 1852 cudbg_put_buff(&temp_buff, dbg_buff); 1853 return rc; 1854 } 1855 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1856 return rc; 1857 } 1858 1859 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init, 1860 struct cudbg_buffer *dbg_buff, 1861 struct cudbg_error *cudbg_err) 1862 { 1863 struct adapter *padap = pdbg_init->adap; 1864 struct cudbg_buffer temp_buff = { 0 }; 1865 char vpd_str[CUDBG_VPD_VER_LEN + 1]; 1866 u32 scfg_vers, vpd_vers, fw_vers; 1867 struct cudbg_vpd_data *vpd_data; 1868 struct vpd_params vpd = { 0 }; 1869 int rc, ret; 1870 1871 rc = t4_get_raw_vpd_params(padap, &vpd); 1872 if (rc) 1873 return rc; 1874 1875 rc = t4_get_fw_version(padap, &fw_vers); 1876 if (rc) 1877 return rc; 1878 1879 /* Serial Configuration Version is located beyond the PF's vpd size. 1880 * Temporarily give access to entire EEPROM to get it. 1881 */ 1882 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE); 1883 if (rc < 0) 1884 return rc; 1885 1886 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN, 1887 &scfg_vers); 1888 1889 /* Restore back to original PF's vpd size */ 1890 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE); 1891 if (rc < 0) 1892 return rc; 1893 1894 if (ret) 1895 return ret; 1896 1897 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN, 1898 vpd_str); 1899 if (rc) 1900 return rc; 1901 1902 vpd_str[CUDBG_VPD_VER_LEN] = '\0'; 1903 rc = kstrtouint(vpd_str, 0, &vpd_vers); 1904 if (rc) 1905 return rc; 1906 1907 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_vpd_data), 1908 &temp_buff); 1909 if (rc) 1910 return rc; 1911 1912 vpd_data = (struct cudbg_vpd_data *)temp_buff.data; 1913 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1); 1914 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1); 1915 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1); 1916 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1); 1917 vpd_data->scfg_vers = scfg_vers; 1918 vpd_data->vpd_vers = vpd_vers; 1919 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers); 1920 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers); 1921 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers); 1922 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers); 1923 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 1924 return rc; 1925 } 1926 1927 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid, 1928 struct cudbg_tid_data *tid_data) 1929 { 1930 struct adapter *padap = pdbg_init->adap; 1931 int i, cmd_retry = 8; 1932 u32 val; 1933 1934 /* Fill REQ_DATA regs with 0's */ 1935 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++) 1936 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0); 1937 1938 /* Write DBIG command */ 1939 val = DBGICMD_V(4) | DBGITID_V(tid); 1940 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val); 1941 tid_data->dbig_cmd = val; 1942 1943 val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */ 1944 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val); 1945 tid_data->dbig_conf = val; 1946 1947 /* Poll the DBGICMDBUSY bit */ 1948 val = 1; 1949 while (val) { 1950 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A); 1951 val = val & DBGICMDBUSY_F; 1952 cmd_retry--; 1953 if (!cmd_retry) 1954 return CUDBG_SYSTEM_ERROR; 1955 } 1956 1957 /* Check RESP status */ 1958 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A); 1959 tid_data->dbig_rsp_stat = val; 1960 if (!(val & 1)) 1961 return CUDBG_SYSTEM_ERROR; 1962 1963 /* Read RESP data */ 1964 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++) 1965 tid_data->data[i] = t4_read_reg(padap, 1966 LE_DB_DBGI_RSP_DATA_A + 1967 (i << 2)); 1968 tid_data->tid = tid; 1969 return 0; 1970 } 1971 1972 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region) 1973 { 1974 int type = LE_ET_UNKNOWN; 1975 1976 if (tid < tcam_region.server_start) 1977 type = LE_ET_TCAM_CON; 1978 else if (tid < tcam_region.filter_start) 1979 type = LE_ET_TCAM_SERVER; 1980 else if (tid < tcam_region.clip_start) 1981 type = LE_ET_TCAM_FILTER; 1982 else if (tid < tcam_region.routing_start) 1983 type = LE_ET_TCAM_CLIP; 1984 else if (tid < tcam_region.tid_hash_base) 1985 type = LE_ET_TCAM_ROUTING; 1986 else if (tid < tcam_region.max_tid) 1987 type = LE_ET_HASH_CON; 1988 else 1989 type = LE_ET_INVALID_TID; 1990 1991 return type; 1992 } 1993 1994 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data, 1995 struct cudbg_tcam tcam_region) 1996 { 1997 int ipv6 = 0; 1998 int le_type; 1999 2000 le_type = cudbg_get_le_type(tid_data->tid, tcam_region); 2001 if (tid_data->tid & 1) 2002 return 0; 2003 2004 if (le_type == LE_ET_HASH_CON) { 2005 ipv6 = tid_data->data[16] & 0x8000; 2006 } else if (le_type == LE_ET_TCAM_CON) { 2007 ipv6 = tid_data->data[16] & 0x8000; 2008 if (ipv6) 2009 ipv6 = tid_data->data[9] == 0x00C00000; 2010 } else { 2011 ipv6 = 0; 2012 } 2013 return ipv6; 2014 } 2015 2016 void cudbg_fill_le_tcam_info(struct adapter *padap, 2017 struct cudbg_tcam *tcam_region) 2018 { 2019 u32 value; 2020 2021 /* Get the LE regions */ 2022 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */ 2023 tcam_region->tid_hash_base = value; 2024 2025 /* Get routing table index */ 2026 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A); 2027 tcam_region->routing_start = value; 2028 2029 /*Get clip table index */ 2030 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A); 2031 tcam_region->clip_start = value; 2032 2033 /* Get filter table index */ 2034 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A); 2035 tcam_region->filter_start = value; 2036 2037 /* Get server table index */ 2038 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A); 2039 tcam_region->server_start = value; 2040 2041 /* Check whether hash is enabled and calculate the max tids */ 2042 value = t4_read_reg(padap, LE_DB_CONFIG_A); 2043 if ((value >> HASHEN_S) & 1) { 2044 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A); 2045 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { 2046 tcam_region->max_tid = (value & 0xFFFFF) + 2047 tcam_region->tid_hash_base; 2048 } else { 2049 value = HASHTIDSIZE_G(value); 2050 value = 1 << value; 2051 tcam_region->max_tid = value + 2052 tcam_region->tid_hash_base; 2053 } 2054 } else { /* hash not enabled */ 2055 tcam_region->max_tid = CUDBG_MAX_TCAM_TID; 2056 } 2057 } 2058 2059 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init, 2060 struct cudbg_buffer *dbg_buff, 2061 struct cudbg_error *cudbg_err) 2062 { 2063 struct adapter *padap = pdbg_init->adap; 2064 struct cudbg_buffer temp_buff = { 0 }; 2065 struct cudbg_tcam tcam_region = { 0 }; 2066 struct cudbg_tid_data *tid_data; 2067 u32 bytes = 0; 2068 int rc, size; 2069 u32 i; 2070 2071 cudbg_fill_le_tcam_info(padap, &tcam_region); 2072 2073 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid; 2074 size += sizeof(struct cudbg_tcam); 2075 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2076 if (rc) 2077 return rc; 2078 2079 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam)); 2080 bytes = sizeof(struct cudbg_tcam); 2081 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes); 2082 /* read all tid */ 2083 for (i = 0; i < tcam_region.max_tid; ) { 2084 rc = cudbg_read_tid(pdbg_init, i, tid_data); 2085 if (rc) { 2086 cudbg_err->sys_err = rc; 2087 cudbg_put_buff(&temp_buff, dbg_buff); 2088 return rc; 2089 } 2090 2091 /* ipv6 takes two tids */ 2092 cudbg_is_ipv6_entry(tid_data, tcam_region) ? i += 2 : i++; 2093 2094 tid_data++; 2095 bytes += sizeof(struct cudbg_tid_data); 2096 } 2097 2098 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2099 return rc; 2100 } 2101 2102 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init, 2103 struct cudbg_buffer *dbg_buff, 2104 struct cudbg_error *cudbg_err) 2105 { 2106 struct adapter *padap = pdbg_init->adap; 2107 struct cudbg_buffer temp_buff = { 0 }; 2108 u32 size; 2109 int rc; 2110 2111 size = sizeof(u16) * NMTUS * NCCTRL_WIN; 2112 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2113 if (rc) 2114 return rc; 2115 2116 t4_read_cong_tbl(padap, (void *)temp_buff.data); 2117 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2118 return rc; 2119 } 2120 2121 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init, 2122 struct cudbg_buffer *dbg_buff, 2123 struct cudbg_error *cudbg_err) 2124 { 2125 struct adapter *padap = pdbg_init->adap; 2126 struct cudbg_buffer temp_buff = { 0 }; 2127 struct ireg_buf *ma_indr; 2128 int i, rc, n; 2129 u32 size, j; 2130 2131 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2132 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2133 2134 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2135 size = sizeof(struct ireg_buf) * n * 2; 2136 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2137 if (rc) 2138 return rc; 2139 2140 ma_indr = (struct ireg_buf *)temp_buff.data; 2141 for (i = 0; i < n; i++) { 2142 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2143 u32 *buff = ma_indr->outbuf; 2144 2145 ma_fli->ireg_addr = t6_ma_ireg_array[i][0]; 2146 ma_fli->ireg_data = t6_ma_ireg_array[i][1]; 2147 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2]; 2148 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3]; 2149 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data, 2150 buff, ma_fli->ireg_offset_range, 2151 ma_fli->ireg_local_offset); 2152 ma_indr++; 2153 } 2154 2155 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32)); 2156 for (i = 0; i < n; i++) { 2157 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2158 u32 *buff = ma_indr->outbuf; 2159 2160 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0]; 2161 ma_fli->ireg_data = t6_ma_ireg_array2[i][1]; 2162 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2]; 2163 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) { 2164 t4_read_indirect(padap, ma_fli->ireg_addr, 2165 ma_fli->ireg_data, buff, 1, 2166 ma_fli->ireg_local_offset); 2167 buff++; 2168 ma_fli->ireg_local_offset += 0x20; 2169 } 2170 ma_indr++; 2171 } 2172 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2173 return rc; 2174 } 2175 2176 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init, 2177 struct cudbg_buffer *dbg_buff, 2178 struct cudbg_error *cudbg_err) 2179 { 2180 struct adapter *padap = pdbg_init->adap; 2181 struct cudbg_buffer temp_buff = { 0 }; 2182 struct cudbg_ulptx_la *ulptx_la_buff; 2183 u32 i, j; 2184 int rc; 2185 2186 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_ulptx_la), 2187 &temp_buff); 2188 if (rc) 2189 return rc; 2190 2191 ulptx_la_buff = (struct cudbg_ulptx_la *)temp_buff.data; 2192 for (i = 0; i < CUDBG_NUM_ULPTX; i++) { 2193 ulptx_la_buff->rdptr[i] = t4_read_reg(padap, 2194 ULP_TX_LA_RDPTR_0_A + 2195 0x10 * i); 2196 ulptx_la_buff->wrptr[i] = t4_read_reg(padap, 2197 ULP_TX_LA_WRPTR_0_A + 2198 0x10 * i); 2199 ulptx_la_buff->rddata[i] = t4_read_reg(padap, 2200 ULP_TX_LA_RDDATA_0_A + 2201 0x10 * i); 2202 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++) 2203 ulptx_la_buff->rd_data[i][j] = 2204 t4_read_reg(padap, 2205 ULP_TX_LA_RDDATA_0_A + 0x10 * i); 2206 } 2207 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2208 return rc; 2209 } 2210 2211 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init, 2212 struct cudbg_buffer *dbg_buff, 2213 struct cudbg_error *cudbg_err) 2214 { 2215 struct adapter *padap = pdbg_init->adap; 2216 struct cudbg_buffer temp_buff = { 0 }; 2217 struct ireg_buf *up_cim; 2218 int i, rc, n; 2219 u32 size; 2220 2221 n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2222 size = sizeof(struct ireg_buf) * n; 2223 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2224 if (rc) 2225 return rc; 2226 2227 up_cim = (struct ireg_buf *)temp_buff.data; 2228 for (i = 0; i < n; i++) { 2229 struct ireg_field *up_cim_reg = &up_cim->tp_pio; 2230 u32 *buff = up_cim->outbuf; 2231 2232 if (is_t5(padap->params.chip)) { 2233 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0]; 2234 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1]; 2235 up_cim_reg->ireg_local_offset = 2236 t5_up_cim_reg_array[i][2]; 2237 up_cim_reg->ireg_offset_range = 2238 t5_up_cim_reg_array[i][3]; 2239 } else if (is_t6(padap->params.chip)) { 2240 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0]; 2241 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1]; 2242 up_cim_reg->ireg_local_offset = 2243 t6_up_cim_reg_array[i][2]; 2244 up_cim_reg->ireg_offset_range = 2245 t6_up_cim_reg_array[i][3]; 2246 } 2247 2248 rc = t4_cim_read(padap, up_cim_reg->ireg_local_offset, 2249 up_cim_reg->ireg_offset_range, buff); 2250 if (rc) { 2251 cudbg_put_buff(&temp_buff, dbg_buff); 2252 return rc; 2253 } 2254 up_cim++; 2255 } 2256 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2257 return rc; 2258 } 2259 2260 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init, 2261 struct cudbg_buffer *dbg_buff, 2262 struct cudbg_error *cudbg_err) 2263 { 2264 struct adapter *padap = pdbg_init->adap; 2265 struct cudbg_buffer temp_buff = { 0 }; 2266 struct cudbg_pbt_tables *pbt; 2267 int i, rc; 2268 u32 addr; 2269 2270 rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pbt_tables), 2271 &temp_buff); 2272 if (rc) 2273 return rc; 2274 2275 pbt = (struct cudbg_pbt_tables *)temp_buff.data; 2276 /* PBT dynamic entries */ 2277 addr = CUDBG_CHAC_PBT_ADDR; 2278 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) { 2279 rc = t4_cim_read(padap, addr + (i * 4), 1, 2280 &pbt->pbt_dynamic[i]); 2281 if (rc) { 2282 cudbg_err->sys_err = rc; 2283 cudbg_put_buff(&temp_buff, dbg_buff); 2284 return rc; 2285 } 2286 } 2287 2288 /* PBT static entries */ 2289 /* static entries start when bit 6 is set */ 2290 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6); 2291 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) { 2292 rc = t4_cim_read(padap, addr + (i * 4), 1, 2293 &pbt->pbt_static[i]); 2294 if (rc) { 2295 cudbg_err->sys_err = rc; 2296 cudbg_put_buff(&temp_buff, dbg_buff); 2297 return rc; 2298 } 2299 } 2300 2301 /* LRF entries */ 2302 addr = CUDBG_CHAC_PBT_LRF; 2303 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) { 2304 rc = t4_cim_read(padap, addr + (i * 4), 1, 2305 &pbt->lrf_table[i]); 2306 if (rc) { 2307 cudbg_err->sys_err = rc; 2308 cudbg_put_buff(&temp_buff, dbg_buff); 2309 return rc; 2310 } 2311 } 2312 2313 /* PBT data entries */ 2314 addr = CUDBG_CHAC_PBT_DATA; 2315 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) { 2316 rc = t4_cim_read(padap, addr + (i * 4), 1, 2317 &pbt->pbt_data[i]); 2318 if (rc) { 2319 cudbg_err->sys_err = rc; 2320 cudbg_put_buff(&temp_buff, dbg_buff); 2321 return rc; 2322 } 2323 } 2324 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2325 return rc; 2326 } 2327 2328 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init, 2329 struct cudbg_buffer *dbg_buff, 2330 struct cudbg_error *cudbg_err) 2331 { 2332 struct adapter *padap = pdbg_init->adap; 2333 struct cudbg_mbox_log *mboxlog = NULL; 2334 struct cudbg_buffer temp_buff = { 0 }; 2335 struct mbox_cmd_log *log = NULL; 2336 struct mbox_cmd *entry; 2337 unsigned int entry_idx; 2338 u16 mbox_cmds; 2339 int i, k, rc; 2340 u64 flit; 2341 u32 size; 2342 2343 log = padap->mbox_log; 2344 mbox_cmds = padap->mbox_log->size; 2345 size = sizeof(struct cudbg_mbox_log) * mbox_cmds; 2346 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2347 if (rc) 2348 return rc; 2349 2350 mboxlog = (struct cudbg_mbox_log *)temp_buff.data; 2351 for (k = 0; k < mbox_cmds; k++) { 2352 entry_idx = log->cursor + k; 2353 if (entry_idx >= log->size) 2354 entry_idx -= log->size; 2355 2356 entry = mbox_cmd_log_entry(log, entry_idx); 2357 /* skip over unused entries */ 2358 if (entry->timestamp == 0) 2359 continue; 2360 2361 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd)); 2362 for (i = 0; i < MBOX_LEN / 8; i++) { 2363 flit = entry->cmd[i]; 2364 mboxlog->hi[i] = (u32)(flit >> 32); 2365 mboxlog->lo[i] = (u32)flit; 2366 } 2367 mboxlog++; 2368 } 2369 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2370 return rc; 2371 } 2372 2373 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init, 2374 struct cudbg_buffer *dbg_buff, 2375 struct cudbg_error *cudbg_err) 2376 { 2377 struct adapter *padap = pdbg_init->adap; 2378 struct cudbg_buffer temp_buff = { 0 }; 2379 struct ireg_buf *hma_indr; 2380 int i, rc, n; 2381 u32 size; 2382 2383 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2384 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2385 2386 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2387 size = sizeof(struct ireg_buf) * n; 2388 rc = cudbg_get_buff(dbg_buff, size, &temp_buff); 2389 if (rc) 2390 return rc; 2391 2392 hma_indr = (struct ireg_buf *)temp_buff.data; 2393 for (i = 0; i < n; i++) { 2394 struct ireg_field *hma_fli = &hma_indr->tp_pio; 2395 u32 *buff = hma_indr->outbuf; 2396 2397 hma_fli->ireg_addr = t6_hma_ireg_array[i][0]; 2398 hma_fli->ireg_data = t6_hma_ireg_array[i][1]; 2399 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2]; 2400 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3]; 2401 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data, 2402 buff, hma_fli->ireg_offset_range, 2403 hma_fli->ireg_local_offset); 2404 hma_indr++; 2405 } 2406 cudbg_write_and_release_buff(&temp_buff, dbg_buff); 2407 return rc; 2408 } 2409