1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #include <linux/sort.h> 19 20 #include "t4_regs.h" 21 #include "cxgb4.h" 22 #include "cudbg_if.h" 23 #include "cudbg_lib_common.h" 24 #include "cudbg_entity.h" 25 #include "cudbg_lib.h" 26 #include "cudbg_zlib.h" 27 28 static int cudbg_do_compression(struct cudbg_init *pdbg_init, 29 struct cudbg_buffer *pin_buff, 30 struct cudbg_buffer *dbg_buff) 31 { 32 struct cudbg_buffer temp_in_buff = { 0 }; 33 int bytes_left, bytes_read, bytes; 34 u32 offset = dbg_buff->offset; 35 int rc; 36 37 temp_in_buff.offset = pin_buff->offset; 38 temp_in_buff.data = pin_buff->data; 39 temp_in_buff.size = pin_buff->size; 40 41 bytes_left = pin_buff->size; 42 bytes_read = 0; 43 while (bytes_left > 0) { 44 /* Do compression in smaller chunks */ 45 bytes = min_t(unsigned long, bytes_left, 46 (unsigned long)CUDBG_CHUNK_SIZE); 47 temp_in_buff.data = (char *)pin_buff->data + bytes_read; 48 temp_in_buff.size = bytes; 49 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff); 50 if (rc) 51 return rc; 52 bytes_left -= bytes; 53 bytes_read += bytes; 54 } 55 56 pin_buff->size = dbg_buff->offset - offset; 57 return 0; 58 } 59 60 static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init, 61 struct cudbg_buffer *pin_buff, 62 struct cudbg_buffer *dbg_buff) 63 { 64 int rc = 0; 65 66 if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) { 67 cudbg_update_buff(pin_buff, dbg_buff); 68 } else { 69 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff); 70 if (rc) 71 goto out; 72 } 73 74 out: 75 cudbg_put_buff(pdbg_init, pin_buff); 76 return rc; 77 } 78 79 static int is_fw_attached(struct cudbg_init *pdbg_init) 80 { 81 struct adapter *padap = pdbg_init->adap; 82 83 if (!(padap->flags & FW_OK) || padap->use_bd) 84 return 0; 85 86 return 1; 87 } 88 89 /* This function will add additional padding bytes into debug_buffer to make it 90 * 4 byte aligned. 91 */ 92 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff, 93 struct cudbg_entity_hdr *entity_hdr) 94 { 95 u8 zero_buf[4] = {0}; 96 u8 padding, remain; 97 98 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4; 99 padding = 4 - remain; 100 if (remain) { 101 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf, 102 padding); 103 dbg_buff->offset += padding; 104 entity_hdr->num_pad = padding; 105 } 106 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset; 107 } 108 109 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i) 110 { 111 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf; 112 113 return (struct cudbg_entity_hdr *) 114 ((char *)outbuf + cudbg_hdr->hdr_len + 115 (sizeof(struct cudbg_entity_hdr) * (i - 1))); 116 } 117 118 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len, 119 void *dest) 120 { 121 int vaddr, rc; 122 123 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE); 124 if (vaddr < 0) 125 return vaddr; 126 127 rc = pci_read_vpd(padap->pdev, vaddr, len, dest); 128 if (rc < 0) 129 return rc; 130 131 return 0; 132 } 133 134 static int cudbg_mem_desc_cmp(const void *a, const void *b) 135 { 136 return ((const struct cudbg_mem_desc *)a)->base - 137 ((const struct cudbg_mem_desc *)b)->base; 138 } 139 140 int cudbg_fill_meminfo(struct adapter *padap, 141 struct cudbg_meminfo *meminfo_buff) 142 { 143 struct cudbg_mem_desc *md; 144 u32 lo, hi, used, alloc; 145 int n, i; 146 147 memset(meminfo_buff->avail, 0, 148 ARRAY_SIZE(meminfo_buff->avail) * 149 sizeof(struct cudbg_mem_desc)); 150 memset(meminfo_buff->mem, 0, 151 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc)); 152 md = meminfo_buff->mem; 153 154 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) { 155 meminfo_buff->mem[i].limit = 0; 156 meminfo_buff->mem[i].idx = i; 157 } 158 159 /* Find and sort the populated memory ranges */ 160 i = 0; 161 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A); 162 if (lo & EDRAM0_ENABLE_F) { 163 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A); 164 meminfo_buff->avail[i].base = 165 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi)); 166 meminfo_buff->avail[i].limit = 167 meminfo_buff->avail[i].base + 168 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi)); 169 meminfo_buff->avail[i].idx = 0; 170 i++; 171 } 172 173 if (lo & EDRAM1_ENABLE_F) { 174 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A); 175 meminfo_buff->avail[i].base = 176 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi)); 177 meminfo_buff->avail[i].limit = 178 meminfo_buff->avail[i].base + 179 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi)); 180 meminfo_buff->avail[i].idx = 1; 181 i++; 182 } 183 184 if (is_t5(padap->params.chip)) { 185 if (lo & EXT_MEM0_ENABLE_F) { 186 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A); 187 meminfo_buff->avail[i].base = 188 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 189 meminfo_buff->avail[i].limit = 190 meminfo_buff->avail[i].base + 191 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 192 meminfo_buff->avail[i].idx = 3; 193 i++; 194 } 195 196 if (lo & EXT_MEM1_ENABLE_F) { 197 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 198 meminfo_buff->avail[i].base = 199 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 200 meminfo_buff->avail[i].limit = 201 meminfo_buff->avail[i].base + 202 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 203 meminfo_buff->avail[i].idx = 4; 204 i++; 205 } 206 } else { 207 if (lo & EXT_MEM_ENABLE_F) { 208 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A); 209 meminfo_buff->avail[i].base = 210 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 211 meminfo_buff->avail[i].limit = 212 meminfo_buff->avail[i].base + 213 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 214 meminfo_buff->avail[i].idx = 2; 215 i++; 216 } 217 218 if (lo & HMA_MUX_F) { 219 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 220 meminfo_buff->avail[i].base = 221 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 222 meminfo_buff->avail[i].limit = 223 meminfo_buff->avail[i].base + 224 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 225 meminfo_buff->avail[i].idx = 5; 226 i++; 227 } 228 } 229 230 if (!i) /* no memory available */ 231 return CUDBG_STATUS_ENTITY_NOT_FOUND; 232 233 meminfo_buff->avail_c = i; 234 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc), 235 cudbg_mem_desc_cmp, NULL); 236 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); 237 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); 238 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); 239 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A); 240 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A); 241 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A); 242 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A); 243 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A); 244 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A); 245 246 /* the next few have explicit upper bounds */ 247 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A); 248 md->limit = md->base - 1 + 249 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) * 250 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A)); 251 md++; 252 253 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A); 254 md->limit = md->base - 1 + 255 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) * 256 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A)); 257 md++; 258 259 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) { 260 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) { 261 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4; 262 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 263 } else { 264 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 265 md->base = t4_read_reg(padap, 266 LE_DB_HASH_TBL_BASE_ADDR_A); 267 } 268 md->limit = 0; 269 } else { 270 md->base = 0; 271 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 272 } 273 md++; 274 275 #define ulp_region(reg) do { \ 276 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ 277 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\ 278 } while (0) 279 280 ulp_region(RX_ISCSI); 281 ulp_region(RX_TDDP); 282 ulp_region(TX_TPT); 283 ulp_region(RX_STAG); 284 ulp_region(RX_RQ); 285 ulp_region(RX_RQUDP); 286 ulp_region(RX_PBL); 287 ulp_region(TX_PBL); 288 #undef ulp_region 289 md->base = 0; 290 md->idx = ARRAY_SIZE(cudbg_region); 291 if (!is_t4(padap->params.chip)) { 292 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A); 293 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A); 294 u32 size = 0; 295 296 if (is_t5(padap->params.chip)) { 297 if (sge_ctrl & VFIFO_ENABLE_F) 298 size = DBVFIFO_SIZE_G(fifo_size); 299 } else { 300 size = T6_DBVFIFO_SIZE_G(fifo_size); 301 } 302 303 if (size) { 304 md->base = BASEADDR_G(t4_read_reg(padap, 305 SGE_DBVFIFO_BADDR_A)); 306 md->limit = md->base + (size << 2) - 1; 307 } 308 } 309 310 md++; 311 312 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A); 313 md->limit = 0; 314 md++; 315 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A); 316 md->limit = 0; 317 md++; 318 319 md->base = padap->vres.ocq.start; 320 if (padap->vres.ocq.size) 321 md->limit = md->base + padap->vres.ocq.size - 1; 322 else 323 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 324 md++; 325 326 /* add any address-space holes, there can be up to 3 */ 327 for (n = 0; n < i - 1; n++) 328 if (meminfo_buff->avail[n].limit < 329 meminfo_buff->avail[n + 1].base) 330 (md++)->base = meminfo_buff->avail[n].limit; 331 332 if (meminfo_buff->avail[n].limit) 333 (md++)->base = meminfo_buff->avail[n].limit; 334 335 n = md - meminfo_buff->mem; 336 meminfo_buff->mem_c = n; 337 338 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc), 339 cudbg_mem_desc_cmp, NULL); 340 341 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A); 342 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1; 343 meminfo_buff->up_ram_lo = lo; 344 meminfo_buff->up_ram_hi = hi; 345 346 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A); 347 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1; 348 meminfo_buff->up_extmem2_lo = lo; 349 meminfo_buff->up_extmem2_hi = hi; 350 351 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A); 352 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo); 353 meminfo_buff->rx_pages_data[1] = 354 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10; 355 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1; 356 357 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A); 358 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A); 359 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo); 360 meminfo_buff->tx_pages_data[1] = 361 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10); 362 meminfo_buff->tx_pages_data[2] = 363 hi >= (1 << 20) ? 'M' : 'K'; 364 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo); 365 366 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A); 367 368 for (i = 0; i < 4; i++) { 369 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 370 lo = t4_read_reg(padap, 371 MPS_RX_MAC_BG_PG_CNT0_A + i * 4); 372 else 373 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4); 374 if (is_t5(padap->params.chip)) { 375 used = T5_USED_G(lo); 376 alloc = T5_ALLOC_G(lo); 377 } else { 378 used = USED_G(lo); 379 alloc = ALLOC_G(lo); 380 } 381 meminfo_buff->port_used[i] = used; 382 meminfo_buff->port_alloc[i] = alloc; 383 } 384 385 for (i = 0; i < padap->params.arch.nchan; i++) { 386 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 387 lo = t4_read_reg(padap, 388 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4); 389 else 390 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4); 391 if (is_t5(padap->params.chip)) { 392 used = T5_USED_G(lo); 393 alloc = T5_ALLOC_G(lo); 394 } else { 395 used = USED_G(lo); 396 alloc = ALLOC_G(lo); 397 } 398 meminfo_buff->loopback_used[i] = used; 399 meminfo_buff->loopback_alloc[i] = alloc; 400 } 401 402 return 0; 403 } 404 405 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init, 406 struct cudbg_buffer *dbg_buff, 407 struct cudbg_error *cudbg_err) 408 { 409 struct adapter *padap = pdbg_init->adap; 410 struct cudbg_buffer temp_buff = { 0 }; 411 u32 buf_size = 0; 412 int rc = 0; 413 414 if (is_t4(padap->params.chip)) 415 buf_size = T4_REGMAP_SIZE; 416 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip)) 417 buf_size = T5_REGMAP_SIZE; 418 419 rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff); 420 if (rc) 421 return rc; 422 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size); 423 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 424 } 425 426 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init, 427 struct cudbg_buffer *dbg_buff, 428 struct cudbg_error *cudbg_err) 429 { 430 struct adapter *padap = pdbg_init->adap; 431 struct cudbg_buffer temp_buff = { 0 }; 432 struct devlog_params *dparams; 433 int rc = 0; 434 435 rc = t4_init_devlog_params(padap); 436 if (rc < 0) { 437 cudbg_err->sys_err = rc; 438 return rc; 439 } 440 441 dparams = &padap->params.devlog; 442 rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff); 443 if (rc) 444 return rc; 445 446 /* Collect FW devlog */ 447 if (dparams->start != 0) { 448 spin_lock(&padap->win0_lock); 449 rc = t4_memory_rw(padap, padap->params.drv_memwin, 450 dparams->memtype, dparams->start, 451 dparams->size, 452 (__be32 *)(char *)temp_buff.data, 453 1); 454 spin_unlock(&padap->win0_lock); 455 if (rc) { 456 cudbg_err->sys_err = rc; 457 cudbg_put_buff(pdbg_init, &temp_buff); 458 return rc; 459 } 460 } 461 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 462 } 463 464 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init, 465 struct cudbg_buffer *dbg_buff, 466 struct cudbg_error *cudbg_err) 467 { 468 struct adapter *padap = pdbg_init->adap; 469 struct cudbg_buffer temp_buff = { 0 }; 470 int size, rc; 471 u32 cfg = 0; 472 473 if (is_t6(padap->params.chip)) { 474 size = padap->params.cim_la_size / 10 + 1; 475 size *= 10 * sizeof(u32); 476 } else { 477 size = padap->params.cim_la_size / 8; 478 size *= 8 * sizeof(u32); 479 } 480 481 size += sizeof(cfg); 482 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 483 if (rc) 484 return rc; 485 486 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 487 if (rc) { 488 cudbg_err->sys_err = rc; 489 cudbg_put_buff(pdbg_init, &temp_buff); 490 return rc; 491 } 492 493 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg)); 494 rc = t4_cim_read_la(padap, 495 (u32 *)((char *)temp_buff.data + sizeof(cfg)), 496 NULL); 497 if (rc < 0) { 498 cudbg_err->sys_err = rc; 499 cudbg_put_buff(pdbg_init, &temp_buff); 500 return rc; 501 } 502 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 503 } 504 505 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init, 506 struct cudbg_buffer *dbg_buff, 507 struct cudbg_error *cudbg_err) 508 { 509 struct adapter *padap = pdbg_init->adap; 510 struct cudbg_buffer temp_buff = { 0 }; 511 int size, rc; 512 513 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); 514 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 515 if (rc) 516 return rc; 517 518 t4_cim_read_ma_la(padap, 519 (u32 *)temp_buff.data, 520 (u32 *)((char *)temp_buff.data + 521 5 * CIM_MALA_SIZE)); 522 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 523 } 524 525 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init, 526 struct cudbg_buffer *dbg_buff, 527 struct cudbg_error *cudbg_err) 528 { 529 struct adapter *padap = pdbg_init->adap; 530 struct cudbg_buffer temp_buff = { 0 }; 531 struct cudbg_cim_qcfg *cim_qcfg_data; 532 int rc; 533 534 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg), 535 &temp_buff); 536 if (rc) 537 return rc; 538 539 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data; 540 cim_qcfg_data->chip = padap->params.chip; 541 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A, 542 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat); 543 if (rc) { 544 cudbg_err->sys_err = rc; 545 cudbg_put_buff(pdbg_init, &temp_buff); 546 return rc; 547 } 548 549 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A, 550 ARRAY_SIZE(cim_qcfg_data->obq_wr), 551 cim_qcfg_data->obq_wr); 552 if (rc) { 553 cudbg_err->sys_err = rc; 554 cudbg_put_buff(pdbg_init, &temp_buff); 555 return rc; 556 } 557 558 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size, 559 cim_qcfg_data->thres); 560 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 561 } 562 563 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init, 564 struct cudbg_buffer *dbg_buff, 565 struct cudbg_error *cudbg_err, int qid) 566 { 567 struct adapter *padap = pdbg_init->adap; 568 struct cudbg_buffer temp_buff = { 0 }; 569 int no_of_read_words, rc = 0; 570 u32 qsize; 571 572 /* collect CIM IBQ */ 573 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32); 574 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff); 575 if (rc) 576 return rc; 577 578 /* t4_read_cim_ibq will return no. of read words or error */ 579 no_of_read_words = t4_read_cim_ibq(padap, qid, 580 (u32 *)temp_buff.data, qsize); 581 /* no_of_read_words is less than or equal to 0 means error */ 582 if (no_of_read_words <= 0) { 583 if (!no_of_read_words) 584 rc = CUDBG_SYSTEM_ERROR; 585 else 586 rc = no_of_read_words; 587 cudbg_err->sys_err = rc; 588 cudbg_put_buff(pdbg_init, &temp_buff); 589 return rc; 590 } 591 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 592 } 593 594 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init, 595 struct cudbg_buffer *dbg_buff, 596 struct cudbg_error *cudbg_err) 597 { 598 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0); 599 } 600 601 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init, 602 struct cudbg_buffer *dbg_buff, 603 struct cudbg_error *cudbg_err) 604 { 605 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1); 606 } 607 608 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init, 609 struct cudbg_buffer *dbg_buff, 610 struct cudbg_error *cudbg_err) 611 { 612 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2); 613 } 614 615 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init, 616 struct cudbg_buffer *dbg_buff, 617 struct cudbg_error *cudbg_err) 618 { 619 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3); 620 } 621 622 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init, 623 struct cudbg_buffer *dbg_buff, 624 struct cudbg_error *cudbg_err) 625 { 626 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4); 627 } 628 629 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init, 630 struct cudbg_buffer *dbg_buff, 631 struct cudbg_error *cudbg_err) 632 { 633 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5); 634 } 635 636 u32 cudbg_cim_obq_size(struct adapter *padap, int qid) 637 { 638 u32 value; 639 640 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 641 QUENUMSELECT_V(qid)); 642 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A); 643 value = CIMQSIZE_G(value) * 64; /* size in number of words */ 644 return value * sizeof(u32); 645 } 646 647 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init, 648 struct cudbg_buffer *dbg_buff, 649 struct cudbg_error *cudbg_err, int qid) 650 { 651 struct adapter *padap = pdbg_init->adap; 652 struct cudbg_buffer temp_buff = { 0 }; 653 int no_of_read_words, rc = 0; 654 u32 qsize; 655 656 /* collect CIM OBQ */ 657 qsize = cudbg_cim_obq_size(padap, qid); 658 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff); 659 if (rc) 660 return rc; 661 662 /* t4_read_cim_obq will return no. of read words or error */ 663 no_of_read_words = t4_read_cim_obq(padap, qid, 664 (u32 *)temp_buff.data, qsize); 665 /* no_of_read_words is less than or equal to 0 means error */ 666 if (no_of_read_words <= 0) { 667 if (!no_of_read_words) 668 rc = CUDBG_SYSTEM_ERROR; 669 else 670 rc = no_of_read_words; 671 cudbg_err->sys_err = rc; 672 cudbg_put_buff(pdbg_init, &temp_buff); 673 return rc; 674 } 675 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 676 } 677 678 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init, 679 struct cudbg_buffer *dbg_buff, 680 struct cudbg_error *cudbg_err) 681 { 682 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0); 683 } 684 685 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init, 686 struct cudbg_buffer *dbg_buff, 687 struct cudbg_error *cudbg_err) 688 { 689 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1); 690 } 691 692 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init, 693 struct cudbg_buffer *dbg_buff, 694 struct cudbg_error *cudbg_err) 695 { 696 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2); 697 } 698 699 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init, 700 struct cudbg_buffer *dbg_buff, 701 struct cudbg_error *cudbg_err) 702 { 703 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3); 704 } 705 706 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init, 707 struct cudbg_buffer *dbg_buff, 708 struct cudbg_error *cudbg_err) 709 { 710 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4); 711 } 712 713 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init, 714 struct cudbg_buffer *dbg_buff, 715 struct cudbg_error *cudbg_err) 716 { 717 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5); 718 } 719 720 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init, 721 struct cudbg_buffer *dbg_buff, 722 struct cudbg_error *cudbg_err) 723 { 724 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6); 725 } 726 727 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init, 728 struct cudbg_buffer *dbg_buff, 729 struct cudbg_error *cudbg_err) 730 { 731 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7); 732 } 733 734 static int cudbg_meminfo_get_mem_index(struct adapter *padap, 735 struct cudbg_meminfo *mem_info, 736 u8 mem_type, u8 *idx) 737 { 738 u8 i, flag; 739 740 switch (mem_type) { 741 case MEM_EDC0: 742 flag = EDC0_FLAG; 743 break; 744 case MEM_EDC1: 745 flag = EDC1_FLAG; 746 break; 747 case MEM_MC0: 748 /* Some T5 cards have both MC0 and MC1. */ 749 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG; 750 break; 751 case MEM_MC1: 752 flag = MC1_FLAG; 753 break; 754 case MEM_HMA: 755 flag = HMA_FLAG; 756 break; 757 default: 758 return CUDBG_STATUS_ENTITY_NOT_FOUND; 759 } 760 761 for (i = 0; i < mem_info->avail_c; i++) { 762 if (mem_info->avail[i].idx == flag) { 763 *idx = i; 764 return 0; 765 } 766 } 767 768 return CUDBG_STATUS_ENTITY_NOT_FOUND; 769 } 770 771 /* Fetch the @region_name's start and end from @meminfo. */ 772 static int cudbg_get_mem_region(struct adapter *padap, 773 struct cudbg_meminfo *meminfo, 774 u8 mem_type, const char *region_name, 775 struct cudbg_mem_desc *mem_desc) 776 { 777 u8 mc, found = 0; 778 u32 i, idx = 0; 779 int rc; 780 781 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc); 782 if (rc) 783 return rc; 784 785 for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) { 786 if (!strcmp(cudbg_region[i], region_name)) { 787 found = 1; 788 idx = i; 789 break; 790 } 791 } 792 if (!found) 793 return -EINVAL; 794 795 found = 0; 796 for (i = 0; i < meminfo->mem_c; i++) { 797 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region)) 798 continue; /* Skip holes */ 799 800 if (!(meminfo->mem[i].limit)) 801 meminfo->mem[i].limit = 802 i < meminfo->mem_c - 1 ? 803 meminfo->mem[i + 1].base - 1 : ~0; 804 805 if (meminfo->mem[i].idx == idx) { 806 /* Check if the region exists in @mem_type memory */ 807 if (meminfo->mem[i].base < meminfo->avail[mc].base && 808 meminfo->mem[i].limit < meminfo->avail[mc].base) 809 return -EINVAL; 810 811 if (meminfo->mem[i].base > meminfo->avail[mc].limit) 812 return -EINVAL; 813 814 memcpy(mem_desc, &meminfo->mem[i], 815 sizeof(struct cudbg_mem_desc)); 816 found = 1; 817 break; 818 } 819 } 820 if (!found) 821 return -EINVAL; 822 823 return 0; 824 } 825 826 /* Fetch and update the start and end of the requested memory region w.r.t 0 827 * in the corresponding EDC/MC/HMA. 828 */ 829 static int cudbg_get_mem_relative(struct adapter *padap, 830 struct cudbg_meminfo *meminfo, 831 u8 mem_type, u32 *out_base, u32 *out_end) 832 { 833 u8 mc_idx; 834 int rc; 835 836 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx); 837 if (rc) 838 return rc; 839 840 if (*out_base < meminfo->avail[mc_idx].base) 841 *out_base = 0; 842 else 843 *out_base -= meminfo->avail[mc_idx].base; 844 845 if (*out_end > meminfo->avail[mc_idx].limit) 846 *out_end = meminfo->avail[mc_idx].limit; 847 else 848 *out_end -= meminfo->avail[mc_idx].base; 849 850 return 0; 851 } 852 853 /* Get TX and RX Payload region */ 854 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type, 855 const char *region_name, 856 struct cudbg_region_info *payload) 857 { 858 struct cudbg_mem_desc mem_desc = { 0 }; 859 struct cudbg_meminfo meminfo; 860 int rc; 861 862 rc = cudbg_fill_meminfo(padap, &meminfo); 863 if (rc) 864 return rc; 865 866 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name, 867 &mem_desc); 868 if (rc) { 869 payload->exist = false; 870 return 0; 871 } 872 873 payload->exist = true; 874 payload->start = mem_desc.base; 875 payload->end = mem_desc.limit; 876 877 return cudbg_get_mem_relative(padap, &meminfo, mem_type, 878 &payload->start, &payload->end); 879 } 880 881 static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win, 882 int mtype, u32 addr, u32 len, void *hbuf) 883 { 884 u32 win_pf, memoffset, mem_aperture, mem_base; 885 struct adapter *adap = pdbg_init->adap; 886 u32 pos, offset, resid; 887 u32 *res_buf; 888 u64 *buf; 889 int ret; 890 891 /* Argument sanity checks ... 892 */ 893 if (addr & 0x3 || (uintptr_t)hbuf & 0x3) 894 return -EINVAL; 895 896 buf = (u64 *)hbuf; 897 898 /* Try to do 64-bit reads. Residual will be handled later. */ 899 resid = len & 0x7; 900 len -= resid; 901 902 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base, 903 &mem_aperture); 904 if (ret) 905 return ret; 906 907 addr = addr + memoffset; 908 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); 909 910 pos = addr & ~(mem_aperture - 1); 911 offset = addr - pos; 912 913 /* Set up initial PCI-E Memory Window to cover the start of our 914 * transfer. 915 */ 916 t4_memory_update_win(adap, win, pos | win_pf); 917 918 /* Transfer data from the adapter */ 919 while (len > 0) { 920 *buf++ = le64_to_cpu((__force __le64) 921 t4_read_reg64(adap, mem_base + offset)); 922 offset += sizeof(u64); 923 len -= sizeof(u64); 924 925 /* If we've reached the end of our current window aperture, 926 * move the PCI-E Memory Window on to the next. 927 */ 928 if (offset == mem_aperture) { 929 pos += mem_aperture; 930 offset = 0; 931 t4_memory_update_win(adap, win, pos | win_pf); 932 } 933 } 934 935 res_buf = (u32 *)buf; 936 /* Read residual in 32-bit multiples */ 937 while (resid > sizeof(u32)) { 938 *res_buf++ = le32_to_cpu((__force __le32) 939 t4_read_reg(adap, mem_base + offset)); 940 offset += sizeof(u32); 941 resid -= sizeof(u32); 942 943 /* If we've reached the end of our current window aperture, 944 * move the PCI-E Memory Window on to the next. 945 */ 946 if (offset == mem_aperture) { 947 pos += mem_aperture; 948 offset = 0; 949 t4_memory_update_win(adap, win, pos | win_pf); 950 } 951 } 952 953 /* Transfer residual < 32-bits */ 954 if (resid) 955 t4_memory_rw_residual(adap, resid, mem_base + offset, 956 (u8 *)res_buf, T4_MEMORY_READ); 957 958 return 0; 959 } 960 961 #define CUDBG_YIELD_ITERATION 256 962 963 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init, 964 struct cudbg_buffer *dbg_buff, u8 mem_type, 965 unsigned long tot_len, 966 struct cudbg_error *cudbg_err) 967 { 968 static const char * const region_name[] = { "Tx payload:", 969 "Rx payload:" }; 970 unsigned long bytes, bytes_left, bytes_read = 0; 971 struct adapter *padap = pdbg_init->adap; 972 struct cudbg_buffer temp_buff = { 0 }; 973 struct cudbg_region_info payload[2]; 974 u32 yield_count = 0; 975 int rc = 0; 976 u8 i; 977 978 /* Get TX/RX Payload region range if they exist */ 979 memset(payload, 0, sizeof(payload)); 980 for (i = 0; i < ARRAY_SIZE(region_name); i++) { 981 rc = cudbg_get_payload_range(padap, mem_type, region_name[i], 982 &payload[i]); 983 if (rc) 984 return rc; 985 986 if (payload[i].exist) { 987 /* Align start and end to avoid wrap around */ 988 payload[i].start = roundup(payload[i].start, 989 CUDBG_CHUNK_SIZE); 990 payload[i].end = rounddown(payload[i].end, 991 CUDBG_CHUNK_SIZE); 992 } 993 } 994 995 bytes_left = tot_len; 996 while (bytes_left > 0) { 997 /* As MC size is huge and read through PIO access, this 998 * loop will hold cpu for a longer time. OS may think that 999 * the process is hanged and will generate CPU stall traces. 1000 * So yield the cpu regularly. 1001 */ 1002 yield_count++; 1003 if (!(yield_count % CUDBG_YIELD_ITERATION)) 1004 schedule(); 1005 1006 bytes = min_t(unsigned long, bytes_left, 1007 (unsigned long)CUDBG_CHUNK_SIZE); 1008 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff); 1009 if (rc) 1010 return rc; 1011 1012 for (i = 0; i < ARRAY_SIZE(payload); i++) 1013 if (payload[i].exist && 1014 bytes_read >= payload[i].start && 1015 bytes_read + bytes <= payload[i].end) 1016 /* TX and RX Payload regions can't overlap */ 1017 goto skip_read; 1018 1019 spin_lock(&padap->win0_lock); 1020 rc = cudbg_memory_read(pdbg_init, MEMWIN_NIC, mem_type, 1021 bytes_read, bytes, temp_buff.data); 1022 spin_unlock(&padap->win0_lock); 1023 if (rc) { 1024 cudbg_err->sys_err = rc; 1025 cudbg_put_buff(pdbg_init, &temp_buff); 1026 return rc; 1027 } 1028 1029 skip_read: 1030 bytes_left -= bytes; 1031 bytes_read += bytes; 1032 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff, 1033 dbg_buff); 1034 if (rc) { 1035 cudbg_put_buff(pdbg_init, &temp_buff); 1036 return rc; 1037 } 1038 } 1039 return rc; 1040 } 1041 1042 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init, 1043 struct cudbg_error *cudbg_err) 1044 { 1045 struct adapter *padap = pdbg_init->adap; 1046 int rc; 1047 1048 if (is_fw_attached(pdbg_init)) { 1049 /* Flush uP dcache before reading edcX/mcX */ 1050 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH); 1051 if (rc) 1052 cudbg_err->sys_warn = rc; 1053 } 1054 } 1055 1056 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init, 1057 struct cudbg_buffer *dbg_buff, 1058 struct cudbg_error *cudbg_err, 1059 u8 mem_type) 1060 { 1061 struct adapter *padap = pdbg_init->adap; 1062 struct cudbg_meminfo mem_info; 1063 unsigned long size; 1064 u8 mc_idx; 1065 int rc; 1066 1067 memset(&mem_info, 0, sizeof(struct cudbg_meminfo)); 1068 rc = cudbg_fill_meminfo(padap, &mem_info); 1069 if (rc) 1070 return rc; 1071 1072 cudbg_t4_fwcache(pdbg_init, cudbg_err); 1073 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx); 1074 if (rc) 1075 return rc; 1076 1077 size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base; 1078 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size, 1079 cudbg_err); 1080 } 1081 1082 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init, 1083 struct cudbg_buffer *dbg_buff, 1084 struct cudbg_error *cudbg_err) 1085 { 1086 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1087 MEM_EDC0); 1088 } 1089 1090 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init, 1091 struct cudbg_buffer *dbg_buff, 1092 struct cudbg_error *cudbg_err) 1093 { 1094 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1095 MEM_EDC1); 1096 } 1097 1098 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init, 1099 struct cudbg_buffer *dbg_buff, 1100 struct cudbg_error *cudbg_err) 1101 { 1102 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1103 MEM_MC0); 1104 } 1105 1106 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init, 1107 struct cudbg_buffer *dbg_buff, 1108 struct cudbg_error *cudbg_err) 1109 { 1110 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1111 MEM_MC1); 1112 } 1113 1114 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init, 1115 struct cudbg_buffer *dbg_buff, 1116 struct cudbg_error *cudbg_err) 1117 { 1118 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1119 MEM_HMA); 1120 } 1121 1122 int cudbg_collect_rss(struct cudbg_init *pdbg_init, 1123 struct cudbg_buffer *dbg_buff, 1124 struct cudbg_error *cudbg_err) 1125 { 1126 struct adapter *padap = pdbg_init->adap; 1127 struct cudbg_buffer temp_buff = { 0 }; 1128 int rc, nentries; 1129 1130 nentries = t4_chip_rss_size(padap); 1131 rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16), 1132 &temp_buff); 1133 if (rc) 1134 return rc; 1135 1136 rc = t4_read_rss(padap, (u16 *)temp_buff.data); 1137 if (rc) { 1138 cudbg_err->sys_err = rc; 1139 cudbg_put_buff(pdbg_init, &temp_buff); 1140 return rc; 1141 } 1142 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1143 } 1144 1145 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init, 1146 struct cudbg_buffer *dbg_buff, 1147 struct cudbg_error *cudbg_err) 1148 { 1149 struct adapter *padap = pdbg_init->adap; 1150 struct cudbg_buffer temp_buff = { 0 }; 1151 struct cudbg_rss_vf_conf *vfconf; 1152 int vf, rc, vf_count; 1153 1154 vf_count = padap->params.arch.vfcount; 1155 rc = cudbg_get_buff(pdbg_init, dbg_buff, 1156 vf_count * sizeof(struct cudbg_rss_vf_conf), 1157 &temp_buff); 1158 if (rc) 1159 return rc; 1160 1161 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data; 1162 for (vf = 0; vf < vf_count; vf++) 1163 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl, 1164 &vfconf[vf].rss_vf_vfh, true); 1165 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1166 } 1167 1168 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init, 1169 struct cudbg_buffer *dbg_buff, 1170 struct cudbg_error *cudbg_err) 1171 { 1172 struct adapter *padap = pdbg_init->adap; 1173 struct cudbg_buffer temp_buff = { 0 }; 1174 int rc; 1175 1176 rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16), 1177 &temp_buff); 1178 if (rc) 1179 return rc; 1180 1181 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL); 1182 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1183 } 1184 1185 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init, 1186 struct cudbg_buffer *dbg_buff, 1187 struct cudbg_error *cudbg_err) 1188 { 1189 struct adapter *padap = pdbg_init->adap; 1190 struct cudbg_buffer temp_buff = { 0 }; 1191 struct cudbg_pm_stats *pm_stats_buff; 1192 int rc; 1193 1194 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats), 1195 &temp_buff); 1196 if (rc) 1197 return rc; 1198 1199 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data; 1200 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc); 1201 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc); 1202 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1203 } 1204 1205 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init, 1206 struct cudbg_buffer *dbg_buff, 1207 struct cudbg_error *cudbg_err) 1208 { 1209 struct adapter *padap = pdbg_init->adap; 1210 struct cudbg_buffer temp_buff = { 0 }; 1211 struct cudbg_hw_sched *hw_sched_buff; 1212 int i, rc = 0; 1213 1214 if (!padap->params.vpd.cclk) 1215 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1216 1217 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched), 1218 &temp_buff); 1219 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data; 1220 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A); 1221 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A)); 1222 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab); 1223 for (i = 0; i < NTX_SCHED; ++i) 1224 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i], 1225 &hw_sched_buff->ipg[i], true); 1226 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1227 } 1228 1229 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init, 1230 struct cudbg_buffer *dbg_buff, 1231 struct cudbg_error *cudbg_err) 1232 { 1233 struct adapter *padap = pdbg_init->adap; 1234 struct cudbg_buffer temp_buff = { 0 }; 1235 struct ireg_buf *ch_tp_pio; 1236 int i, rc, n = 0; 1237 u32 size; 1238 1239 if (is_t5(padap->params.chip)) 1240 n = sizeof(t5_tp_pio_array) + 1241 sizeof(t5_tp_tm_pio_array) + 1242 sizeof(t5_tp_mib_index_array); 1243 else 1244 n = sizeof(t6_tp_pio_array) + 1245 sizeof(t6_tp_tm_pio_array) + 1246 sizeof(t6_tp_mib_index_array); 1247 1248 n = n / (IREG_NUM_ELEM * sizeof(u32)); 1249 size = sizeof(struct ireg_buf) * n; 1250 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1251 if (rc) 1252 return rc; 1253 1254 ch_tp_pio = (struct ireg_buf *)temp_buff.data; 1255 1256 /* TP_PIO */ 1257 if (is_t5(padap->params.chip)) 1258 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1259 else if (is_t6(padap->params.chip)) 1260 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1261 1262 for (i = 0; i < n; i++) { 1263 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1264 u32 *buff = ch_tp_pio->outbuf; 1265 1266 if (is_t5(padap->params.chip)) { 1267 tp_pio->ireg_addr = t5_tp_pio_array[i][0]; 1268 tp_pio->ireg_data = t5_tp_pio_array[i][1]; 1269 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2]; 1270 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3]; 1271 } else if (is_t6(padap->params.chip)) { 1272 tp_pio->ireg_addr = t6_tp_pio_array[i][0]; 1273 tp_pio->ireg_data = t6_tp_pio_array[i][1]; 1274 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2]; 1275 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3]; 1276 } 1277 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range, 1278 tp_pio->ireg_local_offset, true); 1279 ch_tp_pio++; 1280 } 1281 1282 /* TP_TM_PIO */ 1283 if (is_t5(padap->params.chip)) 1284 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1285 else if (is_t6(padap->params.chip)) 1286 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1287 1288 for (i = 0; i < n; i++) { 1289 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1290 u32 *buff = ch_tp_pio->outbuf; 1291 1292 if (is_t5(padap->params.chip)) { 1293 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0]; 1294 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1]; 1295 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2]; 1296 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3]; 1297 } else if (is_t6(padap->params.chip)) { 1298 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0]; 1299 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1]; 1300 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2]; 1301 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3]; 1302 } 1303 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range, 1304 tp_pio->ireg_local_offset, true); 1305 ch_tp_pio++; 1306 } 1307 1308 /* TP_MIB_INDEX */ 1309 if (is_t5(padap->params.chip)) 1310 n = sizeof(t5_tp_mib_index_array) / 1311 (IREG_NUM_ELEM * sizeof(u32)); 1312 else if (is_t6(padap->params.chip)) 1313 n = sizeof(t6_tp_mib_index_array) / 1314 (IREG_NUM_ELEM * sizeof(u32)); 1315 1316 for (i = 0; i < n ; i++) { 1317 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1318 u32 *buff = ch_tp_pio->outbuf; 1319 1320 if (is_t5(padap->params.chip)) { 1321 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0]; 1322 tp_pio->ireg_data = t5_tp_mib_index_array[i][1]; 1323 tp_pio->ireg_local_offset = 1324 t5_tp_mib_index_array[i][2]; 1325 tp_pio->ireg_offset_range = 1326 t5_tp_mib_index_array[i][3]; 1327 } else if (is_t6(padap->params.chip)) { 1328 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0]; 1329 tp_pio->ireg_data = t6_tp_mib_index_array[i][1]; 1330 tp_pio->ireg_local_offset = 1331 t6_tp_mib_index_array[i][2]; 1332 tp_pio->ireg_offset_range = 1333 t6_tp_mib_index_array[i][3]; 1334 } 1335 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range, 1336 tp_pio->ireg_local_offset, true); 1337 ch_tp_pio++; 1338 } 1339 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1340 } 1341 1342 static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap, 1343 struct sge_qbase_reg_field *qbase, 1344 u32 func, bool is_pf) 1345 { 1346 u32 *buff, i; 1347 1348 if (is_pf) { 1349 buff = qbase->pf_data_value[func]; 1350 } else { 1351 buff = qbase->vf_data_value[func]; 1352 /* In SGE_QBASE_INDEX, 1353 * Entries 0->7 are PF0->7, Entries 8->263 are VFID0->256. 1354 */ 1355 func += 8; 1356 } 1357 1358 t4_write_reg(padap, qbase->reg_addr, func); 1359 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++) 1360 *buff = t4_read_reg(padap, qbase->reg_data[i]); 1361 } 1362 1363 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init, 1364 struct cudbg_buffer *dbg_buff, 1365 struct cudbg_error *cudbg_err) 1366 { 1367 struct adapter *padap = pdbg_init->adap; 1368 struct cudbg_buffer temp_buff = { 0 }; 1369 struct sge_qbase_reg_field *sge_qbase; 1370 struct ireg_buf *ch_sge_dbg; 1371 int i, rc; 1372 1373 rc = cudbg_get_buff(pdbg_init, dbg_buff, 1374 sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase), 1375 &temp_buff); 1376 if (rc) 1377 return rc; 1378 1379 ch_sge_dbg = (struct ireg_buf *)temp_buff.data; 1380 for (i = 0; i < 2; i++) { 1381 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio; 1382 u32 *buff = ch_sge_dbg->outbuf; 1383 1384 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0]; 1385 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1]; 1386 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2]; 1387 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3]; 1388 t4_read_indirect(padap, 1389 sge_pio->ireg_addr, 1390 sge_pio->ireg_data, 1391 buff, 1392 sge_pio->ireg_offset_range, 1393 sge_pio->ireg_local_offset); 1394 ch_sge_dbg++; 1395 } 1396 1397 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { 1398 sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg; 1399 /* 1 addr reg SGE_QBASE_INDEX and 4 data reg 1400 * SGE_QBASE_MAP[0-3] 1401 */ 1402 sge_qbase->reg_addr = t6_sge_qbase_index_array[0]; 1403 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++) 1404 sge_qbase->reg_data[i] = 1405 t6_sge_qbase_index_array[i + 1]; 1406 1407 for (i = 0; i <= PCIE_FW_MASTER_M; i++) 1408 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase, 1409 i, true); 1410 1411 for (i = 0; i < padap->params.arch.vfcount; i++) 1412 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase, 1413 i, false); 1414 1415 sge_qbase->vfcount = padap->params.arch.vfcount; 1416 } 1417 1418 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1419 } 1420 1421 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init, 1422 struct cudbg_buffer *dbg_buff, 1423 struct cudbg_error *cudbg_err) 1424 { 1425 struct adapter *padap = pdbg_init->adap; 1426 struct cudbg_buffer temp_buff = { 0 }; 1427 struct cudbg_ulprx_la *ulprx_la_buff; 1428 int rc; 1429 1430 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la), 1431 &temp_buff); 1432 if (rc) 1433 return rc; 1434 1435 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data; 1436 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data); 1437 ulprx_la_buff->size = ULPRX_LA_SIZE; 1438 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1439 } 1440 1441 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init, 1442 struct cudbg_buffer *dbg_buff, 1443 struct cudbg_error *cudbg_err) 1444 { 1445 struct adapter *padap = pdbg_init->adap; 1446 struct cudbg_buffer temp_buff = { 0 }; 1447 struct cudbg_tp_la *tp_la_buff; 1448 int size, rc; 1449 1450 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); 1451 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1452 if (rc) 1453 return rc; 1454 1455 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data; 1456 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A)); 1457 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL); 1458 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1459 } 1460 1461 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init, 1462 struct cudbg_buffer *dbg_buff, 1463 struct cudbg_error *cudbg_err) 1464 { 1465 struct adapter *padap = pdbg_init->adap; 1466 struct cudbg_buffer temp_buff = { 0 }; 1467 struct cudbg_meminfo *meminfo_buff; 1468 int rc; 1469 1470 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_meminfo), 1471 &temp_buff); 1472 if (rc) 1473 return rc; 1474 1475 meminfo_buff = (struct cudbg_meminfo *)temp_buff.data; 1476 rc = cudbg_fill_meminfo(padap, meminfo_buff); 1477 if (rc) { 1478 cudbg_err->sys_err = rc; 1479 cudbg_put_buff(pdbg_init, &temp_buff); 1480 return rc; 1481 } 1482 1483 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1484 } 1485 1486 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init, 1487 struct cudbg_buffer *dbg_buff, 1488 struct cudbg_error *cudbg_err) 1489 { 1490 struct cudbg_cim_pif_la *cim_pif_la_buff; 1491 struct adapter *padap = pdbg_init->adap; 1492 struct cudbg_buffer temp_buff = { 0 }; 1493 int size, rc; 1494 1495 size = sizeof(struct cudbg_cim_pif_la) + 1496 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); 1497 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1498 if (rc) 1499 return rc; 1500 1501 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data; 1502 cim_pif_la_buff->size = CIM_PIFLA_SIZE; 1503 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data, 1504 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE, 1505 NULL, NULL); 1506 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1507 } 1508 1509 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init, 1510 struct cudbg_buffer *dbg_buff, 1511 struct cudbg_error *cudbg_err) 1512 { 1513 struct adapter *padap = pdbg_init->adap; 1514 struct cudbg_buffer temp_buff = { 0 }; 1515 struct cudbg_clk_info *clk_info_buff; 1516 u64 tp_tick_us; 1517 int rc; 1518 1519 if (!padap->params.vpd.cclk) 1520 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1521 1522 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info), 1523 &temp_buff); 1524 if (rc) 1525 return rc; 1526 1527 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data; 1528 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */ 1529 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A); 1530 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res); 1531 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res); 1532 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000; 1533 1534 clk_info_buff->dack_timer = 1535 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 * 1536 t4_read_reg(padap, TP_DACK_TIMER_A); 1537 clk_info_buff->retransmit_min = 1538 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A); 1539 clk_info_buff->retransmit_max = 1540 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A); 1541 clk_info_buff->persist_timer_min = 1542 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A); 1543 clk_info_buff->persist_timer_max = 1544 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A); 1545 clk_info_buff->keepalive_idle_timer = 1546 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A); 1547 clk_info_buff->keepalive_interval = 1548 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A); 1549 clk_info_buff->initial_srtt = 1550 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A)); 1551 clk_info_buff->finwait2_timer = 1552 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A); 1553 1554 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1555 } 1556 1557 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init, 1558 struct cudbg_buffer *dbg_buff, 1559 struct cudbg_error *cudbg_err) 1560 { 1561 struct adapter *padap = pdbg_init->adap; 1562 struct cudbg_buffer temp_buff = { 0 }; 1563 struct ireg_buf *ch_pcie; 1564 int i, rc, n; 1565 u32 size; 1566 1567 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1568 size = sizeof(struct ireg_buf) * n * 2; 1569 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1570 if (rc) 1571 return rc; 1572 1573 ch_pcie = (struct ireg_buf *)temp_buff.data; 1574 /* PCIE_PDBG */ 1575 for (i = 0; i < n; i++) { 1576 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1577 u32 *buff = ch_pcie->outbuf; 1578 1579 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0]; 1580 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1]; 1581 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2]; 1582 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3]; 1583 t4_read_indirect(padap, 1584 pcie_pio->ireg_addr, 1585 pcie_pio->ireg_data, 1586 buff, 1587 pcie_pio->ireg_offset_range, 1588 pcie_pio->ireg_local_offset); 1589 ch_pcie++; 1590 } 1591 1592 /* PCIE_CDBG */ 1593 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1594 for (i = 0; i < n; i++) { 1595 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1596 u32 *buff = ch_pcie->outbuf; 1597 1598 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0]; 1599 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1]; 1600 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2]; 1601 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3]; 1602 t4_read_indirect(padap, 1603 pcie_pio->ireg_addr, 1604 pcie_pio->ireg_data, 1605 buff, 1606 pcie_pio->ireg_offset_range, 1607 pcie_pio->ireg_local_offset); 1608 ch_pcie++; 1609 } 1610 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1611 } 1612 1613 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init, 1614 struct cudbg_buffer *dbg_buff, 1615 struct cudbg_error *cudbg_err) 1616 { 1617 struct adapter *padap = pdbg_init->adap; 1618 struct cudbg_buffer temp_buff = { 0 }; 1619 struct ireg_buf *ch_pm; 1620 int i, rc, n; 1621 u32 size; 1622 1623 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1624 size = sizeof(struct ireg_buf) * n * 2; 1625 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1626 if (rc) 1627 return rc; 1628 1629 ch_pm = (struct ireg_buf *)temp_buff.data; 1630 /* PM_RX */ 1631 for (i = 0; i < n; i++) { 1632 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1633 u32 *buff = ch_pm->outbuf; 1634 1635 pm_pio->ireg_addr = t5_pm_rx_array[i][0]; 1636 pm_pio->ireg_data = t5_pm_rx_array[i][1]; 1637 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2]; 1638 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3]; 1639 t4_read_indirect(padap, 1640 pm_pio->ireg_addr, 1641 pm_pio->ireg_data, 1642 buff, 1643 pm_pio->ireg_offset_range, 1644 pm_pio->ireg_local_offset); 1645 ch_pm++; 1646 } 1647 1648 /* PM_TX */ 1649 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1650 for (i = 0; i < n; i++) { 1651 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1652 u32 *buff = ch_pm->outbuf; 1653 1654 pm_pio->ireg_addr = t5_pm_tx_array[i][0]; 1655 pm_pio->ireg_data = t5_pm_tx_array[i][1]; 1656 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2]; 1657 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3]; 1658 t4_read_indirect(padap, 1659 pm_pio->ireg_addr, 1660 pm_pio->ireg_data, 1661 buff, 1662 pm_pio->ireg_offset_range, 1663 pm_pio->ireg_local_offset); 1664 ch_pm++; 1665 } 1666 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1667 } 1668 1669 int cudbg_collect_tid(struct cudbg_init *pdbg_init, 1670 struct cudbg_buffer *dbg_buff, 1671 struct cudbg_error *cudbg_err) 1672 { 1673 struct adapter *padap = pdbg_init->adap; 1674 struct cudbg_tid_info_region_rev1 *tid1; 1675 struct cudbg_buffer temp_buff = { 0 }; 1676 struct cudbg_tid_info_region *tid; 1677 u32 para[2], val[2]; 1678 int rc; 1679 1680 rc = cudbg_get_buff(pdbg_init, dbg_buff, 1681 sizeof(struct cudbg_tid_info_region_rev1), 1682 &temp_buff); 1683 if (rc) 1684 return rc; 1685 1686 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data; 1687 tid = &tid1->tid; 1688 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE; 1689 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV; 1690 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) - 1691 sizeof(struct cudbg_ver_hdr); 1692 1693 /* If firmware is not attached/alive, use backdoor register 1694 * access to collect dump. 1695 */ 1696 if (!is_fw_attached(pdbg_init)) 1697 goto fill_tid; 1698 1699 #define FW_PARAM_PFVF_A(param) \ 1700 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 1701 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 1702 FW_PARAMS_PARAM_Y_V(0) | \ 1703 FW_PARAMS_PARAM_Z_V(0)) 1704 1705 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START); 1706 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END); 1707 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val); 1708 if (rc < 0) { 1709 cudbg_err->sys_err = rc; 1710 cudbg_put_buff(pdbg_init, &temp_buff); 1711 return rc; 1712 } 1713 tid->uotid_base = val[0]; 1714 tid->nuotids = val[1] - val[0] + 1; 1715 1716 if (is_t5(padap->params.chip)) { 1717 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4; 1718 } else if (is_t6(padap->params.chip)) { 1719 tid1->tid_start = 1720 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A); 1721 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A); 1722 1723 para[0] = FW_PARAM_PFVF_A(HPFILTER_START); 1724 para[1] = FW_PARAM_PFVF_A(HPFILTER_END); 1725 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, 1726 para, val); 1727 if (rc < 0) { 1728 cudbg_err->sys_err = rc; 1729 cudbg_put_buff(pdbg_init, &temp_buff); 1730 return rc; 1731 } 1732 tid->hpftid_base = val[0]; 1733 tid->nhpftids = val[1] - val[0] + 1; 1734 } 1735 1736 #undef FW_PARAM_PFVF_A 1737 1738 fill_tid: 1739 tid->ntids = padap->tids.ntids; 1740 tid->nstids = padap->tids.nstids; 1741 tid->stid_base = padap->tids.stid_base; 1742 tid->hash_base = padap->tids.hash_base; 1743 1744 tid->natids = padap->tids.natids; 1745 tid->nftids = padap->tids.nftids; 1746 tid->ftid_base = padap->tids.ftid_base; 1747 tid->aftid_base = padap->tids.aftid_base; 1748 tid->aftid_end = padap->tids.aftid_end; 1749 1750 tid->sftid_base = padap->tids.sftid_base; 1751 tid->nsftids = padap->tids.nsftids; 1752 1753 tid->flags = padap->flags; 1754 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A); 1755 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A); 1756 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A); 1757 1758 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1759 } 1760 1761 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init, 1762 struct cudbg_buffer *dbg_buff, 1763 struct cudbg_error *cudbg_err) 1764 { 1765 struct adapter *padap = pdbg_init->adap; 1766 struct cudbg_buffer temp_buff = { 0 }; 1767 u32 size, *value, j; 1768 int i, rc, n; 1769 1770 size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS; 1771 n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32)); 1772 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1773 if (rc) 1774 return rc; 1775 1776 value = (u32 *)temp_buff.data; 1777 for (i = 0; i < n; i++) { 1778 for (j = t5_pcie_config_array[i][0]; 1779 j <= t5_pcie_config_array[i][1]; j += 4) { 1780 t4_hw_pci_read_cfg4(padap, j, value); 1781 value++; 1782 } 1783 } 1784 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1785 } 1786 1787 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type) 1788 { 1789 int index, bit, bit_pos = 0; 1790 1791 switch (type) { 1792 case CTXT_EGRESS: 1793 bit_pos = 176; 1794 break; 1795 case CTXT_INGRESS: 1796 bit_pos = 141; 1797 break; 1798 case CTXT_FLM: 1799 bit_pos = 89; 1800 break; 1801 } 1802 index = bit_pos / 32; 1803 bit = bit_pos % 32; 1804 return buf[index] & (1U << bit); 1805 } 1806 1807 static int cudbg_get_ctxt_region_info(struct adapter *padap, 1808 struct cudbg_region_info *ctx_info, 1809 u8 *mem_type) 1810 { 1811 struct cudbg_mem_desc mem_desc; 1812 struct cudbg_meminfo meminfo; 1813 u32 i, j, value, found; 1814 u8 flq; 1815 int rc; 1816 1817 rc = cudbg_fill_meminfo(padap, &meminfo); 1818 if (rc) 1819 return rc; 1820 1821 /* Get EGRESS and INGRESS context region size */ 1822 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) { 1823 found = 0; 1824 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc)); 1825 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) { 1826 rc = cudbg_get_mem_region(padap, &meminfo, j, 1827 cudbg_region[i], 1828 &mem_desc); 1829 if (!rc) { 1830 found = 1; 1831 rc = cudbg_get_mem_relative(padap, &meminfo, j, 1832 &mem_desc.base, 1833 &mem_desc.limit); 1834 if (rc) { 1835 ctx_info[i].exist = false; 1836 break; 1837 } 1838 ctx_info[i].exist = true; 1839 ctx_info[i].start = mem_desc.base; 1840 ctx_info[i].end = mem_desc.limit; 1841 mem_type[i] = j; 1842 break; 1843 } 1844 } 1845 if (!found) 1846 ctx_info[i].exist = false; 1847 } 1848 1849 /* Get FLM and CNM max qid. */ 1850 value = t4_read_reg(padap, SGE_FLM_CFG_A); 1851 1852 /* Get number of data freelist queues */ 1853 flq = HDRSTARTFLQ_G(value); 1854 ctx_info[CTXT_FLM].exist = true; 1855 ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE; 1856 1857 /* The number of CONM contexts are same as number of freelist 1858 * queues. 1859 */ 1860 ctx_info[CTXT_CNM].exist = true; 1861 ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end; 1862 1863 return 0; 1864 } 1865 1866 int cudbg_dump_context_size(struct adapter *padap) 1867 { 1868 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} }; 1869 u8 mem_type[CTXT_INGRESS + 1] = { 0 }; 1870 u32 i, size = 0; 1871 int rc; 1872 1873 /* Get max valid qid for each type of queue */ 1874 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); 1875 if (rc) 1876 return rc; 1877 1878 for (i = 0; i < CTXT_CNM; i++) { 1879 if (!region_info[i].exist) { 1880 if (i == CTXT_EGRESS || i == CTXT_INGRESS) 1881 size += CUDBG_LOWMEM_MAX_CTXT_QIDS * 1882 SGE_CTXT_SIZE; 1883 continue; 1884 } 1885 1886 size += (region_info[i].end - region_info[i].start + 1) / 1887 SGE_CTXT_SIZE; 1888 } 1889 return size * sizeof(struct cudbg_ch_cntxt); 1890 } 1891 1892 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid, 1893 enum ctxt_type ctype, u32 *data) 1894 { 1895 struct adapter *padap = pdbg_init->adap; 1896 int rc = -1; 1897 1898 /* Under heavy traffic, the SGE Queue contexts registers will be 1899 * frequently accessed by firmware. 1900 * 1901 * To avoid conflicts with firmware, always ask firmware to fetch 1902 * the SGE Queue contexts via mailbox. On failure, fallback to 1903 * accessing hardware registers directly. 1904 */ 1905 if (is_fw_attached(pdbg_init)) 1906 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data); 1907 if (rc) 1908 t4_sge_ctxt_rd_bd(padap, cid, ctype, data); 1909 } 1910 1911 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid, 1912 u8 ctxt_type, 1913 struct cudbg_ch_cntxt **out_buff) 1914 { 1915 struct cudbg_ch_cntxt *buff = *out_buff; 1916 int rc; 1917 u32 j; 1918 1919 for (j = 0; j < max_qid; j++) { 1920 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data); 1921 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type); 1922 if (!rc) 1923 continue; 1924 1925 buff->cntxt_type = ctxt_type; 1926 buff->cntxt_id = j; 1927 buff++; 1928 if (ctxt_type == CTXT_FLM) { 1929 cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data); 1930 buff->cntxt_type = CTXT_CNM; 1931 buff->cntxt_id = j; 1932 buff++; 1933 } 1934 } 1935 1936 *out_buff = buff; 1937 } 1938 1939 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init, 1940 struct cudbg_buffer *dbg_buff, 1941 struct cudbg_error *cudbg_err) 1942 { 1943 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} }; 1944 struct adapter *padap = pdbg_init->adap; 1945 u32 j, size, max_ctx_size, max_ctx_qid; 1946 u8 mem_type[CTXT_INGRESS + 1] = { 0 }; 1947 struct cudbg_buffer temp_buff = { 0 }; 1948 struct cudbg_ch_cntxt *buff; 1949 u64 *dst_off, *src_off; 1950 u8 *ctx_buf; 1951 u8 i, k; 1952 int rc; 1953 1954 /* Get max valid qid for each type of queue */ 1955 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); 1956 if (rc) 1957 return rc; 1958 1959 rc = cudbg_dump_context_size(padap); 1960 if (rc <= 0) 1961 return CUDBG_STATUS_ENTITY_NOT_FOUND; 1962 1963 size = rc; 1964 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1965 if (rc) 1966 return rc; 1967 1968 /* Get buffer with enough space to read the biggest context 1969 * region in memory. 1970 */ 1971 max_ctx_size = max(region_info[CTXT_EGRESS].end - 1972 region_info[CTXT_EGRESS].start + 1, 1973 region_info[CTXT_INGRESS].end - 1974 region_info[CTXT_INGRESS].start + 1); 1975 1976 ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL); 1977 if (!ctx_buf) { 1978 cudbg_put_buff(pdbg_init, &temp_buff); 1979 return -ENOMEM; 1980 } 1981 1982 buff = (struct cudbg_ch_cntxt *)temp_buff.data; 1983 1984 /* Collect EGRESS and INGRESS context data. 1985 * In case of failures, fallback to collecting via FW or 1986 * backdoor access. 1987 */ 1988 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) { 1989 if (!region_info[i].exist) { 1990 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS; 1991 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i, 1992 &buff); 1993 continue; 1994 } 1995 1996 max_ctx_size = region_info[i].end - region_info[i].start + 1; 1997 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE; 1998 1999 /* If firmware is not attached/alive, use backdoor register 2000 * access to collect dump. 2001 */ 2002 if (is_fw_attached(pdbg_init)) { 2003 t4_sge_ctxt_flush(padap, padap->mbox, i); 2004 2005 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i], 2006 region_info[i].start, max_ctx_size, 2007 (__be32 *)ctx_buf, 1); 2008 } 2009 2010 if (rc || !is_fw_attached(pdbg_init)) { 2011 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS; 2012 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i, 2013 &buff); 2014 continue; 2015 } 2016 2017 for (j = 0; j < max_ctx_qid; j++) { 2018 src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE); 2019 dst_off = (u64 *)buff->data; 2020 2021 /* The data is stored in 64-bit cpu order. Convert it 2022 * to big endian before parsing. 2023 */ 2024 for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++) 2025 dst_off[k] = cpu_to_be64(src_off[k]); 2026 2027 rc = cudbg_sge_ctxt_check_valid(buff->data, i); 2028 if (!rc) 2029 continue; 2030 2031 buff->cntxt_type = i; 2032 buff->cntxt_id = j; 2033 buff++; 2034 } 2035 } 2036 2037 kvfree(ctx_buf); 2038 2039 /* Collect FREELIST and CONGESTION MANAGER contexts */ 2040 max_ctx_size = region_info[CTXT_FLM].end - 2041 region_info[CTXT_FLM].start + 1; 2042 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE; 2043 /* Since FLM and CONM are 1-to-1 mapped, the below function 2044 * will fetch both FLM and CONM contexts. 2045 */ 2046 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff); 2047 2048 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2049 } 2050 2051 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 2052 { 2053 *mask = x | y; 2054 y = (__force u64)cpu_to_be64(y); 2055 memcpy(addr, (char *)&y + 2, ETH_ALEN); 2056 } 2057 2058 static void cudbg_mps_rpl_backdoor(struct adapter *padap, 2059 struct fw_ldst_mps_rplc *mps_rplc) 2060 { 2061 if (is_t5(padap->params.chip)) { 2062 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 2063 MPS_VF_RPLCT_MAP3_A)); 2064 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 2065 MPS_VF_RPLCT_MAP2_A)); 2066 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 2067 MPS_VF_RPLCT_MAP1_A)); 2068 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 2069 MPS_VF_RPLCT_MAP0_A)); 2070 } else { 2071 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 2072 MPS_VF_RPLCT_MAP7_A)); 2073 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 2074 MPS_VF_RPLCT_MAP6_A)); 2075 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 2076 MPS_VF_RPLCT_MAP5_A)); 2077 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 2078 MPS_VF_RPLCT_MAP4_A)); 2079 } 2080 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A)); 2081 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A)); 2082 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A)); 2083 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A)); 2084 } 2085 2086 static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init, 2087 struct cudbg_mps_tcam *tcam, u32 idx) 2088 { 2089 struct adapter *padap = pdbg_init->adap; 2090 u64 tcamy, tcamx, val; 2091 u32 ctl, data2; 2092 int rc = 0; 2093 2094 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) { 2095 /* CtlReqID - 1: use Host Driver Requester ID 2096 * CtlCmdType - 0: Read, 1: Write 2097 * CtlTcamSel - 0: TCAM0, 1: TCAM1 2098 * CtlXYBitSel- 0: Y bit, 1: X bit 2099 */ 2100 2101 /* Read tcamy */ 2102 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 2103 if (idx < 256) 2104 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 2105 else 2106 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1); 2107 2108 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 2109 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 2110 tcamy = DMACH_G(val) << 32; 2111 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 2112 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 2113 tcam->lookup_type = DATALKPTYPE_G(data2); 2114 2115 /* 0 - Outer header, 1 - Inner header 2116 * [71:48] bit locations are overloaded for 2117 * outer vs. inner lookup types. 2118 */ 2119 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 2120 /* Inner header VNI */ 2121 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 2122 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val); 2123 tcam->dip_hit = data2 & DATADIPHIT_F; 2124 } else { 2125 tcam->vlan_vld = data2 & DATAVIDH2_F; 2126 tcam->ivlan = VIDL_G(val); 2127 } 2128 2129 tcam->port_num = DATAPORTNUM_G(data2); 2130 2131 /* Read tcamx. Change the control param */ 2132 ctl |= CTLXYBITSEL_V(1); 2133 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 2134 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 2135 tcamx = DMACH_G(val) << 32; 2136 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 2137 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 2138 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 2139 /* Inner header VNI mask */ 2140 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 2141 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val); 2142 } 2143 } else { 2144 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx)); 2145 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx)); 2146 } 2147 2148 /* If no entry, return */ 2149 if (tcamx & tcamy) 2150 return rc; 2151 2152 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx)); 2153 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx)); 2154 2155 if (is_t5(padap->params.chip)) 2156 tcam->repli = (tcam->cls_lo & REPLICATE_F); 2157 else if (is_t6(padap->params.chip)) 2158 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F); 2159 2160 if (tcam->repli) { 2161 struct fw_ldst_cmd ldst_cmd; 2162 struct fw_ldst_mps_rplc mps_rplc; 2163 2164 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 2165 ldst_cmd.op_to_addrspace = 2166 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 2167 FW_CMD_REQUEST_F | FW_CMD_READ_F | 2168 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS)); 2169 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 2170 ldst_cmd.u.mps.rplc.fid_idx = 2171 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 2172 FW_LDST_CMD_IDX_V(idx)); 2173 2174 /* If firmware is not attached/alive, use backdoor register 2175 * access to collect dump. 2176 */ 2177 if (is_fw_attached(pdbg_init)) 2178 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd, 2179 sizeof(ldst_cmd), &ldst_cmd); 2180 2181 if (rc || !is_fw_attached(pdbg_init)) { 2182 cudbg_mps_rpl_backdoor(padap, &mps_rplc); 2183 /* Ignore error since we collected directly from 2184 * reading registers. 2185 */ 2186 rc = 0; 2187 } else { 2188 mps_rplc = ldst_cmd.u.mps.rplc; 2189 } 2190 2191 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0); 2192 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32); 2193 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64); 2194 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96); 2195 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) { 2196 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128); 2197 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160); 2198 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192); 2199 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224); 2200 } 2201 } 2202 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask); 2203 tcam->idx = idx; 2204 tcam->rplc_size = padap->params.arch.mps_rplc_size; 2205 return rc; 2206 } 2207 2208 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init, 2209 struct cudbg_buffer *dbg_buff, 2210 struct cudbg_error *cudbg_err) 2211 { 2212 struct adapter *padap = pdbg_init->adap; 2213 struct cudbg_buffer temp_buff = { 0 }; 2214 u32 size = 0, i, n, total_size = 0; 2215 struct cudbg_mps_tcam *tcam; 2216 int rc; 2217 2218 n = padap->params.arch.mps_tcam_size; 2219 size = sizeof(struct cudbg_mps_tcam) * n; 2220 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2221 if (rc) 2222 return rc; 2223 2224 tcam = (struct cudbg_mps_tcam *)temp_buff.data; 2225 for (i = 0; i < n; i++) { 2226 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i); 2227 if (rc) { 2228 cudbg_err->sys_err = rc; 2229 cudbg_put_buff(pdbg_init, &temp_buff); 2230 return rc; 2231 } 2232 total_size += sizeof(struct cudbg_mps_tcam); 2233 tcam++; 2234 } 2235 2236 if (!total_size) { 2237 rc = CUDBG_SYSTEM_ERROR; 2238 cudbg_err->sys_err = rc; 2239 cudbg_put_buff(pdbg_init, &temp_buff); 2240 return rc; 2241 } 2242 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2243 } 2244 2245 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init, 2246 struct cudbg_buffer *dbg_buff, 2247 struct cudbg_error *cudbg_err) 2248 { 2249 struct adapter *padap = pdbg_init->adap; 2250 struct cudbg_buffer temp_buff = { 0 }; 2251 char vpd_str[CUDBG_VPD_VER_LEN + 1]; 2252 u32 scfg_vers, vpd_vers, fw_vers; 2253 struct cudbg_vpd_data *vpd_data; 2254 struct vpd_params vpd = { 0 }; 2255 int rc, ret; 2256 2257 rc = t4_get_raw_vpd_params(padap, &vpd); 2258 if (rc) 2259 return rc; 2260 2261 rc = t4_get_fw_version(padap, &fw_vers); 2262 if (rc) 2263 return rc; 2264 2265 /* Serial Configuration Version is located beyond the PF's vpd size. 2266 * Temporarily give access to entire EEPROM to get it. 2267 */ 2268 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE); 2269 if (rc < 0) 2270 return rc; 2271 2272 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN, 2273 &scfg_vers); 2274 2275 /* Restore back to original PF's vpd size */ 2276 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE); 2277 if (rc < 0) 2278 return rc; 2279 2280 if (ret) 2281 return ret; 2282 2283 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN, 2284 vpd_str); 2285 if (rc) 2286 return rc; 2287 2288 vpd_str[CUDBG_VPD_VER_LEN] = '\0'; 2289 rc = kstrtouint(vpd_str, 0, &vpd_vers); 2290 if (rc) 2291 return rc; 2292 2293 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data), 2294 &temp_buff); 2295 if (rc) 2296 return rc; 2297 2298 vpd_data = (struct cudbg_vpd_data *)temp_buff.data; 2299 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1); 2300 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1); 2301 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1); 2302 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1); 2303 vpd_data->scfg_vers = scfg_vers; 2304 vpd_data->vpd_vers = vpd_vers; 2305 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers); 2306 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers); 2307 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers); 2308 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers); 2309 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2310 } 2311 2312 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid, 2313 struct cudbg_tid_data *tid_data) 2314 { 2315 struct adapter *padap = pdbg_init->adap; 2316 int i, cmd_retry = 8; 2317 u32 val; 2318 2319 /* Fill REQ_DATA regs with 0's */ 2320 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++) 2321 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0); 2322 2323 /* Write DBIG command */ 2324 val = DBGICMD_V(4) | DBGITID_V(tid); 2325 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val); 2326 tid_data->dbig_cmd = val; 2327 2328 val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */ 2329 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val); 2330 tid_data->dbig_conf = val; 2331 2332 /* Poll the DBGICMDBUSY bit */ 2333 val = 1; 2334 while (val) { 2335 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A); 2336 val = val & DBGICMDBUSY_F; 2337 cmd_retry--; 2338 if (!cmd_retry) 2339 return CUDBG_SYSTEM_ERROR; 2340 } 2341 2342 /* Check RESP status */ 2343 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A); 2344 tid_data->dbig_rsp_stat = val; 2345 if (!(val & 1)) 2346 return CUDBG_SYSTEM_ERROR; 2347 2348 /* Read RESP data */ 2349 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++) 2350 tid_data->data[i] = t4_read_reg(padap, 2351 LE_DB_DBGI_RSP_DATA_A + 2352 (i << 2)); 2353 tid_data->tid = tid; 2354 return 0; 2355 } 2356 2357 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region) 2358 { 2359 int type = LE_ET_UNKNOWN; 2360 2361 if (tid < tcam_region.server_start) 2362 type = LE_ET_TCAM_CON; 2363 else if (tid < tcam_region.filter_start) 2364 type = LE_ET_TCAM_SERVER; 2365 else if (tid < tcam_region.clip_start) 2366 type = LE_ET_TCAM_FILTER; 2367 else if (tid < tcam_region.routing_start) 2368 type = LE_ET_TCAM_CLIP; 2369 else if (tid < tcam_region.tid_hash_base) 2370 type = LE_ET_TCAM_ROUTING; 2371 else if (tid < tcam_region.max_tid) 2372 type = LE_ET_HASH_CON; 2373 else 2374 type = LE_ET_INVALID_TID; 2375 2376 return type; 2377 } 2378 2379 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data, 2380 struct cudbg_tcam tcam_region) 2381 { 2382 int ipv6 = 0; 2383 int le_type; 2384 2385 le_type = cudbg_get_le_type(tid_data->tid, tcam_region); 2386 if (tid_data->tid & 1) 2387 return 0; 2388 2389 if (le_type == LE_ET_HASH_CON) { 2390 ipv6 = tid_data->data[16] & 0x8000; 2391 } else if (le_type == LE_ET_TCAM_CON) { 2392 ipv6 = tid_data->data[16] & 0x8000; 2393 if (ipv6) 2394 ipv6 = tid_data->data[9] == 0x00C00000; 2395 } else { 2396 ipv6 = 0; 2397 } 2398 return ipv6; 2399 } 2400 2401 void cudbg_fill_le_tcam_info(struct adapter *padap, 2402 struct cudbg_tcam *tcam_region) 2403 { 2404 u32 value; 2405 2406 /* Get the LE regions */ 2407 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */ 2408 tcam_region->tid_hash_base = value; 2409 2410 /* Get routing table index */ 2411 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A); 2412 tcam_region->routing_start = value; 2413 2414 /* Get clip table index. For T6 there is separate CLIP TCAM */ 2415 if (is_t6(padap->params.chip)) 2416 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A); 2417 else 2418 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A); 2419 tcam_region->clip_start = value; 2420 2421 /* Get filter table index */ 2422 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A); 2423 tcam_region->filter_start = value; 2424 2425 /* Get server table index */ 2426 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A); 2427 tcam_region->server_start = value; 2428 2429 /* Check whether hash is enabled and calculate the max tids */ 2430 value = t4_read_reg(padap, LE_DB_CONFIG_A); 2431 if ((value >> HASHEN_S) & 1) { 2432 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A); 2433 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { 2434 tcam_region->max_tid = (value & 0xFFFFF) + 2435 tcam_region->tid_hash_base; 2436 } else { 2437 value = HASHTIDSIZE_G(value); 2438 value = 1 << value; 2439 tcam_region->max_tid = value + 2440 tcam_region->tid_hash_base; 2441 } 2442 } else { /* hash not enabled */ 2443 if (is_t6(padap->params.chip)) 2444 tcam_region->max_tid = (value & ASLIPCOMPEN_F) ? 2445 CUDBG_MAX_TID_COMP_EN : 2446 CUDBG_MAX_TID_COMP_DIS; 2447 else 2448 tcam_region->max_tid = CUDBG_MAX_TCAM_TID; 2449 } 2450 2451 if (is_t6(padap->params.chip)) 2452 tcam_region->max_tid += CUDBG_T6_CLIP; 2453 } 2454 2455 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init, 2456 struct cudbg_buffer *dbg_buff, 2457 struct cudbg_error *cudbg_err) 2458 { 2459 struct adapter *padap = pdbg_init->adap; 2460 struct cudbg_buffer temp_buff = { 0 }; 2461 struct cudbg_tcam tcam_region = { 0 }; 2462 struct cudbg_tid_data *tid_data; 2463 u32 bytes = 0; 2464 int rc, size; 2465 u32 i; 2466 2467 cudbg_fill_le_tcam_info(padap, &tcam_region); 2468 2469 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid; 2470 size += sizeof(struct cudbg_tcam); 2471 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2472 if (rc) 2473 return rc; 2474 2475 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam)); 2476 bytes = sizeof(struct cudbg_tcam); 2477 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes); 2478 /* read all tid */ 2479 for (i = 0; i < tcam_region.max_tid; ) { 2480 rc = cudbg_read_tid(pdbg_init, i, tid_data); 2481 if (rc) { 2482 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA; 2483 /* Update tcam header and exit */ 2484 tcam_region.max_tid = i; 2485 memcpy(temp_buff.data, &tcam_region, 2486 sizeof(struct cudbg_tcam)); 2487 goto out; 2488 } 2489 2490 if (cudbg_is_ipv6_entry(tid_data, tcam_region)) { 2491 /* T6 CLIP TCAM: ipv6 takes 4 entries */ 2492 if (is_t6(padap->params.chip) && 2493 i >= tcam_region.clip_start && 2494 i < tcam_region.clip_start + CUDBG_T6_CLIP) 2495 i += 4; 2496 else /* Main TCAM: ipv6 takes two tids */ 2497 i += 2; 2498 } else { 2499 i++; 2500 } 2501 2502 tid_data++; 2503 bytes += sizeof(struct cudbg_tid_data); 2504 } 2505 2506 out: 2507 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2508 } 2509 2510 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init, 2511 struct cudbg_buffer *dbg_buff, 2512 struct cudbg_error *cudbg_err) 2513 { 2514 struct adapter *padap = pdbg_init->adap; 2515 struct cudbg_buffer temp_buff = { 0 }; 2516 u32 size; 2517 int rc; 2518 2519 size = sizeof(u16) * NMTUS * NCCTRL_WIN; 2520 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2521 if (rc) 2522 return rc; 2523 2524 t4_read_cong_tbl(padap, (void *)temp_buff.data); 2525 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2526 } 2527 2528 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init, 2529 struct cudbg_buffer *dbg_buff, 2530 struct cudbg_error *cudbg_err) 2531 { 2532 struct adapter *padap = pdbg_init->adap; 2533 struct cudbg_buffer temp_buff = { 0 }; 2534 struct ireg_buf *ma_indr; 2535 int i, rc, n; 2536 u32 size, j; 2537 2538 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2539 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2540 2541 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2542 size = sizeof(struct ireg_buf) * n * 2; 2543 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2544 if (rc) 2545 return rc; 2546 2547 ma_indr = (struct ireg_buf *)temp_buff.data; 2548 for (i = 0; i < n; i++) { 2549 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2550 u32 *buff = ma_indr->outbuf; 2551 2552 ma_fli->ireg_addr = t6_ma_ireg_array[i][0]; 2553 ma_fli->ireg_data = t6_ma_ireg_array[i][1]; 2554 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2]; 2555 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3]; 2556 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data, 2557 buff, ma_fli->ireg_offset_range, 2558 ma_fli->ireg_local_offset); 2559 ma_indr++; 2560 } 2561 2562 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32)); 2563 for (i = 0; i < n; i++) { 2564 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2565 u32 *buff = ma_indr->outbuf; 2566 2567 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0]; 2568 ma_fli->ireg_data = t6_ma_ireg_array2[i][1]; 2569 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2]; 2570 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) { 2571 t4_read_indirect(padap, ma_fli->ireg_addr, 2572 ma_fli->ireg_data, buff, 1, 2573 ma_fli->ireg_local_offset); 2574 buff++; 2575 ma_fli->ireg_local_offset += 0x20; 2576 } 2577 ma_indr++; 2578 } 2579 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2580 } 2581 2582 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init, 2583 struct cudbg_buffer *dbg_buff, 2584 struct cudbg_error *cudbg_err) 2585 { 2586 struct adapter *padap = pdbg_init->adap; 2587 struct cudbg_buffer temp_buff = { 0 }; 2588 struct cudbg_ulptx_la *ulptx_la_buff; 2589 u32 i, j; 2590 int rc; 2591 2592 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulptx_la), 2593 &temp_buff); 2594 if (rc) 2595 return rc; 2596 2597 ulptx_la_buff = (struct cudbg_ulptx_la *)temp_buff.data; 2598 for (i = 0; i < CUDBG_NUM_ULPTX; i++) { 2599 ulptx_la_buff->rdptr[i] = t4_read_reg(padap, 2600 ULP_TX_LA_RDPTR_0_A + 2601 0x10 * i); 2602 ulptx_la_buff->wrptr[i] = t4_read_reg(padap, 2603 ULP_TX_LA_WRPTR_0_A + 2604 0x10 * i); 2605 ulptx_la_buff->rddata[i] = t4_read_reg(padap, 2606 ULP_TX_LA_RDDATA_0_A + 2607 0x10 * i); 2608 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++) 2609 ulptx_la_buff->rd_data[i][j] = 2610 t4_read_reg(padap, 2611 ULP_TX_LA_RDDATA_0_A + 0x10 * i); 2612 } 2613 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2614 } 2615 2616 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init, 2617 struct cudbg_buffer *dbg_buff, 2618 struct cudbg_error *cudbg_err) 2619 { 2620 struct adapter *padap = pdbg_init->adap; 2621 struct cudbg_buffer temp_buff = { 0 }; 2622 u32 local_offset, local_range; 2623 struct ireg_buf *up_cim; 2624 u32 size, j, iter; 2625 u32 instance = 0; 2626 int i, rc, n; 2627 2628 if (is_t5(padap->params.chip)) 2629 n = sizeof(t5_up_cim_reg_array) / 2630 ((IREG_NUM_ELEM + 1) * sizeof(u32)); 2631 else if (is_t6(padap->params.chip)) 2632 n = sizeof(t6_up_cim_reg_array) / 2633 ((IREG_NUM_ELEM + 1) * sizeof(u32)); 2634 else 2635 return CUDBG_STATUS_NOT_IMPLEMENTED; 2636 2637 size = sizeof(struct ireg_buf) * n; 2638 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2639 if (rc) 2640 return rc; 2641 2642 up_cim = (struct ireg_buf *)temp_buff.data; 2643 for (i = 0; i < n; i++) { 2644 struct ireg_field *up_cim_reg = &up_cim->tp_pio; 2645 u32 *buff = up_cim->outbuf; 2646 2647 if (is_t5(padap->params.chip)) { 2648 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0]; 2649 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1]; 2650 up_cim_reg->ireg_local_offset = 2651 t5_up_cim_reg_array[i][2]; 2652 up_cim_reg->ireg_offset_range = 2653 t5_up_cim_reg_array[i][3]; 2654 instance = t5_up_cim_reg_array[i][4]; 2655 } else if (is_t6(padap->params.chip)) { 2656 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0]; 2657 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1]; 2658 up_cim_reg->ireg_local_offset = 2659 t6_up_cim_reg_array[i][2]; 2660 up_cim_reg->ireg_offset_range = 2661 t6_up_cim_reg_array[i][3]; 2662 instance = t6_up_cim_reg_array[i][4]; 2663 } 2664 2665 switch (instance) { 2666 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES: 2667 iter = up_cim_reg->ireg_offset_range; 2668 local_offset = 0x120; 2669 local_range = 1; 2670 break; 2671 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES: 2672 iter = up_cim_reg->ireg_offset_range; 2673 local_offset = 0x10; 2674 local_range = 1; 2675 break; 2676 default: 2677 iter = 1; 2678 local_offset = 0; 2679 local_range = up_cim_reg->ireg_offset_range; 2680 break; 2681 } 2682 2683 for (j = 0; j < iter; j++, buff++) { 2684 rc = t4_cim_read(padap, 2685 up_cim_reg->ireg_local_offset + 2686 (j * local_offset), local_range, buff); 2687 if (rc) { 2688 cudbg_put_buff(pdbg_init, &temp_buff); 2689 return rc; 2690 } 2691 } 2692 up_cim++; 2693 } 2694 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2695 } 2696 2697 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init, 2698 struct cudbg_buffer *dbg_buff, 2699 struct cudbg_error *cudbg_err) 2700 { 2701 struct adapter *padap = pdbg_init->adap; 2702 struct cudbg_buffer temp_buff = { 0 }; 2703 struct cudbg_pbt_tables *pbt; 2704 int i, rc; 2705 u32 addr; 2706 2707 rc = cudbg_get_buff(pdbg_init, dbg_buff, 2708 sizeof(struct cudbg_pbt_tables), 2709 &temp_buff); 2710 if (rc) 2711 return rc; 2712 2713 pbt = (struct cudbg_pbt_tables *)temp_buff.data; 2714 /* PBT dynamic entries */ 2715 addr = CUDBG_CHAC_PBT_ADDR; 2716 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) { 2717 rc = t4_cim_read(padap, addr + (i * 4), 1, 2718 &pbt->pbt_dynamic[i]); 2719 if (rc) { 2720 cudbg_err->sys_err = rc; 2721 cudbg_put_buff(pdbg_init, &temp_buff); 2722 return rc; 2723 } 2724 } 2725 2726 /* PBT static entries */ 2727 /* static entries start when bit 6 is set */ 2728 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6); 2729 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) { 2730 rc = t4_cim_read(padap, addr + (i * 4), 1, 2731 &pbt->pbt_static[i]); 2732 if (rc) { 2733 cudbg_err->sys_err = rc; 2734 cudbg_put_buff(pdbg_init, &temp_buff); 2735 return rc; 2736 } 2737 } 2738 2739 /* LRF entries */ 2740 addr = CUDBG_CHAC_PBT_LRF; 2741 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) { 2742 rc = t4_cim_read(padap, addr + (i * 4), 1, 2743 &pbt->lrf_table[i]); 2744 if (rc) { 2745 cudbg_err->sys_err = rc; 2746 cudbg_put_buff(pdbg_init, &temp_buff); 2747 return rc; 2748 } 2749 } 2750 2751 /* PBT data entries */ 2752 addr = CUDBG_CHAC_PBT_DATA; 2753 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) { 2754 rc = t4_cim_read(padap, addr + (i * 4), 1, 2755 &pbt->pbt_data[i]); 2756 if (rc) { 2757 cudbg_err->sys_err = rc; 2758 cudbg_put_buff(pdbg_init, &temp_buff); 2759 return rc; 2760 } 2761 } 2762 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2763 } 2764 2765 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init, 2766 struct cudbg_buffer *dbg_buff, 2767 struct cudbg_error *cudbg_err) 2768 { 2769 struct adapter *padap = pdbg_init->adap; 2770 struct cudbg_mbox_log *mboxlog = NULL; 2771 struct cudbg_buffer temp_buff = { 0 }; 2772 struct mbox_cmd_log *log = NULL; 2773 struct mbox_cmd *entry; 2774 unsigned int entry_idx; 2775 u16 mbox_cmds; 2776 int i, k, rc; 2777 u64 flit; 2778 u32 size; 2779 2780 log = padap->mbox_log; 2781 mbox_cmds = padap->mbox_log->size; 2782 size = sizeof(struct cudbg_mbox_log) * mbox_cmds; 2783 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2784 if (rc) 2785 return rc; 2786 2787 mboxlog = (struct cudbg_mbox_log *)temp_buff.data; 2788 for (k = 0; k < mbox_cmds; k++) { 2789 entry_idx = log->cursor + k; 2790 if (entry_idx >= log->size) 2791 entry_idx -= log->size; 2792 2793 entry = mbox_cmd_log_entry(log, entry_idx); 2794 /* skip over unused entries */ 2795 if (entry->timestamp == 0) 2796 continue; 2797 2798 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd)); 2799 for (i = 0; i < MBOX_LEN / 8; i++) { 2800 flit = entry->cmd[i]; 2801 mboxlog->hi[i] = (u32)(flit >> 32); 2802 mboxlog->lo[i] = (u32)flit; 2803 } 2804 mboxlog++; 2805 } 2806 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2807 } 2808 2809 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init, 2810 struct cudbg_buffer *dbg_buff, 2811 struct cudbg_error *cudbg_err) 2812 { 2813 struct adapter *padap = pdbg_init->adap; 2814 struct cudbg_buffer temp_buff = { 0 }; 2815 struct ireg_buf *hma_indr; 2816 int i, rc, n; 2817 u32 size; 2818 2819 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2820 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2821 2822 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2823 size = sizeof(struct ireg_buf) * n; 2824 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2825 if (rc) 2826 return rc; 2827 2828 hma_indr = (struct ireg_buf *)temp_buff.data; 2829 for (i = 0; i < n; i++) { 2830 struct ireg_field *hma_fli = &hma_indr->tp_pio; 2831 u32 *buff = hma_indr->outbuf; 2832 2833 hma_fli->ireg_addr = t6_hma_ireg_array[i][0]; 2834 hma_fli->ireg_data = t6_hma_ireg_array[i][1]; 2835 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2]; 2836 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3]; 2837 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data, 2838 buff, hma_fli->ireg_offset_range, 2839 hma_fli->ireg_local_offset); 2840 hma_indr++; 2841 } 2842 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2843 } 2844