1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #include <linux/sort.h> 19 20 #include "t4_regs.h" 21 #include "cxgb4.h" 22 #include "cudbg_if.h" 23 #include "cudbg_lib_common.h" 24 #include "cudbg_entity.h" 25 #include "cudbg_lib.h" 26 #include "cudbg_zlib.h" 27 28 static int cudbg_do_compression(struct cudbg_init *pdbg_init, 29 struct cudbg_buffer *pin_buff, 30 struct cudbg_buffer *dbg_buff) 31 { 32 struct cudbg_buffer temp_in_buff = { 0 }; 33 int bytes_left, bytes_read, bytes; 34 u32 offset = dbg_buff->offset; 35 int rc; 36 37 temp_in_buff.offset = pin_buff->offset; 38 temp_in_buff.data = pin_buff->data; 39 temp_in_buff.size = pin_buff->size; 40 41 bytes_left = pin_buff->size; 42 bytes_read = 0; 43 while (bytes_left > 0) { 44 /* Do compression in smaller chunks */ 45 bytes = min_t(unsigned long, bytes_left, 46 (unsigned long)CUDBG_CHUNK_SIZE); 47 temp_in_buff.data = (char *)pin_buff->data + bytes_read; 48 temp_in_buff.size = bytes; 49 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff); 50 if (rc) 51 return rc; 52 bytes_left -= bytes; 53 bytes_read += bytes; 54 } 55 56 pin_buff->size = dbg_buff->offset - offset; 57 return 0; 58 } 59 60 static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init, 61 struct cudbg_buffer *pin_buff, 62 struct cudbg_buffer *dbg_buff) 63 { 64 int rc = 0; 65 66 if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) { 67 cudbg_update_buff(pin_buff, dbg_buff); 68 } else { 69 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff); 70 if (rc) 71 goto out; 72 } 73 74 out: 75 cudbg_put_buff(pdbg_init, pin_buff); 76 return rc; 77 } 78 79 static int is_fw_attached(struct cudbg_init *pdbg_init) 80 { 81 struct adapter *padap = pdbg_init->adap; 82 83 if (!(padap->flags & FW_OK) || padap->use_bd) 84 return 0; 85 86 return 1; 87 } 88 89 /* This function will add additional padding bytes into debug_buffer to make it 90 * 4 byte aligned. 91 */ 92 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff, 93 struct cudbg_entity_hdr *entity_hdr) 94 { 95 u8 zero_buf[4] = {0}; 96 u8 padding, remain; 97 98 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4; 99 padding = 4 - remain; 100 if (remain) { 101 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf, 102 padding); 103 dbg_buff->offset += padding; 104 entity_hdr->num_pad = padding; 105 } 106 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset; 107 } 108 109 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i) 110 { 111 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf; 112 113 return (struct cudbg_entity_hdr *) 114 ((char *)outbuf + cudbg_hdr->hdr_len + 115 (sizeof(struct cudbg_entity_hdr) * (i - 1))); 116 } 117 118 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len, 119 void *dest) 120 { 121 int vaddr, rc; 122 123 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE); 124 if (vaddr < 0) 125 return vaddr; 126 127 rc = pci_read_vpd(padap->pdev, vaddr, len, dest); 128 if (rc < 0) 129 return rc; 130 131 return 0; 132 } 133 134 static int cudbg_mem_desc_cmp(const void *a, const void *b) 135 { 136 return ((const struct cudbg_mem_desc *)a)->base - 137 ((const struct cudbg_mem_desc *)b)->base; 138 } 139 140 int cudbg_fill_meminfo(struct adapter *padap, 141 struct cudbg_meminfo *meminfo_buff) 142 { 143 struct cudbg_mem_desc *md; 144 u32 lo, hi, used, alloc; 145 int n, i; 146 147 memset(meminfo_buff->avail, 0, 148 ARRAY_SIZE(meminfo_buff->avail) * 149 sizeof(struct cudbg_mem_desc)); 150 memset(meminfo_buff->mem, 0, 151 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc)); 152 md = meminfo_buff->mem; 153 154 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) { 155 meminfo_buff->mem[i].limit = 0; 156 meminfo_buff->mem[i].idx = i; 157 } 158 159 /* Find and sort the populated memory ranges */ 160 i = 0; 161 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A); 162 if (lo & EDRAM0_ENABLE_F) { 163 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A); 164 meminfo_buff->avail[i].base = 165 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi)); 166 meminfo_buff->avail[i].limit = 167 meminfo_buff->avail[i].base + 168 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi)); 169 meminfo_buff->avail[i].idx = 0; 170 i++; 171 } 172 173 if (lo & EDRAM1_ENABLE_F) { 174 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A); 175 meminfo_buff->avail[i].base = 176 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi)); 177 meminfo_buff->avail[i].limit = 178 meminfo_buff->avail[i].base + 179 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi)); 180 meminfo_buff->avail[i].idx = 1; 181 i++; 182 } 183 184 if (is_t5(padap->params.chip)) { 185 if (lo & EXT_MEM0_ENABLE_F) { 186 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A); 187 meminfo_buff->avail[i].base = 188 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 189 meminfo_buff->avail[i].limit = 190 meminfo_buff->avail[i].base + 191 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 192 meminfo_buff->avail[i].idx = 3; 193 i++; 194 } 195 196 if (lo & EXT_MEM1_ENABLE_F) { 197 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 198 meminfo_buff->avail[i].base = 199 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 200 meminfo_buff->avail[i].limit = 201 meminfo_buff->avail[i].base + 202 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 203 meminfo_buff->avail[i].idx = 4; 204 i++; 205 } 206 } else { 207 if (lo & EXT_MEM_ENABLE_F) { 208 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A); 209 meminfo_buff->avail[i].base = 210 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi)); 211 meminfo_buff->avail[i].limit = 212 meminfo_buff->avail[i].base + 213 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi)); 214 meminfo_buff->avail[i].idx = 2; 215 i++; 216 } 217 218 if (lo & HMA_MUX_F) { 219 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A); 220 meminfo_buff->avail[i].base = 221 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi)); 222 meminfo_buff->avail[i].limit = 223 meminfo_buff->avail[i].base + 224 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi)); 225 meminfo_buff->avail[i].idx = 5; 226 i++; 227 } 228 } 229 230 if (!i) /* no memory available */ 231 return CUDBG_STATUS_ENTITY_NOT_FOUND; 232 233 meminfo_buff->avail_c = i; 234 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc), 235 cudbg_mem_desc_cmp, NULL); 236 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); 237 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); 238 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); 239 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A); 240 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A); 241 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A); 242 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A); 243 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A); 244 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A); 245 246 /* the next few have explicit upper bounds */ 247 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A); 248 md->limit = md->base - 1 + 249 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) * 250 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A)); 251 md++; 252 253 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A); 254 md->limit = md->base - 1 + 255 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) * 256 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A)); 257 md++; 258 259 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) { 260 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) { 261 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4; 262 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 263 } else { 264 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); 265 md->base = t4_read_reg(padap, 266 LE_DB_HASH_TBL_BASE_ADDR_A); 267 } 268 md->limit = 0; 269 } else { 270 md->base = 0; 271 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 272 } 273 md++; 274 275 #define ulp_region(reg) do { \ 276 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ 277 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\ 278 } while (0) 279 280 ulp_region(RX_ISCSI); 281 ulp_region(RX_TDDP); 282 ulp_region(TX_TPT); 283 ulp_region(RX_STAG); 284 ulp_region(RX_RQ); 285 ulp_region(RX_RQUDP); 286 ulp_region(RX_PBL); 287 ulp_region(TX_PBL); 288 #undef ulp_region 289 md->base = 0; 290 md->idx = ARRAY_SIZE(cudbg_region); 291 if (!is_t4(padap->params.chip)) { 292 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A); 293 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A); 294 u32 size = 0; 295 296 if (is_t5(padap->params.chip)) { 297 if (sge_ctrl & VFIFO_ENABLE_F) 298 size = DBVFIFO_SIZE_G(fifo_size); 299 } else { 300 size = T6_DBVFIFO_SIZE_G(fifo_size); 301 } 302 303 if (size) { 304 md->base = BASEADDR_G(t4_read_reg(padap, 305 SGE_DBVFIFO_BADDR_A)); 306 md->limit = md->base + (size << 2) - 1; 307 } 308 } 309 310 md++; 311 312 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A); 313 md->limit = 0; 314 md++; 315 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A); 316 md->limit = 0; 317 md++; 318 319 md->base = padap->vres.ocq.start; 320 if (padap->vres.ocq.size) 321 md->limit = md->base + padap->vres.ocq.size - 1; 322 else 323 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */ 324 md++; 325 326 /* add any address-space holes, there can be up to 3 */ 327 for (n = 0; n < i - 1; n++) 328 if (meminfo_buff->avail[n].limit < 329 meminfo_buff->avail[n + 1].base) 330 (md++)->base = meminfo_buff->avail[n].limit; 331 332 if (meminfo_buff->avail[n].limit) 333 (md++)->base = meminfo_buff->avail[n].limit; 334 335 n = md - meminfo_buff->mem; 336 meminfo_buff->mem_c = n; 337 338 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc), 339 cudbg_mem_desc_cmp, NULL); 340 341 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A); 342 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1; 343 meminfo_buff->up_ram_lo = lo; 344 meminfo_buff->up_ram_hi = hi; 345 346 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A); 347 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1; 348 meminfo_buff->up_extmem2_lo = lo; 349 meminfo_buff->up_extmem2_hi = hi; 350 351 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A); 352 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo); 353 meminfo_buff->rx_pages_data[1] = 354 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10; 355 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1; 356 357 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A); 358 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A); 359 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo); 360 meminfo_buff->tx_pages_data[1] = 361 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10); 362 meminfo_buff->tx_pages_data[2] = 363 hi >= (1 << 20) ? 'M' : 'K'; 364 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo); 365 366 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A); 367 368 for (i = 0; i < 4; i++) { 369 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 370 lo = t4_read_reg(padap, 371 MPS_RX_MAC_BG_PG_CNT0_A + i * 4); 372 else 373 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4); 374 if (is_t5(padap->params.chip)) { 375 used = T5_USED_G(lo); 376 alloc = T5_ALLOC_G(lo); 377 } else { 378 used = USED_G(lo); 379 alloc = ALLOC_G(lo); 380 } 381 meminfo_buff->port_used[i] = used; 382 meminfo_buff->port_alloc[i] = alloc; 383 } 384 385 for (i = 0; i < padap->params.arch.nchan; i++) { 386 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) 387 lo = t4_read_reg(padap, 388 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4); 389 else 390 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4); 391 if (is_t5(padap->params.chip)) { 392 used = T5_USED_G(lo); 393 alloc = T5_ALLOC_G(lo); 394 } else { 395 used = USED_G(lo); 396 alloc = ALLOC_G(lo); 397 } 398 meminfo_buff->loopback_used[i] = used; 399 meminfo_buff->loopback_alloc[i] = alloc; 400 } 401 402 return 0; 403 } 404 405 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init, 406 struct cudbg_buffer *dbg_buff, 407 struct cudbg_error *cudbg_err) 408 { 409 struct adapter *padap = pdbg_init->adap; 410 struct cudbg_buffer temp_buff = { 0 }; 411 u32 buf_size = 0; 412 int rc = 0; 413 414 if (is_t4(padap->params.chip)) 415 buf_size = T4_REGMAP_SIZE; 416 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip)) 417 buf_size = T5_REGMAP_SIZE; 418 419 rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff); 420 if (rc) 421 return rc; 422 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size); 423 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 424 } 425 426 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init, 427 struct cudbg_buffer *dbg_buff, 428 struct cudbg_error *cudbg_err) 429 { 430 struct adapter *padap = pdbg_init->adap; 431 struct cudbg_buffer temp_buff = { 0 }; 432 struct devlog_params *dparams; 433 int rc = 0; 434 435 rc = t4_init_devlog_params(padap); 436 if (rc < 0) { 437 cudbg_err->sys_err = rc; 438 return rc; 439 } 440 441 dparams = &padap->params.devlog; 442 rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff); 443 if (rc) 444 return rc; 445 446 /* Collect FW devlog */ 447 if (dparams->start != 0) { 448 spin_lock(&padap->win0_lock); 449 rc = t4_memory_rw(padap, padap->params.drv_memwin, 450 dparams->memtype, dparams->start, 451 dparams->size, 452 (__be32 *)(char *)temp_buff.data, 453 1); 454 spin_unlock(&padap->win0_lock); 455 if (rc) { 456 cudbg_err->sys_err = rc; 457 cudbg_put_buff(pdbg_init, &temp_buff); 458 return rc; 459 } 460 } 461 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 462 } 463 464 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init, 465 struct cudbg_buffer *dbg_buff, 466 struct cudbg_error *cudbg_err) 467 { 468 struct adapter *padap = pdbg_init->adap; 469 struct cudbg_buffer temp_buff = { 0 }; 470 int size, rc; 471 u32 cfg = 0; 472 473 if (is_t6(padap->params.chip)) { 474 size = padap->params.cim_la_size / 10 + 1; 475 size *= 11 * sizeof(u32); 476 } else { 477 size = padap->params.cim_la_size / 8; 478 size *= 8 * sizeof(u32); 479 } 480 481 size += sizeof(cfg); 482 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 483 if (rc) 484 return rc; 485 486 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 487 if (rc) { 488 cudbg_err->sys_err = rc; 489 cudbg_put_buff(pdbg_init, &temp_buff); 490 return rc; 491 } 492 493 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg)); 494 rc = t4_cim_read_la(padap, 495 (u32 *)((char *)temp_buff.data + sizeof(cfg)), 496 NULL); 497 if (rc < 0) { 498 cudbg_err->sys_err = rc; 499 cudbg_put_buff(pdbg_init, &temp_buff); 500 return rc; 501 } 502 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 503 } 504 505 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init, 506 struct cudbg_buffer *dbg_buff, 507 struct cudbg_error *cudbg_err) 508 { 509 struct adapter *padap = pdbg_init->adap; 510 struct cudbg_buffer temp_buff = { 0 }; 511 int size, rc; 512 513 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); 514 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 515 if (rc) 516 return rc; 517 518 t4_cim_read_ma_la(padap, 519 (u32 *)temp_buff.data, 520 (u32 *)((char *)temp_buff.data + 521 5 * CIM_MALA_SIZE)); 522 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 523 } 524 525 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init, 526 struct cudbg_buffer *dbg_buff, 527 struct cudbg_error *cudbg_err) 528 { 529 struct adapter *padap = pdbg_init->adap; 530 struct cudbg_buffer temp_buff = { 0 }; 531 struct cudbg_cim_qcfg *cim_qcfg_data; 532 int rc; 533 534 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg), 535 &temp_buff); 536 if (rc) 537 return rc; 538 539 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data; 540 cim_qcfg_data->chip = padap->params.chip; 541 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A, 542 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat); 543 if (rc) { 544 cudbg_err->sys_err = rc; 545 cudbg_put_buff(pdbg_init, &temp_buff); 546 return rc; 547 } 548 549 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A, 550 ARRAY_SIZE(cim_qcfg_data->obq_wr), 551 cim_qcfg_data->obq_wr); 552 if (rc) { 553 cudbg_err->sys_err = rc; 554 cudbg_put_buff(pdbg_init, &temp_buff); 555 return rc; 556 } 557 558 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size, 559 cim_qcfg_data->thres); 560 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 561 } 562 563 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init, 564 struct cudbg_buffer *dbg_buff, 565 struct cudbg_error *cudbg_err, int qid) 566 { 567 struct adapter *padap = pdbg_init->adap; 568 struct cudbg_buffer temp_buff = { 0 }; 569 int no_of_read_words, rc = 0; 570 u32 qsize; 571 572 /* collect CIM IBQ */ 573 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32); 574 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff); 575 if (rc) 576 return rc; 577 578 /* t4_read_cim_ibq will return no. of read words or error */ 579 no_of_read_words = t4_read_cim_ibq(padap, qid, 580 (u32 *)temp_buff.data, qsize); 581 /* no_of_read_words is less than or equal to 0 means error */ 582 if (no_of_read_words <= 0) { 583 if (!no_of_read_words) 584 rc = CUDBG_SYSTEM_ERROR; 585 else 586 rc = no_of_read_words; 587 cudbg_err->sys_err = rc; 588 cudbg_put_buff(pdbg_init, &temp_buff); 589 return rc; 590 } 591 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 592 } 593 594 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init, 595 struct cudbg_buffer *dbg_buff, 596 struct cudbg_error *cudbg_err) 597 { 598 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0); 599 } 600 601 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init, 602 struct cudbg_buffer *dbg_buff, 603 struct cudbg_error *cudbg_err) 604 { 605 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1); 606 } 607 608 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init, 609 struct cudbg_buffer *dbg_buff, 610 struct cudbg_error *cudbg_err) 611 { 612 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2); 613 } 614 615 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init, 616 struct cudbg_buffer *dbg_buff, 617 struct cudbg_error *cudbg_err) 618 { 619 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3); 620 } 621 622 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init, 623 struct cudbg_buffer *dbg_buff, 624 struct cudbg_error *cudbg_err) 625 { 626 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4); 627 } 628 629 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init, 630 struct cudbg_buffer *dbg_buff, 631 struct cudbg_error *cudbg_err) 632 { 633 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5); 634 } 635 636 u32 cudbg_cim_obq_size(struct adapter *padap, int qid) 637 { 638 u32 value; 639 640 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 641 QUENUMSELECT_V(qid)); 642 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A); 643 value = CIMQSIZE_G(value) * 64; /* size in number of words */ 644 return value * sizeof(u32); 645 } 646 647 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init, 648 struct cudbg_buffer *dbg_buff, 649 struct cudbg_error *cudbg_err, int qid) 650 { 651 struct adapter *padap = pdbg_init->adap; 652 struct cudbg_buffer temp_buff = { 0 }; 653 int no_of_read_words, rc = 0; 654 u32 qsize; 655 656 /* collect CIM OBQ */ 657 qsize = cudbg_cim_obq_size(padap, qid); 658 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff); 659 if (rc) 660 return rc; 661 662 /* t4_read_cim_obq will return no. of read words or error */ 663 no_of_read_words = t4_read_cim_obq(padap, qid, 664 (u32 *)temp_buff.data, qsize); 665 /* no_of_read_words is less than or equal to 0 means error */ 666 if (no_of_read_words <= 0) { 667 if (!no_of_read_words) 668 rc = CUDBG_SYSTEM_ERROR; 669 else 670 rc = no_of_read_words; 671 cudbg_err->sys_err = rc; 672 cudbg_put_buff(pdbg_init, &temp_buff); 673 return rc; 674 } 675 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 676 } 677 678 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init, 679 struct cudbg_buffer *dbg_buff, 680 struct cudbg_error *cudbg_err) 681 { 682 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0); 683 } 684 685 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init, 686 struct cudbg_buffer *dbg_buff, 687 struct cudbg_error *cudbg_err) 688 { 689 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1); 690 } 691 692 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init, 693 struct cudbg_buffer *dbg_buff, 694 struct cudbg_error *cudbg_err) 695 { 696 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2); 697 } 698 699 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init, 700 struct cudbg_buffer *dbg_buff, 701 struct cudbg_error *cudbg_err) 702 { 703 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3); 704 } 705 706 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init, 707 struct cudbg_buffer *dbg_buff, 708 struct cudbg_error *cudbg_err) 709 { 710 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4); 711 } 712 713 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init, 714 struct cudbg_buffer *dbg_buff, 715 struct cudbg_error *cudbg_err) 716 { 717 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5); 718 } 719 720 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init, 721 struct cudbg_buffer *dbg_buff, 722 struct cudbg_error *cudbg_err) 723 { 724 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6); 725 } 726 727 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init, 728 struct cudbg_buffer *dbg_buff, 729 struct cudbg_error *cudbg_err) 730 { 731 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7); 732 } 733 734 static int cudbg_meminfo_get_mem_index(struct adapter *padap, 735 struct cudbg_meminfo *mem_info, 736 u8 mem_type, u8 *idx) 737 { 738 u8 i, flag; 739 740 switch (mem_type) { 741 case MEM_EDC0: 742 flag = EDC0_FLAG; 743 break; 744 case MEM_EDC1: 745 flag = EDC1_FLAG; 746 break; 747 case MEM_MC0: 748 /* Some T5 cards have both MC0 and MC1. */ 749 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG; 750 break; 751 case MEM_MC1: 752 flag = MC1_FLAG; 753 break; 754 case MEM_HMA: 755 flag = HMA_FLAG; 756 break; 757 default: 758 return CUDBG_STATUS_ENTITY_NOT_FOUND; 759 } 760 761 for (i = 0; i < mem_info->avail_c; i++) { 762 if (mem_info->avail[i].idx == flag) { 763 *idx = i; 764 return 0; 765 } 766 } 767 768 return CUDBG_STATUS_ENTITY_NOT_FOUND; 769 } 770 771 /* Fetch the @region_name's start and end from @meminfo. */ 772 static int cudbg_get_mem_region(struct adapter *padap, 773 struct cudbg_meminfo *meminfo, 774 u8 mem_type, const char *region_name, 775 struct cudbg_mem_desc *mem_desc) 776 { 777 u8 mc, found = 0; 778 u32 i, idx = 0; 779 int rc; 780 781 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc); 782 if (rc) 783 return rc; 784 785 for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) { 786 if (!strcmp(cudbg_region[i], region_name)) { 787 found = 1; 788 idx = i; 789 break; 790 } 791 } 792 if (!found) 793 return -EINVAL; 794 795 found = 0; 796 for (i = 0; i < meminfo->mem_c; i++) { 797 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region)) 798 continue; /* Skip holes */ 799 800 if (!(meminfo->mem[i].limit)) 801 meminfo->mem[i].limit = 802 i < meminfo->mem_c - 1 ? 803 meminfo->mem[i + 1].base - 1 : ~0; 804 805 if (meminfo->mem[i].idx == idx) { 806 /* Check if the region exists in @mem_type memory */ 807 if (meminfo->mem[i].base < meminfo->avail[mc].base && 808 meminfo->mem[i].limit < meminfo->avail[mc].base) 809 return -EINVAL; 810 811 if (meminfo->mem[i].base > meminfo->avail[mc].limit) 812 return -EINVAL; 813 814 memcpy(mem_desc, &meminfo->mem[i], 815 sizeof(struct cudbg_mem_desc)); 816 found = 1; 817 break; 818 } 819 } 820 if (!found) 821 return -EINVAL; 822 823 return 0; 824 } 825 826 /* Fetch and update the start and end of the requested memory region w.r.t 0 827 * in the corresponding EDC/MC/HMA. 828 */ 829 static int cudbg_get_mem_relative(struct adapter *padap, 830 struct cudbg_meminfo *meminfo, 831 u8 mem_type, u32 *out_base, u32 *out_end) 832 { 833 u8 mc_idx; 834 int rc; 835 836 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx); 837 if (rc) 838 return rc; 839 840 if (*out_base < meminfo->avail[mc_idx].base) 841 *out_base = 0; 842 else 843 *out_base -= meminfo->avail[mc_idx].base; 844 845 if (*out_end > meminfo->avail[mc_idx].limit) 846 *out_end = meminfo->avail[mc_idx].limit; 847 else 848 *out_end -= meminfo->avail[mc_idx].base; 849 850 return 0; 851 } 852 853 /* Get TX and RX Payload region */ 854 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type, 855 const char *region_name, 856 struct cudbg_region_info *payload) 857 { 858 struct cudbg_mem_desc mem_desc = { 0 }; 859 struct cudbg_meminfo meminfo; 860 int rc; 861 862 rc = cudbg_fill_meminfo(padap, &meminfo); 863 if (rc) 864 return rc; 865 866 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name, 867 &mem_desc); 868 if (rc) { 869 payload->exist = false; 870 return 0; 871 } 872 873 payload->exist = true; 874 payload->start = mem_desc.base; 875 payload->end = mem_desc.limit; 876 877 return cudbg_get_mem_relative(padap, &meminfo, mem_type, 878 &payload->start, &payload->end); 879 } 880 881 #define CUDBG_YIELD_ITERATION 256 882 883 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init, 884 struct cudbg_buffer *dbg_buff, u8 mem_type, 885 unsigned long tot_len, 886 struct cudbg_error *cudbg_err) 887 { 888 static const char * const region_name[] = { "Tx payload:", 889 "Rx payload:" }; 890 unsigned long bytes, bytes_left, bytes_read = 0; 891 struct adapter *padap = pdbg_init->adap; 892 struct cudbg_buffer temp_buff = { 0 }; 893 struct cudbg_region_info payload[2]; 894 u32 yield_count = 0; 895 int rc = 0; 896 u8 i; 897 898 /* Get TX/RX Payload region range if they exist */ 899 memset(payload, 0, sizeof(payload)); 900 for (i = 0; i < ARRAY_SIZE(region_name); i++) { 901 rc = cudbg_get_payload_range(padap, mem_type, region_name[i], 902 &payload[i]); 903 if (rc) 904 return rc; 905 906 if (payload[i].exist) { 907 /* Align start and end to avoid wrap around */ 908 payload[i].start = roundup(payload[i].start, 909 CUDBG_CHUNK_SIZE); 910 payload[i].end = rounddown(payload[i].end, 911 CUDBG_CHUNK_SIZE); 912 } 913 } 914 915 bytes_left = tot_len; 916 while (bytes_left > 0) { 917 /* As MC size is huge and read through PIO access, this 918 * loop will hold cpu for a longer time. OS may think that 919 * the process is hanged and will generate CPU stall traces. 920 * So yield the cpu regularly. 921 */ 922 yield_count++; 923 if (!(yield_count % CUDBG_YIELD_ITERATION)) 924 schedule(); 925 926 bytes = min_t(unsigned long, bytes_left, 927 (unsigned long)CUDBG_CHUNK_SIZE); 928 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff); 929 if (rc) 930 return rc; 931 932 for (i = 0; i < ARRAY_SIZE(payload); i++) 933 if (payload[i].exist && 934 bytes_read >= payload[i].start && 935 bytes_read + bytes <= payload[i].end) 936 /* TX and RX Payload regions can't overlap */ 937 goto skip_read; 938 939 spin_lock(&padap->win0_lock); 940 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type, 941 bytes_read, bytes, 942 (__be32 *)temp_buff.data, 943 1); 944 spin_unlock(&padap->win0_lock); 945 if (rc) { 946 cudbg_err->sys_err = rc; 947 cudbg_put_buff(pdbg_init, &temp_buff); 948 return rc; 949 } 950 951 skip_read: 952 bytes_left -= bytes; 953 bytes_read += bytes; 954 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff, 955 dbg_buff); 956 if (rc) { 957 cudbg_put_buff(pdbg_init, &temp_buff); 958 return rc; 959 } 960 } 961 return rc; 962 } 963 964 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init, 965 struct cudbg_error *cudbg_err) 966 { 967 struct adapter *padap = pdbg_init->adap; 968 int rc; 969 970 if (is_fw_attached(pdbg_init)) { 971 /* Flush uP dcache before reading edcX/mcX */ 972 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH); 973 if (rc) 974 cudbg_err->sys_warn = rc; 975 } 976 } 977 978 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init, 979 struct cudbg_buffer *dbg_buff, 980 struct cudbg_error *cudbg_err, 981 u8 mem_type) 982 { 983 struct adapter *padap = pdbg_init->adap; 984 struct cudbg_meminfo mem_info; 985 unsigned long size; 986 u8 mc_idx; 987 int rc; 988 989 memset(&mem_info, 0, sizeof(struct cudbg_meminfo)); 990 rc = cudbg_fill_meminfo(padap, &mem_info); 991 if (rc) 992 return rc; 993 994 cudbg_t4_fwcache(pdbg_init, cudbg_err); 995 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx); 996 if (rc) 997 return rc; 998 999 size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base; 1000 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size, 1001 cudbg_err); 1002 } 1003 1004 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init, 1005 struct cudbg_buffer *dbg_buff, 1006 struct cudbg_error *cudbg_err) 1007 { 1008 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1009 MEM_EDC0); 1010 } 1011 1012 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init, 1013 struct cudbg_buffer *dbg_buff, 1014 struct cudbg_error *cudbg_err) 1015 { 1016 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1017 MEM_EDC1); 1018 } 1019 1020 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init, 1021 struct cudbg_buffer *dbg_buff, 1022 struct cudbg_error *cudbg_err) 1023 { 1024 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1025 MEM_MC0); 1026 } 1027 1028 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init, 1029 struct cudbg_buffer *dbg_buff, 1030 struct cudbg_error *cudbg_err) 1031 { 1032 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1033 MEM_MC1); 1034 } 1035 1036 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init, 1037 struct cudbg_buffer *dbg_buff, 1038 struct cudbg_error *cudbg_err) 1039 { 1040 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err, 1041 MEM_HMA); 1042 } 1043 1044 int cudbg_collect_rss(struct cudbg_init *pdbg_init, 1045 struct cudbg_buffer *dbg_buff, 1046 struct cudbg_error *cudbg_err) 1047 { 1048 struct adapter *padap = pdbg_init->adap; 1049 struct cudbg_buffer temp_buff = { 0 }; 1050 int rc, nentries; 1051 1052 nentries = t4_chip_rss_size(padap); 1053 rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16), 1054 &temp_buff); 1055 if (rc) 1056 return rc; 1057 1058 rc = t4_read_rss(padap, (u16 *)temp_buff.data); 1059 if (rc) { 1060 cudbg_err->sys_err = rc; 1061 cudbg_put_buff(pdbg_init, &temp_buff); 1062 return rc; 1063 } 1064 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1065 } 1066 1067 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init, 1068 struct cudbg_buffer *dbg_buff, 1069 struct cudbg_error *cudbg_err) 1070 { 1071 struct adapter *padap = pdbg_init->adap; 1072 struct cudbg_buffer temp_buff = { 0 }; 1073 struct cudbg_rss_vf_conf *vfconf; 1074 int vf, rc, vf_count; 1075 1076 vf_count = padap->params.arch.vfcount; 1077 rc = cudbg_get_buff(pdbg_init, dbg_buff, 1078 vf_count * sizeof(struct cudbg_rss_vf_conf), 1079 &temp_buff); 1080 if (rc) 1081 return rc; 1082 1083 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data; 1084 for (vf = 0; vf < vf_count; vf++) 1085 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl, 1086 &vfconf[vf].rss_vf_vfh, true); 1087 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1088 } 1089 1090 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init, 1091 struct cudbg_buffer *dbg_buff, 1092 struct cudbg_error *cudbg_err) 1093 { 1094 struct adapter *padap = pdbg_init->adap; 1095 struct cudbg_buffer temp_buff = { 0 }; 1096 int rc; 1097 1098 rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16), 1099 &temp_buff); 1100 if (rc) 1101 return rc; 1102 1103 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL); 1104 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1105 } 1106 1107 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init, 1108 struct cudbg_buffer *dbg_buff, 1109 struct cudbg_error *cudbg_err) 1110 { 1111 struct adapter *padap = pdbg_init->adap; 1112 struct cudbg_buffer temp_buff = { 0 }; 1113 struct cudbg_pm_stats *pm_stats_buff; 1114 int rc; 1115 1116 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats), 1117 &temp_buff); 1118 if (rc) 1119 return rc; 1120 1121 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data; 1122 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc); 1123 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc); 1124 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1125 } 1126 1127 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init, 1128 struct cudbg_buffer *dbg_buff, 1129 struct cudbg_error *cudbg_err) 1130 { 1131 struct adapter *padap = pdbg_init->adap; 1132 struct cudbg_buffer temp_buff = { 0 }; 1133 struct cudbg_hw_sched *hw_sched_buff; 1134 int i, rc = 0; 1135 1136 if (!padap->params.vpd.cclk) 1137 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1138 1139 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched), 1140 &temp_buff); 1141 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data; 1142 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A); 1143 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A)); 1144 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab); 1145 for (i = 0; i < NTX_SCHED; ++i) 1146 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i], 1147 &hw_sched_buff->ipg[i], true); 1148 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1149 } 1150 1151 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init, 1152 struct cudbg_buffer *dbg_buff, 1153 struct cudbg_error *cudbg_err) 1154 { 1155 struct adapter *padap = pdbg_init->adap; 1156 struct cudbg_buffer temp_buff = { 0 }; 1157 struct ireg_buf *ch_tp_pio; 1158 int i, rc, n = 0; 1159 u32 size; 1160 1161 if (is_t5(padap->params.chip)) 1162 n = sizeof(t5_tp_pio_array) + 1163 sizeof(t5_tp_tm_pio_array) + 1164 sizeof(t5_tp_mib_index_array); 1165 else 1166 n = sizeof(t6_tp_pio_array) + 1167 sizeof(t6_tp_tm_pio_array) + 1168 sizeof(t6_tp_mib_index_array); 1169 1170 n = n / (IREG_NUM_ELEM * sizeof(u32)); 1171 size = sizeof(struct ireg_buf) * n; 1172 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1173 if (rc) 1174 return rc; 1175 1176 ch_tp_pio = (struct ireg_buf *)temp_buff.data; 1177 1178 /* TP_PIO */ 1179 if (is_t5(padap->params.chip)) 1180 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1181 else if (is_t6(padap->params.chip)) 1182 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1183 1184 for (i = 0; i < n; i++) { 1185 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1186 u32 *buff = ch_tp_pio->outbuf; 1187 1188 if (is_t5(padap->params.chip)) { 1189 tp_pio->ireg_addr = t5_tp_pio_array[i][0]; 1190 tp_pio->ireg_data = t5_tp_pio_array[i][1]; 1191 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2]; 1192 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3]; 1193 } else if (is_t6(padap->params.chip)) { 1194 tp_pio->ireg_addr = t6_tp_pio_array[i][0]; 1195 tp_pio->ireg_data = t6_tp_pio_array[i][1]; 1196 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2]; 1197 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3]; 1198 } 1199 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range, 1200 tp_pio->ireg_local_offset, true); 1201 ch_tp_pio++; 1202 } 1203 1204 /* TP_TM_PIO */ 1205 if (is_t5(padap->params.chip)) 1206 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1207 else if (is_t6(padap->params.chip)) 1208 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32)); 1209 1210 for (i = 0; i < n; i++) { 1211 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1212 u32 *buff = ch_tp_pio->outbuf; 1213 1214 if (is_t5(padap->params.chip)) { 1215 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0]; 1216 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1]; 1217 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2]; 1218 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3]; 1219 } else if (is_t6(padap->params.chip)) { 1220 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0]; 1221 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1]; 1222 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2]; 1223 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3]; 1224 } 1225 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range, 1226 tp_pio->ireg_local_offset, true); 1227 ch_tp_pio++; 1228 } 1229 1230 /* TP_MIB_INDEX */ 1231 if (is_t5(padap->params.chip)) 1232 n = sizeof(t5_tp_mib_index_array) / 1233 (IREG_NUM_ELEM * sizeof(u32)); 1234 else if (is_t6(padap->params.chip)) 1235 n = sizeof(t6_tp_mib_index_array) / 1236 (IREG_NUM_ELEM * sizeof(u32)); 1237 1238 for (i = 0; i < n ; i++) { 1239 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio; 1240 u32 *buff = ch_tp_pio->outbuf; 1241 1242 if (is_t5(padap->params.chip)) { 1243 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0]; 1244 tp_pio->ireg_data = t5_tp_mib_index_array[i][1]; 1245 tp_pio->ireg_local_offset = 1246 t5_tp_mib_index_array[i][2]; 1247 tp_pio->ireg_offset_range = 1248 t5_tp_mib_index_array[i][3]; 1249 } else if (is_t6(padap->params.chip)) { 1250 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0]; 1251 tp_pio->ireg_data = t6_tp_mib_index_array[i][1]; 1252 tp_pio->ireg_local_offset = 1253 t6_tp_mib_index_array[i][2]; 1254 tp_pio->ireg_offset_range = 1255 t6_tp_mib_index_array[i][3]; 1256 } 1257 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range, 1258 tp_pio->ireg_local_offset, true); 1259 ch_tp_pio++; 1260 } 1261 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1262 } 1263 1264 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init, 1265 struct cudbg_buffer *dbg_buff, 1266 struct cudbg_error *cudbg_err) 1267 { 1268 struct adapter *padap = pdbg_init->adap; 1269 struct cudbg_buffer temp_buff = { 0 }; 1270 struct ireg_buf *ch_sge_dbg; 1271 int i, rc; 1272 1273 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(*ch_sge_dbg) * 2, 1274 &temp_buff); 1275 if (rc) 1276 return rc; 1277 1278 ch_sge_dbg = (struct ireg_buf *)temp_buff.data; 1279 for (i = 0; i < 2; i++) { 1280 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio; 1281 u32 *buff = ch_sge_dbg->outbuf; 1282 1283 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0]; 1284 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1]; 1285 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2]; 1286 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3]; 1287 t4_read_indirect(padap, 1288 sge_pio->ireg_addr, 1289 sge_pio->ireg_data, 1290 buff, 1291 sge_pio->ireg_offset_range, 1292 sge_pio->ireg_local_offset); 1293 ch_sge_dbg++; 1294 } 1295 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1296 } 1297 1298 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init, 1299 struct cudbg_buffer *dbg_buff, 1300 struct cudbg_error *cudbg_err) 1301 { 1302 struct adapter *padap = pdbg_init->adap; 1303 struct cudbg_buffer temp_buff = { 0 }; 1304 struct cudbg_ulprx_la *ulprx_la_buff; 1305 int rc; 1306 1307 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la), 1308 &temp_buff); 1309 if (rc) 1310 return rc; 1311 1312 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data; 1313 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data); 1314 ulprx_la_buff->size = ULPRX_LA_SIZE; 1315 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1316 } 1317 1318 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init, 1319 struct cudbg_buffer *dbg_buff, 1320 struct cudbg_error *cudbg_err) 1321 { 1322 struct adapter *padap = pdbg_init->adap; 1323 struct cudbg_buffer temp_buff = { 0 }; 1324 struct cudbg_tp_la *tp_la_buff; 1325 int size, rc; 1326 1327 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); 1328 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1329 if (rc) 1330 return rc; 1331 1332 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data; 1333 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A)); 1334 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL); 1335 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1336 } 1337 1338 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init, 1339 struct cudbg_buffer *dbg_buff, 1340 struct cudbg_error *cudbg_err) 1341 { 1342 struct adapter *padap = pdbg_init->adap; 1343 struct cudbg_buffer temp_buff = { 0 }; 1344 struct cudbg_meminfo *meminfo_buff; 1345 int rc; 1346 1347 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_meminfo), 1348 &temp_buff); 1349 if (rc) 1350 return rc; 1351 1352 meminfo_buff = (struct cudbg_meminfo *)temp_buff.data; 1353 rc = cudbg_fill_meminfo(padap, meminfo_buff); 1354 if (rc) { 1355 cudbg_err->sys_err = rc; 1356 cudbg_put_buff(pdbg_init, &temp_buff); 1357 return rc; 1358 } 1359 1360 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1361 } 1362 1363 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init, 1364 struct cudbg_buffer *dbg_buff, 1365 struct cudbg_error *cudbg_err) 1366 { 1367 struct cudbg_cim_pif_la *cim_pif_la_buff; 1368 struct adapter *padap = pdbg_init->adap; 1369 struct cudbg_buffer temp_buff = { 0 }; 1370 int size, rc; 1371 1372 size = sizeof(struct cudbg_cim_pif_la) + 1373 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); 1374 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1375 if (rc) 1376 return rc; 1377 1378 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data; 1379 cim_pif_la_buff->size = CIM_PIFLA_SIZE; 1380 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data, 1381 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE, 1382 NULL, NULL); 1383 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1384 } 1385 1386 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init, 1387 struct cudbg_buffer *dbg_buff, 1388 struct cudbg_error *cudbg_err) 1389 { 1390 struct adapter *padap = pdbg_init->adap; 1391 struct cudbg_buffer temp_buff = { 0 }; 1392 struct cudbg_clk_info *clk_info_buff; 1393 u64 tp_tick_us; 1394 int rc; 1395 1396 if (!padap->params.vpd.cclk) 1397 return CUDBG_STATUS_CCLK_NOT_DEFINED; 1398 1399 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info), 1400 &temp_buff); 1401 if (rc) 1402 return rc; 1403 1404 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data; 1405 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */ 1406 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A); 1407 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res); 1408 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res); 1409 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000; 1410 1411 clk_info_buff->dack_timer = 1412 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 * 1413 t4_read_reg(padap, TP_DACK_TIMER_A); 1414 clk_info_buff->retransmit_min = 1415 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A); 1416 clk_info_buff->retransmit_max = 1417 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A); 1418 clk_info_buff->persist_timer_min = 1419 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A); 1420 clk_info_buff->persist_timer_max = 1421 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A); 1422 clk_info_buff->keepalive_idle_timer = 1423 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A); 1424 clk_info_buff->keepalive_interval = 1425 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A); 1426 clk_info_buff->initial_srtt = 1427 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A)); 1428 clk_info_buff->finwait2_timer = 1429 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A); 1430 1431 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1432 } 1433 1434 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init, 1435 struct cudbg_buffer *dbg_buff, 1436 struct cudbg_error *cudbg_err) 1437 { 1438 struct adapter *padap = pdbg_init->adap; 1439 struct cudbg_buffer temp_buff = { 0 }; 1440 struct ireg_buf *ch_pcie; 1441 int i, rc, n; 1442 u32 size; 1443 1444 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1445 size = sizeof(struct ireg_buf) * n * 2; 1446 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1447 if (rc) 1448 return rc; 1449 1450 ch_pcie = (struct ireg_buf *)temp_buff.data; 1451 /* PCIE_PDBG */ 1452 for (i = 0; i < n; i++) { 1453 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1454 u32 *buff = ch_pcie->outbuf; 1455 1456 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0]; 1457 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1]; 1458 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2]; 1459 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3]; 1460 t4_read_indirect(padap, 1461 pcie_pio->ireg_addr, 1462 pcie_pio->ireg_data, 1463 buff, 1464 pcie_pio->ireg_offset_range, 1465 pcie_pio->ireg_local_offset); 1466 ch_pcie++; 1467 } 1468 1469 /* PCIE_CDBG */ 1470 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 1471 for (i = 0; i < n; i++) { 1472 struct ireg_field *pcie_pio = &ch_pcie->tp_pio; 1473 u32 *buff = ch_pcie->outbuf; 1474 1475 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0]; 1476 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1]; 1477 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2]; 1478 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3]; 1479 t4_read_indirect(padap, 1480 pcie_pio->ireg_addr, 1481 pcie_pio->ireg_data, 1482 buff, 1483 pcie_pio->ireg_offset_range, 1484 pcie_pio->ireg_local_offset); 1485 ch_pcie++; 1486 } 1487 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1488 } 1489 1490 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init, 1491 struct cudbg_buffer *dbg_buff, 1492 struct cudbg_error *cudbg_err) 1493 { 1494 struct adapter *padap = pdbg_init->adap; 1495 struct cudbg_buffer temp_buff = { 0 }; 1496 struct ireg_buf *ch_pm; 1497 int i, rc, n; 1498 u32 size; 1499 1500 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1501 size = sizeof(struct ireg_buf) * n * 2; 1502 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1503 if (rc) 1504 return rc; 1505 1506 ch_pm = (struct ireg_buf *)temp_buff.data; 1507 /* PM_RX */ 1508 for (i = 0; i < n; i++) { 1509 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1510 u32 *buff = ch_pm->outbuf; 1511 1512 pm_pio->ireg_addr = t5_pm_rx_array[i][0]; 1513 pm_pio->ireg_data = t5_pm_rx_array[i][1]; 1514 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2]; 1515 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3]; 1516 t4_read_indirect(padap, 1517 pm_pio->ireg_addr, 1518 pm_pio->ireg_data, 1519 buff, 1520 pm_pio->ireg_offset_range, 1521 pm_pio->ireg_local_offset); 1522 ch_pm++; 1523 } 1524 1525 /* PM_TX */ 1526 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32)); 1527 for (i = 0; i < n; i++) { 1528 struct ireg_field *pm_pio = &ch_pm->tp_pio; 1529 u32 *buff = ch_pm->outbuf; 1530 1531 pm_pio->ireg_addr = t5_pm_tx_array[i][0]; 1532 pm_pio->ireg_data = t5_pm_tx_array[i][1]; 1533 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2]; 1534 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3]; 1535 t4_read_indirect(padap, 1536 pm_pio->ireg_addr, 1537 pm_pio->ireg_data, 1538 buff, 1539 pm_pio->ireg_offset_range, 1540 pm_pio->ireg_local_offset); 1541 ch_pm++; 1542 } 1543 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1544 } 1545 1546 int cudbg_collect_tid(struct cudbg_init *pdbg_init, 1547 struct cudbg_buffer *dbg_buff, 1548 struct cudbg_error *cudbg_err) 1549 { 1550 struct adapter *padap = pdbg_init->adap; 1551 struct cudbg_tid_info_region_rev1 *tid1; 1552 struct cudbg_buffer temp_buff = { 0 }; 1553 struct cudbg_tid_info_region *tid; 1554 u32 para[2], val[2]; 1555 int rc; 1556 1557 rc = cudbg_get_buff(pdbg_init, dbg_buff, 1558 sizeof(struct cudbg_tid_info_region_rev1), 1559 &temp_buff); 1560 if (rc) 1561 return rc; 1562 1563 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data; 1564 tid = &tid1->tid; 1565 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE; 1566 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV; 1567 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) - 1568 sizeof(struct cudbg_ver_hdr); 1569 1570 /* If firmware is not attached/alive, use backdoor register 1571 * access to collect dump. 1572 */ 1573 if (!is_fw_attached(pdbg_init)) 1574 goto fill_tid; 1575 1576 #define FW_PARAM_PFVF_A(param) \ 1577 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 1578 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 1579 FW_PARAMS_PARAM_Y_V(0) | \ 1580 FW_PARAMS_PARAM_Z_V(0)) 1581 1582 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START); 1583 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END); 1584 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val); 1585 if (rc < 0) { 1586 cudbg_err->sys_err = rc; 1587 cudbg_put_buff(pdbg_init, &temp_buff); 1588 return rc; 1589 } 1590 tid->uotid_base = val[0]; 1591 tid->nuotids = val[1] - val[0] + 1; 1592 1593 if (is_t5(padap->params.chip)) { 1594 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4; 1595 } else if (is_t6(padap->params.chip)) { 1596 tid1->tid_start = 1597 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A); 1598 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A); 1599 1600 para[0] = FW_PARAM_PFVF_A(HPFILTER_START); 1601 para[1] = FW_PARAM_PFVF_A(HPFILTER_END); 1602 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, 1603 para, val); 1604 if (rc < 0) { 1605 cudbg_err->sys_err = rc; 1606 cudbg_put_buff(pdbg_init, &temp_buff); 1607 return rc; 1608 } 1609 tid->hpftid_base = val[0]; 1610 tid->nhpftids = val[1] - val[0] + 1; 1611 } 1612 1613 #undef FW_PARAM_PFVF_A 1614 1615 fill_tid: 1616 tid->ntids = padap->tids.ntids; 1617 tid->nstids = padap->tids.nstids; 1618 tid->stid_base = padap->tids.stid_base; 1619 tid->hash_base = padap->tids.hash_base; 1620 1621 tid->natids = padap->tids.natids; 1622 tid->nftids = padap->tids.nftids; 1623 tid->ftid_base = padap->tids.ftid_base; 1624 tid->aftid_base = padap->tids.aftid_base; 1625 tid->aftid_end = padap->tids.aftid_end; 1626 1627 tid->sftid_base = padap->tids.sftid_base; 1628 tid->nsftids = padap->tids.nsftids; 1629 1630 tid->flags = padap->flags; 1631 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A); 1632 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A); 1633 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A); 1634 1635 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1636 } 1637 1638 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init, 1639 struct cudbg_buffer *dbg_buff, 1640 struct cudbg_error *cudbg_err) 1641 { 1642 struct adapter *padap = pdbg_init->adap; 1643 struct cudbg_buffer temp_buff = { 0 }; 1644 u32 size, *value, j; 1645 int i, rc, n; 1646 1647 size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS; 1648 n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32)); 1649 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1650 if (rc) 1651 return rc; 1652 1653 value = (u32 *)temp_buff.data; 1654 for (i = 0; i < n; i++) { 1655 for (j = t5_pcie_config_array[i][0]; 1656 j <= t5_pcie_config_array[i][1]; j += 4) { 1657 t4_hw_pci_read_cfg4(padap, j, value); 1658 value++; 1659 } 1660 } 1661 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1662 } 1663 1664 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type) 1665 { 1666 int index, bit, bit_pos = 0; 1667 1668 switch (type) { 1669 case CTXT_EGRESS: 1670 bit_pos = 176; 1671 break; 1672 case CTXT_INGRESS: 1673 bit_pos = 141; 1674 break; 1675 case CTXT_FLM: 1676 bit_pos = 89; 1677 break; 1678 } 1679 index = bit_pos / 32; 1680 bit = bit_pos % 32; 1681 return buf[index] & (1U << bit); 1682 } 1683 1684 static int cudbg_get_ctxt_region_info(struct adapter *padap, 1685 struct cudbg_region_info *ctx_info, 1686 u8 *mem_type) 1687 { 1688 struct cudbg_mem_desc mem_desc; 1689 struct cudbg_meminfo meminfo; 1690 u32 i, j, value, found; 1691 u8 flq; 1692 int rc; 1693 1694 rc = cudbg_fill_meminfo(padap, &meminfo); 1695 if (rc) 1696 return rc; 1697 1698 /* Get EGRESS and INGRESS context region size */ 1699 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) { 1700 found = 0; 1701 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc)); 1702 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) { 1703 rc = cudbg_get_mem_region(padap, &meminfo, j, 1704 cudbg_region[i], 1705 &mem_desc); 1706 if (!rc) { 1707 found = 1; 1708 rc = cudbg_get_mem_relative(padap, &meminfo, j, 1709 &mem_desc.base, 1710 &mem_desc.limit); 1711 if (rc) { 1712 ctx_info[i].exist = false; 1713 break; 1714 } 1715 ctx_info[i].exist = true; 1716 ctx_info[i].start = mem_desc.base; 1717 ctx_info[i].end = mem_desc.limit; 1718 mem_type[i] = j; 1719 break; 1720 } 1721 } 1722 if (!found) 1723 ctx_info[i].exist = false; 1724 } 1725 1726 /* Get FLM and CNM max qid. */ 1727 value = t4_read_reg(padap, SGE_FLM_CFG_A); 1728 1729 /* Get number of data freelist queues */ 1730 flq = HDRSTARTFLQ_G(value); 1731 ctx_info[CTXT_FLM].exist = true; 1732 ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE; 1733 1734 /* The number of CONM contexts are same as number of freelist 1735 * queues. 1736 */ 1737 ctx_info[CTXT_CNM].exist = true; 1738 ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end; 1739 1740 return 0; 1741 } 1742 1743 int cudbg_dump_context_size(struct adapter *padap) 1744 { 1745 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} }; 1746 u8 mem_type[CTXT_INGRESS + 1] = { 0 }; 1747 u32 i, size = 0; 1748 int rc; 1749 1750 /* Get max valid qid for each type of queue */ 1751 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); 1752 if (rc) 1753 return rc; 1754 1755 for (i = 0; i < CTXT_CNM; i++) { 1756 if (!region_info[i].exist) { 1757 if (i == CTXT_EGRESS || i == CTXT_INGRESS) 1758 size += CUDBG_LOWMEM_MAX_CTXT_QIDS * 1759 SGE_CTXT_SIZE; 1760 continue; 1761 } 1762 1763 size += (region_info[i].end - region_info[i].start + 1) / 1764 SGE_CTXT_SIZE; 1765 } 1766 return size * sizeof(struct cudbg_ch_cntxt); 1767 } 1768 1769 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid, 1770 enum ctxt_type ctype, u32 *data) 1771 { 1772 struct adapter *padap = pdbg_init->adap; 1773 int rc = -1; 1774 1775 /* Under heavy traffic, the SGE Queue contexts registers will be 1776 * frequently accessed by firmware. 1777 * 1778 * To avoid conflicts with firmware, always ask firmware to fetch 1779 * the SGE Queue contexts via mailbox. On failure, fallback to 1780 * accessing hardware registers directly. 1781 */ 1782 if (is_fw_attached(pdbg_init)) 1783 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data); 1784 if (rc) 1785 t4_sge_ctxt_rd_bd(padap, cid, ctype, data); 1786 } 1787 1788 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid, 1789 u8 ctxt_type, 1790 struct cudbg_ch_cntxt **out_buff) 1791 { 1792 struct cudbg_ch_cntxt *buff = *out_buff; 1793 int rc; 1794 u32 j; 1795 1796 for (j = 0; j < max_qid; j++) { 1797 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data); 1798 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type); 1799 if (!rc) 1800 continue; 1801 1802 buff->cntxt_type = ctxt_type; 1803 buff->cntxt_id = j; 1804 buff++; 1805 if (ctxt_type == CTXT_FLM) { 1806 cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data); 1807 buff->cntxt_type = CTXT_CNM; 1808 buff->cntxt_id = j; 1809 buff++; 1810 } 1811 } 1812 1813 *out_buff = buff; 1814 } 1815 1816 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init, 1817 struct cudbg_buffer *dbg_buff, 1818 struct cudbg_error *cudbg_err) 1819 { 1820 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} }; 1821 struct adapter *padap = pdbg_init->adap; 1822 u32 j, size, max_ctx_size, max_ctx_qid; 1823 u8 mem_type[CTXT_INGRESS + 1] = { 0 }; 1824 struct cudbg_buffer temp_buff = { 0 }; 1825 struct cudbg_ch_cntxt *buff; 1826 u64 *dst_off, *src_off; 1827 u8 *ctx_buf; 1828 u8 i, k; 1829 int rc; 1830 1831 /* Get max valid qid for each type of queue */ 1832 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type); 1833 if (rc) 1834 return rc; 1835 1836 rc = cudbg_dump_context_size(padap); 1837 if (rc <= 0) 1838 return CUDBG_STATUS_ENTITY_NOT_FOUND; 1839 1840 size = rc; 1841 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 1842 if (rc) 1843 return rc; 1844 1845 /* Get buffer with enough space to read the biggest context 1846 * region in memory. 1847 */ 1848 max_ctx_size = max(region_info[CTXT_EGRESS].end - 1849 region_info[CTXT_EGRESS].start + 1, 1850 region_info[CTXT_INGRESS].end - 1851 region_info[CTXT_INGRESS].start + 1); 1852 1853 ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL); 1854 if (!ctx_buf) { 1855 cudbg_put_buff(pdbg_init, &temp_buff); 1856 return -ENOMEM; 1857 } 1858 1859 buff = (struct cudbg_ch_cntxt *)temp_buff.data; 1860 1861 /* Collect EGRESS and INGRESS context data. 1862 * In case of failures, fallback to collecting via FW or 1863 * backdoor access. 1864 */ 1865 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) { 1866 if (!region_info[i].exist) { 1867 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS; 1868 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i, 1869 &buff); 1870 continue; 1871 } 1872 1873 max_ctx_size = region_info[i].end - region_info[i].start + 1; 1874 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE; 1875 1876 /* If firmware is not attached/alive, use backdoor register 1877 * access to collect dump. 1878 */ 1879 if (is_fw_attached(pdbg_init)) { 1880 t4_sge_ctxt_flush(padap, padap->mbox, i); 1881 1882 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i], 1883 region_info[i].start, max_ctx_size, 1884 (__be32 *)ctx_buf, 1); 1885 } 1886 1887 if (rc || !is_fw_attached(pdbg_init)) { 1888 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS; 1889 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i, 1890 &buff); 1891 continue; 1892 } 1893 1894 for (j = 0; j < max_ctx_qid; j++) { 1895 src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE); 1896 dst_off = (u64 *)buff->data; 1897 1898 /* The data is stored in 64-bit cpu order. Convert it 1899 * to big endian before parsing. 1900 */ 1901 for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++) 1902 dst_off[k] = cpu_to_be64(src_off[k]); 1903 1904 rc = cudbg_sge_ctxt_check_valid(buff->data, i); 1905 if (!rc) 1906 continue; 1907 1908 buff->cntxt_type = i; 1909 buff->cntxt_id = j; 1910 buff++; 1911 } 1912 } 1913 1914 kvfree(ctx_buf); 1915 1916 /* Collect FREELIST and CONGESTION MANAGER contexts */ 1917 max_ctx_size = region_info[CTXT_FLM].end - 1918 region_info[CTXT_FLM].start + 1; 1919 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE; 1920 /* Since FLM and CONM are 1-to-1 mapped, the below function 1921 * will fetch both FLM and CONM contexts. 1922 */ 1923 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff); 1924 1925 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 1926 } 1927 1928 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 1929 { 1930 *mask = x | y; 1931 y = (__force u64)cpu_to_be64(y); 1932 memcpy(addr, (char *)&y + 2, ETH_ALEN); 1933 } 1934 1935 static void cudbg_mps_rpl_backdoor(struct adapter *padap, 1936 struct fw_ldst_mps_rplc *mps_rplc) 1937 { 1938 if (is_t5(padap->params.chip)) { 1939 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 1940 MPS_VF_RPLCT_MAP3_A)); 1941 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 1942 MPS_VF_RPLCT_MAP2_A)); 1943 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 1944 MPS_VF_RPLCT_MAP1_A)); 1945 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 1946 MPS_VF_RPLCT_MAP0_A)); 1947 } else { 1948 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap, 1949 MPS_VF_RPLCT_MAP7_A)); 1950 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap, 1951 MPS_VF_RPLCT_MAP6_A)); 1952 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap, 1953 MPS_VF_RPLCT_MAP5_A)); 1954 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap, 1955 MPS_VF_RPLCT_MAP4_A)); 1956 } 1957 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A)); 1958 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A)); 1959 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A)); 1960 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A)); 1961 } 1962 1963 static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init, 1964 struct cudbg_mps_tcam *tcam, u32 idx) 1965 { 1966 struct adapter *padap = pdbg_init->adap; 1967 u64 tcamy, tcamx, val; 1968 u32 ctl, data2; 1969 int rc = 0; 1970 1971 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) { 1972 /* CtlReqID - 1: use Host Driver Requester ID 1973 * CtlCmdType - 0: Read, 1: Write 1974 * CtlTcamSel - 0: TCAM0, 1: TCAM1 1975 * CtlXYBitSel- 0: Y bit, 1: X bit 1976 */ 1977 1978 /* Read tcamy */ 1979 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 1980 if (idx < 256) 1981 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 1982 else 1983 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1); 1984 1985 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1986 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 1987 tcamy = DMACH_G(val) << 32; 1988 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 1989 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 1990 tcam->lookup_type = DATALKPTYPE_G(data2); 1991 1992 /* 0 - Outer header, 1 - Inner header 1993 * [71:48] bit locations are overloaded for 1994 * outer vs. inner lookup types. 1995 */ 1996 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 1997 /* Inner header VNI */ 1998 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 1999 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val); 2000 tcam->dip_hit = data2 & DATADIPHIT_F; 2001 } else { 2002 tcam->vlan_vld = data2 & DATAVIDH2_F; 2003 tcam->ivlan = VIDL_G(val); 2004 } 2005 2006 tcam->port_num = DATAPORTNUM_G(data2); 2007 2008 /* Read tcamx. Change the control param */ 2009 ctl |= CTLXYBITSEL_V(1); 2010 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 2011 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A); 2012 tcamx = DMACH_G(val) << 32; 2013 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A); 2014 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A); 2015 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) { 2016 /* Inner header VNI mask */ 2017 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2); 2018 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val); 2019 } 2020 } else { 2021 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx)); 2022 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx)); 2023 } 2024 2025 /* If no entry, return */ 2026 if (tcamx & tcamy) 2027 return rc; 2028 2029 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx)); 2030 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx)); 2031 2032 if (is_t5(padap->params.chip)) 2033 tcam->repli = (tcam->cls_lo & REPLICATE_F); 2034 else if (is_t6(padap->params.chip)) 2035 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F); 2036 2037 if (tcam->repli) { 2038 struct fw_ldst_cmd ldst_cmd; 2039 struct fw_ldst_mps_rplc mps_rplc; 2040 2041 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 2042 ldst_cmd.op_to_addrspace = 2043 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 2044 FW_CMD_REQUEST_F | FW_CMD_READ_F | 2045 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS)); 2046 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 2047 ldst_cmd.u.mps.rplc.fid_idx = 2048 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 2049 FW_LDST_CMD_IDX_V(idx)); 2050 2051 /* If firmware is not attached/alive, use backdoor register 2052 * access to collect dump. 2053 */ 2054 if (is_fw_attached(pdbg_init)) 2055 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd, 2056 sizeof(ldst_cmd), &ldst_cmd); 2057 2058 if (rc || !is_fw_attached(pdbg_init)) { 2059 cudbg_mps_rpl_backdoor(padap, &mps_rplc); 2060 /* Ignore error since we collected directly from 2061 * reading registers. 2062 */ 2063 rc = 0; 2064 } else { 2065 mps_rplc = ldst_cmd.u.mps.rplc; 2066 } 2067 2068 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0); 2069 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32); 2070 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64); 2071 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96); 2072 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) { 2073 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128); 2074 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160); 2075 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192); 2076 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224); 2077 } 2078 } 2079 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask); 2080 tcam->idx = idx; 2081 tcam->rplc_size = padap->params.arch.mps_rplc_size; 2082 return rc; 2083 } 2084 2085 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init, 2086 struct cudbg_buffer *dbg_buff, 2087 struct cudbg_error *cudbg_err) 2088 { 2089 struct adapter *padap = pdbg_init->adap; 2090 struct cudbg_buffer temp_buff = { 0 }; 2091 u32 size = 0, i, n, total_size = 0; 2092 struct cudbg_mps_tcam *tcam; 2093 int rc; 2094 2095 n = padap->params.arch.mps_tcam_size; 2096 size = sizeof(struct cudbg_mps_tcam) * n; 2097 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2098 if (rc) 2099 return rc; 2100 2101 tcam = (struct cudbg_mps_tcam *)temp_buff.data; 2102 for (i = 0; i < n; i++) { 2103 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i); 2104 if (rc) { 2105 cudbg_err->sys_err = rc; 2106 cudbg_put_buff(pdbg_init, &temp_buff); 2107 return rc; 2108 } 2109 total_size += sizeof(struct cudbg_mps_tcam); 2110 tcam++; 2111 } 2112 2113 if (!total_size) { 2114 rc = CUDBG_SYSTEM_ERROR; 2115 cudbg_err->sys_err = rc; 2116 cudbg_put_buff(pdbg_init, &temp_buff); 2117 return rc; 2118 } 2119 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2120 } 2121 2122 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init, 2123 struct cudbg_buffer *dbg_buff, 2124 struct cudbg_error *cudbg_err) 2125 { 2126 struct adapter *padap = pdbg_init->adap; 2127 struct cudbg_buffer temp_buff = { 0 }; 2128 char vpd_str[CUDBG_VPD_VER_LEN + 1]; 2129 u32 scfg_vers, vpd_vers, fw_vers; 2130 struct cudbg_vpd_data *vpd_data; 2131 struct vpd_params vpd = { 0 }; 2132 int rc, ret; 2133 2134 rc = t4_get_raw_vpd_params(padap, &vpd); 2135 if (rc) 2136 return rc; 2137 2138 rc = t4_get_fw_version(padap, &fw_vers); 2139 if (rc) 2140 return rc; 2141 2142 /* Serial Configuration Version is located beyond the PF's vpd size. 2143 * Temporarily give access to entire EEPROM to get it. 2144 */ 2145 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE); 2146 if (rc < 0) 2147 return rc; 2148 2149 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN, 2150 &scfg_vers); 2151 2152 /* Restore back to original PF's vpd size */ 2153 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE); 2154 if (rc < 0) 2155 return rc; 2156 2157 if (ret) 2158 return ret; 2159 2160 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN, 2161 vpd_str); 2162 if (rc) 2163 return rc; 2164 2165 vpd_str[CUDBG_VPD_VER_LEN] = '\0'; 2166 rc = kstrtouint(vpd_str, 0, &vpd_vers); 2167 if (rc) 2168 return rc; 2169 2170 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data), 2171 &temp_buff); 2172 if (rc) 2173 return rc; 2174 2175 vpd_data = (struct cudbg_vpd_data *)temp_buff.data; 2176 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1); 2177 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1); 2178 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1); 2179 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1); 2180 vpd_data->scfg_vers = scfg_vers; 2181 vpd_data->vpd_vers = vpd_vers; 2182 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers); 2183 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers); 2184 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers); 2185 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers); 2186 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2187 } 2188 2189 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid, 2190 struct cudbg_tid_data *tid_data) 2191 { 2192 struct adapter *padap = pdbg_init->adap; 2193 int i, cmd_retry = 8; 2194 u32 val; 2195 2196 /* Fill REQ_DATA regs with 0's */ 2197 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++) 2198 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0); 2199 2200 /* Write DBIG command */ 2201 val = DBGICMD_V(4) | DBGITID_V(tid); 2202 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val); 2203 tid_data->dbig_cmd = val; 2204 2205 val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */ 2206 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val); 2207 tid_data->dbig_conf = val; 2208 2209 /* Poll the DBGICMDBUSY bit */ 2210 val = 1; 2211 while (val) { 2212 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A); 2213 val = val & DBGICMDBUSY_F; 2214 cmd_retry--; 2215 if (!cmd_retry) 2216 return CUDBG_SYSTEM_ERROR; 2217 } 2218 2219 /* Check RESP status */ 2220 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A); 2221 tid_data->dbig_rsp_stat = val; 2222 if (!(val & 1)) 2223 return CUDBG_SYSTEM_ERROR; 2224 2225 /* Read RESP data */ 2226 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++) 2227 tid_data->data[i] = t4_read_reg(padap, 2228 LE_DB_DBGI_RSP_DATA_A + 2229 (i << 2)); 2230 tid_data->tid = tid; 2231 return 0; 2232 } 2233 2234 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region) 2235 { 2236 int type = LE_ET_UNKNOWN; 2237 2238 if (tid < tcam_region.server_start) 2239 type = LE_ET_TCAM_CON; 2240 else if (tid < tcam_region.filter_start) 2241 type = LE_ET_TCAM_SERVER; 2242 else if (tid < tcam_region.clip_start) 2243 type = LE_ET_TCAM_FILTER; 2244 else if (tid < tcam_region.routing_start) 2245 type = LE_ET_TCAM_CLIP; 2246 else if (tid < tcam_region.tid_hash_base) 2247 type = LE_ET_TCAM_ROUTING; 2248 else if (tid < tcam_region.max_tid) 2249 type = LE_ET_HASH_CON; 2250 else 2251 type = LE_ET_INVALID_TID; 2252 2253 return type; 2254 } 2255 2256 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data, 2257 struct cudbg_tcam tcam_region) 2258 { 2259 int ipv6 = 0; 2260 int le_type; 2261 2262 le_type = cudbg_get_le_type(tid_data->tid, tcam_region); 2263 if (tid_data->tid & 1) 2264 return 0; 2265 2266 if (le_type == LE_ET_HASH_CON) { 2267 ipv6 = tid_data->data[16] & 0x8000; 2268 } else if (le_type == LE_ET_TCAM_CON) { 2269 ipv6 = tid_data->data[16] & 0x8000; 2270 if (ipv6) 2271 ipv6 = tid_data->data[9] == 0x00C00000; 2272 } else { 2273 ipv6 = 0; 2274 } 2275 return ipv6; 2276 } 2277 2278 void cudbg_fill_le_tcam_info(struct adapter *padap, 2279 struct cudbg_tcam *tcam_region) 2280 { 2281 u32 value; 2282 2283 /* Get the LE regions */ 2284 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */ 2285 tcam_region->tid_hash_base = value; 2286 2287 /* Get routing table index */ 2288 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A); 2289 tcam_region->routing_start = value; 2290 2291 /*Get clip table index */ 2292 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A); 2293 tcam_region->clip_start = value; 2294 2295 /* Get filter table index */ 2296 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A); 2297 tcam_region->filter_start = value; 2298 2299 /* Get server table index */ 2300 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A); 2301 tcam_region->server_start = value; 2302 2303 /* Check whether hash is enabled and calculate the max tids */ 2304 value = t4_read_reg(padap, LE_DB_CONFIG_A); 2305 if ((value >> HASHEN_S) & 1) { 2306 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A); 2307 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) { 2308 tcam_region->max_tid = (value & 0xFFFFF) + 2309 tcam_region->tid_hash_base; 2310 } else { 2311 value = HASHTIDSIZE_G(value); 2312 value = 1 << value; 2313 tcam_region->max_tid = value + 2314 tcam_region->tid_hash_base; 2315 } 2316 } else { /* hash not enabled */ 2317 tcam_region->max_tid = CUDBG_MAX_TCAM_TID; 2318 } 2319 } 2320 2321 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init, 2322 struct cudbg_buffer *dbg_buff, 2323 struct cudbg_error *cudbg_err) 2324 { 2325 struct adapter *padap = pdbg_init->adap; 2326 struct cudbg_buffer temp_buff = { 0 }; 2327 struct cudbg_tcam tcam_region = { 0 }; 2328 struct cudbg_tid_data *tid_data; 2329 u32 bytes = 0; 2330 int rc, size; 2331 u32 i; 2332 2333 cudbg_fill_le_tcam_info(padap, &tcam_region); 2334 2335 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid; 2336 size += sizeof(struct cudbg_tcam); 2337 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2338 if (rc) 2339 return rc; 2340 2341 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam)); 2342 bytes = sizeof(struct cudbg_tcam); 2343 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes); 2344 /* read all tid */ 2345 for (i = 0; i < tcam_region.max_tid; ) { 2346 rc = cudbg_read_tid(pdbg_init, i, tid_data); 2347 if (rc) { 2348 cudbg_err->sys_err = rc; 2349 cudbg_put_buff(pdbg_init, &temp_buff); 2350 return rc; 2351 } 2352 2353 /* ipv6 takes two tids */ 2354 cudbg_is_ipv6_entry(tid_data, tcam_region) ? i += 2 : i++; 2355 2356 tid_data++; 2357 bytes += sizeof(struct cudbg_tid_data); 2358 } 2359 2360 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2361 } 2362 2363 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init, 2364 struct cudbg_buffer *dbg_buff, 2365 struct cudbg_error *cudbg_err) 2366 { 2367 struct adapter *padap = pdbg_init->adap; 2368 struct cudbg_buffer temp_buff = { 0 }; 2369 u32 size; 2370 int rc; 2371 2372 size = sizeof(u16) * NMTUS * NCCTRL_WIN; 2373 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2374 if (rc) 2375 return rc; 2376 2377 t4_read_cong_tbl(padap, (void *)temp_buff.data); 2378 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2379 } 2380 2381 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init, 2382 struct cudbg_buffer *dbg_buff, 2383 struct cudbg_error *cudbg_err) 2384 { 2385 struct adapter *padap = pdbg_init->adap; 2386 struct cudbg_buffer temp_buff = { 0 }; 2387 struct ireg_buf *ma_indr; 2388 int i, rc, n; 2389 u32 size, j; 2390 2391 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2392 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2393 2394 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2395 size = sizeof(struct ireg_buf) * n * 2; 2396 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2397 if (rc) 2398 return rc; 2399 2400 ma_indr = (struct ireg_buf *)temp_buff.data; 2401 for (i = 0; i < n; i++) { 2402 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2403 u32 *buff = ma_indr->outbuf; 2404 2405 ma_fli->ireg_addr = t6_ma_ireg_array[i][0]; 2406 ma_fli->ireg_data = t6_ma_ireg_array[i][1]; 2407 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2]; 2408 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3]; 2409 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data, 2410 buff, ma_fli->ireg_offset_range, 2411 ma_fli->ireg_local_offset); 2412 ma_indr++; 2413 } 2414 2415 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32)); 2416 for (i = 0; i < n; i++) { 2417 struct ireg_field *ma_fli = &ma_indr->tp_pio; 2418 u32 *buff = ma_indr->outbuf; 2419 2420 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0]; 2421 ma_fli->ireg_data = t6_ma_ireg_array2[i][1]; 2422 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2]; 2423 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) { 2424 t4_read_indirect(padap, ma_fli->ireg_addr, 2425 ma_fli->ireg_data, buff, 1, 2426 ma_fli->ireg_local_offset); 2427 buff++; 2428 ma_fli->ireg_local_offset += 0x20; 2429 } 2430 ma_indr++; 2431 } 2432 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2433 } 2434 2435 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init, 2436 struct cudbg_buffer *dbg_buff, 2437 struct cudbg_error *cudbg_err) 2438 { 2439 struct adapter *padap = pdbg_init->adap; 2440 struct cudbg_buffer temp_buff = { 0 }; 2441 struct cudbg_ulptx_la *ulptx_la_buff; 2442 u32 i, j; 2443 int rc; 2444 2445 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulptx_la), 2446 &temp_buff); 2447 if (rc) 2448 return rc; 2449 2450 ulptx_la_buff = (struct cudbg_ulptx_la *)temp_buff.data; 2451 for (i = 0; i < CUDBG_NUM_ULPTX; i++) { 2452 ulptx_la_buff->rdptr[i] = t4_read_reg(padap, 2453 ULP_TX_LA_RDPTR_0_A + 2454 0x10 * i); 2455 ulptx_la_buff->wrptr[i] = t4_read_reg(padap, 2456 ULP_TX_LA_WRPTR_0_A + 2457 0x10 * i); 2458 ulptx_la_buff->rddata[i] = t4_read_reg(padap, 2459 ULP_TX_LA_RDDATA_0_A + 2460 0x10 * i); 2461 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++) 2462 ulptx_la_buff->rd_data[i][j] = 2463 t4_read_reg(padap, 2464 ULP_TX_LA_RDDATA_0_A + 0x10 * i); 2465 } 2466 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2467 } 2468 2469 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init, 2470 struct cudbg_buffer *dbg_buff, 2471 struct cudbg_error *cudbg_err) 2472 { 2473 struct adapter *padap = pdbg_init->adap; 2474 struct cudbg_buffer temp_buff = { 0 }; 2475 u32 local_offset, local_range; 2476 struct ireg_buf *up_cim; 2477 u32 size, j, iter; 2478 u32 instance = 0; 2479 int i, rc, n; 2480 2481 if (is_t5(padap->params.chip)) 2482 n = sizeof(t5_up_cim_reg_array) / 2483 ((IREG_NUM_ELEM + 1) * sizeof(u32)); 2484 else if (is_t6(padap->params.chip)) 2485 n = sizeof(t6_up_cim_reg_array) / 2486 ((IREG_NUM_ELEM + 1) * sizeof(u32)); 2487 else 2488 return CUDBG_STATUS_NOT_IMPLEMENTED; 2489 2490 size = sizeof(struct ireg_buf) * n; 2491 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2492 if (rc) 2493 return rc; 2494 2495 up_cim = (struct ireg_buf *)temp_buff.data; 2496 for (i = 0; i < n; i++) { 2497 struct ireg_field *up_cim_reg = &up_cim->tp_pio; 2498 u32 *buff = up_cim->outbuf; 2499 2500 if (is_t5(padap->params.chip)) { 2501 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0]; 2502 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1]; 2503 up_cim_reg->ireg_local_offset = 2504 t5_up_cim_reg_array[i][2]; 2505 up_cim_reg->ireg_offset_range = 2506 t5_up_cim_reg_array[i][3]; 2507 instance = t5_up_cim_reg_array[i][4]; 2508 } else if (is_t6(padap->params.chip)) { 2509 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0]; 2510 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1]; 2511 up_cim_reg->ireg_local_offset = 2512 t6_up_cim_reg_array[i][2]; 2513 up_cim_reg->ireg_offset_range = 2514 t6_up_cim_reg_array[i][3]; 2515 instance = t6_up_cim_reg_array[i][4]; 2516 } 2517 2518 switch (instance) { 2519 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES: 2520 iter = up_cim_reg->ireg_offset_range; 2521 local_offset = 0x120; 2522 local_range = 1; 2523 break; 2524 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES: 2525 iter = up_cim_reg->ireg_offset_range; 2526 local_offset = 0x10; 2527 local_range = 1; 2528 break; 2529 default: 2530 iter = 1; 2531 local_offset = 0; 2532 local_range = up_cim_reg->ireg_offset_range; 2533 break; 2534 } 2535 2536 for (j = 0; j < iter; j++, buff++) { 2537 rc = t4_cim_read(padap, 2538 up_cim_reg->ireg_local_offset + 2539 (j * local_offset), local_range, buff); 2540 if (rc) { 2541 cudbg_put_buff(pdbg_init, &temp_buff); 2542 return rc; 2543 } 2544 } 2545 up_cim++; 2546 } 2547 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2548 } 2549 2550 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init, 2551 struct cudbg_buffer *dbg_buff, 2552 struct cudbg_error *cudbg_err) 2553 { 2554 struct adapter *padap = pdbg_init->adap; 2555 struct cudbg_buffer temp_buff = { 0 }; 2556 struct cudbg_pbt_tables *pbt; 2557 int i, rc; 2558 u32 addr; 2559 2560 rc = cudbg_get_buff(pdbg_init, dbg_buff, 2561 sizeof(struct cudbg_pbt_tables), 2562 &temp_buff); 2563 if (rc) 2564 return rc; 2565 2566 pbt = (struct cudbg_pbt_tables *)temp_buff.data; 2567 /* PBT dynamic entries */ 2568 addr = CUDBG_CHAC_PBT_ADDR; 2569 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) { 2570 rc = t4_cim_read(padap, addr + (i * 4), 1, 2571 &pbt->pbt_dynamic[i]); 2572 if (rc) { 2573 cudbg_err->sys_err = rc; 2574 cudbg_put_buff(pdbg_init, &temp_buff); 2575 return rc; 2576 } 2577 } 2578 2579 /* PBT static entries */ 2580 /* static entries start when bit 6 is set */ 2581 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6); 2582 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) { 2583 rc = t4_cim_read(padap, addr + (i * 4), 1, 2584 &pbt->pbt_static[i]); 2585 if (rc) { 2586 cudbg_err->sys_err = rc; 2587 cudbg_put_buff(pdbg_init, &temp_buff); 2588 return rc; 2589 } 2590 } 2591 2592 /* LRF entries */ 2593 addr = CUDBG_CHAC_PBT_LRF; 2594 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) { 2595 rc = t4_cim_read(padap, addr + (i * 4), 1, 2596 &pbt->lrf_table[i]); 2597 if (rc) { 2598 cudbg_err->sys_err = rc; 2599 cudbg_put_buff(pdbg_init, &temp_buff); 2600 return rc; 2601 } 2602 } 2603 2604 /* PBT data entries */ 2605 addr = CUDBG_CHAC_PBT_DATA; 2606 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) { 2607 rc = t4_cim_read(padap, addr + (i * 4), 1, 2608 &pbt->pbt_data[i]); 2609 if (rc) { 2610 cudbg_err->sys_err = rc; 2611 cudbg_put_buff(pdbg_init, &temp_buff); 2612 return rc; 2613 } 2614 } 2615 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2616 } 2617 2618 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init, 2619 struct cudbg_buffer *dbg_buff, 2620 struct cudbg_error *cudbg_err) 2621 { 2622 struct adapter *padap = pdbg_init->adap; 2623 struct cudbg_mbox_log *mboxlog = NULL; 2624 struct cudbg_buffer temp_buff = { 0 }; 2625 struct mbox_cmd_log *log = NULL; 2626 struct mbox_cmd *entry; 2627 unsigned int entry_idx; 2628 u16 mbox_cmds; 2629 int i, k, rc; 2630 u64 flit; 2631 u32 size; 2632 2633 log = padap->mbox_log; 2634 mbox_cmds = padap->mbox_log->size; 2635 size = sizeof(struct cudbg_mbox_log) * mbox_cmds; 2636 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2637 if (rc) 2638 return rc; 2639 2640 mboxlog = (struct cudbg_mbox_log *)temp_buff.data; 2641 for (k = 0; k < mbox_cmds; k++) { 2642 entry_idx = log->cursor + k; 2643 if (entry_idx >= log->size) 2644 entry_idx -= log->size; 2645 2646 entry = mbox_cmd_log_entry(log, entry_idx); 2647 /* skip over unused entries */ 2648 if (entry->timestamp == 0) 2649 continue; 2650 2651 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd)); 2652 for (i = 0; i < MBOX_LEN / 8; i++) { 2653 flit = entry->cmd[i]; 2654 mboxlog->hi[i] = (u32)(flit >> 32); 2655 mboxlog->lo[i] = (u32)flit; 2656 } 2657 mboxlog++; 2658 } 2659 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2660 } 2661 2662 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init, 2663 struct cudbg_buffer *dbg_buff, 2664 struct cudbg_error *cudbg_err) 2665 { 2666 struct adapter *padap = pdbg_init->adap; 2667 struct cudbg_buffer temp_buff = { 0 }; 2668 struct ireg_buf *hma_indr; 2669 int i, rc, n; 2670 u32 size; 2671 2672 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) 2673 return CUDBG_STATUS_ENTITY_NOT_FOUND; 2674 2675 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); 2676 size = sizeof(struct ireg_buf) * n; 2677 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff); 2678 if (rc) 2679 return rc; 2680 2681 hma_indr = (struct ireg_buf *)temp_buff.data; 2682 for (i = 0; i < n; i++) { 2683 struct ireg_field *hma_fli = &hma_indr->tp_pio; 2684 u32 *buff = hma_indr->outbuf; 2685 2686 hma_fli->ireg_addr = t6_hma_ireg_array[i][0]; 2687 hma_fli->ireg_data = t6_hma_ireg_array[i][1]; 2688 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2]; 2689 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3]; 2690 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data, 2691 buff, hma_fli->ireg_offset_range, 2692 hma_fli->ireg_local_offset); 2693 hma_indr++; 2694 } 2695 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff); 2696 } 2697