1 /* 2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __CHELSIO_COMMON_H 33 #define __CHELSIO_COMMON_H 34 35 #include <linux/kernel.h> 36 #include <linux/types.h> 37 #include <linux/ctype.h> 38 #include <linux/delay.h> 39 #include <linux/init.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mdio.h> 43 #include "version.h" 44 45 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ##__VA_ARGS__) 46 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ##__VA_ARGS__) 47 #define CH_ALERT(adap, fmt, ...) dev_alert(&adap->pdev->dev, fmt, ##__VA_ARGS__) 48 49 /* 50 * More powerful macro that selectively prints messages based on msg_enable. 51 * For info and debugging messages. 52 */ 53 #define CH_MSG(adapter, level, category, fmt, ...) do { \ 54 if ((adapter)->msg_enable & NETIF_MSG_##category) \ 55 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ 56 ## __VA_ARGS__); \ 57 } while (0) 58 59 #ifdef DEBUG 60 # define CH_DBG(adapter, category, fmt, ...) \ 61 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) 62 #else 63 # define CH_DBG(adapter, category, fmt, ...) 64 #endif 65 66 /* Additional NETIF_MSG_* categories */ 67 #define NETIF_MSG_MMIO 0x8000000 68 69 enum { 70 MAX_NPORTS = 2, /* max # of ports */ 71 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ 72 EEPROMSIZE = 8192, /* Serial EEPROM size */ 73 SERNUM_LEN = 16, /* Serial # length */ 74 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 75 TCB_SIZE = 128, /* TCB size */ 76 NMTUS = 16, /* size of MTU table */ 77 NCCTRL_WIN = 32, /* # of congestion control windows */ 78 PROTO_SRAM_LINES = 128, /* size of TP sram */ 79 }; 80 81 #define MAX_RX_COALESCING_LEN 12288U 82 83 enum { 84 PAUSE_RX = 1 << 0, 85 PAUSE_TX = 1 << 1, 86 PAUSE_AUTONEG = 1 << 2 87 }; 88 89 enum { 90 SUPPORTED_IRQ = 1 << 24 91 }; 92 93 enum { /* adapter interrupt-maintained statistics */ 94 STAT_ULP_CH0_PBL_OOB, 95 STAT_ULP_CH1_PBL_OOB, 96 STAT_PCI_CORR_ECC, 97 98 IRQ_NUM_STATS /* keep last */ 99 }; 100 101 #define TP_VERSION_MAJOR 1 102 #define TP_VERSION_MINOR 1 103 #define TP_VERSION_MICRO 0 104 105 #define S_TP_VERSION_MAJOR 16 106 #define M_TP_VERSION_MAJOR 0xFF 107 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 108 #define G_TP_VERSION_MAJOR(x) \ 109 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 110 111 #define S_TP_VERSION_MINOR 8 112 #define M_TP_VERSION_MINOR 0xFF 113 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 114 #define G_TP_VERSION_MINOR(x) \ 115 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 116 117 #define S_TP_VERSION_MICRO 0 118 #define M_TP_VERSION_MICRO 0xFF 119 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 120 #define G_TP_VERSION_MICRO(x) \ 121 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 122 123 enum { 124 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 125 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 126 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 127 }; 128 129 enum sge_context_type { /* SGE egress context types */ 130 SGE_CNTXT_RDMA = 0, 131 SGE_CNTXT_ETH = 2, 132 SGE_CNTXT_OFLD = 4, 133 SGE_CNTXT_CTRL = 5 134 }; 135 136 enum { 137 AN_PKT_SIZE = 32, /* async notification packet size */ 138 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 139 }; 140 141 struct sg_ent { /* SGE scatter/gather entry */ 142 __be32 len[2]; 143 __be64 addr[2]; 144 }; 145 146 #ifndef SGE_NUM_GENBITS 147 /* Must be 1 or 2 */ 148 # define SGE_NUM_GENBITS 2 149 #endif 150 151 #define TX_DESC_FLITS 16U 152 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 153 154 struct cphy; 155 struct adapter; 156 157 struct mdio_ops { 158 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr, 159 u16 reg_addr); 160 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr, 161 u16 reg_addr, u16 val); 162 unsigned mode_support; 163 }; 164 165 struct adapter_info { 166 unsigned char nports0; /* # of ports on channel 0 */ 167 unsigned char nports1; /* # of ports on channel 1 */ 168 unsigned char phy_base_addr; /* MDIO PHY base address */ 169 unsigned int gpio_out; /* GPIO output settings */ 170 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ 171 unsigned long caps; /* adapter capabilities */ 172 const struct mdio_ops *mdio_ops; /* MDIO operations */ 173 const char *desc; /* product description */ 174 }; 175 176 struct mc5_stats { 177 unsigned long parity_err; 178 unsigned long active_rgn_full; 179 unsigned long nfa_srch_err; 180 unsigned long unknown_cmd; 181 unsigned long reqq_parity_err; 182 unsigned long dispq_parity_err; 183 unsigned long del_act_empty; 184 }; 185 186 struct mc7_stats { 187 unsigned long corr_err; 188 unsigned long uncorr_err; 189 unsigned long parity_err; 190 unsigned long addr_err; 191 }; 192 193 struct mac_stats { 194 u64 tx_octets; /* total # of octets in good frames */ 195 u64 tx_octets_bad; /* total # of octets in error frames */ 196 u64 tx_frames; /* all good frames */ 197 u64 tx_mcast_frames; /* good multicast frames */ 198 u64 tx_bcast_frames; /* good broadcast frames */ 199 u64 tx_pause; /* # of transmitted pause frames */ 200 u64 tx_deferred; /* frames with deferred transmissions */ 201 u64 tx_late_collisions; /* # of late collisions */ 202 u64 tx_total_collisions; /* # of total collisions */ 203 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 204 u64 tx_underrun; /* # of Tx FIFO underruns */ 205 u64 tx_len_errs; /* # of Tx length errors */ 206 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 207 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 208 u64 tx_fcs_errs; /* # of frames with bad FCS */ 209 210 u64 tx_frames_64; /* # of Tx frames in a particular range */ 211 u64 tx_frames_65_127; 212 u64 tx_frames_128_255; 213 u64 tx_frames_256_511; 214 u64 tx_frames_512_1023; 215 u64 tx_frames_1024_1518; 216 u64 tx_frames_1519_max; 217 218 u64 rx_octets; /* total # of octets in good frames */ 219 u64 rx_octets_bad; /* total # of octets in error frames */ 220 u64 rx_frames; /* all good frames */ 221 u64 rx_mcast_frames; /* good multicast frames */ 222 u64 rx_bcast_frames; /* good broadcast frames */ 223 u64 rx_pause; /* # of received pause frames */ 224 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 225 u64 rx_align_errs; /* alignment errors */ 226 u64 rx_symbol_errs; /* symbol errors */ 227 u64 rx_data_errs; /* data errors */ 228 u64 rx_sequence_errs; /* sequence errors */ 229 u64 rx_runt; /* # of runt frames */ 230 u64 rx_jabber; /* # of jabber frames */ 231 u64 rx_short; /* # of short frames */ 232 u64 rx_too_long; /* # of oversized frames */ 233 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 234 235 u64 rx_frames_64; /* # of Rx frames in a particular range */ 236 u64 rx_frames_65_127; 237 u64 rx_frames_128_255; 238 u64 rx_frames_256_511; 239 u64 rx_frames_512_1023; 240 u64 rx_frames_1024_1518; 241 u64 rx_frames_1519_max; 242 243 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 244 245 unsigned long tx_fifo_parity_err; 246 unsigned long rx_fifo_parity_err; 247 unsigned long tx_fifo_urun; 248 unsigned long rx_fifo_ovfl; 249 unsigned long serdes_signal_loss; 250 unsigned long xaui_pcs_ctc_err; 251 unsigned long xaui_pcs_align_change; 252 253 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 254 unsigned long num_resets; /* # times reset due to stuck TX */ 255 256 unsigned long link_faults; /* # detected link faults */ 257 }; 258 259 struct tp_mib_stats { 260 u32 ipInReceive_hi; 261 u32 ipInReceive_lo; 262 u32 ipInHdrErrors_hi; 263 u32 ipInHdrErrors_lo; 264 u32 ipInAddrErrors_hi; 265 u32 ipInAddrErrors_lo; 266 u32 ipInUnknownProtos_hi; 267 u32 ipInUnknownProtos_lo; 268 u32 ipInDiscards_hi; 269 u32 ipInDiscards_lo; 270 u32 ipInDelivers_hi; 271 u32 ipInDelivers_lo; 272 u32 ipOutRequests_hi; 273 u32 ipOutRequests_lo; 274 u32 ipOutDiscards_hi; 275 u32 ipOutDiscards_lo; 276 u32 ipOutNoRoutes_hi; 277 u32 ipOutNoRoutes_lo; 278 u32 ipReasmTimeout; 279 u32 ipReasmReqds; 280 u32 ipReasmOKs; 281 u32 ipReasmFails; 282 283 u32 reserved[8]; 284 285 u32 tcpActiveOpens; 286 u32 tcpPassiveOpens; 287 u32 tcpAttemptFails; 288 u32 tcpEstabResets; 289 u32 tcpOutRsts; 290 u32 tcpCurrEstab; 291 u32 tcpInSegs_hi; 292 u32 tcpInSegs_lo; 293 u32 tcpOutSegs_hi; 294 u32 tcpOutSegs_lo; 295 u32 tcpRetransSeg_hi; 296 u32 tcpRetransSeg_lo; 297 u32 tcpInErrs_hi; 298 u32 tcpInErrs_lo; 299 u32 tcpRtoMin; 300 u32 tcpRtoMax; 301 }; 302 303 struct tp_params { 304 unsigned int nchan; /* # of channels */ 305 unsigned int pmrx_size; /* total PMRX capacity */ 306 unsigned int pmtx_size; /* total PMTX capacity */ 307 unsigned int cm_size; /* total CM capacity */ 308 unsigned int chan_rx_size; /* per channel Rx size */ 309 unsigned int chan_tx_size; /* per channel Tx size */ 310 unsigned int rx_pg_size; /* Rx page size */ 311 unsigned int tx_pg_size; /* Tx page size */ 312 unsigned int rx_num_pgs; /* # of Rx pages */ 313 unsigned int tx_num_pgs; /* # of Tx pages */ 314 unsigned int ntimer_qs; /* # of timer queues */ 315 }; 316 317 struct qset_params { /* SGE queue set parameters */ 318 unsigned int polling; /* polling/interrupt service for rspq */ 319 unsigned int coalesce_usecs; /* irq coalescing timer */ 320 unsigned int rspq_size; /* # of entries in response queue */ 321 unsigned int fl_size; /* # of entries in regular free list */ 322 unsigned int jumbo_size; /* # of entries in jumbo free list */ 323 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 324 unsigned int cong_thres; /* FL congestion threshold */ 325 unsigned int vector; /* Interrupt (line or vector) number */ 326 }; 327 328 struct sge_params { 329 unsigned int max_pkt_size; /* max offload pkt size */ 330 struct qset_params qset[SGE_QSETS]; 331 }; 332 333 struct mc5_params { 334 unsigned int mode; /* selects MC5 width */ 335 unsigned int nservers; /* size of server region */ 336 unsigned int nfilters; /* size of filter region */ 337 unsigned int nroutes; /* size of routing region */ 338 }; 339 340 /* Default MC5 region sizes */ 341 enum { 342 DEFAULT_NSERVERS = 512, 343 DEFAULT_NFILTERS = 128 344 }; 345 346 /* MC5 modes, these must be non-0 */ 347 enum { 348 MC5_MODE_144_BIT = 1, 349 MC5_MODE_72_BIT = 2 350 }; 351 352 /* MC5 min active region size */ 353 enum { MC5_MIN_TIDS = 16 }; 354 355 struct vpd_params { 356 unsigned int cclk; 357 unsigned int mclk; 358 unsigned int uclk; 359 unsigned int mdc; 360 unsigned int mem_timing; 361 u8 sn[SERNUM_LEN + 1]; 362 u8 eth_base[6]; 363 u8 port_type[MAX_NPORTS]; 364 unsigned short xauicfg[2]; 365 }; 366 367 struct pci_params { 368 unsigned int vpd_cap_addr; 369 unsigned short speed; 370 unsigned char width; 371 unsigned char variant; 372 }; 373 374 enum { 375 PCI_VARIANT_PCI, 376 PCI_VARIANT_PCIX_MODE1_PARITY, 377 PCI_VARIANT_PCIX_MODE1_ECC, 378 PCI_VARIANT_PCIX_266_MODE2, 379 PCI_VARIANT_PCIE 380 }; 381 382 struct adapter_params { 383 struct sge_params sge; 384 struct mc5_params mc5; 385 struct tp_params tp; 386 struct vpd_params vpd; 387 struct pci_params pci; 388 389 const struct adapter_info *info; 390 391 unsigned short mtus[NMTUS]; 392 unsigned short a_wnd[NCCTRL_WIN]; 393 unsigned short b_wnd[NCCTRL_WIN]; 394 395 unsigned int nports; /* # of ethernet ports */ 396 unsigned int chan_map; /* bitmap of in-use Tx channels */ 397 unsigned int stats_update_period; /* MAC stats accumulation period */ 398 unsigned int linkpoll_period; /* link poll period in 0.1s */ 399 unsigned int rev; /* chip revision */ 400 unsigned int offload; 401 }; 402 403 enum { /* chip revisions */ 404 T3_REV_A = 0, 405 T3_REV_B = 2, 406 T3_REV_B2 = 3, 407 T3_REV_C = 4, 408 }; 409 410 struct trace_params { 411 u32 sip; 412 u32 sip_mask; 413 u32 dip; 414 u32 dip_mask; 415 u16 sport; 416 u16 sport_mask; 417 u16 dport; 418 u16 dport_mask; 419 u32 vlan:12; 420 u32 vlan_mask:12; 421 u32 intf:4; 422 u32 intf_mask:4; 423 u8 proto; 424 u8 proto_mask; 425 }; 426 427 struct link_config { 428 unsigned int supported; /* link capabilities */ 429 unsigned int advertising; /* advertised capabilities */ 430 unsigned short requested_speed; /* speed user has requested */ 431 unsigned short speed; /* actual link speed */ 432 unsigned char requested_duplex; /* duplex user has requested */ 433 unsigned char duplex; /* actual link duplex */ 434 unsigned char requested_fc; /* flow control user has requested */ 435 unsigned char fc; /* actual link flow control */ 436 unsigned char autoneg; /* autonegotiating? */ 437 unsigned int link_ok; /* link up? */ 438 }; 439 440 #define SPEED_INVALID 0xffff 441 #define DUPLEX_INVALID 0xff 442 443 struct mc5 { 444 struct adapter *adapter; 445 unsigned int tcam_size; 446 unsigned char part_type; 447 unsigned char parity_enabled; 448 unsigned char mode; 449 struct mc5_stats stats; 450 }; 451 452 static inline unsigned int t3_mc5_size(const struct mc5 *p) 453 { 454 return p->tcam_size; 455 } 456 457 struct mc7 { 458 struct adapter *adapter; /* backpointer to adapter */ 459 unsigned int size; /* memory size in bytes */ 460 unsigned int width; /* MC7 interface width */ 461 unsigned int offset; /* register address offset for MC7 instance */ 462 const char *name; /* name of MC7 instance */ 463 struct mc7_stats stats; /* MC7 statistics */ 464 }; 465 466 static inline unsigned int t3_mc7_size(const struct mc7 *p) 467 { 468 return p->size; 469 } 470 471 struct cmac { 472 struct adapter *adapter; 473 unsigned int offset; 474 unsigned int nucast; /* # of address filters for unicast MACs */ 475 unsigned int tx_tcnt; 476 unsigned int tx_xcnt; 477 u64 tx_mcnt; 478 unsigned int rx_xcnt; 479 unsigned int rx_ocnt; 480 u64 rx_mcnt; 481 unsigned int toggle_cnt; 482 unsigned int txen; 483 u64 rx_pause; 484 struct mac_stats stats; 485 }; 486 487 enum { 488 MAC_DIRECTION_RX = 1, 489 MAC_DIRECTION_TX = 2, 490 MAC_RXFIFO_SIZE = 32768 491 }; 492 493 /* PHY loopback direction */ 494 enum { 495 PHY_LOOPBACK_TX = 1, 496 PHY_LOOPBACK_RX = 2 497 }; 498 499 /* PHY interrupt types */ 500 enum { 501 cphy_cause_link_change = 1, 502 cphy_cause_fifo_error = 2, 503 cphy_cause_module_change = 4, 504 }; 505 506 /* PHY module types */ 507 enum { 508 phy_modtype_none, 509 phy_modtype_sr, 510 phy_modtype_lr, 511 phy_modtype_lrm, 512 phy_modtype_twinax, 513 phy_modtype_twinax_long, 514 phy_modtype_unknown 515 }; 516 517 /* PHY operations */ 518 struct cphy_ops { 519 int (*reset)(struct cphy *phy, int wait); 520 521 int (*intr_enable)(struct cphy *phy); 522 int (*intr_disable)(struct cphy *phy); 523 int (*intr_clear)(struct cphy *phy); 524 int (*intr_handler)(struct cphy *phy); 525 526 int (*autoneg_enable)(struct cphy *phy); 527 int (*autoneg_restart)(struct cphy *phy); 528 529 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 530 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 531 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 532 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 533 int *duplex, int *fc); 534 int (*power_down)(struct cphy *phy, int enable); 535 536 u32 mmds; 537 }; 538 enum { 539 EDC_OPT_AEL2005 = 0, 540 EDC_OPT_AEL2005_SIZE = 1084, 541 EDC_TWX_AEL2005 = 1, 542 EDC_TWX_AEL2005_SIZE = 1464, 543 EDC_TWX_AEL2020 = 2, 544 EDC_TWX_AEL2020_SIZE = 1628, 545 EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */ 546 }; 547 548 /* A PHY instance */ 549 struct cphy { 550 u8 modtype; /* PHY module type */ 551 short priv; /* scratch pad */ 552 unsigned int caps; /* PHY capabilities */ 553 struct adapter *adapter; /* associated adapter */ 554 const char *desc; /* PHY description */ 555 unsigned long fifo_errors; /* FIFO over/under-flows */ 556 const struct cphy_ops *ops; /* PHY operations */ 557 struct mdio_if_info mdio; 558 u16 phy_cache[EDC_MAX_SIZE]; /* EDC cache */ 559 }; 560 561 /* Convenience MDIO read/write wrappers */ 562 static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg, 563 unsigned int *valp) 564 { 565 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg); 566 *valp = (rc >= 0) ? rc : -1; 567 return (rc >= 0) ? 0 : rc; 568 } 569 570 static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg, 571 unsigned int val) 572 { 573 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd, 574 reg, val); 575 } 576 577 /* Convenience initializer */ 578 static inline void cphy_init(struct cphy *phy, struct adapter *adapter, 579 int phy_addr, struct cphy_ops *phy_ops, 580 const struct mdio_ops *mdio_ops, 581 unsigned int caps, const char *desc) 582 { 583 phy->caps = caps; 584 phy->adapter = adapter; 585 phy->desc = desc; 586 phy->ops = phy_ops; 587 if (mdio_ops) { 588 phy->mdio.prtad = phy_addr; 589 phy->mdio.mmds = phy_ops->mmds; 590 phy->mdio.mode_support = mdio_ops->mode_support; 591 phy->mdio.mdio_read = mdio_ops->read; 592 phy->mdio.mdio_write = mdio_ops->write; 593 } 594 } 595 596 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 597 #define MAC_STATS_ACCUM_SECS 180 598 599 #define XGM_REG(reg_addr, idx) \ 600 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 601 602 struct addr_val_pair { 603 unsigned int reg_addr; 604 unsigned int val; 605 }; 606 607 #include "adapter.h" 608 609 #ifndef PCI_VENDOR_ID_CHELSIO 610 # define PCI_VENDOR_ID_CHELSIO 0x1425 611 #endif 612 613 #define for_each_port(adapter, iter) \ 614 for (iter = 0; iter < (adapter)->params.nports; ++iter) 615 616 #define adapter_info(adap) ((adap)->params.info) 617 618 static inline int uses_xaui(const struct adapter *adap) 619 { 620 return adapter_info(adap)->caps & SUPPORTED_AUI; 621 } 622 623 static inline int is_10G(const struct adapter *adap) 624 { 625 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 626 } 627 628 static inline int is_offload(const struct adapter *adap) 629 { 630 return adap->params.offload; 631 } 632 633 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 634 { 635 return adap->params.vpd.cclk / 1000; 636 } 637 638 static inline unsigned int is_pcie(const struct adapter *adap) 639 { 640 return adap->params.pci.variant == PCI_VARIANT_PCIE; 641 } 642 643 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 644 u32 val); 645 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, 646 int n, unsigned int offset); 647 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 648 int polarity, int attempts, int delay, u32 *valp); 649 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, 650 int polarity, int attempts, int delay) 651 { 652 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 653 delay, NULL); 654 } 655 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 656 unsigned int set); 657 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 658 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 659 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 660 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 661 int t3_phy_lasi_intr_enable(struct cphy *phy); 662 int t3_phy_lasi_intr_disable(struct cphy *phy); 663 int t3_phy_lasi_intr_clear(struct cphy *phy); 664 int t3_phy_lasi_intr_handler(struct cphy *phy); 665 666 void t3_intr_enable(struct adapter *adapter); 667 void t3_intr_disable(struct adapter *adapter); 668 void t3_intr_clear(struct adapter *adapter); 669 void t3_xgm_intr_enable(struct adapter *adapter, int idx); 670 void t3_xgm_intr_disable(struct adapter *adapter, int idx); 671 void t3_port_intr_enable(struct adapter *adapter, int idx); 672 void t3_port_intr_disable(struct adapter *adapter, int idx); 673 int t3_slow_intr_handler(struct adapter *adapter); 674 int t3_phy_intr_handler(struct adapter *adapter); 675 676 void t3_link_changed(struct adapter *adapter, int port_id); 677 void t3_link_fault(struct adapter *adapter, int port_id); 678 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 679 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 680 int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data); 681 int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data); 682 int t3_seeprom_wp(struct adapter *adapter, int enable); 683 int t3_get_tp_version(struct adapter *adapter, u32 *vers); 684 int t3_check_tpsram_version(struct adapter *adapter); 685 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram, 686 unsigned int size); 687 int t3_set_proto_sram(struct adapter *adap, const u8 *data); 688 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); 689 int t3_get_fw_version(struct adapter *adapter, u32 *vers); 690 int t3_check_fw_version(struct adapter *adapter); 691 int t3_init_hw(struct adapter *adapter, u32 fw_params); 692 int t3_reset_adapter(struct adapter *adapter); 693 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, 694 int reset); 695 int t3_replay_prep_adapter(struct adapter *adapter); 696 void t3_led_ready(struct adapter *adapter); 697 void t3_fatal_err(struct adapter *adapter); 698 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on); 699 void t3_config_rss(struct adapter *adapter, unsigned int rss_config, 700 const u8 * cpus, const u16 *rspq); 701 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, 702 unsigned int n, unsigned int *valp); 703 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 704 u64 *buf); 705 706 int t3_mac_reset(struct cmac *mac); 707 void t3b_pcs_reset(struct cmac *mac); 708 void t3_mac_disable_exact_filters(struct cmac *mac); 709 void t3_mac_enable_exact_filters(struct cmac *mac); 710 int t3_mac_enable(struct cmac *mac, int which); 711 int t3_mac_disable(struct cmac *mac, int which); 712 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 713 int t3_mac_set_rx_mode(struct cmac *mac, struct net_device *dev); 714 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 715 int t3_mac_set_num_ucast(struct cmac *mac, int n); 716 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 717 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); 718 int t3b2_mac_watchdog_task(struct cmac *mac); 719 720 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); 721 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 722 unsigned int nroutes); 723 void t3_mc5_intr_handler(struct mc5 *mc5); 724 725 void t3_tp_set_offload_mode(struct adapter *adap, int enable); 726 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps); 727 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], 728 unsigned short alpha[NCCTRL_WIN], 729 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 730 void t3_config_trace_filter(struct adapter *adapter, 731 const struct trace_params *tp, int filter_index, 732 int invert, int enable); 733 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched); 734 735 void t3_sge_prep(struct adapter *adap, struct sge_params *p); 736 void t3_sge_init(struct adapter *adap, struct sge_params *p); 737 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, 738 enum sge_context_type type, int respq, u64 base_addr, 739 unsigned int size, unsigned int token, int gen, 740 unsigned int cidx); 741 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, 742 int gts_enable, u64 base_addr, unsigned int size, 743 unsigned int esize, unsigned int cong_thres, int gen, 744 unsigned int cidx); 745 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, 746 int irq_vec_idx, u64 base_addr, unsigned int size, 747 unsigned int fl_thres, int gen, unsigned int cidx); 748 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, 749 unsigned int size, int rspq, int ovfl_mode, 750 unsigned int credits, unsigned int credit_thres); 751 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable); 752 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id); 753 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id); 754 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id); 755 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, 756 unsigned int credits); 757 758 int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, 759 int phy_addr, const struct mdio_ops *mdio_ops); 760 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, 761 int phy_addr, const struct mdio_ops *mdio_ops); 762 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, 763 int phy_addr, const struct mdio_ops *mdio_ops); 764 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, 765 int phy_addr, const struct mdio_ops *mdio_ops); 766 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, 767 int phy_addr, const struct mdio_ops *mdio_ops); 768 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, 769 const struct mdio_ops *mdio_ops); 770 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, 771 int phy_addr, const struct mdio_ops *mdio_ops); 772 int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter, 773 int phy_addr, const struct mdio_ops *mdio_ops); 774 #endif /* __CHELSIO_COMMON_H */ 775