1f7917c00SJeff Kirsher /*
2f7917c00SJeff Kirsher * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
3f7917c00SJeff Kirsher *
4f7917c00SJeff Kirsher * This software is available to you under a choice of one of two
5f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU
6f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file
7f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the
8f7917c00SJeff Kirsher * OpenIB.org BSD license below:
9f7917c00SJeff Kirsher *
10f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or
11f7917c00SJeff Kirsher * without modification, are permitted provided that the following
12f7917c00SJeff Kirsher * conditions are met:
13f7917c00SJeff Kirsher *
14f7917c00SJeff Kirsher * - Redistributions of source code must retain the above
15f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following
16f7917c00SJeff Kirsher * disclaimer.
17f7917c00SJeff Kirsher *
18f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above
19f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following
20f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials
21f7917c00SJeff Kirsher * provided with the distribution.
22f7917c00SJeff Kirsher *
23f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30f7917c00SJeff Kirsher * SOFTWARE.
31f7917c00SJeff Kirsher */
32f7917c00SJeff Kirsher
33f7917c00SJeff Kirsher #include "common.h"
34f7917c00SJeff Kirsher #include "regs.h"
35f7917c00SJeff Kirsher
36f7917c00SJeff Kirsher enum {
37f7917c00SJeff Kirsher /* MDIO_DEV_PMA_PMD registers */
38f7917c00SJeff Kirsher AQ_LINK_STAT = 0xe800,
39f7917c00SJeff Kirsher AQ_IMASK_PMA = 0xf000,
40f7917c00SJeff Kirsher
41f7917c00SJeff Kirsher /* MDIO_DEV_XGXS registers */
42f7917c00SJeff Kirsher AQ_XAUI_RX_CFG = 0xc400,
43f7917c00SJeff Kirsher AQ_XAUI_TX_CFG = 0xe400,
44f7917c00SJeff Kirsher
45f7917c00SJeff Kirsher /* MDIO_DEV_ANEG registers */
46f7917c00SJeff Kirsher AQ_1G_CTRL = 0xc400,
47f7917c00SJeff Kirsher AQ_ANEG_STAT = 0xc800,
48f7917c00SJeff Kirsher
49f7917c00SJeff Kirsher /* MDIO_DEV_VEND1 registers */
50f7917c00SJeff Kirsher AQ_FW_VERSION = 0x0020,
51f7917c00SJeff Kirsher AQ_IFLAG_GLOBAL = 0xfc00,
52f7917c00SJeff Kirsher AQ_IMASK_GLOBAL = 0xff00,
53f7917c00SJeff Kirsher };
54f7917c00SJeff Kirsher
55f7917c00SJeff Kirsher enum {
56f7917c00SJeff Kirsher IMASK_PMA = 1 << 2,
57f7917c00SJeff Kirsher IMASK_GLOBAL = 1 << 15,
58f7917c00SJeff Kirsher ADV_1G_FULL = 1 << 15,
59f7917c00SJeff Kirsher ADV_1G_HALF = 1 << 14,
60f7917c00SJeff Kirsher ADV_10G_FULL = 1 << 12,
61f7917c00SJeff Kirsher AQ_RESET = (1 << 14) | (1 << 15),
62f7917c00SJeff Kirsher AQ_LOWPOWER = 1 << 12,
63f7917c00SJeff Kirsher };
64f7917c00SJeff Kirsher
aq100x_reset(struct cphy * phy,int wait)65f7917c00SJeff Kirsher static int aq100x_reset(struct cphy *phy, int wait)
66f7917c00SJeff Kirsher {
67f7917c00SJeff Kirsher /*
68f7917c00SJeff Kirsher * Ignore the caller specified wait time; always wait for the reset to
69f7917c00SJeff Kirsher * complete. Can take up to 3s.
70f7917c00SJeff Kirsher */
71f7917c00SJeff Kirsher int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000);
72f7917c00SJeff Kirsher
73f7917c00SJeff Kirsher if (err)
74f7917c00SJeff Kirsher CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n",
75f7917c00SJeff Kirsher phy->mdio.prtad, err);
76f7917c00SJeff Kirsher
77f7917c00SJeff Kirsher return err;
78f7917c00SJeff Kirsher }
79f7917c00SJeff Kirsher
aq100x_intr_enable(struct cphy * phy)80f7917c00SJeff Kirsher static int aq100x_intr_enable(struct cphy *phy)
81f7917c00SJeff Kirsher {
82f7917c00SJeff Kirsher int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AQ_IMASK_PMA, IMASK_PMA);
83f7917c00SJeff Kirsher if (err)
84f7917c00SJeff Kirsher return err;
85f7917c00SJeff Kirsher
86f7917c00SJeff Kirsher err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL);
87f7917c00SJeff Kirsher return err;
88f7917c00SJeff Kirsher }
89f7917c00SJeff Kirsher
aq100x_intr_disable(struct cphy * phy)90f7917c00SJeff Kirsher static int aq100x_intr_disable(struct cphy *phy)
91f7917c00SJeff Kirsher {
92f7917c00SJeff Kirsher return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0);
93f7917c00SJeff Kirsher }
94f7917c00SJeff Kirsher
aq100x_intr_clear(struct cphy * phy)95f7917c00SJeff Kirsher static int aq100x_intr_clear(struct cphy *phy)
96f7917c00SJeff Kirsher {
97f7917c00SJeff Kirsher unsigned int v;
98f7917c00SJeff Kirsher
99f7917c00SJeff Kirsher t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v);
100f7917c00SJeff Kirsher t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v);
101f7917c00SJeff Kirsher
102f7917c00SJeff Kirsher return 0;
103f7917c00SJeff Kirsher }
104f7917c00SJeff Kirsher
aq100x_intr_handler(struct cphy * phy)105f7917c00SJeff Kirsher static int aq100x_intr_handler(struct cphy *phy)
106f7917c00SJeff Kirsher {
107f7917c00SJeff Kirsher int err;
108f7917c00SJeff Kirsher unsigned int cause, v;
109f7917c00SJeff Kirsher
110f7917c00SJeff Kirsher err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause);
111f7917c00SJeff Kirsher if (err)
112f7917c00SJeff Kirsher return err;
113f7917c00SJeff Kirsher
114f7917c00SJeff Kirsher /* Read (and reset) the latching version of the status */
115f7917c00SJeff Kirsher t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v);
116f7917c00SJeff Kirsher
117f7917c00SJeff Kirsher return cphy_cause_link_change;
118f7917c00SJeff Kirsher }
119f7917c00SJeff Kirsher
aq100x_power_down(struct cphy * phy,int off)120f7917c00SJeff Kirsher static int aq100x_power_down(struct cphy *phy, int off)
121f7917c00SJeff Kirsher {
122f7917c00SJeff Kirsher return mdio_set_flag(&phy->mdio, phy->mdio.prtad,
123f7917c00SJeff Kirsher MDIO_MMD_PMAPMD, MDIO_CTRL1,
124f7917c00SJeff Kirsher MDIO_CTRL1_LPOWER, off);
125f7917c00SJeff Kirsher }
126f7917c00SJeff Kirsher
aq100x_autoneg_enable(struct cphy * phy)127f7917c00SJeff Kirsher static int aq100x_autoneg_enable(struct cphy *phy)
128f7917c00SJeff Kirsher {
129f7917c00SJeff Kirsher int err;
130f7917c00SJeff Kirsher
131f7917c00SJeff Kirsher err = aq100x_power_down(phy, 0);
132f7917c00SJeff Kirsher if (!err)
133f7917c00SJeff Kirsher err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
134f7917c00SJeff Kirsher MDIO_MMD_AN, MDIO_CTRL1,
135f7917c00SJeff Kirsher BMCR_ANENABLE | BMCR_ANRESTART, 1);
136f7917c00SJeff Kirsher
137f7917c00SJeff Kirsher return err;
138f7917c00SJeff Kirsher }
139f7917c00SJeff Kirsher
aq100x_autoneg_restart(struct cphy * phy)140f7917c00SJeff Kirsher static int aq100x_autoneg_restart(struct cphy *phy)
141f7917c00SJeff Kirsher {
142f7917c00SJeff Kirsher int err;
143f7917c00SJeff Kirsher
144f7917c00SJeff Kirsher err = aq100x_power_down(phy, 0);
145f7917c00SJeff Kirsher if (!err)
146f7917c00SJeff Kirsher err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
147f7917c00SJeff Kirsher MDIO_MMD_AN, MDIO_CTRL1,
148f7917c00SJeff Kirsher BMCR_ANENABLE | BMCR_ANRESTART, 1);
149f7917c00SJeff Kirsher
150f7917c00SJeff Kirsher return err;
151f7917c00SJeff Kirsher }
152f7917c00SJeff Kirsher
aq100x_advertise(struct cphy * phy,unsigned int advertise_map)153f7917c00SJeff Kirsher static int aq100x_advertise(struct cphy *phy, unsigned int advertise_map)
154f7917c00SJeff Kirsher {
155f7917c00SJeff Kirsher unsigned int adv;
156f7917c00SJeff Kirsher int err;
157f7917c00SJeff Kirsher
158f7917c00SJeff Kirsher /* 10G advertisement */
159f7917c00SJeff Kirsher adv = 0;
160f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_10000baseT_Full)
161f7917c00SJeff Kirsher adv |= ADV_10G_FULL;
162f7917c00SJeff Kirsher err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
163f7917c00SJeff Kirsher ADV_10G_FULL, adv);
164f7917c00SJeff Kirsher if (err)
165f7917c00SJeff Kirsher return err;
166f7917c00SJeff Kirsher
167f7917c00SJeff Kirsher /* 1G advertisement */
168f7917c00SJeff Kirsher adv = 0;
169f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_1000baseT_Full)
170f7917c00SJeff Kirsher adv |= ADV_1G_FULL;
171f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_1000baseT_Half)
172f7917c00SJeff Kirsher adv |= ADV_1G_HALF;
173f7917c00SJeff Kirsher err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL,
174f7917c00SJeff Kirsher ADV_1G_FULL | ADV_1G_HALF, adv);
175f7917c00SJeff Kirsher if (err)
176f7917c00SJeff Kirsher return err;
177f7917c00SJeff Kirsher
178f7917c00SJeff Kirsher /* 100M, pause advertisement */
179f7917c00SJeff Kirsher adv = 0;
180f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_100baseT_Half)
181f7917c00SJeff Kirsher adv |= ADVERTISE_100HALF;
182f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_100baseT_Full)
183f7917c00SJeff Kirsher adv |= ADVERTISE_100FULL;
184f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_Pause)
185f7917c00SJeff Kirsher adv |= ADVERTISE_PAUSE_CAP;
186f7917c00SJeff Kirsher if (advertise_map & ADVERTISED_Asym_Pause)
187f7917c00SJeff Kirsher adv |= ADVERTISE_PAUSE_ASYM;
188f7917c00SJeff Kirsher err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
189f7917c00SJeff Kirsher 0xfe0, adv);
190f7917c00SJeff Kirsher
191f7917c00SJeff Kirsher return err;
192f7917c00SJeff Kirsher }
193f7917c00SJeff Kirsher
aq100x_set_loopback(struct cphy * phy,int mmd,int dir,int enable)194f7917c00SJeff Kirsher static int aq100x_set_loopback(struct cphy *phy, int mmd, int dir, int enable)
195f7917c00SJeff Kirsher {
196f7917c00SJeff Kirsher return mdio_set_flag(&phy->mdio, phy->mdio.prtad,
197f7917c00SJeff Kirsher MDIO_MMD_PMAPMD, MDIO_CTRL1,
198f7917c00SJeff Kirsher BMCR_LOOPBACK, enable);
199f7917c00SJeff Kirsher }
200f7917c00SJeff Kirsher
aq100x_set_speed_duplex(struct cphy * phy,int speed,int duplex)201f7917c00SJeff Kirsher static int aq100x_set_speed_duplex(struct cphy *phy, int speed, int duplex)
202f7917c00SJeff Kirsher {
203f7917c00SJeff Kirsher /* no can do */
204f7917c00SJeff Kirsher return -1;
205f7917c00SJeff Kirsher }
206f7917c00SJeff Kirsher
aq100x_get_link_status(struct cphy * phy,int * link_ok,int * speed,int * duplex,int * fc)207f7917c00SJeff Kirsher static int aq100x_get_link_status(struct cphy *phy, int *link_ok,
208f7917c00SJeff Kirsher int *speed, int *duplex, int *fc)
209f7917c00SJeff Kirsher {
210f7917c00SJeff Kirsher int err;
211f7917c00SJeff Kirsher unsigned int v;
212f7917c00SJeff Kirsher
213f7917c00SJeff Kirsher if (link_ok) {
214f7917c00SJeff Kirsher err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AQ_LINK_STAT, &v);
215f7917c00SJeff Kirsher if (err)
216f7917c00SJeff Kirsher return err;
217f7917c00SJeff Kirsher
218f7917c00SJeff Kirsher *link_ok = v & 1;
219f7917c00SJeff Kirsher if (!*link_ok)
220f7917c00SJeff Kirsher return 0;
221f7917c00SJeff Kirsher }
222f7917c00SJeff Kirsher
223f7917c00SJeff Kirsher err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v);
224f7917c00SJeff Kirsher if (err)
225f7917c00SJeff Kirsher return err;
226f7917c00SJeff Kirsher
227f7917c00SJeff Kirsher if (speed) {
228f7917c00SJeff Kirsher switch (v & 0x6) {
229f7917c00SJeff Kirsher case 0x6:
230f7917c00SJeff Kirsher *speed = SPEED_10000;
231f7917c00SJeff Kirsher break;
232f7917c00SJeff Kirsher case 0x4:
233f7917c00SJeff Kirsher *speed = SPEED_1000;
234f7917c00SJeff Kirsher break;
235f7917c00SJeff Kirsher case 0x2:
236f7917c00SJeff Kirsher *speed = SPEED_100;
237f7917c00SJeff Kirsher break;
238f7917c00SJeff Kirsher case 0x0:
239f7917c00SJeff Kirsher *speed = SPEED_10;
240f7917c00SJeff Kirsher break;
241f7917c00SJeff Kirsher }
242f7917c00SJeff Kirsher }
243f7917c00SJeff Kirsher
244f7917c00SJeff Kirsher if (duplex)
245f7917c00SJeff Kirsher *duplex = v & 1 ? DUPLEX_FULL : DUPLEX_HALF;
246f7917c00SJeff Kirsher
247f7917c00SJeff Kirsher return 0;
248f7917c00SJeff Kirsher }
249f7917c00SJeff Kirsher
25046f85a92SJulia Lawall static const struct cphy_ops aq100x_ops = {
251f7917c00SJeff Kirsher .reset = aq100x_reset,
252f7917c00SJeff Kirsher .intr_enable = aq100x_intr_enable,
253f7917c00SJeff Kirsher .intr_disable = aq100x_intr_disable,
254f7917c00SJeff Kirsher .intr_clear = aq100x_intr_clear,
255f7917c00SJeff Kirsher .intr_handler = aq100x_intr_handler,
256f7917c00SJeff Kirsher .autoneg_enable = aq100x_autoneg_enable,
257f7917c00SJeff Kirsher .autoneg_restart = aq100x_autoneg_restart,
258f7917c00SJeff Kirsher .advertise = aq100x_advertise,
259f7917c00SJeff Kirsher .set_loopback = aq100x_set_loopback,
260f7917c00SJeff Kirsher .set_speed_duplex = aq100x_set_speed_duplex,
261f7917c00SJeff Kirsher .get_link_status = aq100x_get_link_status,
262f7917c00SJeff Kirsher .power_down = aq100x_power_down,
263f7917c00SJeff Kirsher .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
264f7917c00SJeff Kirsher };
265f7917c00SJeff Kirsher
t3_aq100x_phy_prep(struct cphy * phy,struct adapter * adapter,int phy_addr,const struct mdio_ops * mdio_ops)266f7917c00SJeff Kirsher int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
267f7917c00SJeff Kirsher const struct mdio_ops *mdio_ops)
268f7917c00SJeff Kirsher {
269f7917c00SJeff Kirsher unsigned int v, v2, gpio, wait;
270f7917c00SJeff Kirsher int err;
271f7917c00SJeff Kirsher
272f7917c00SJeff Kirsher cphy_init(phy, adapter, phy_addr, &aq100x_ops, mdio_ops,
273f7917c00SJeff Kirsher SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full |
274f7917c00SJeff Kirsher SUPPORTED_TP | SUPPORTED_Autoneg | SUPPORTED_AUI,
275f7917c00SJeff Kirsher "1000/10GBASE-T");
276f7917c00SJeff Kirsher
277f7917c00SJeff Kirsher /*
278f7917c00SJeff Kirsher * The PHY has been out of reset ever since the system powered up. So
279f7917c00SJeff Kirsher * we do a hard reset over here.
280f7917c00SJeff Kirsher */
281f7917c00SJeff Kirsher gpio = phy_addr ? F_GPIO10_OUT_VAL : F_GPIO6_OUT_VAL;
282f7917c00SJeff Kirsher t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, 0);
283f7917c00SJeff Kirsher msleep(1);
284f7917c00SJeff Kirsher t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, gpio);
285f7917c00SJeff Kirsher
286f7917c00SJeff Kirsher /*
287f7917c00SJeff Kirsher * Give it enough time to load the firmware and get ready for mdio.
288f7917c00SJeff Kirsher */
289f7917c00SJeff Kirsher msleep(1000);
290f7917c00SJeff Kirsher wait = 500; /* in 10ms increments */
291f7917c00SJeff Kirsher do {
292f7917c00SJeff Kirsher err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
293f7917c00SJeff Kirsher if (err || v == 0xffff) {
294f7917c00SJeff Kirsher
295f7917c00SJeff Kirsher /* Allow prep_adapter to succeed when ffff is read */
296f7917c00SJeff Kirsher
297f7917c00SJeff Kirsher CH_WARN(adapter, "PHY%d: reset failed (0x%x, 0x%x).\n",
298f7917c00SJeff Kirsher phy_addr, err, v);
299f7917c00SJeff Kirsher goto done;
300f7917c00SJeff Kirsher }
301f7917c00SJeff Kirsher
302f7917c00SJeff Kirsher v &= AQ_RESET;
303f7917c00SJeff Kirsher if (v)
304f7917c00SJeff Kirsher msleep(10);
305f7917c00SJeff Kirsher } while (v && --wait);
306f7917c00SJeff Kirsher if (v) {
307f7917c00SJeff Kirsher CH_WARN(adapter, "PHY%d: reset timed out (0x%x).\n",
308f7917c00SJeff Kirsher phy_addr, v);
309f7917c00SJeff Kirsher
310f7917c00SJeff Kirsher goto done; /* let prep_adapter succeed */
311f7917c00SJeff Kirsher }
312f7917c00SJeff Kirsher
313f7917c00SJeff Kirsher /* Datasheet says 3s max but this has been observed */
314f7917c00SJeff Kirsher wait = (500 - wait) * 10 + 1000;
315f7917c00SJeff Kirsher if (wait > 3000)
316f7917c00SJeff Kirsher CH_WARN(adapter, "PHY%d: reset took %ums\n", phy_addr, wait);
317f7917c00SJeff Kirsher
318f7917c00SJeff Kirsher /* Firmware version check. */
319f7917c00SJeff Kirsher t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v);
320f7917c00SJeff Kirsher if (v != 101)
321f7917c00SJeff Kirsher CH_WARN(adapter, "PHY%d: unsupported firmware %d\n",
322f7917c00SJeff Kirsher phy_addr, v);
323f7917c00SJeff Kirsher
324f7917c00SJeff Kirsher /*
325f7917c00SJeff Kirsher * The PHY should start in really-low-power mode. Prepare it for normal
326f7917c00SJeff Kirsher * operations.
327f7917c00SJeff Kirsher */
328f7917c00SJeff Kirsher err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
329f7917c00SJeff Kirsher if (err)
330f7917c00SJeff Kirsher return err;
331f7917c00SJeff Kirsher if (v & AQ_LOWPOWER) {
332f7917c00SJeff Kirsher err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1,
333f7917c00SJeff Kirsher AQ_LOWPOWER, 0);
334f7917c00SJeff Kirsher if (err)
335f7917c00SJeff Kirsher return err;
336f7917c00SJeff Kirsher msleep(10);
337f7917c00SJeff Kirsher } else
338f7917c00SJeff Kirsher CH_WARN(adapter, "PHY%d does not start in low power mode.\n",
339f7917c00SJeff Kirsher phy_addr);
340f7917c00SJeff Kirsher
341f7917c00SJeff Kirsher /*
342f7917c00SJeff Kirsher * Verify XAUI settings, but let prep succeed no matter what.
343f7917c00SJeff Kirsher */
344f7917c00SJeff Kirsher v = v2 = 0;
345f7917c00SJeff Kirsher t3_mdio_read(phy, MDIO_MMD_PHYXS, AQ_XAUI_RX_CFG, &v);
346f7917c00SJeff Kirsher t3_mdio_read(phy, MDIO_MMD_PHYXS, AQ_XAUI_TX_CFG, &v2);
347f7917c00SJeff Kirsher if (v != 0x1b || v2 != 0x1b)
348f7917c00SJeff Kirsher CH_WARN(adapter,
349f7917c00SJeff Kirsher "PHY%d: incorrect XAUI settings (0x%x, 0x%x).\n",
350f7917c00SJeff Kirsher phy_addr, v, v2);
351f7917c00SJeff Kirsher
352f7917c00SJeff Kirsher done:
353f7917c00SJeff Kirsher return err;
354f7917c00SJeff Kirsher }
355