1 /*****************************************************************************
2  *                                                                           *
3  * File: suni1x10gexp_regs.h                                                 *
4  * $Revision: 1.9 $                                                          *
5  * $Date: 2005/06/22 00:17:04 $                                              *
6  * Description:                                                              *
7  *  PMC/SIERRA (pm3393) MAC-PHY functionality.                               *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  * This program is free software; you can redistribute it and/or modify      *
11  * it under the terms of the GNU General Public License, version 2, as       *
12  * published by the Free Software Foundation.                                *
13  *                                                                           *
14  * You should have received a copy of the GNU General Public License along   *
15  * with this program; if not, see <http://www.gnu.org/licenses/>.            *
16  *                                                                           *
17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
18  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
20  *                                                                           *
21  * http://www.chelsio.com                                                    *
22  *                                                                           *
23  * Maintainers: maintainers@chelsio.com                                      *
24  *                                                                           *
25  * Authors: PMC/SIERRA                                                       *
26  *                                                                           *
27  * History:                                                                  *
28  *                                                                           *
29  ****************************************************************************/
30 
31 #ifndef _CXGB_SUNI1x10GEXP_REGS_H_
32 #define _CXGB_SUNI1x10GEXP_REGS_H_
33 
34 /*
35 ** Space allocated for each Exact Match Filter
36 **     There are 8 filter configurations
37 */
38 #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
39 
40 #define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)       ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
41 
42 /*
43 ** Space allocated for VLAN-Id Filter
44 **      There are 8 filter configurations
45 */
46 #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
47 
48 #define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)   ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
49 
50 /*
51 ** Space allocated for each MSTAT Counter
52 */
53 #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
54 
55 #define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)       ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
56 
57 
58 /******************************************************************************/
59 /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP                                     **/
60 /******************************************************************************/
61 /* Refer to the Register Bit Masks bellow for the naming of each register and */
62 /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit        */
63 /******************************************************************************/
64 
65 
66 #define SUNI1x10GEXP_REG_IDENTIFICATION                                  0x0000
67 #define SUNI1x10GEXP_REG_PRODUCT_REVISION                                0x0001
68 #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL                        0x0002
69 #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL                              0x0003
70 #define SUNI1x10GEXP_REG_DEVICE_STATUS                                   0x0004
71 #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE               0x0005
72 
73 #define SUNI1x10GEXP_REG_MDIO_COMMAND                                    0x0006
74 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE                           0x0007
75 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS                           0x0008
76 #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS                                 0x0009
77 #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA                        0x000A
78 #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA                           0x000B
79 
80 #define SUNI1x10GEXP_REG_OAM_INTF_CTRL                                   0x000C
81 #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS                         0x000D
82 #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE                         0x000E
83 #define SUNI1x10GEXP_REG_FREE                                            0x000F
84 
85 #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL                                  0x0010
86 #define SUNI1x10GEXP_REG_XRF_MISC_CTRL                                   0x0011
87 
88 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1                            0x0100
89 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2                            0x0101
90 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE                    0x0102
91 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE                   0x0103
92 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS                    0x0104
93 #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG                         0x0107
94 
95 #define SUNI1x10GEXP_REG_RXXG_CONFIG_1                                   0x2040
96 #define SUNI1x10GEXP_REG_RXXG_CONFIG_2                                   0x2041
97 #define SUNI1x10GEXP_REG_RXXG_CONFIG_3                                   0x2042
98 #define SUNI1x10GEXP_REG_RXXG_INTERRUPT                                  0x2043
99 #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH                           0x2045
100 #define SUNI1x10GEXP_REG_RXXG_SA_15_0                                    0x2046
101 #define SUNI1x10GEXP_REG_RXXG_SA_31_16                                   0x2047
102 #define SUNI1x10GEXP_REG_RXXG_SA_47_32                                   0x2048
103 #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD                     0x2049
104 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
105 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
106 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
107 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId)      (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId))
108 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW                     0x204A
109 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID                     0x204B
110 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH                    0x204C
111 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW                     0x204D
112 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID                     0x204E
113 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH                    0x204F
114 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW                     0x2050
115 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID                     0x2051
116 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH                    0x2052
117 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW                     0x2053
118 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID                     0x2054
119 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH                    0x2055
120 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW                     0x2056
121 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID                     0x2057
122 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH                    0x2058
123 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW                     0x2059
124 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID                     0x205A
125 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH                    0x205B
126 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW                     0x205C
127 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID                     0x205D
128 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH                    0x205E
129 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW                     0x205F
130 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID                     0x2060
131 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH                    0x2061
132 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0                          0x2062
133 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1                          0x2063
134 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2                          0x2064
135 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3                          0x2065
136 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4                          0x2066
137 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5                          0x2067
138 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6                          0x2068
139 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7                          0x2069
140 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW                         0x206A
141 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW                      0x206B
142 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH                     0x206C
143 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH                        0x206D
144 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0                   0x206E
145 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1                   0x206F
146 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2                   0x2070
147 
148 #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL                            0x2081
149 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0                       0x2084
150 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1                       0x2085
151 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2                       0x2086
152 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3                       0x2087
153 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE                            0x2088
154 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS                            0x2089
155 #define SUNI1x10GEXP_REG_XRF_ERR_STATUS                                  0x208A
156 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE                       0x208B
157 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS                       0x208C
158 #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES                              0x2092
159 
160 #define SUNI1x10GEXP_REG_RXOAM_CONFIG                                    0x20C0
161 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG                           0x20C1
162 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG                           0x20C2
163 #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2                                  0x20C3
164 #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG                                0x20C4
165 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES                             0x20C5
166 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE                          0x20C7
167 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS                          0x20C8
168 #define SUNI1x10GEXP_REG_RXOAM_STATUS                                    0x20C9
169 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT                             0x20CA
170 #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT                       0x20CB
171 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB                 0x20CC
172 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB                 0x20CD
173 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB               0x20CE
174 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB               0x20CF
175 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB               0x20D0
176 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB               0x20D1
177 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB                     0x20D2
178 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB                     0x20D3
179 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB                     0x20D4
180 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB                     0x20D5
181 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB                 0x20D6
182 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB                 0x20D7
183 
184 #define SUNI1x10GEXP_REG_MSTAT_CONTROL                                   0x2100
185 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0                        0x2101
186 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1                        0x2102
187 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2                        0x2103
188 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3                        0x2104
189 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0                          0x2105
190 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1                          0x2106
191 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2                          0x2107
192 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3                          0x2108
193 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS                     0x2109
194 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW                    0x210A
195 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE                 0x210B
196 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH                   0x210C
197 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId)   (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
198 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId)   (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
199 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId)  (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
200 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW                             0x2110
201 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID                             0x2111
202 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH                            0x2112
203 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD                           0x2113
204 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW                             0x2114
205 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID                             0x2115
206 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH                            0x2116
207 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD                           0x2117
208 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW                             0x2118
209 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID                             0x2119
210 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH                            0x211A
211 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD                           0x211B
212 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW                             0x211C
213 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID                             0x211D
214 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH                            0x211E
215 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD                           0x211F
216 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW                             0x2120
217 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID                             0x2121
218 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH                            0x2122
219 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD                           0x2123
220 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW                             0x2124
221 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID                             0x2125
222 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH                            0x2126
223 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD                           0x2127
224 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW                             0x2128
225 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID                             0x2129
226 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH                            0x212A
227 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD                           0x212B
228 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW                             0x212C
229 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID                             0x212D
230 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH                            0x212E
231 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD                           0x212F
232 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW                             0x2130
233 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID                             0x2131
234 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH                            0x2132
235 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD                           0x2133
236 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW                             0x2134
237 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID                             0x2135
238 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH                            0x2136
239 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD                           0x2137
240 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW                            0x2138
241 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID                            0x2139
242 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH                           0x213A
243 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD                          0x213B
244 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW                            0x213C
245 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID                            0x213D
246 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH                           0x213E
247 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD                          0x213F
248 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW                            0x2140
249 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID                            0x2141
250 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH                           0x2142
251 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD                          0x2143
252 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW                            0x2144
253 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID                            0x2145
254 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH                           0x2146
255 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD                          0x2147
256 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW                            0x2148
257 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID                            0x2149
258 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH                           0x214A
259 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD                          0x214B
260 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW                            0x214C
261 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID                            0x214D
262 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH                           0x214E
263 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD                          0x214F
264 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW                            0x2150
265 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID                            0x2151
266 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH                           0x2152
267 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD                          0x2153
268 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW                            0x2154
269 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID                            0x2155
270 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH                           0x2156
271 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD                          0x2157
272 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW                            0x2158
273 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID                            0x2159
274 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH                           0x215A
275 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD                          0x215B
276 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW                            0x215C
277 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID                            0x215D
278 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH                           0x215E
279 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD                          0x215F
280 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW                            0x2160
281 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID                            0x2161
282 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH                           0x2162
283 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD                          0x2163
284 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW                            0x2164
285 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID                            0x2165
286 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH                           0x2166
287 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD                          0x2167
288 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW                            0x2168
289 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID                            0x2169
290 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH                           0x216A
291 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD                          0x216B
292 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW                            0x216C
293 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID                            0x216D
294 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH                           0x216E
295 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD                          0x216F
296 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW                            0x2170
297 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID                            0x2171
298 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH                           0x2172
299 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD                          0x2173
300 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW                            0x2174
301 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID                            0x2175
302 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH                           0x2176
303 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD                          0x2177
304 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW                            0x2178
305 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID                            0x2179
306 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH                           0x217a
307 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD                          0x217b
308 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW                            0x217c
309 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID                            0x217d
310 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH                           0x217e
311 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD                          0x217f
312 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW                            0x2180
313 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID                            0x2181
314 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH                           0x2182
315 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD                          0x2183
316 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW                            0x2184
317 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID                            0x2185
318 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH                           0x2186
319 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD                          0x2187
320 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW                            0x2188
321 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID                            0x2189
322 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH                           0x218A
323 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD                          0x218B
324 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW                            0x218C
325 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID                            0x218D
326 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH                           0x218E
327 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD                          0x218F
328 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW                            0x2190
329 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID                            0x2191
330 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH                           0x2192
331 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD                          0x2193
332 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW                            0x2194
333 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID                            0x2195
334 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH                           0x2196
335 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD                          0x2197
336 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW                            0x2198
337 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID                            0x2199
338 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH                           0x219A
339 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD                          0x219B
340 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW                            0x219C
341 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID                            0x219D
342 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH                           0x219E
343 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD                          0x219F
344 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW                            0x21A0
345 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID                            0x21A1
346 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH                           0x21A2
347 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD                          0x21A3
348 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW                            0x21A4
349 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID                            0x21A5
350 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH                           0x21A6
351 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD                          0x21A7
352 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW                            0x21A8
353 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID                            0x21A9
354 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH                           0x21AA
355 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD                          0x21AB
356 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW                            0x21AC
357 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID                            0x21AD
358 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH                           0x21AE
359 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD                          0x21AF
360 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW                            0x21B0
361 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID                            0x21B1
362 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH                           0x21B2
363 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD                          0x21B3
364 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW                            0x21B4
365 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID                            0x21B5
366 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH                           0x21B6
367 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD                          0x21B7
368 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW                            0x21B8
369 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID                            0x21B9
370 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH                           0x21BA
371 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD                          0x21BB
372 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW                            0x21BC
373 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID                            0x21BD
374 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH                           0x21BE
375 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD                          0x21BF
376 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW                            0x21C0
377 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID                            0x21C1
378 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH                           0x21C2
379 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD                          0x21C3
380 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW                            0x21C4
381 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID                            0x21C5
382 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH                           0x21C6
383 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD                          0x21C7
384 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW                            0x21C8
385 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID                            0x21C9
386 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH                           0x21CA
387 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD                          0x21CB
388 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW                            0x21CC
389 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID                            0x21CD
390 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH                           0x21CE
391 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD                          0x21CF
392 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW                            0x21D0
393 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID                            0x21D1
394 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH                           0x21D2
395 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD                          0x21D3
396 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW                            0x21D4
397 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID                            0x21D5
398 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH                           0x21D6
399 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD                          0x21D7
400 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW                            0x21D8
401 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID                            0x21D9
402 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH                           0x21DA
403 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD                          0x21DB
404 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW                            0x21DC
405 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID                            0x21DD
406 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH                           0x21DE
407 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD                          0x21DF
408 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW                            0x21E0
409 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID                            0x21E1
410 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH                           0x21E2
411 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD                          0x21E3
412 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW                            0x21E4
413 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID                            0x21E5
414 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH                           0x21E6
415 #define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM                               51
416 
417 #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG                              0x2200
418 #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION                          0x2201
419 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE                       0x2209
420 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT                    0x220A
421 #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS                      0x220D
422 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION     0x220E
423 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT              0x220F
424 #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT        0x2210
425 #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT      0x2211
426 
427 #define SUNI1x10GEXP_REG_PL4MOS_CONFIG                                   0x2240
428 #define SUNI1x10GEXP_REG_PL4MOS_MASK                                     0x2241
429 #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING                         0x2242
430 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1                                0x2243
431 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2                                0x2244
432 #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE                            0x2245
433 
434 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG                                   0x2280
435 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK                           0x2282
436 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT                                0x2283
437 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T                             0x2284
438 
439 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS                        0x2300
440 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE                        0x2301
441 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK                          0x2302
442 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS                        0x2303
443 #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS                      0x2304
444 #define SUNI1x10GEXP_REG_PL4IO_CONFIG                                    0x2305
445 
446 #define SUNI1x10GEXP_REG_TXXG_CONFIG_1                                   0x3040
447 #define SUNI1x10GEXP_REG_TXXG_CONFIG_2                                   0x3041
448 #define SUNI1x10GEXP_REG_TXXG_CONFIG_3                                   0x3042
449 #define SUNI1x10GEXP_REG_TXXG_INTERRUPT                                  0x3043
450 #define SUNI1x10GEXP_REG_TXXG_STATUS                                     0x3044
451 #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE                             0x3045
452 #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE                             0x3046
453 #define SUNI1x10GEXP_REG_TXXG_SA_15_0                                    0x3047
454 #define SUNI1x10GEXP_REG_TXXG_SA_31_16                                   0x3048
455 #define SUNI1x10GEXP_REG_TXXG_SA_47_32                                   0x3049
456 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER                                0x304D
457 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL                       0x304E
458 #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER                       0x3051
459 #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG                       0x3052
460 
461 #define SUNI1x10GEXP_REG_XTEF_CTRL                                       0x3080
462 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS                           0x3084
463 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE                           0x3085
464 #define SUNI1x10GEXP_REG_XTEF_VISIBILITY                                 0x3086
465 
466 #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG                                0x30C0
467 #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG                          0x30C1
468 #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG                      0x30C2
469 #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES                        0x30C3
470 #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES                        0x30C4
471 #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES                        0x30C5
472 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE                          0x30C6
473 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS                          0x30C7
474 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB                          0x30C8
475 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB                          0x30C9
476 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB                        0x30CA
477 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB                        0x30CB
478 #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK                            0x30CC
479 #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK                            0x30CD
480 #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK                            0x30CE
481 #define SUNI1x10GEXP_REG_TXOAM_COSET                                     0x30CF
482 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB                 0x30D0
483 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB                 0x30D1
484 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB               0x30D2
485 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB               0x30D3
486 
487 
488 #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG                              0x3200
489 #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS                         0x3201
490 #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS                      0x3202
491 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT                       0x3203
492 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT                      0x3204
493 #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT    0x3205
494 #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT  0x3206
495 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD           0x3207
496 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE                 0x320C
497 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION             0x320D
498 #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION                          0x3210
499 
500 #define SUNI1x10GEXP_REG_PL4IDU_CONFIG                                   0x3280
501 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK                           0x3282
502 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT                                0x3283
503 
504 
505 /*----------------------------------------*/
506 #define SUNI1x10GEXP_REG_MAX_OFFSET                                      0x3480
507 
508 /******************************************************************************/
509 /*                 -- End register offset definitions --                      */
510 /******************************************************************************/
511 
512 /******************************************************************************/
513 /** SUNI-1x10GE-XP REGISTER BIT MASKS                                        **/
514 /******************************************************************************/
515 
516 #define SUNI1x10GEXP_BITMSK_BITS_1   0x00001
517 #define SUNI1x10GEXP_BITMSK_BITS_2   0x00003
518 #define SUNI1x10GEXP_BITMSK_BITS_3   0x00007
519 #define SUNI1x10GEXP_BITMSK_BITS_4   0x0000f
520 #define SUNI1x10GEXP_BITMSK_BITS_5   0x0001f
521 #define SUNI1x10GEXP_BITMSK_BITS_6   0x0003f
522 #define SUNI1x10GEXP_BITMSK_BITS_7   0x0007f
523 #define SUNI1x10GEXP_BITMSK_BITS_8   0x000ff
524 #define SUNI1x10GEXP_BITMSK_BITS_9   0x001ff
525 #define SUNI1x10GEXP_BITMSK_BITS_10  0x003ff
526 #define SUNI1x10GEXP_BITMSK_BITS_11  0x007ff
527 #define SUNI1x10GEXP_BITMSK_BITS_12  0x00fff
528 #define SUNI1x10GEXP_BITMSK_BITS_13  0x01fff
529 #define SUNI1x10GEXP_BITMSK_BITS_14  0x03fff
530 #define SUNI1x10GEXP_BITMSK_BITS_15  0x07fff
531 #define SUNI1x10GEXP_BITMSK_BITS_16  0x0ffff
532 
533 #define mSUNI1x10GEXP_CLR_MSBITS_1(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
534 #define mSUNI1x10GEXP_CLR_MSBITS_2(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
535 #define mSUNI1x10GEXP_CLR_MSBITS_3(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
536 #define mSUNI1x10GEXP_CLR_MSBITS_4(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
537 #define mSUNI1x10GEXP_CLR_MSBITS_5(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
538 #define mSUNI1x10GEXP_CLR_MSBITS_6(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
539 #define mSUNI1x10GEXP_CLR_MSBITS_7(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
540 #define mSUNI1x10GEXP_CLR_MSBITS_8(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
541 #define mSUNI1x10GEXP_CLR_MSBITS_9(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
542 #define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
543 #define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
544 #define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
545 #define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
546 #define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
547 #define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
548 
549 #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
550 
551 
552 
553 /*----------------------------------------------------------------------------
554  * Register 0x0001: S/UNI-1x10GE-XP Product Revision
555  *    Bit 3-0  REVISION
556  *----------------------------------------------------------------------------*/
557 #define SUNI1x10GEXP_BITMSK_REVISION  0x000F
558 
559 /*----------------------------------------------------------------------------
560  * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
561  *    Bit 2  XAUI_ARESETB
562  *    Bit 1  PL4_ARESETB
563  *    Bit 0  DRESETB
564  *----------------------------------------------------------------------------*/
565 #define SUNI1x10GEXP_BITMSK_XAUI_ARESET  0x0004
566 #define SUNI1x10GEXP_BITMSK_PL4_ARESET   0x0002
567 #define SUNI1x10GEXP_BITMSK_DRESETB      0x0001
568 
569 /*----------------------------------------------------------------------------
570  * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
571  *    Bit 11  PL4IO_OUTCLKSEL
572  *    Bit 9   SYSPCSLB
573  *    Bit 8   LINEPCSLB
574  *    Bit 7   MSTAT_BYPASS
575  *    Bit 6   RXXG_BYPASS
576  *    Bit 5   TXXG_BYPASS
577  *    Bit 4   SOP_PAD_EN
578  *    Bit 1   LOS_INV
579  *    Bit 0   OVERRIDE_LOS
580  *----------------------------------------------------------------------------*/
581 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL  0x0800
582 #define SUNI1x10GEXP_BITMSK_SYSPCSLB         0x0200
583 #define SUNI1x10GEXP_BITMSK_LINEPCSLB        0x0100
584 #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS     0x0080
585 #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS      0x0040
586 #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS      0x0020
587 #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN       0x0010
588 #define SUNI1x10GEXP_BITMSK_LOS_INV          0x0002
589 #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS     0x0001
590 
591 /*----------------------------------------------------------------------------
592  * Register 0x0004: S/UNI-1x10GE-XP Device Status
593  *    Bit 9 TOP_SXRA_EXPIRED
594  *    Bit 8 TOP_MDIO_BUSY
595  *    Bit 7 TOP_DTRB
596  *    Bit 6 TOP_EXPIRED
597  *    Bit 5 TOP_PAUSED
598  *    Bit 4 TOP_PL4_ID_DOOL
599  *    Bit 3 TOP_PL4_IS_DOOL
600  *    Bit 2 TOP_PL4_ID_ROOL
601  *    Bit 1 TOP_PL4_IS_ROOL
602  *    Bit 0 TOP_PL4_OUT_ROOL
603  *----------------------------------------------------------------------------*/
604 #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED  0x0200
605 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY     0x0100
606 #define SUNI1x10GEXP_BITMSK_TOP_DTRB          0x0080
607 #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED       0x0040
608 #define SUNI1x10GEXP_BITMSK_TOP_PAUSED        0x0020
609 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL   0x0010
610 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL   0x0008
611 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL   0x0004
612 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL   0x0002
613 #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL  0x0001
614 
615 /*----------------------------------------------------------------------------
616  * Register 0x0005: Global Performance Update and Clock Monitors
617  *    Bit 15 TIP
618  *    Bit 8  XAUI_REF_CLKA
619  *    Bit 7  RXLANE3CLKA
620  *    Bit 6  RXLANE2CLKA
621  *    Bit 5  RXLANE1CLKA
622  *    Bit 4  RXLANE0CLKA
623  *    Bit 3  CSUCLKA
624  *    Bit 2  TDCLKA
625  *    Bit 1  RSCLKA
626  *    Bit 0  RDCLKA
627  *----------------------------------------------------------------------------*/
628 #define SUNI1x10GEXP_BITMSK_TIP            0x8000
629 #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA  0x0100
630 #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA    0x0080
631 #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA    0x0040
632 #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA    0x0020
633 #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA    0x0010
634 #define SUNI1x10GEXP_BITMSK_CSUCLKA        0x0008
635 #define SUNI1x10GEXP_BITMSK_TDCLKA         0x0004
636 #define SUNI1x10GEXP_BITMSK_RSCLKA         0x0002
637 #define SUNI1x10GEXP_BITMSK_RDCLKA         0x0001
638 
639 /*----------------------------------------------------------------------------
640  * Register 0x0006: MDIO Command
641  *    Bit 4 MDIO_RDINC
642  *    Bit 3 MDIO_RSTAT
643  *    Bit 2 MDIO_LCTLD
644  *    Bit 1 MDIO_LCTLA
645  *    Bit 0 MDIO_SPRE
646  *----------------------------------------------------------------------------*/
647 #define SUNI1x10GEXP_BITMSK_MDIO_RDINC  0x0010
648 #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT  0x0008
649 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD  0x0004
650 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA  0x0002
651 #define SUNI1x10GEXP_BITMSK_MDIO_SPRE   0x0001
652 
653 /*----------------------------------------------------------------------------
654  * Register 0x0007: MDIO Interrupt Enable
655  *    Bit 0 MDIO_BUSY_EN
656  *----------------------------------------------------------------------------*/
657 #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN  0x0001
658 
659 /*----------------------------------------------------------------------------
660  * Register 0x0008: MDIO Interrupt Status
661  *    Bit 0 MDIO_BUSYI
662  *----------------------------------------------------------------------------*/
663 #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI  0x0001
664 
665 /*----------------------------------------------------------------------------
666  * Register 0x0009: MMD PHY Address
667  *    Bit 12-8 MDIO_DEVADR
668  *    Bit 4-0 MDIO_PRTADR
669  *----------------------------------------------------------------------------*/
670 #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR  0x1F00
671 #define SUNI1x10GEXP_BITOFF_MDIO_DEVADR  8
672 #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR  0x001F
673 #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR  0
674 
675 /*----------------------------------------------------------------------------
676  * Register 0x000C: OAM Interface Control
677  *    Bit 6 MDO_OD_ENB
678  *    Bit 5 MDI_INV
679  *    Bit 4 MDI_SEL
680  *    Bit 3 RXOAMEN
681  *    Bit 2 RXOAMCLKEN
682  *    Bit 1 TXOAMEN
683  *    Bit 0 TXOAMCLKEN
684  *----------------------------------------------------------------------------*/
685 #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB  0x0040
686 #define SUNI1x10GEXP_BITMSK_MDI_INV     0x0020
687 #define SUNI1x10GEXP_BITMSK_MDI_SEL     0x0010
688 #define SUNI1x10GEXP_BITMSK_RXOAMEN     0x0008
689 #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN  0x0004
690 #define SUNI1x10GEXP_BITMSK_TXOAMEN     0x0002
691 #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN  0x0001
692 
693 /*----------------------------------------------------------------------------
694  * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
695  *    Bit 15 TOP_PL4IO_INT
696  *    Bit 14 TOP_IRAM_INT
697  *    Bit 13 TOP_ERAM_INT
698  *    Bit 12 TOP_XAUI_INT
699  *    Bit 11 TOP_MSTAT_INT
700  *    Bit 10 TOP_RXXG_INT
701  *    Bit 9 TOP_TXXG_INT
702  *    Bit 8 TOP_XRF_INT
703  *    Bit 7 TOP_XTEF_INT
704  *    Bit 6 TOP_MDIO_BUSY_INT
705  *    Bit 5 TOP_RXOAM_INT
706  *    Bit 4 TOP_TXOAM_INT
707  *    Bit 3 TOP_IFLX_INT
708  *    Bit 2 TOP_EFLX_INT
709  *    Bit 1 TOP_PL4ODP_INT
710  *    Bit 0 TOP_PL4IDU_INT
711  *----------------------------------------------------------------------------*/
712 #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT      0x8000
713 #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT       0x4000
714 #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT       0x2000
715 #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT       0x1000
716 #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT      0x0800
717 #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT       0x0400
718 #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT       0x0200
719 #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT        0x0100
720 #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT       0x0080
721 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT  0x0040
722 #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT      0x0020
723 #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT      0x0010
724 #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT       0x0008
725 #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT       0x0004
726 #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT     0x0002
727 #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT     0x0001
728 
729 /*----------------------------------------------------------------------------
730  * Register 0x000E:PM3393 Global interrupt enable
731  *    Bit 15 TOP_INTE
732  *----------------------------------------------------------------------------*/
733 #define SUNI1x10GEXP_BITMSK_TOP_INTE  0x8000
734 
735 /*----------------------------------------------------------------------------
736  * Register 0x0010: XTEF Miscellaneous Control
737  *    Bit 7 RF_VAL
738  *    Bit 6 RF_OVERRIDE
739  *    Bit 5 LF_VAL
740  *    Bit 4 LF_OVERRIDE
741  *----------------------------------------------------------------------------*/
742 #define SUNI1x10GEXP_BITMSK_RF_VAL             0x0080
743 #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE        0x0040
744 #define SUNI1x10GEXP_BITMSK_LF_VAL             0x0020
745 #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE        0x0010
746 #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL  0x00F0
747 
748 /*----------------------------------------------------------------------------
749  * Register 0x0011: XRF Miscellaneous Control
750  *    Bit 6-4 EN_IDLE_REP
751  *----------------------------------------------------------------------------*/
752 #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP  0x0070
753 
754 /*----------------------------------------------------------------------------
755  * Register 0x0100: SERDES 3125 Configuration Register 1
756  *    Bit 10 RXEQB_3
757  *    Bit 8  RXEQB_2
758  *    Bit 6  RXEQB_1
759  *    Bit 4  RXEQB_0
760  *----------------------------------------------------------------------------*/
761 #define SUNI1x10GEXP_BITMSK_RXEQB    0x0FF0
762 #define SUNI1x10GEXP_BITOFF_RXEQB_3  10
763 #define SUNI1x10GEXP_BITOFF_RXEQB_2  8
764 #define SUNI1x10GEXP_BITOFF_RXEQB_1  6
765 #define SUNI1x10GEXP_BITOFF_RXEQB_0  4
766 
767 /*----------------------------------------------------------------------------
768  * Register 0x0101: SERDES 3125 Configuration Register 2
769  *    Bit 12 YSEL
770  *    Bit  7 PRE_EMPH_3
771  *    Bit  6 PRE_EMPH_2
772  *    Bit  5 PRE_EMPH_1
773  *    Bit  4 PRE_EMPH_0
774  *----------------------------------------------------------------------------*/
775 #define SUNI1x10GEXP_BITMSK_YSEL        0x1000
776 #define SUNI1x10GEXP_BITMSK_PRE_EMPH    0x00F0
777 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3  0x0080
778 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2  0x0040
779 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1  0x0020
780 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0  0x0010
781 
782 /*----------------------------------------------------------------------------
783  * Register 0x0102: SERDES 3125 Interrupt Enable Register
784  *    Bit 3 LASIE
785  *    Bit 2 SPLL_RAE
786  *    Bit 1 MPLL_RAE
787  *    Bit 0 PLL_LOCKE
788  *----------------------------------------------------------------------------*/
789 #define SUNI1x10GEXP_BITMSK_LASIE      0x0008
790 #define SUNI1x10GEXP_BITMSK_SPLL_RAE   0x0004
791 #define SUNI1x10GEXP_BITMSK_MPLL_RAE   0x0002
792 #define SUNI1x10GEXP_BITMSK_PLL_LOCKE  0x0001
793 
794 /*----------------------------------------------------------------------------
795  * Register 0x0103: SERDES 3125 Interrupt Visibility Register
796  *    Bit 3 LASIV
797  *    Bit 2 SPLL_RAV
798  *    Bit 1 MPLL_RAV
799  *    Bit 0 PLL_LOCKV
800  *----------------------------------------------------------------------------*/
801 #define SUNI1x10GEXP_BITMSK_LASIV      0x0008
802 #define SUNI1x10GEXP_BITMSK_SPLL_RAV   0x0004
803 #define SUNI1x10GEXP_BITMSK_MPLL_RAV   0x0002
804 #define SUNI1x10GEXP_BITMSK_PLL_LOCKV  0x0001
805 
806 /*----------------------------------------------------------------------------
807  * Register 0x0104: SERDES 3125 Interrupt Status Register
808  *    Bit 3 LASII
809  *    Bit 2 SPLL_RAI
810  *    Bit 1 MPLL_RAI
811  *    Bit 0 PLL_LOCKI
812  *----------------------------------------------------------------------------*/
813 #define SUNI1x10GEXP_BITMSK_LASII      0x0008
814 #define SUNI1x10GEXP_BITMSK_SPLL_RAI   0x0004
815 #define SUNI1x10GEXP_BITMSK_MPLL_RAI   0x0002
816 #define SUNI1x10GEXP_BITMSK_PLL_LOCKI  0x0001
817 
818 /*----------------------------------------------------------------------------
819  * Register 0x0107: SERDES 3125 Test Configuration
820  *    Bit 12 DUALTX
821  *    Bit 10 HC_1
822  *    Bit  9 HC_0
823  *----------------------------------------------------------------------------*/
824 #define SUNI1x10GEXP_BITMSK_DUALTX  0x1000
825 #define SUNI1x10GEXP_BITMSK_HC      0x0600
826 #define SUNI1x10GEXP_BITOFF_HC_0    9
827 
828 /*----------------------------------------------------------------------------
829  * Register 0x2040: RXXG Configuration 1
830  *    Bit 15  RXXG_RXEN
831  *    Bit 14  RXXG_ROCF
832  *    Bit 13  RXXG_PAD_STRIP
833  *    Bit 10  RXXG_PUREP
834  *    Bit 9   RXXG_LONGP
835  *    Bit 8   RXXG_PARF
836  *    Bit 7   RXXG_FLCHK
837  *    Bit 5   RXXG_PASS_CTRL
838  *    Bit 3   RXXG_CRC_STRIP
839  *    Bit 2-0 RXXG_MIFG
840  *----------------------------------------------------------------------------*/
841 #define SUNI1x10GEXP_BITMSK_RXXG_RXEN       0x8000
842 #define SUNI1x10GEXP_BITMSK_RXXG_ROCF       0x4000
843 #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP  0x2000
844 #define SUNI1x10GEXP_BITMSK_RXXG_PUREP      0x0400
845 #define SUNI1x10GEXP_BITMSK_RXXG_LONGP      0x0200
846 #define SUNI1x10GEXP_BITMSK_RXXG_PARF       0x0100
847 #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK      0x0080
848 #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL  0x0020
849 #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP  0x0008
850 
851 /*----------------------------------------------------------------------------
852  * Register 0x02041: RXXG Configuration 2
853  *    Bit 7-0 RXXG_HDRSIZE
854  *----------------------------------------------------------------------------*/
855 #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE  0x00FF
856 
857 /*----------------------------------------------------------------------------
858  * Register 0x2042: RXXG Configuration 3
859  *    Bit 15 RXXG_MIN_LERRE
860  *    Bit 14 RXXG_MAX_LERRE
861  *    Bit 12 RXXG_LINE_ERRE
862  *    Bit 10 RXXG_RX_OVRE
863  *    Bit 9  RXXG_ADR_FILTERE
864  *    Bit 8  RXXG_ERR_FILTERE
865  *    Bit 5  RXXG_PRMB_ERRE
866  *----------------------------------------------------------------------------*/
867 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE     0x8000
868 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE     0x4000
869 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE     0x1000
870 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE       0x0400
871 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE   0x0200
872 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE  0x0100
873 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE     0x0020
874 
875 /*----------------------------------------------------------------------------
876  * Register 0x2043: RXXG Interrupt
877  *    Bit 15 RXXG_MIN_LERRI
878  *    Bit 14 RXXG_MAX_LERRI
879  *    Bit 12 RXXG_LINE_ERRI
880  *    Bit 10 RXXG_RX_OVRI
881  *    Bit 9  RXXG_ADR_FILTERI
882  *    Bit 8  RXXG_ERR_FILTERI
883  *    Bit 5  RXXG_PRMB_ERRE
884  *----------------------------------------------------------------------------*/
885 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI    0x8000
886 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI    0x4000
887 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI    0x1000
888 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI      0x0400
889 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI  0x0200
890 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI  0x0100
891 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE    0x0020
892 
893 /*----------------------------------------------------------------------------
894  * Register 0x2049: RXXG Receive FIFO Threshold
895  *    Bit 2-0 RXXG_CUT_THRU
896  *----------------------------------------------------------------------------*/
897 #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU  0x0007
898 #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU  0
899 
900 /*----------------------------------------------------------------------------
901  * Register 0x2062H - 0x2069: RXXG Exact Match VID
902  *    Bit 11-0 RXXG_VID_MATCH
903  *----------------------------------------------------------------------------*/
904 #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH  0x0FFF
905 #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH  0
906 
907 /*----------------------------------------------------------------------------
908  * Register 0x206EH - 0x206F: RXXG Address Filter Control
909  *    Bit 3 RXXG_FORWARD_ENABLE
910  *    Bit 2 RXXG_VLAN_ENABLE
911  *    Bit 1 RXXG_SRC_ADDR
912  *    Bit 0 RXXG_MATCH_ENABLE
913  *----------------------------------------------------------------------------*/
914 #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE  0x0008
915 #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE     0x0004
916 #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR        0x0002
917 #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE    0x0001
918 
919 /*----------------------------------------------------------------------------
920  * Register 0x2070: RXXG Address Filter Control 2
921  *    Bit 1 RXXG_PMODE
922  *    Bit 0 RXXG_MHASH_EN
923  *----------------------------------------------------------------------------*/
924 #define SUNI1x10GEXP_BITMSK_RXXG_PMODE     0x0002
925 #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN  0x0001
926 
927 /*----------------------------------------------------------------------------
928  * Register 0x2081: XRF Control Register 2
929  *    Bit 6   EN_PKT_GEN
930  *    Bit 4-2 PATT
931  *----------------------------------------------------------------------------*/
932 #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN  0x0040
933 #define SUNI1x10GEXP_BITMSK_PATT        0x001C
934 #define SUNI1x10GEXP_BITOFF_PATT        2
935 
936 /*----------------------------------------------------------------------------
937  * Register 0x2088: XRF Interrupt Enable
938  *    Bit 12-9 LANE_HICERE
939  *    Bit 8-5  HS_SD_LANEE
940  *    Bit 4    ALIGN_STATUS_ERRE
941  *    Bit 3-0  LANE_SYNC_STAT_ERRE
942  *----------------------------------------------------------------------------*/
943 #define SUNI1x10GEXP_BITMSK_LANE_HICERE          0x1E00
944 #define SUNI1x10GEXP_BITOFF_LANE_HICERE          9
945 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE          0x01E0
946 #define SUNI1x10GEXP_BITOFF_HS_SD_LANEE          5
947 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE    0x0010
948 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE  0x000F
949 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE  0
950 
951 /*----------------------------------------------------------------------------
952  * Register 0x2089: XRF Interrupt Status
953  *    Bit 12-9 LANE_HICERI
954  *    Bit 8-5  HS_SD_LANEI
955  *    Bit 4    ALIGN_STATUS_ERRI
956  *    Bit 3-0  LANE_SYNC_STAT_ERRI
957  *----------------------------------------------------------------------------*/
958 #define SUNI1x10GEXP_BITMSK_LANE_HICERI          0x1E00
959 #define SUNI1x10GEXP_BITOFF_LANE_HICERI          9
960 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI          0x01E0
961 #define SUNI1x10GEXP_BITOFF_HS_SD_LANEI          5
962 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI    0x0010
963 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI  0x000F
964 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI  0
965 
966 /*----------------------------------------------------------------------------
967  * Register 0x208A: XRF Error Status
968  *    Bit 8-5  HS_SD_LANE
969  *    Bit 4    ALIGN_STATUS_ERR
970  *    Bit 3-0  LANE_SYNC_STAT_ERR
971  *----------------------------------------------------------------------------*/
972 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3          0x0100
973 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2          0x0080
974 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1          0x0040
975 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0          0x0020
976 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR     0x0010
977 #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR  0x0008
978 #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR  0x0004
979 #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR  0x0002
980 #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR  0x0001
981 
982 /*----------------------------------------------------------------------------
983  * Register 0x208B: XRF Diagnostic Interrupt Enable
984  *    Bit 7-4 LANE_OVERRUNE
985  *    Bit 3-0 LANE_UNDERRUNE
986  *----------------------------------------------------------------------------*/
987 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE   0x00F0
988 #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE   4
989 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE  0x000F
990 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE  0
991 
992 /*----------------------------------------------------------------------------
993  * Register 0x208C: XRF Diagnostic Interrupt Status
994  *    Bit 7-4 LANE_OVERRUNI
995  *    Bit 3-0 LANE_UNDERRUNI
996  *----------------------------------------------------------------------------*/
997 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI   0x00F0
998 #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI   4
999 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI  0x000F
1000 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI  0
1001 
1002 /*----------------------------------------------------------------------------
1003  * Register 0x20C0: RXOAM Configuration
1004  *    Bit 15    RXOAM_BUSY
1005  *    Bit 14-12 RXOAM_F2_SEL
1006  *    Bit 10-8  RXOAM_F1_SEL
1007  *    Bit 7-6   RXOAM_FILTER_CTRL
1008  *    Bit 5-0   RXOAM_PX_EN
1009  *----------------------------------------------------------------------------*/
1010 #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY         0x8000
1011 #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL       0x7000
1012 #define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL       12
1013 #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL       0x0700
1014 #define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL       8
1015 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL  0x00C0
1016 #define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL  6
1017 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN        0x003F
1018 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN        0
1019 
1020 /*----------------------------------------------------------------------------
1021  * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1022  *    Bit 15-8 RXOAM_FX_MASK
1023  *    Bit 7-0  RXOAM_FX_VAL
1024  *----------------------------------------------------------------------------*/
1025 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK  0xFF00
1026 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK  8
1027 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL   0x00FF
1028 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl   0
1029 
1030 /*----------------------------------------------------------------------------
1031  * Register 0x20C3: RXOAM Configuration Register 2
1032  *    Bit 13    RXOAM_REC_BYTE_VAL
1033  *    Bit 11-10 RXOAM_BYPASS_MODE
1034  *    Bit 5-0   RXOAM_PX_CLEAR
1035  *----------------------------------------------------------------------------*/
1036 #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL  0x2000
1037 #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE   0x0C00
1038 #define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE   10
1039 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR      0x003F
1040 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR      0
1041 
1042 /*----------------------------------------------------------------------------
1043  * Register 0x20C4: RXOAM HEC Configuration
1044  *    Bit 15-8 RXOAM_COSET
1045  *    Bit 2    RXOAM_HEC_ERR_PKT
1046  *    Bit 0    RXOAM_HEC_EN
1047  *----------------------------------------------------------------------------*/
1048 #define SUNI1x10GEXP_BITMSK_RXOAM_COSET        0xFF00
1049 #define SUNI1x10GEXP_BITOFF_RXOAM_COSET        8
1050 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT  0x0004
1051 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN       0x0001
1052 
1053 /*----------------------------------------------------------------------------
1054  * Register 0x20C7: RXOAM Interrupt Enable
1055  *    Bit 10 RXOAM_FILTER_THRSHE
1056  *    Bit 9  RXOAM_OAM_ERRE
1057  *    Bit 8  RXOAM_HECE_THRSHE
1058  *    Bit 7  RXOAM_SOPE
1059  *    Bit 6  RXOAM_RFE
1060  *    Bit 5  RXOAM_LFE
1061  *    Bit 4  RXOAM_DV_ERRE
1062  *    Bit 3  RXOAM_DATA_INVALIDE
1063  *    Bit 2  RXOAM_FILTER_DROPE
1064  *    Bit 1  RXOAM_HECE
1065  *    Bit 0  RXOAM_OFLE
1066  *----------------------------------------------------------------------------*/
1067 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE  0x0400
1068 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE       0x0200
1069 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE    0x0100
1070 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE           0x0080
1071 #define SUNI1x10GEXP_BITMSK_RXOAM_RFE            0x0040
1072 #define SUNI1x10GEXP_BITMSK_RXOAM_LFE            0x0020
1073 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE        0x0010
1074 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE  0x0008
1075 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE   0x0004
1076 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE           0x0002
1077 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE           0x0001
1078 
1079 /*----------------------------------------------------------------------------
1080  * Register 0x20C8: RXOAM Interrupt Status
1081  *    Bit 10 RXOAM_FILTER_THRSHI
1082  *    Bit 9  RXOAM_OAM_ERRI
1083  *    Bit 8  RXOAM_HECE_THRSHI
1084  *    Bit 7  RXOAM_SOPI
1085  *    Bit 6  RXOAM_RFI
1086  *    Bit 5  RXOAM_LFI
1087  *    Bit 4  RXOAM_DV_ERRI
1088  *    Bit 3  RXOAM_DATA_INVALIDI
1089  *    Bit 2  RXOAM_FILTER_DROPI
1090  *    Bit 1  RXOAM_HECI
1091  *    Bit 0  RXOAM_OFLI
1092  *----------------------------------------------------------------------------*/
1093 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI  0x0400
1094 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI       0x0200
1095 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI    0x0100
1096 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI           0x0080
1097 #define SUNI1x10GEXP_BITMSK_RXOAM_RFI            0x0040
1098 #define SUNI1x10GEXP_BITMSK_RXOAM_LFI            0x0020
1099 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI        0x0010
1100 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI  0x0008
1101 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI   0x0004
1102 #define SUNI1x10GEXP_BITMSK_RXOAM_HECI           0x0002
1103 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI           0x0001
1104 
1105 /*----------------------------------------------------------------------------
1106  * Register 0x20C9: RXOAM Status
1107  *    Bit 10 RXOAM_FILTER_THRSHV
1108  *    Bit 8  RXOAM_HECE_THRSHV
1109  *    Bit 6  RXOAM_RFV
1110  *    Bit 5  RXOAM_LFV
1111  *----------------------------------------------------------------------------*/
1112 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV  0x0400
1113 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV    0x0100
1114 #define SUNI1x10GEXP_BITMSK_RXOAM_RFV            0x0040
1115 #define SUNI1x10GEXP_BITMSK_RXOAM_LFV            0x0020
1116 
1117 /*----------------------------------------------------------------------------
1118  * Register 0x2100: MSTAT Control
1119  *    Bit 2 MSTAT_WRITE
1120  *    Bit 1 MSTAT_CLEAR
1121  *    Bit 0 MSTAT_SNAP
1122  *----------------------------------------------------------------------------*/
1123 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE  0x0004
1124 #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR  0x0002
1125 #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP   0x0001
1126 
1127 /*----------------------------------------------------------------------------
1128  * Register 0x2109: MSTAT Counter Write Address
1129  *    Bit 5-0 MSTAT_WRITE_ADDRESS
1130  *----------------------------------------------------------------------------*/
1131 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1132 #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1133 
1134 /*----------------------------------------------------------------------------
1135  * Register 0x2200: IFLX Global Configuration Register
1136  *    Bit 15   IFLX_IRCU_ENABLE
1137  *    Bit 14   IFLX_IDSWT_ENABLE
1138  *    Bit 13-0 IFLX_IFD_CNT
1139  *----------------------------------------------------------------------------*/
1140 #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE   0x8000
1141 #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE  0x4000
1142 #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT       0x3FFF
1143 #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT       0
1144 
1145 /*----------------------------------------------------------------------------
1146  * Register 0x2209: IFLX FIFO Overflow Enable
1147  *    Bit 0 IFLX_OVFE
1148  *----------------------------------------------------------------------------*/
1149 #define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1150 
1151 /*----------------------------------------------------------------------------
1152  * Register 0x220A: IFLX FIFO Overflow Interrupt
1153  *    Bit 0 IFLX_OVFI
1154  *----------------------------------------------------------------------------*/
1155 #define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1156 
1157 /*----------------------------------------------------------------------------
1158  * Register 0x220D: IFLX Indirect Channel Address
1159  *    Bit 15 IFLX_BUSY
1160  *    Bit 14 IFLX_RWB
1161  *----------------------------------------------------------------------------*/
1162 #define SUNI1x10GEXP_BITMSK_IFLX_BUSY  0x8000
1163 #define SUNI1x10GEXP_BITMSK_IFLX_RWB   0x4000
1164 
1165 /*----------------------------------------------------------------------------
1166  * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1167  *    Bit 9-0 IFLX_LOLIM
1168  *----------------------------------------------------------------------------*/
1169 #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM  0x03FF
1170 #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM  0
1171 
1172 /*----------------------------------------------------------------------------
1173  * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1174  *    Bit 9-0 IFLX_HILIM
1175  *----------------------------------------------------------------------------*/
1176 #define SUNI1x10GEXP_BITMSK_IFLX_HILIM  0x03FF
1177 #define SUNI1x10GEXP_BITOFF_IFLX_HILIM  0
1178 
1179 /*----------------------------------------------------------------------------
1180  * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1181  *    Bit 15   IFLX_FULL
1182  *    Bit 14   IFLX_AFULL
1183  *    Bit 13-0 IFLX_AFTH
1184  *----------------------------------------------------------------------------*/
1185 #define SUNI1x10GEXP_BITMSK_IFLX_FULL   0x8000
1186 #define SUNI1x10GEXP_BITMSK_IFLX_AFULL  0x4000
1187 #define SUNI1x10GEXP_BITMSK_IFLX_AFTH   0x3FFF
1188 #define SUNI1x10GEXP_BITOFF_IFLX_AFTH   0
1189 
1190 /*----------------------------------------------------------------------------
1191  * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1192  *    Bit 15   IFLX_EMPTY
1193  *    Bit 14   IFLX_AEMPTY
1194  *    Bit 13-0 IFLX_AETH
1195  *----------------------------------------------------------------------------*/
1196 #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY   0x8000
1197 #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY  0x4000
1198 #define SUNI1x10GEXP_BITMSK_IFLX_AETH    0x3FFF
1199 #define SUNI1x10GEXP_BITOFF_IFLX_AETH    0
1200 
1201 /*----------------------------------------------------------------------------
1202  * Register 0x2240: PL4MOS Configuration Register
1203  *    Bit 3 PL4MOS_RE_INIT
1204  *    Bit 2 PL4MOS_EN
1205  *    Bit 1 PL4MOS_NO_STATUS
1206  *----------------------------------------------------------------------------*/
1207 #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT          0x0008
1208 #define SUNI1x10GEXP_BITMSK_PL4MOS_EN               0x0004
1209 #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS        0x0002
1210 
1211 /*----------------------------------------------------------------------------
1212  * Register 0x2243: PL4MOS MaxBurst1 Register
1213  *    Bit 11-0 PL4MOS_MAX_BURST1
1214  *----------------------------------------------------------------------------*/
1215 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1  0x0FFF
1216 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1  0
1217 
1218 /*----------------------------------------------------------------------------
1219  * Register 0x2244: PL4MOS MaxBurst2 Register
1220  *    Bit 11-0 PL4MOS_MAX_BURST2
1221  *----------------------------------------------------------------------------*/
1222 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2  0x0FFF
1223 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2  0
1224 
1225 /*----------------------------------------------------------------------------
1226  * Register 0x2245: PL4MOS Transfer Size Register
1227  *    Bit 7-0 PL4MOS_MAX_TRANSFER
1228  *----------------------------------------------------------------------------*/
1229 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER  0x00FF
1230 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER  0
1231 
1232 /*----------------------------------------------------------------------------
1233  * Register 0x2280: PL4ODP Configuration
1234  *    Bit 15-12 PL4ODP_REPEAT_T
1235  *    Bit 8     PL4ODP_SOP_RULE
1236  *    Bit 1     PL4ODP_EN_PORTS
1237  *    Bit 0     PL4ODP_EN_DFWD
1238  *----------------------------------------------------------------------------*/
1239 #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T   0xF000
1240 #define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T   12
1241 #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE   0x0100
1242 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS   0x0002
1243 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD    0x0001
1244 
1245 /*----------------------------------------------------------------------------
1246  * Register 0x2282: PL4ODP Interrupt Mask
1247  *    Bit 0 PL4ODP_OUT_DISE
1248  *----------------------------------------------------------------------------*/
1249 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE     0x0001
1250 
1251 
1252 
1253 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE  0x0080
1254 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE  0x0040
1255 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE    0x0008
1256 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE    0x0004
1257 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE      0x0002
1258 
1259 
1260 /*----------------------------------------------------------------------------
1261  * Register 0x2283: PL4ODP Interrupt
1262  *    Bit 0 PL4ODP_OUT_DISI
1263  *----------------------------------------------------------------------------*/
1264 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI     0x0001
1265 
1266 
1267 
1268 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI  0x0080
1269 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI  0x0040
1270 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI    0x0008
1271 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI    0x0004
1272 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI      0x0002
1273 
1274 /*----------------------------------------------------------------------------
1275  * Register 0x2300:  PL4IO Lock Detect Status
1276  *    Bit 15 PL4IO_OUT_ROOLV
1277  *    Bit 12 PL4IO_IS_ROOLV
1278  *    Bit 11 PL4IO_DIP2_ERRV
1279  *    Bit 8  PL4IO_ID_ROOLV
1280  *    Bit 4  PL4IO_IS_DOOLV
1281  *    Bit 0  PL4IO_ID_DOOLV
1282  *----------------------------------------------------------------------------*/
1283 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV  0x8000
1284 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV   0x1000
1285 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV  0x0800
1286 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV   0x0100
1287 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV   0x0010
1288 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV   0x0001
1289 
1290 /*----------------------------------------------------------------------------
1291  * Register 0x2301:  PL4IO Lock Detect Change
1292  *    Bit 15 PL4IO_OUT_ROOLI
1293  *    Bit 12 PL4IO_IS_ROOLI
1294  *    Bit 11 PL4IO_DIP2_ERRI
1295  *    Bit 8  PL4IO_ID_ROOLI
1296  *    Bit 4  PL4IO_IS_DOOLI
1297  *    Bit 0  PL4IO_ID_DOOLI
1298  *----------------------------------------------------------------------------*/
1299 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI  0x8000
1300 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI   0x1000
1301 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI  0x0800
1302 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI   0x0100
1303 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI   0x0010
1304 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI   0x0001
1305 
1306 /*----------------------------------------------------------------------------
1307  * Register 0x2302:  PL4IO Lock Detect Mask
1308  *    Bit 15 PL4IO_OUT_ROOLE
1309  *    Bit 12 PL4IO_IS_ROOLE
1310  *    Bit 11 PL4IO_DIP2_ERRE
1311  *    Bit 8  PL4IO_ID_ROOLE
1312  *    Bit 4  PL4IO_IS_DOOLE
1313  *    Bit 0  PL4IO_ID_DOOLE
1314  *----------------------------------------------------------------------------*/
1315 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE  0x8000
1316 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE   0x1000
1317 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE  0x0800
1318 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE   0x0100
1319 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE   0x0010
1320 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE   0x0001
1321 
1322 /*----------------------------------------------------------------------------
1323  * Register 0x2303:  PL4IO Lock Detect Limits
1324  *    Bit 15-8 PL4IO_REF_LIMIT
1325  *    Bit 7-0  PL4IO_TRAN_LIMIT
1326  *----------------------------------------------------------------------------*/
1327 #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT   0xFF00
1328 #define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT   8
1329 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT  0x00FF
1330 #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT  0
1331 
1332 /*----------------------------------------------------------------------------
1333  * Register 0x2304:  PL4IO Calendar Repetitions
1334  *    Bit 15-8 PL4IO_IN_MUL
1335  *    Bit 7-0  PL4IO_OUT_MUL
1336  *----------------------------------------------------------------------------*/
1337 #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL   0xFF00
1338 #define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL   8
1339 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL  0x00FF
1340 #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL  0
1341 
1342 /*----------------------------------------------------------------------------
1343  * Register 0x2305:  PL4IO Configuration
1344  *    Bit 15  PL4IO_DIP2_ERR_CHK
1345  *    Bit 11  PL4IO_ODAT_DIS
1346  *    Bit 10  PL4IO_TRAIN_DIS
1347  *    Bit 9   PL4IO_OSTAT_DIS
1348  *    Bit 8   PL4IO_ISTAT_DIS
1349  *    Bit 7   PL4IO_NO_ISTAT
1350  *    Bit 6   PL4IO_STAT_OUTSEL
1351  *    Bit 5   PL4IO_INSEL
1352  *    Bit 4   PL4IO_DLSEL
1353  *    Bit 1-0 PL4IO_OUTSEL
1354  *----------------------------------------------------------------------------*/
1355 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK  0x8000
1356 #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS      0x0800
1357 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS     0x0400
1358 #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS     0x0200
1359 #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS     0x0100
1360 #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT      0x0080
1361 #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL   0x0040
1362 #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL         0x0020
1363 #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL         0x0010
1364 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL        0x0003
1365 #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL        0
1366 
1367 /*----------------------------------------------------------------------------
1368  * Register 0x3040: TXXG Configuration Register 1
1369  *    Bit 15   TXXG_TXEN0
1370  *    Bit 13   TXXG_HOSTPAUSE
1371  *    Bit 12-7 TXXG_IPGT
1372  *    Bit 5    TXXG_32BIT_ALIGN
1373  *    Bit 4    TXXG_CRCEN
1374  *    Bit 3    TXXG_FCTX
1375  *    Bit 2    TXXG_FCRX
1376  *    Bit 1    TXXG_PADEN
1377  *    Bit 0    TXXG_SPRE
1378  *----------------------------------------------------------------------------*/
1379 #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0        0x8000
1380 #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE    0x2000
1381 #define SUNI1x10GEXP_BITMSK_TXXG_IPGT         0x1F80
1382 #define SUNI1x10GEXP_BITOFF_TXXG_IPGT         7
1383 #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN  0x0020
1384 #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN        0x0010
1385 #define SUNI1x10GEXP_BITMSK_TXXG_FCTX         0x0008
1386 #define SUNI1x10GEXP_BITMSK_TXXG_FCRX         0x0004
1387 #define SUNI1x10GEXP_BITMSK_TXXG_PADEN        0x0002
1388 #define SUNI1x10GEXP_BITMSK_TXXG_SPRE         0x0001
1389 
1390 /*----------------------------------------------------------------------------
1391  * Register 0x3041: TXXG Configuration Register 2
1392  *    Bit 7-0   TXXG_HDRSIZE
1393  *----------------------------------------------------------------------------*/
1394 #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE  0x00FF
1395 
1396 /*----------------------------------------------------------------------------
1397  * Register 0x3042: TXXG Configuration Register 3
1398  *    Bit 15 TXXG_FIFO_ERRE
1399  *    Bit 14 TXXG_FIFO_UDRE
1400  *    Bit 13 TXXG_MAX_LERRE
1401  *    Bit 12 TXXG_MIN_LERRE
1402  *    Bit 11 TXXG_XFERE
1403  *----------------------------------------------------------------------------*/
1404 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE  0x8000
1405 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE  0x4000
1406 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE  0x2000
1407 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE  0x1000
1408 #define SUNI1x10GEXP_BITMSK_TXXG_XFERE      0x0800
1409 
1410 /*----------------------------------------------------------------------------
1411  * Register 0x3043: TXXG Interrupt
1412  *    Bit 15 TXXG_FIFO_ERRI
1413  *    Bit 14 TXXG_FIFO_UDRI
1414  *    Bit 13 TXXG_MAX_LERRI
1415  *    Bit 12 TXXG_MIN_LERRI
1416  *    Bit 11 TXXG_XFERI
1417  *----------------------------------------------------------------------------*/
1418 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI  0x8000
1419 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI  0x4000
1420 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI  0x2000
1421 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI  0x1000
1422 #define SUNI1x10GEXP_BITMSK_TXXG_XFERI      0x0800
1423 
1424 /*----------------------------------------------------------------------------
1425  * Register 0x3044: TXXG Status Register
1426  *    Bit 1 TXXG_TXACTIVE
1427  *    Bit 0 TXXG_PAUSED
1428  *----------------------------------------------------------------------------*/
1429 #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE  0x0002
1430 #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED    0x0001
1431 
1432 /*----------------------------------------------------------------------------
1433  * Register 0x3046: TXXG TX_MINFR -  Transmit Min Frame Size Register
1434  *    Bit 7-0 TXXG_TX_MINFR
1435  *----------------------------------------------------------------------------*/
1436 #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR  0x00FF
1437 #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR  0
1438 
1439 /*----------------------------------------------------------------------------
1440  * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1441  *    Bit 7-0 TXXG_FC_PAUSE_QNTM
1442  *----------------------------------------------------------------------------*/
1443 #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM  0x00FF
1444 #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM  0
1445 
1446 /*----------------------------------------------------------------------------
1447  * Register 0x3080: XTEF Control
1448  *    Bit 3-0 XTEF_FORCE_PARITY_ERR
1449  *----------------------------------------------------------------------------*/
1450 #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR  0x000F
1451 #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR  0
1452 
1453 /*----------------------------------------------------------------------------
1454  * Register 0x3084: XTEF Interrupt Event Register
1455  *    Bit 0 XTEF_LOST_SYNCI
1456  *----------------------------------------------------------------------------*/
1457 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI  0x0001
1458 
1459 /*----------------------------------------------------------------------------
1460  * Register 0x3085: XTEF Interrupt Enable Register
1461  *    Bit 0 XTEF_LOST_SYNCE
1462  *----------------------------------------------------------------------------*/
1463 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE  0x0001
1464 
1465 /*----------------------------------------------------------------------------
1466  * Register 0x3086: XTEF Visibility Register
1467  *    Bit 0 XTEF_LOST_SYNCV
1468  *----------------------------------------------------------------------------*/
1469 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV  0x0001
1470 
1471 /*----------------------------------------------------------------------------
1472  * Register 0x30C0: TXOAM OAM Configuration
1473  *    Bit 15   TXOAM_HEC_EN
1474  *    Bit 14   TXOAM_EMPTYCODE_EN
1475  *    Bit 13   TXOAM_FORCE_IDLE
1476  *    Bit 12   TXOAM_IGNORE_IDLE
1477  *    Bit 11-6 TXOAM_PX_OVERWRITE
1478  *    Bit 5-0  TXOAM_PX_SEL
1479  *----------------------------------------------------------------------------*/
1480 #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN        0x8000
1481 #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN  0x4000
1482 #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE    0x2000
1483 #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE   0x1000
1484 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE  0x0FC0
1485 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE  6
1486 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL        0x003F
1487 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL        0
1488 
1489 /*----------------------------------------------------------------------------
1490  * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1491  *    Bit 15   TXOAM_MINIDIS
1492  *    Bit 14   TXOAM_BUSY
1493  *    Bit 13   TXOAM_TRANS_EN
1494  *    Bit 10-0 TXOAM_MINIRATE
1495  *----------------------------------------------------------------------------*/
1496 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS   0x8000
1497 #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY      0x4000
1498 #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN  0x2000
1499 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE  0x07FF
1500 
1501 /*----------------------------------------------------------------------------
1502  * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1503  *    Bit 13-10 TXOAM_FTHRESH
1504  *    Bit 9-6   TXOAM_MINIPOST
1505  *    Bit 5-0   TXOAM_MINIPRE
1506  *----------------------------------------------------------------------------*/
1507 #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH   0x3C00
1508 #define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH   10
1509 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST  0x03C0
1510 #define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST  6
1511 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE   0x003F
1512 
1513 /*----------------------------------------------------------------------------
1514  * Register 0x30C6: TXOAM Interrupt Enable
1515  *    Bit 2 TXOAM_SOP_ERRE
1516  *    Bit 1 TXOAM_OFLE
1517  *    Bit 0 TXOAM_ERRE
1518  *----------------------------------------------------------------------------*/
1519 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE    0x0004
1520 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE        0x0002
1521 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE        0x0001
1522 
1523 /*----------------------------------------------------------------------------
1524  * Register 0x30C7: TXOAM Interrupt Status
1525  *    Bit 2 TXOAM_SOP_ERRI
1526  *    Bit 1 TXOAM_OFLI
1527  *    Bit 0 TXOAM_ERRI
1528  *----------------------------------------------------------------------------*/
1529 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI    0x0004
1530 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI        0x0002
1531 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI        0x0001
1532 
1533 /*----------------------------------------------------------------------------
1534  * Register 0x30CF: TXOAM Coset
1535  *    Bit 7-0 TXOAM_COSET
1536  *----------------------------------------------------------------------------*/
1537 #define SUNI1x10GEXP_BITMSK_TXOAM_COSET  0x00FF
1538 
1539 /*----------------------------------------------------------------------------
1540  * Register 0x3200: EFLX Global Configuration
1541  *    Bit 15 EFLX_ERCU_EN
1542  *    Bit 7  EFLX_EN_EDSWT
1543  *----------------------------------------------------------------------------*/
1544 #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN   0x8000
1545 #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT  0x0080
1546 
1547 /*----------------------------------------------------------------------------
1548  * Register 0x3201: EFLX ERCU Global Status
1549  *    Bit 13 EFLX_OVF_ERR
1550  *----------------------------------------------------------------------------*/
1551 #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR  0x2000
1552 
1553 /*----------------------------------------------------------------------------
1554  * Register 0x3202: EFLX Indirect Channel Address
1555  *    Bit 15 EFLX_BUSY
1556  *    Bit 14 EFLX_RDWRB
1557  *----------------------------------------------------------------------------*/
1558 #define SUNI1x10GEXP_BITMSK_EFLX_BUSY   0x8000
1559 #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB  0x4000
1560 
1561 /*----------------------------------------------------------------------------
1562  * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1563  *----------------------------------------------------------------------------*/
1564 #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM                    0x03FF
1565 #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM                    0
1566 
1567 /*----------------------------------------------------------------------------
1568  * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1569  *----------------------------------------------------------------------------*/
1570 #define SUNI1x10GEXP_BITMSK_EFLX_HILIM                    0x03FF
1571 #define SUNI1x10GEXP_BITOFF_EFLX_HILIM                    0
1572 
1573 /*----------------------------------------------------------------------------
1574  * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1575  *    Bit 15   EFLX_FULL
1576  *    Bit 14   EFLX_AFULL
1577  *    Bit 13-0 EFLX_AFTH
1578  *----------------------------------------------------------------------------*/
1579 #define SUNI1x10GEXP_BITMSK_EFLX_FULL   0x8000
1580 #define SUNI1x10GEXP_BITMSK_EFLX_AFULL  0x4000
1581 #define SUNI1x10GEXP_BITMSK_EFLX_AFTH   0x3FFF
1582 #define SUNI1x10GEXP_BITOFF_EFLX_AFTH   0
1583 
1584 /*----------------------------------------------------------------------------
1585  * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1586  *    Bit 15   EFLX_EMPTY
1587  *    Bit 14   EFLX_AEMPTY
1588  *    Bit 13-0 EFLX_AETH
1589  *----------------------------------------------------------------------------*/
1590 #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY   0x8000
1591 #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY  0x4000
1592 #define SUNI1x10GEXP_BITMSK_EFLX_AETH    0x3FFF
1593 #define SUNI1x10GEXP_BITOFF_EFLX_AETH    0
1594 
1595 /*----------------------------------------------------------------------------
1596  * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1597  *----------------------------------------------------------------------------*/
1598 #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU                 0x3FFF
1599 #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU                 0
1600 
1601 /*----------------------------------------------------------------------------
1602  * Register 0x320C: EFLX FIFO Overflow Error Enable
1603  *    Bit 0 EFLX_OVFE
1604  *----------------------------------------------------------------------------*/
1605 #define SUNI1x10GEXP_BITMSK_EFLX_OVFE  0x0001
1606 
1607 /*----------------------------------------------------------------------------
1608  * Register 0x320D: EFLX FIFO Overflow Error Indication
1609  *    Bit 0 EFLX_OVFI
1610  *----------------------------------------------------------------------------*/
1611 #define SUNI1x10GEXP_BITMSK_EFLX_OVFI  0x0001
1612 
1613 /*----------------------------------------------------------------------------
1614  * Register 0x3210: EFLX Channel Provision
1615  *    Bit 0 EFLX_PROV
1616  *----------------------------------------------------------------------------*/
1617 #define SUNI1x10GEXP_BITMSK_EFLX_PROV  0x0001
1618 
1619 /*----------------------------------------------------------------------------
1620  * Register 0x3280: PL4IDU Configuration
1621  *    Bit 2 PL4IDU_SYNCH_ON_TRAIN
1622  *    Bit 1 PL4IDU_EN_PORTS
1623  *    Bit 0 PL4IDU_EN_DFWD
1624  *----------------------------------------------------------------------------*/
1625 #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN  0x0004
1626 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS        0x0002
1627 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD         0x0001
1628 
1629 /*----------------------------------------------------------------------------
1630  * Register 0x3282: PL4IDU Interrupt Mask
1631  *    Bit 1 PL4IDU_DIP4E
1632  *----------------------------------------------------------------------------*/
1633 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E       0x0002
1634 
1635 /*----------------------------------------------------------------------------
1636  * Register 0x3283: PL4IDU Interrupt
1637  *    Bit 1 PL4IDU_DIP4I
1638  *----------------------------------------------------------------------------*/
1639 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I       0x0002
1640 
1641 #endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
1642 
1643