1 /*****************************************************************************
2  *                                                                           *
3  * File: regs.h                                                              *
4  * $Revision: 1.8 $                                                          *
5  * $Date: 2005/06/21 18:29:48 $                                              *
6  * Description:                                                              *
7  *  part of the Chelsio 10Gb Ethernet Driver.                                *
8  *                                                                           *
9  * This program is free software; you can redistribute it and/or modify      *
10  * it under the terms of the GNU General Public License, version 2, as       *
11  * published by the Free Software Foundation.                                *
12  *                                                                           *
13  * You should have received a copy of the GNU General Public License along   *
14  * with this program; if not, see <http://www.gnu.org/licenses/>.            *
15  *                                                                           *
16  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
17  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
19  *                                                                           *
20  * http://www.chelsio.com                                                    *
21  *                                                                           *
22  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
23  * All rights reserved.                                                      *
24  *                                                                           *
25  * Maintainers: maintainers@chelsio.com                                      *
26  *                                                                           *
27  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
28  *          Tina Yang               <tainay@chelsio.com>                     *
29  *          Felix Marti             <felix@chelsio.com>                      *
30  *          Scott Bardone           <sbardone@chelsio.com>                   *
31  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
32  *          Frank DiMambro          <frank@chelsio.com>                      *
33  *                                                                           *
34  * History:                                                                  *
35  *                                                                           *
36  ****************************************************************************/
37 
38 #ifndef _CXGB_REGS_H_
39 #define _CXGB_REGS_H_
40 
41 /* SGE registers */
42 #define A_SG_CONTROL 0x0
43 
44 #define S_CMDQ0_ENABLE    0
45 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
46 #define F_CMDQ0_ENABLE    V_CMDQ0_ENABLE(1U)
47 
48 #define S_CMDQ1_ENABLE    1
49 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
50 #define F_CMDQ1_ENABLE    V_CMDQ1_ENABLE(1U)
51 
52 #define S_FL0_ENABLE    2
53 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
54 #define F_FL0_ENABLE    V_FL0_ENABLE(1U)
55 
56 #define S_FL1_ENABLE    3
57 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
58 #define F_FL1_ENABLE    V_FL1_ENABLE(1U)
59 
60 #define S_CPL_ENABLE    4
61 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
62 #define F_CPL_ENABLE    V_CPL_ENABLE(1U)
63 
64 #define S_RESPONSE_QUEUE_ENABLE    5
65 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
66 #define F_RESPONSE_QUEUE_ENABLE    V_RESPONSE_QUEUE_ENABLE(1U)
67 
68 #define S_CMDQ_PRIORITY    6
69 #define M_CMDQ_PRIORITY    0x3
70 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
71 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
72 
73 #define S_DISABLE_CMDQ0_GTS    8
74 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
75 #define F_DISABLE_CMDQ0_GTS    V_DISABLE_CMDQ0_GTS(1U)
76 
77 #define S_DISABLE_CMDQ1_GTS    9
78 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
79 #define F_DISABLE_CMDQ1_GTS    V_DISABLE_CMDQ1_GTS(1U)
80 
81 #define S_DISABLE_FL0_GTS    10
82 #define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
83 #define F_DISABLE_FL0_GTS    V_DISABLE_FL0_GTS(1U)
84 
85 #define S_DISABLE_FL1_GTS    11
86 #define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
87 #define F_DISABLE_FL1_GTS    V_DISABLE_FL1_GTS(1U)
88 
89 #define S_ENABLE_BIG_ENDIAN    12
90 #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
91 #define F_ENABLE_BIG_ENDIAN    V_ENABLE_BIG_ENDIAN(1U)
92 
93 #define S_FL_SELECTION_CRITERIA    13
94 #define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
95 #define F_FL_SELECTION_CRITERIA    V_FL_SELECTION_CRITERIA(1U)
96 
97 #define S_ISCSI_COALESCE    14
98 #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
99 #define F_ISCSI_COALESCE    V_ISCSI_COALESCE(1U)
100 
101 #define S_RX_PKT_OFFSET    15
102 #define M_RX_PKT_OFFSET    0x7
103 #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
104 #define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
105 
106 #define S_VLAN_XTRACT    18
107 #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
108 #define F_VLAN_XTRACT    V_VLAN_XTRACT(1U)
109 
110 #define A_SG_DOORBELL 0x4
111 #define A_SG_CMD0BASELWR 0x8
112 #define A_SG_CMD0BASEUPR 0xc
113 #define A_SG_CMD1BASELWR 0x10
114 #define A_SG_CMD1BASEUPR 0x14
115 #define A_SG_FL0BASELWR 0x18
116 #define A_SG_FL0BASEUPR 0x1c
117 #define A_SG_FL1BASELWR 0x20
118 #define A_SG_FL1BASEUPR 0x24
119 #define A_SG_CMD0SIZE 0x28
120 
121 #define S_CMDQ0_SIZE    0
122 #define M_CMDQ0_SIZE    0x1ffff
123 #define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
124 #define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
125 
126 #define A_SG_FL0SIZE 0x2c
127 
128 #define S_FL0_SIZE    0
129 #define M_FL0_SIZE    0x1ffff
130 #define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
131 #define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
132 
133 #define A_SG_RSPSIZE 0x30
134 
135 #define S_RESPQ_SIZE    0
136 #define M_RESPQ_SIZE    0x1ffff
137 #define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
138 #define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
139 
140 #define A_SG_RSPBASELWR 0x34
141 #define A_SG_RSPBASEUPR 0x38
142 #define A_SG_FLTHRESHOLD 0x3c
143 
144 #define S_FL_THRESHOLD    0
145 #define M_FL_THRESHOLD    0xffff
146 #define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
147 #define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
148 
149 #define A_SG_RSPQUEUECREDIT 0x40
150 
151 #define S_RESPQ_CREDIT    0
152 #define M_RESPQ_CREDIT    0x1ffff
153 #define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
154 #define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
155 
156 #define A_SG_SLEEPING 0x48
157 
158 #define S_SLEEPING    0
159 #define M_SLEEPING    0xffff
160 #define V_SLEEPING(x) ((x) << S_SLEEPING)
161 #define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
162 
163 #define A_SG_INTRTIMER 0x4c
164 
165 #define S_INTERRUPT_TIMER_COUNT    0
166 #define M_INTERRUPT_TIMER_COUNT    0xffffff
167 #define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
168 #define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
169 
170 #define A_SG_CMD0PTR 0x50
171 
172 #define S_CMDQ0_POINTER    0
173 #define M_CMDQ0_POINTER    0xffff
174 #define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
175 #define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
176 
177 #define S_CURRENT_GENERATION_BIT    16
178 #define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
179 #define F_CURRENT_GENERATION_BIT    V_CURRENT_GENERATION_BIT(1U)
180 
181 #define A_SG_CMD1PTR 0x54
182 
183 #define S_CMDQ1_POINTER    0
184 #define M_CMDQ1_POINTER    0xffff
185 #define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
186 #define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
187 
188 #define A_SG_FL0PTR 0x58
189 
190 #define S_FL0_POINTER    0
191 #define M_FL0_POINTER    0xffff
192 #define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
193 #define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
194 
195 #define A_SG_FL1PTR 0x5c
196 
197 #define S_FL1_POINTER    0
198 #define M_FL1_POINTER    0xffff
199 #define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
200 #define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
201 
202 #define A_SG_VERSION 0x6c
203 
204 #define S_DAY    0
205 #define M_DAY    0x1f
206 #define V_DAY(x) ((x) << S_DAY)
207 #define G_DAY(x) (((x) >> S_DAY) & M_DAY)
208 
209 #define S_MONTH    5
210 #define M_MONTH    0xf
211 #define V_MONTH(x) ((x) << S_MONTH)
212 #define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
213 
214 #define A_SG_CMD1SIZE 0xb0
215 
216 #define S_CMDQ1_SIZE    0
217 #define M_CMDQ1_SIZE    0x1ffff
218 #define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
219 #define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
220 
221 #define A_SG_FL1SIZE 0xb4
222 
223 #define S_FL1_SIZE    0
224 #define M_FL1_SIZE    0x1ffff
225 #define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
226 #define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
227 
228 #define A_SG_INT_ENABLE 0xb8
229 
230 #define S_RESPQ_EXHAUSTED    0
231 #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
232 #define F_RESPQ_EXHAUSTED    V_RESPQ_EXHAUSTED(1U)
233 
234 #define S_RESPQ_OVERFLOW    1
235 #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
236 #define F_RESPQ_OVERFLOW    V_RESPQ_OVERFLOW(1U)
237 
238 #define S_FL_EXHAUSTED    2
239 #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
240 #define F_FL_EXHAUSTED    V_FL_EXHAUSTED(1U)
241 
242 #define S_PACKET_TOO_BIG    3
243 #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
244 #define F_PACKET_TOO_BIG    V_PACKET_TOO_BIG(1U)
245 
246 #define S_PACKET_MISMATCH    4
247 #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
248 #define F_PACKET_MISMATCH    V_PACKET_MISMATCH(1U)
249 
250 #define A_SG_INT_CAUSE 0xbc
251 #define A_SG_RESPACCUTIMER 0xc0
252 
253 /* MC3 registers */
254 #define A_MC3_CFG 0x100
255 
256 #define S_CLK_ENABLE    0
257 #define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
258 #define F_CLK_ENABLE    V_CLK_ENABLE(1U)
259 
260 #define S_READY    1
261 #define V_READY(x) ((x) << S_READY)
262 #define F_READY    V_READY(1U)
263 
264 #define S_READ_TO_WRITE_DELAY    2
265 #define M_READ_TO_WRITE_DELAY    0x7
266 #define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
267 #define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
268 
269 #define S_WRITE_TO_READ_DELAY    5
270 #define M_WRITE_TO_READ_DELAY    0x7
271 #define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
272 #define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
273 
274 #define S_MC3_BANK_CYCLE    8
275 #define M_MC3_BANK_CYCLE    0xf
276 #define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
277 #define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
278 
279 #define S_REFRESH_CYCLE    12
280 #define M_REFRESH_CYCLE    0xf
281 #define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
282 #define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
283 
284 #define S_PRECHARGE_CYCLE    16
285 #define M_PRECHARGE_CYCLE    0x3
286 #define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
287 #define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
288 
289 #define S_ACTIVE_TO_READ_WRITE_DELAY    18
290 #define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
291 #define F_ACTIVE_TO_READ_WRITE_DELAY    V_ACTIVE_TO_READ_WRITE_DELAY(1U)
292 
293 #define S_ACTIVE_TO_PRECHARGE_DELAY    19
294 #define M_ACTIVE_TO_PRECHARGE_DELAY    0x7
295 #define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
296 #define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
297 
298 #define S_WRITE_RECOVERY_DELAY    22
299 #define M_WRITE_RECOVERY_DELAY    0x3
300 #define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
301 #define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
302 
303 #define S_DENSITY    24
304 #define M_DENSITY    0x3
305 #define V_DENSITY(x) ((x) << S_DENSITY)
306 #define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
307 
308 #define S_ORGANIZATION    26
309 #define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
310 #define F_ORGANIZATION    V_ORGANIZATION(1U)
311 
312 #define S_BANKS    27
313 #define V_BANKS(x) ((x) << S_BANKS)
314 #define F_BANKS    V_BANKS(1U)
315 
316 #define S_UNREGISTERED    28
317 #define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
318 #define F_UNREGISTERED    V_UNREGISTERED(1U)
319 
320 #define S_MC3_WIDTH    29
321 #define M_MC3_WIDTH    0x3
322 #define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
323 #define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
324 
325 #define S_MC3_SLOW    31
326 #define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
327 #define F_MC3_SLOW    V_MC3_SLOW(1U)
328 
329 #define A_MC3_MODE 0x104
330 
331 #define S_MC3_MODE    0
332 #define M_MC3_MODE    0x3fff
333 #define V_MC3_MODE(x) ((x) << S_MC3_MODE)
334 #define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
335 
336 #define S_BUSY    31
337 #define V_BUSY(x) ((x) << S_BUSY)
338 #define F_BUSY    V_BUSY(1U)
339 
340 #define A_MC3_EXT_MODE 0x108
341 
342 #define S_MC3_EXTENDED_MODE    0
343 #define M_MC3_EXTENDED_MODE    0x3fff
344 #define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
345 #define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
346 
347 #define A_MC3_PRECHARG 0x10c
348 #define A_MC3_REFRESH 0x110
349 
350 #define S_REFRESH_ENABLE    0
351 #define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
352 #define F_REFRESH_ENABLE    V_REFRESH_ENABLE(1U)
353 
354 #define S_REFRESH_DIVISOR    1
355 #define M_REFRESH_DIVISOR    0x3fff
356 #define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
357 #define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
358 
359 #define A_MC3_STROBE 0x114
360 
361 #define S_MASTER_DLL_RESET    0
362 #define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
363 #define F_MASTER_DLL_RESET    V_MASTER_DLL_RESET(1U)
364 
365 #define S_MASTER_DLL_TAP_COUNT    1
366 #define M_MASTER_DLL_TAP_COUNT    0xff
367 #define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
368 #define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
369 
370 #define S_MASTER_DLL_LOCKED    9
371 #define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
372 #define F_MASTER_DLL_LOCKED    V_MASTER_DLL_LOCKED(1U)
373 
374 #define S_MASTER_DLL_MAX_TAP_COUNT    10
375 #define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
376 #define F_MASTER_DLL_MAX_TAP_COUNT    V_MASTER_DLL_MAX_TAP_COUNT(1U)
377 
378 #define S_MASTER_DLL_TAP_COUNT_OFFSET    11
379 #define M_MASTER_DLL_TAP_COUNT_OFFSET    0x3f
380 #define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
381 #define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
382 
383 #define S_SLAVE_DLL_RESET    11
384 #define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
385 #define F_SLAVE_DLL_RESET    V_SLAVE_DLL_RESET(1U)
386 
387 #define S_SLAVE_DLL_DELTA    12
388 #define M_SLAVE_DLL_DELTA    0xf
389 #define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
390 #define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
391 
392 #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT    17
393 #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT    0x3f
394 #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
395 #define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
396 
397 #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE    23
398 #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
399 #define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE    V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
400 
401 #define S_SLAVE_DELAY_LINE_TAP_COUNT    24
402 #define M_SLAVE_DELAY_LINE_TAP_COUNT    0x3f
403 #define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
404 #define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
405 
406 #define A_MC3_ECC_CNTL 0x118
407 
408 #define S_ECC_GENERATION_ENABLE    0
409 #define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
410 #define F_ECC_GENERATION_ENABLE    V_ECC_GENERATION_ENABLE(1U)
411 
412 #define S_ECC_CHECK_ENABLE    1
413 #define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
414 #define F_ECC_CHECK_ENABLE    V_ECC_CHECK_ENABLE(1U)
415 
416 #define S_CORRECTABLE_ERROR_COUNT    2
417 #define M_CORRECTABLE_ERROR_COUNT    0xff
418 #define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
419 #define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
420 
421 #define S_UNCORRECTABLE_ERROR_COUNT    10
422 #define M_UNCORRECTABLE_ERROR_COUNT    0xff
423 #define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
424 #define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
425 
426 #define A_MC3_CE_ADDR 0x11c
427 
428 #define S_MC3_CE_ADDR    4
429 #define M_MC3_CE_ADDR    0xfffffff
430 #define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
431 #define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
432 
433 #define A_MC3_CE_DATA0 0x120
434 #define A_MC3_CE_DATA1 0x124
435 #define A_MC3_CE_DATA2 0x128
436 #define A_MC3_CE_DATA3 0x12c
437 #define A_MC3_CE_DATA4 0x130
438 #define A_MC3_UE_ADDR 0x134
439 
440 #define S_MC3_UE_ADDR    4
441 #define M_MC3_UE_ADDR    0xfffffff
442 #define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
443 #define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
444 
445 #define A_MC3_UE_DATA0 0x138
446 #define A_MC3_UE_DATA1 0x13c
447 #define A_MC3_UE_DATA2 0x140
448 #define A_MC3_UE_DATA3 0x144
449 #define A_MC3_UE_DATA4 0x148
450 #define A_MC3_BD_ADDR 0x14c
451 #define A_MC3_BD_DATA0 0x150
452 #define A_MC3_BD_DATA1 0x154
453 #define A_MC3_BD_DATA2 0x158
454 #define A_MC3_BD_DATA3 0x15c
455 #define A_MC3_BD_DATA4 0x160
456 #define A_MC3_BD_OP 0x164
457 
458 #define S_BACK_DOOR_OPERATION    0
459 #define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
460 #define F_BACK_DOOR_OPERATION    V_BACK_DOOR_OPERATION(1U)
461 
462 #define A_MC3_BIST_ADDR_BEG 0x168
463 #define A_MC3_BIST_ADDR_END 0x16c
464 #define A_MC3_BIST_DATA 0x170
465 #define A_MC3_BIST_OP 0x174
466 
467 #define S_OP    0
468 #define V_OP(x) ((x) << S_OP)
469 #define F_OP    V_OP(1U)
470 
471 #define S_DATA_PATTERN    1
472 #define M_DATA_PATTERN    0x3
473 #define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
474 #define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
475 
476 #define S_CONTINUOUS    3
477 #define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
478 #define F_CONTINUOUS    V_CONTINUOUS(1U)
479 
480 #define A_MC3_INT_ENABLE 0x178
481 
482 #define S_MC3_CORR_ERR    0
483 #define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
484 #define F_MC3_CORR_ERR    V_MC3_CORR_ERR(1U)
485 
486 #define S_MC3_UNCORR_ERR    1
487 #define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
488 #define F_MC3_UNCORR_ERR    V_MC3_UNCORR_ERR(1U)
489 
490 #define S_MC3_PARITY_ERR    2
491 #define M_MC3_PARITY_ERR    0xff
492 #define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
493 #define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
494 
495 #define S_MC3_ADDR_ERR    10
496 #define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
497 #define F_MC3_ADDR_ERR    V_MC3_ADDR_ERR(1U)
498 
499 #define A_MC3_INT_CAUSE 0x17c
500 
501 /* MC4 registers */
502 #define A_MC4_CFG 0x180
503 
504 #define S_POWER_UP    0
505 #define V_POWER_UP(x) ((x) << S_POWER_UP)
506 #define F_POWER_UP    V_POWER_UP(1U)
507 
508 #define S_MC4_BANK_CYCLE    8
509 #define M_MC4_BANK_CYCLE    0x7
510 #define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
511 #define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
512 
513 #define S_MC4_NARROW    24
514 #define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
515 #define F_MC4_NARROW    V_MC4_NARROW(1U)
516 
517 #define S_MC4_SLOW    25
518 #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
519 #define F_MC4_SLOW    V_MC4_SLOW(1U)
520 
521 #define S_MC4A_WIDTH    24
522 #define M_MC4A_WIDTH    0x3
523 #define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
524 #define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
525 
526 #define S_MC4A_SLOW    26
527 #define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
528 #define F_MC4A_SLOW    V_MC4A_SLOW(1U)
529 
530 #define A_MC4_MODE 0x184
531 
532 #define S_MC4_MODE    0
533 #define M_MC4_MODE    0x7fff
534 #define V_MC4_MODE(x) ((x) << S_MC4_MODE)
535 #define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
536 
537 #define A_MC4_EXT_MODE 0x188
538 
539 #define S_MC4_EXTENDED_MODE    0
540 #define M_MC4_EXTENDED_MODE    0x7fff
541 #define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
542 #define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
543 
544 #define A_MC4_REFRESH 0x190
545 #define A_MC4_STROBE 0x194
546 #define A_MC4_ECC_CNTL 0x198
547 #define A_MC4_CE_ADDR 0x19c
548 
549 #define S_MC4_CE_ADDR    4
550 #define M_MC4_CE_ADDR    0xffffff
551 #define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
552 #define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
553 
554 #define A_MC4_CE_DATA0 0x1a0
555 #define A_MC4_CE_DATA1 0x1a4
556 #define A_MC4_CE_DATA2 0x1a8
557 #define A_MC4_CE_DATA3 0x1ac
558 #define A_MC4_CE_DATA4 0x1b0
559 #define A_MC4_UE_ADDR 0x1b4
560 
561 #define S_MC4_UE_ADDR    4
562 #define M_MC4_UE_ADDR    0xffffff
563 #define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
564 #define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
565 
566 #define A_MC4_UE_DATA0 0x1b8
567 #define A_MC4_UE_DATA1 0x1bc
568 #define A_MC4_UE_DATA2 0x1c0
569 #define A_MC4_UE_DATA3 0x1c4
570 #define A_MC4_UE_DATA4 0x1c8
571 #define A_MC4_BD_ADDR 0x1cc
572 
573 #define S_MC4_BACK_DOOR_ADDR    0
574 #define M_MC4_BACK_DOOR_ADDR    0xfffffff
575 #define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
576 #define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
577 
578 #define A_MC4_BD_DATA0 0x1d0
579 #define A_MC4_BD_DATA1 0x1d4
580 #define A_MC4_BD_DATA2 0x1d8
581 #define A_MC4_BD_DATA3 0x1dc
582 #define A_MC4_BD_DATA4 0x1e0
583 #define A_MC4_BD_OP 0x1e4
584 
585 #define S_OPERATION    0
586 #define V_OPERATION(x) ((x) << S_OPERATION)
587 #define F_OPERATION    V_OPERATION(1U)
588 
589 #define A_MC4_BIST_ADDR_BEG 0x1e8
590 #define A_MC4_BIST_ADDR_END 0x1ec
591 #define A_MC4_BIST_DATA 0x1f0
592 #define A_MC4_BIST_OP 0x1f4
593 #define A_MC4_INT_ENABLE 0x1f8
594 
595 #define S_MC4_CORR_ERR    0
596 #define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
597 #define F_MC4_CORR_ERR    V_MC4_CORR_ERR(1U)
598 
599 #define S_MC4_UNCORR_ERR    1
600 #define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
601 #define F_MC4_UNCORR_ERR    V_MC4_UNCORR_ERR(1U)
602 
603 #define S_MC4_ADDR_ERR    2
604 #define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
605 #define F_MC4_ADDR_ERR    V_MC4_ADDR_ERR(1U)
606 
607 #define A_MC4_INT_CAUSE 0x1fc
608 
609 /* TPI registers */
610 #define A_TPI_ADDR 0x280
611 
612 #define S_TPI_ADDRESS    0
613 #define M_TPI_ADDRESS    0xffffff
614 #define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
615 #define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
616 
617 #define A_TPI_WR_DATA 0x284
618 #define A_TPI_RD_DATA 0x288
619 #define A_TPI_CSR 0x28c
620 
621 #define S_TPIWR    0
622 #define V_TPIWR(x) ((x) << S_TPIWR)
623 #define F_TPIWR    V_TPIWR(1U)
624 
625 #define S_TPIRDY    1
626 #define V_TPIRDY(x) ((x) << S_TPIRDY)
627 #define F_TPIRDY    V_TPIRDY(1U)
628 
629 #define S_INT_DIR    31
630 #define V_INT_DIR(x) ((x) << S_INT_DIR)
631 #define F_INT_DIR    V_INT_DIR(1U)
632 
633 #define A_TPI_PAR 0x29c
634 
635 #define S_TPIPAR    0
636 #define M_TPIPAR    0x7f
637 #define V_TPIPAR(x) ((x) << S_TPIPAR)
638 #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
639 
640 
641 /* TP registers */
642 #define A_TP_IN_CONFIG 0x300
643 
644 #define S_TP_IN_CSPI_TUNNEL    0
645 #define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
646 #define F_TP_IN_CSPI_TUNNEL    V_TP_IN_CSPI_TUNNEL(1U)
647 
648 #define S_TP_IN_CSPI_ETHERNET    1
649 #define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
650 #define F_TP_IN_CSPI_ETHERNET    V_TP_IN_CSPI_ETHERNET(1U)
651 
652 #define S_TP_IN_CSPI_CPL    3
653 #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
654 #define F_TP_IN_CSPI_CPL    V_TP_IN_CSPI_CPL(1U)
655 
656 #define S_TP_IN_CSPI_POS    4
657 #define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
658 #define F_TP_IN_CSPI_POS    V_TP_IN_CSPI_POS(1U)
659 
660 #define S_TP_IN_CSPI_CHECK_IP_CSUM    5
661 #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
662 #define F_TP_IN_CSPI_CHECK_IP_CSUM    V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
663 
664 #define S_TP_IN_CSPI_CHECK_TCP_CSUM    6
665 #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
666 #define F_TP_IN_CSPI_CHECK_TCP_CSUM    V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
667 
668 #define S_TP_IN_ESPI_TUNNEL    7
669 #define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
670 #define F_TP_IN_ESPI_TUNNEL    V_TP_IN_ESPI_TUNNEL(1U)
671 
672 #define S_TP_IN_ESPI_ETHERNET    8
673 #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
674 #define F_TP_IN_ESPI_ETHERNET    V_TP_IN_ESPI_ETHERNET(1U)
675 
676 #define S_TP_IN_ESPI_CPL    10
677 #define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
678 #define F_TP_IN_ESPI_CPL    V_TP_IN_ESPI_CPL(1U)
679 
680 #define S_TP_IN_ESPI_POS    11
681 #define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
682 #define F_TP_IN_ESPI_POS    V_TP_IN_ESPI_POS(1U)
683 
684 #define S_TP_IN_ESPI_CHECK_IP_CSUM    12
685 #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
686 #define F_TP_IN_ESPI_CHECK_IP_CSUM    V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
687 
688 #define S_TP_IN_ESPI_CHECK_TCP_CSUM    13
689 #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
690 #define F_TP_IN_ESPI_CHECK_TCP_CSUM    V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
691 
692 #define S_OFFLOAD_DISABLE    14
693 #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
694 #define F_OFFLOAD_DISABLE    V_OFFLOAD_DISABLE(1U)
695 
696 #define A_TP_OUT_CONFIG 0x304
697 
698 #define S_TP_OUT_C_ETH    0
699 #define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
700 #define F_TP_OUT_C_ETH    V_TP_OUT_C_ETH(1U)
701 
702 #define S_TP_OUT_CSPI_CPL    2
703 #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
704 #define F_TP_OUT_CSPI_CPL    V_TP_OUT_CSPI_CPL(1U)
705 
706 #define S_TP_OUT_CSPI_POS    3
707 #define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
708 #define F_TP_OUT_CSPI_POS    V_TP_OUT_CSPI_POS(1U)
709 
710 #define S_TP_OUT_CSPI_GENERATE_IP_CSUM    4
711 #define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
712 #define F_TP_OUT_CSPI_GENERATE_IP_CSUM    V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
713 
714 #define S_TP_OUT_CSPI_GENERATE_TCP_CSUM    5
715 #define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
716 #define F_TP_OUT_CSPI_GENERATE_TCP_CSUM    V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
717 
718 #define S_TP_OUT_ESPI_ETHERNET    6
719 #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
720 #define F_TP_OUT_ESPI_ETHERNET    V_TP_OUT_ESPI_ETHERNET(1U)
721 
722 #define S_TP_OUT_ESPI_TAG_ETHERNET    7
723 #define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
724 #define F_TP_OUT_ESPI_TAG_ETHERNET    V_TP_OUT_ESPI_TAG_ETHERNET(1U)
725 
726 #define S_TP_OUT_ESPI_CPL    8
727 #define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
728 #define F_TP_OUT_ESPI_CPL    V_TP_OUT_ESPI_CPL(1U)
729 
730 #define S_TP_OUT_ESPI_POS    9
731 #define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
732 #define F_TP_OUT_ESPI_POS    V_TP_OUT_ESPI_POS(1U)
733 
734 #define S_TP_OUT_ESPI_GENERATE_IP_CSUM    10
735 #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
736 #define F_TP_OUT_ESPI_GENERATE_IP_CSUM    V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
737 
738 #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM    11
739 #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
740 #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM    V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
741 
742 #define A_TP_GLOBAL_CONFIG 0x308
743 
744 #define S_IP_TTL    0
745 #define M_IP_TTL    0xff
746 #define V_IP_TTL(x) ((x) << S_IP_TTL)
747 #define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
748 
749 #define S_TCAM_SERVER_REGION_USAGE    8
750 #define M_TCAM_SERVER_REGION_USAGE    0x3
751 #define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
752 #define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
753 
754 #define S_QOS_MAPPING    10
755 #define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
756 #define F_QOS_MAPPING    V_QOS_MAPPING(1U)
757 
758 #define S_TCP_CSUM    11
759 #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
760 #define F_TCP_CSUM    V_TCP_CSUM(1U)
761 
762 #define S_UDP_CSUM    12
763 #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
764 #define F_UDP_CSUM    V_UDP_CSUM(1U)
765 
766 #define S_IP_CSUM    13
767 #define V_IP_CSUM(x) ((x) << S_IP_CSUM)
768 #define F_IP_CSUM    V_IP_CSUM(1U)
769 
770 #define S_IP_ID_SPLIT    14
771 #define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
772 #define F_IP_ID_SPLIT    V_IP_ID_SPLIT(1U)
773 
774 #define S_PATH_MTU    15
775 #define V_PATH_MTU(x) ((x) << S_PATH_MTU)
776 #define F_PATH_MTU    V_PATH_MTU(1U)
777 
778 #define S_5TUPLE_LOOKUP    17
779 #define M_5TUPLE_LOOKUP    0x3
780 #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
781 #define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
782 
783 #define S_IP_FRAGMENT_DROP    19
784 #define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
785 #define F_IP_FRAGMENT_DROP    V_IP_FRAGMENT_DROP(1U)
786 
787 #define S_PING_DROP    20
788 #define V_PING_DROP(x) ((x) << S_PING_DROP)
789 #define F_PING_DROP    V_PING_DROP(1U)
790 
791 #define S_PROTECT_MODE    21
792 #define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
793 #define F_PROTECT_MODE    V_PROTECT_MODE(1U)
794 
795 #define S_SYN_COOKIE_ALGORITHM    22
796 #define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
797 #define F_SYN_COOKIE_ALGORITHM    V_SYN_COOKIE_ALGORITHM(1U)
798 
799 #define S_ATTACK_FILTER    23
800 #define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
801 #define F_ATTACK_FILTER    V_ATTACK_FILTER(1U)
802 
803 #define S_INTERFACE_TYPE    24
804 #define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
805 #define F_INTERFACE_TYPE    V_INTERFACE_TYPE(1U)
806 
807 #define S_DISABLE_RX_FLOW_CONTROL    25
808 #define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
809 #define F_DISABLE_RX_FLOW_CONTROL    V_DISABLE_RX_FLOW_CONTROL(1U)
810 
811 #define S_SYN_COOKIE_PARAMETER    26
812 #define M_SYN_COOKIE_PARAMETER    0x3f
813 #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
814 #define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
815 
816 #define A_TP_GLOBAL_RX_CREDITS 0x30c
817 #define A_TP_CM_SIZE 0x310
818 #define A_TP_CM_MM_BASE 0x314
819 
820 #define S_CM_MEMMGR_BASE    0
821 #define M_CM_MEMMGR_BASE    0xfffffff
822 #define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
823 #define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
824 
825 #define A_TP_CM_TIMER_BASE 0x318
826 
827 #define S_CM_TIMER_BASE    0
828 #define M_CM_TIMER_BASE    0xfffffff
829 #define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
830 #define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
831 
832 #define A_TP_PM_SIZE 0x31c
833 #define A_TP_PM_TX_BASE 0x320
834 #define A_TP_PM_DEFRAG_BASE 0x324
835 #define A_TP_PM_RX_BASE 0x328
836 #define A_TP_PM_RX_PG_SIZE 0x32c
837 #define A_TP_PM_RX_MAX_PGS 0x330
838 #define A_TP_PM_TX_PG_SIZE 0x334
839 #define A_TP_PM_TX_MAX_PGS 0x338
840 #define A_TP_TCP_OPTIONS 0x340
841 
842 #define S_TIMESTAMP    0
843 #define M_TIMESTAMP    0x3
844 #define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
845 #define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
846 
847 #define S_WINDOW_SCALE    2
848 #define M_WINDOW_SCALE    0x3
849 #define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
850 #define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
851 
852 #define S_SACK    4
853 #define M_SACK    0x3
854 #define V_SACK(x) ((x) << S_SACK)
855 #define G_SACK(x) (((x) >> S_SACK) & M_SACK)
856 
857 #define S_ECN    6
858 #define M_ECN    0x3
859 #define V_ECN(x) ((x) << S_ECN)
860 #define G_ECN(x) (((x) >> S_ECN) & M_ECN)
861 
862 #define S_SACK_ALGORITHM    8
863 #define M_SACK_ALGORITHM    0x3
864 #define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
865 #define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
866 
867 #define S_MSS    10
868 #define V_MSS(x) ((x) << S_MSS)
869 #define F_MSS    V_MSS(1U)
870 
871 #define S_DEFAULT_PEER_MSS    16
872 #define M_DEFAULT_PEER_MSS    0xffff
873 #define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
874 #define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
875 
876 #define A_TP_DACK_CONFIG 0x344
877 
878 #define S_DACK_MODE    0
879 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
880 #define F_DACK_MODE    V_DACK_MODE(1U)
881 
882 #define S_DACK_AUTO_MGMT    1
883 #define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
884 #define F_DACK_AUTO_MGMT    V_DACK_AUTO_MGMT(1U)
885 
886 #define S_DACK_AUTO_CAREFUL    2
887 #define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
888 #define F_DACK_AUTO_CAREFUL    V_DACK_AUTO_CAREFUL(1U)
889 
890 #define S_DACK_MSS_SELECTOR    3
891 #define M_DACK_MSS_SELECTOR    0x3
892 #define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
893 #define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
894 
895 #define S_DACK_BYTE_THRESHOLD    5
896 #define M_DACK_BYTE_THRESHOLD    0xfffff
897 #define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
898 #define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
899 
900 #define A_TP_PC_CONFIG 0x348
901 
902 #define S_TP_ACCESS_LATENCY    0
903 #define M_TP_ACCESS_LATENCY    0xf
904 #define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
905 #define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
906 
907 #define S_HELD_FIN_DISABLE    4
908 #define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
909 #define F_HELD_FIN_DISABLE    V_HELD_FIN_DISABLE(1U)
910 
911 #define S_DDP_FC_ENABLE    5
912 #define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
913 #define F_DDP_FC_ENABLE    V_DDP_FC_ENABLE(1U)
914 
915 #define S_RDMA_ERR_ENABLE    6
916 #define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
917 #define F_RDMA_ERR_ENABLE    V_RDMA_ERR_ENABLE(1U)
918 
919 #define S_FAST_PDU_DELIVERY    7
920 #define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
921 #define F_FAST_PDU_DELIVERY    V_FAST_PDU_DELIVERY(1U)
922 
923 #define S_CLEAR_FIN    8
924 #define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
925 #define F_CLEAR_FIN    V_CLEAR_FIN(1U)
926 
927 #define S_DIS_TX_FILL_WIN_PUSH    12
928 #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
929 #define F_DIS_TX_FILL_WIN_PUSH    V_DIS_TX_FILL_WIN_PUSH(1U)
930 
931 #define S_TP_PC_REV    30
932 #define M_TP_PC_REV    0x3
933 #define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
934 #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
935 
936 #define A_TP_BACKOFF0 0x350
937 
938 #define S_ELEMENT0    0
939 #define M_ELEMENT0    0xff
940 #define V_ELEMENT0(x) ((x) << S_ELEMENT0)
941 #define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
942 
943 #define S_ELEMENT1    8
944 #define M_ELEMENT1    0xff
945 #define V_ELEMENT1(x) ((x) << S_ELEMENT1)
946 #define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
947 
948 #define S_ELEMENT2    16
949 #define M_ELEMENT2    0xff
950 #define V_ELEMENT2(x) ((x) << S_ELEMENT2)
951 #define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
952 
953 #define S_ELEMENT3    24
954 #define M_ELEMENT3    0xff
955 #define V_ELEMENT3(x) ((x) << S_ELEMENT3)
956 #define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
957 
958 #define A_TP_BACKOFF1 0x354
959 #define A_TP_BACKOFF2 0x358
960 #define A_TP_BACKOFF3 0x35c
961 #define A_TP_PARA_REG0 0x360
962 
963 #define S_VAR_MULT    0
964 #define M_VAR_MULT    0xf
965 #define V_VAR_MULT(x) ((x) << S_VAR_MULT)
966 #define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
967 
968 #define S_VAR_GAIN    4
969 #define M_VAR_GAIN    0xf
970 #define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
971 #define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
972 
973 #define S_SRTT_GAIN    8
974 #define M_SRTT_GAIN    0xf
975 #define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
976 #define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
977 
978 #define S_RTTVAR_INIT    12
979 #define M_RTTVAR_INIT    0xf
980 #define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
981 #define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
982 
983 #define S_DUP_THRESH    20
984 #define M_DUP_THRESH    0xf
985 #define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
986 #define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
987 
988 #define S_INIT_CONG_WIN    24
989 #define M_INIT_CONG_WIN    0x7
990 #define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
991 #define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
992 
993 #define A_TP_PARA_REG1 0x364
994 
995 #define S_INITIAL_SLOW_START_THRESHOLD    0
996 #define M_INITIAL_SLOW_START_THRESHOLD    0xffff
997 #define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
998 #define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
999 
1000 #define S_RECEIVE_BUFFER_SIZE    16
1001 #define M_RECEIVE_BUFFER_SIZE    0xffff
1002 #define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
1003 #define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
1004 
1005 #define A_TP_PARA_REG2 0x368
1006 
1007 #define S_RX_COALESCE_SIZE    0
1008 #define M_RX_COALESCE_SIZE    0xffff
1009 #define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
1010 #define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
1011 
1012 #define S_MAX_RX_SIZE    16
1013 #define M_MAX_RX_SIZE    0xffff
1014 #define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
1015 #define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
1016 
1017 #define A_TP_PARA_REG3 0x36c
1018 
1019 #define S_RX_COALESCING_PSH_DELIVER    0
1020 #define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1021 #define F_RX_COALESCING_PSH_DELIVER    V_RX_COALESCING_PSH_DELIVER(1U)
1022 
1023 #define S_RX_COALESCING_ENABLE    1
1024 #define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1025 #define F_RX_COALESCING_ENABLE    V_RX_COALESCING_ENABLE(1U)
1026 
1027 #define S_TAHOE_ENABLE    2
1028 #define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1029 #define F_TAHOE_ENABLE    V_TAHOE_ENABLE(1U)
1030 
1031 #define S_MAX_REORDER_FRAGMENTS    12
1032 #define M_MAX_REORDER_FRAGMENTS    0x7
1033 #define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1034 #define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1035 
1036 #define A_TP_TIMER_RESOLUTION 0x390
1037 
1038 #define S_DELAYED_ACK_TIMER_RESOLUTION    0
1039 #define M_DELAYED_ACK_TIMER_RESOLUTION    0x3f
1040 #define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1041 #define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1042 
1043 #define S_GENERIC_TIMER_RESOLUTION    16
1044 #define M_GENERIC_TIMER_RESOLUTION    0x3f
1045 #define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1046 #define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1047 
1048 #define A_TP_2MSL 0x394
1049 
1050 #define S_2MSL    0
1051 #define M_2MSL    0x3fffffff
1052 #define V_2MSL(x) ((x) << S_2MSL)
1053 #define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1054 
1055 #define A_TP_RXT_MIN 0x398
1056 
1057 #define S_RETRANSMIT_TIMER_MIN    0
1058 #define M_RETRANSMIT_TIMER_MIN    0xffff
1059 #define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1060 #define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1061 
1062 #define A_TP_RXT_MAX 0x39c
1063 
1064 #define S_RETRANSMIT_TIMER_MAX    0
1065 #define M_RETRANSMIT_TIMER_MAX    0x3fffffff
1066 #define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1067 #define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1068 
1069 #define A_TP_PERS_MIN 0x3a0
1070 
1071 #define S_PERSIST_TIMER_MIN    0
1072 #define M_PERSIST_TIMER_MIN    0xffff
1073 #define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1074 #define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1075 
1076 #define A_TP_PERS_MAX 0x3a4
1077 
1078 #define S_PERSIST_TIMER_MAX    0
1079 #define M_PERSIST_TIMER_MAX    0x3fffffff
1080 #define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1081 #define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1082 
1083 #define A_TP_KEEP_IDLE 0x3ac
1084 
1085 #define S_KEEP_ALIVE_IDLE_TIME    0
1086 #define M_KEEP_ALIVE_IDLE_TIME    0x3fffffff
1087 #define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1088 #define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1089 
1090 #define A_TP_KEEP_INTVL 0x3b0
1091 
1092 #define S_KEEP_ALIVE_INTERVAL_TIME    0
1093 #define M_KEEP_ALIVE_INTERVAL_TIME    0x3fffffff
1094 #define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1095 #define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1096 
1097 #define A_TP_INIT_SRTT 0x3b4
1098 
1099 #define S_INITIAL_SRTT    0
1100 #define M_INITIAL_SRTT    0xffff
1101 #define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1102 #define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1103 
1104 #define A_TP_DACK_TIME 0x3b8
1105 
1106 #define S_DELAYED_ACK_TIME    0
1107 #define M_DELAYED_ACK_TIME    0x7ff
1108 #define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1109 #define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1110 
1111 #define A_TP_FINWAIT2_TIME 0x3bc
1112 
1113 #define S_FINWAIT2_TIME    0
1114 #define M_FINWAIT2_TIME    0x3fffffff
1115 #define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1116 #define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1117 
1118 #define A_TP_FAST_FINWAIT2_TIME 0x3c0
1119 
1120 #define S_FAST_FINWAIT2_TIME    0
1121 #define M_FAST_FINWAIT2_TIME    0x3fffffff
1122 #define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1123 #define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1124 
1125 #define A_TP_SHIFT_CNT 0x3c4
1126 
1127 #define S_KEEPALIVE_MAX    0
1128 #define M_KEEPALIVE_MAX    0xff
1129 #define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1130 #define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1131 
1132 #define S_WINDOWPROBE_MAX    8
1133 #define M_WINDOWPROBE_MAX    0xff
1134 #define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1135 #define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1136 
1137 #define S_RETRANSMISSION_MAX    16
1138 #define M_RETRANSMISSION_MAX    0xff
1139 #define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1140 #define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1141 
1142 #define S_SYN_MAX    24
1143 #define M_SYN_MAX    0xff
1144 #define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1145 #define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1146 
1147 #define A_TP_QOS_REG0 0x3e0
1148 
1149 #define S_L3_VALUE    0
1150 #define M_L3_VALUE    0x3f
1151 #define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1152 #define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1153 
1154 #define A_TP_QOS_REG1 0x3e4
1155 #define A_TP_QOS_REG2 0x3e8
1156 #define A_TP_QOS_REG3 0x3ec
1157 #define A_TP_QOS_REG4 0x3f0
1158 #define A_TP_QOS_REG5 0x3f4
1159 #define A_TP_QOS_REG6 0x3f8
1160 #define A_TP_QOS_REG7 0x3fc
1161 #define A_TP_MTU_REG0 0x404
1162 #define A_TP_MTU_REG1 0x408
1163 #define A_TP_MTU_REG2 0x40c
1164 #define A_TP_MTU_REG3 0x410
1165 #define A_TP_MTU_REG4 0x414
1166 #define A_TP_MTU_REG5 0x418
1167 #define A_TP_MTU_REG6 0x41c
1168 #define A_TP_MTU_REG7 0x420
1169 #define A_TP_RESET 0x44c
1170 
1171 #define S_TP_RESET    0
1172 #define V_TP_RESET(x) ((x) << S_TP_RESET)
1173 #define F_TP_RESET    V_TP_RESET(1U)
1174 
1175 #define S_CM_MEMMGR_INIT    1
1176 #define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1177 #define F_CM_MEMMGR_INIT    V_CM_MEMMGR_INIT(1U)
1178 
1179 #define A_TP_MIB_INDEX 0x450
1180 #define A_TP_MIB_DATA 0x454
1181 #define A_TP_SYNC_TIME_HI 0x458
1182 #define A_TP_SYNC_TIME_LO 0x45c
1183 #define A_TP_CM_MM_RX_FLST_BASE 0x460
1184 
1185 #define S_CM_MEMMGR_RX_FREE_LIST_BASE    0
1186 #define M_CM_MEMMGR_RX_FREE_LIST_BASE    0xfffffff
1187 #define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1188 #define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1189 
1190 #define A_TP_CM_MM_TX_FLST_BASE 0x464
1191 
1192 #define S_CM_MEMMGR_TX_FREE_LIST_BASE    0
1193 #define M_CM_MEMMGR_TX_FREE_LIST_BASE    0xfffffff
1194 #define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1195 #define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1196 
1197 #define A_TP_CM_MM_P_FLST_BASE 0x468
1198 
1199 #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE    0
1200 #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE    0xfffffff
1201 #define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1202 #define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1203 
1204 #define A_TP_CM_MM_MAX_P 0x46c
1205 
1206 #define S_CM_MEMMGR_MAX_PSTRUCT    0
1207 #define M_CM_MEMMGR_MAX_PSTRUCT    0xfffffff
1208 #define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1209 #define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1210 
1211 #define A_TP_INT_ENABLE 0x470
1212 
1213 #define S_TX_FREE_LIST_EMPTY    0
1214 #define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1215 #define F_TX_FREE_LIST_EMPTY    V_TX_FREE_LIST_EMPTY(1U)
1216 
1217 #define S_RX_FREE_LIST_EMPTY    1
1218 #define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1219 #define F_RX_FREE_LIST_EMPTY    V_RX_FREE_LIST_EMPTY(1U)
1220 
1221 #define A_TP_INT_CAUSE 0x474
1222 #define A_TP_TIMER_SEPARATOR 0x4a4
1223 
1224 #define S_DISABLE_PAST_TIMER_INSERTION    0
1225 #define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1226 #define F_DISABLE_PAST_TIMER_INSERTION    V_DISABLE_PAST_TIMER_INSERTION(1U)
1227 
1228 #define S_MODULATION_TIMER_SEPARATOR    1
1229 #define M_MODULATION_TIMER_SEPARATOR    0x7fff
1230 #define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1231 #define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1232 
1233 #define S_GLOBAL_TIMER_SEPARATOR    16
1234 #define M_GLOBAL_TIMER_SEPARATOR    0xffff
1235 #define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1236 #define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1237 
1238 #define A_TP_CM_FC_MODE 0x4b0
1239 #define A_TP_PC_CONGESTION_CNTL 0x4b4
1240 #define A_TP_TX_DROP_CONFIG 0x4b8
1241 
1242 #define S_ENABLE_TX_DROP    31
1243 #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
1244 #define F_ENABLE_TX_DROP    V_ENABLE_TX_DROP(1U)
1245 
1246 #define S_ENABLE_TX_ERROR    30
1247 #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
1248 #define F_ENABLE_TX_ERROR    V_ENABLE_TX_ERROR(1U)
1249 
1250 #define S_DROP_TICKS_CNT    4
1251 #define M_DROP_TICKS_CNT    0x3ffffff
1252 #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1253 #define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
1254 
1255 #define S_NUM_PKTS_DROPPED    0
1256 #define M_NUM_PKTS_DROPPED    0xf
1257 #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1258 #define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1259 
1260 #define A_TP_TX_DROP_COUNT 0x4bc
1261 
1262 /* RAT registers */
1263 #define A_RAT_ROUTE_CONTROL 0x580
1264 
1265 #define S_USE_ROUTE_TABLE    0
1266 #define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1267 #define F_USE_ROUTE_TABLE    V_USE_ROUTE_TABLE(1U)
1268 
1269 #define S_ENABLE_CSPI    1
1270 #define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1271 #define F_ENABLE_CSPI    V_ENABLE_CSPI(1U)
1272 
1273 #define S_ENABLE_PCIX    2
1274 #define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1275 #define F_ENABLE_PCIX    V_ENABLE_PCIX(1U)
1276 
1277 #define A_RAT_ROUTE_TABLE_INDEX 0x584
1278 
1279 #define S_ROUTE_TABLE_INDEX    0
1280 #define M_ROUTE_TABLE_INDEX    0xf
1281 #define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1282 #define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1283 
1284 #define A_RAT_ROUTE_TABLE_DATA 0x588
1285 #define A_RAT_NO_ROUTE 0x58c
1286 
1287 #define S_CPL_OPCODE    0
1288 #define M_CPL_OPCODE    0xff
1289 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1290 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1291 
1292 #define A_RAT_INTR_ENABLE 0x590
1293 
1294 #define S_ZEROROUTEERROR    0
1295 #define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1296 #define F_ZEROROUTEERROR    V_ZEROROUTEERROR(1U)
1297 
1298 #define S_CSPIFRAMINGERROR    1
1299 #define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1300 #define F_CSPIFRAMINGERROR    V_CSPIFRAMINGERROR(1U)
1301 
1302 #define S_SGEFRAMINGERROR    2
1303 #define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1304 #define F_SGEFRAMINGERROR    V_SGEFRAMINGERROR(1U)
1305 
1306 #define S_TPFRAMINGERROR    3
1307 #define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1308 #define F_TPFRAMINGERROR    V_TPFRAMINGERROR(1U)
1309 
1310 #define A_RAT_INTR_CAUSE 0x594
1311 
1312 /* CSPI registers */
1313 #define A_CSPI_RX_AE_WM 0x810
1314 #define A_CSPI_RX_AF_WM 0x814
1315 #define A_CSPI_CALENDAR_LEN 0x818
1316 
1317 #define S_CALENDARLENGTH    0
1318 #define M_CALENDARLENGTH    0xffff
1319 #define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1320 #define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1321 
1322 #define A_CSPI_FIFO_STATUS_ENABLE 0x820
1323 
1324 #define S_FIFOSTATUSENABLE    0
1325 #define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1326 #define F_FIFOSTATUSENABLE    V_FIFOSTATUSENABLE(1U)
1327 
1328 #define A_CSPI_MAXBURST1_MAXBURST2 0x828
1329 
1330 #define S_MAXBURST1    0
1331 #define M_MAXBURST1    0xffff
1332 #define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1333 #define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1334 
1335 #define S_MAXBURST2    16
1336 #define M_MAXBURST2    0xffff
1337 #define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1338 #define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1339 
1340 #define A_CSPI_TRAIN 0x82c
1341 
1342 #define S_CSPI_TRAIN_ALPHA    0
1343 #define M_CSPI_TRAIN_ALPHA    0xffff
1344 #define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1345 #define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1346 
1347 #define S_CSPI_TRAIN_DATA_MAXT    16
1348 #define M_CSPI_TRAIN_DATA_MAXT    0xffff
1349 #define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1350 #define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1351 
1352 #define A_CSPI_INTR_STATUS 0x848
1353 
1354 #define S_DIP4ERR    0
1355 #define V_DIP4ERR(x) ((x) << S_DIP4ERR)
1356 #define F_DIP4ERR    V_DIP4ERR(1U)
1357 
1358 #define S_RXDROP    1
1359 #define V_RXDROP(x) ((x) << S_RXDROP)
1360 #define F_RXDROP    V_RXDROP(1U)
1361 
1362 #define S_TXDROP    2
1363 #define V_TXDROP(x) ((x) << S_TXDROP)
1364 #define F_TXDROP    V_TXDROP(1U)
1365 
1366 #define S_RXOVERFLOW    3
1367 #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
1368 #define F_RXOVERFLOW    V_RXOVERFLOW(1U)
1369 
1370 #define S_RAMPARITYERR    4
1371 #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
1372 #define F_RAMPARITYERR    V_RAMPARITYERR(1U)
1373 
1374 #define A_CSPI_INTR_ENABLE 0x84c
1375 
1376 /* ESPI registers */
1377 #define A_ESPI_SCH_TOKEN0 0x880
1378 
1379 #define S_SCHTOKEN0    0
1380 #define M_SCHTOKEN0    0xffff
1381 #define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1382 #define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1383 
1384 #define A_ESPI_SCH_TOKEN1 0x884
1385 
1386 #define S_SCHTOKEN1    0
1387 #define M_SCHTOKEN1    0xffff
1388 #define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1389 #define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1390 
1391 #define A_ESPI_SCH_TOKEN2 0x888
1392 
1393 #define S_SCHTOKEN2    0
1394 #define M_SCHTOKEN2    0xffff
1395 #define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1396 #define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1397 
1398 #define A_ESPI_SCH_TOKEN3 0x88c
1399 
1400 #define S_SCHTOKEN3    0
1401 #define M_SCHTOKEN3    0xffff
1402 #define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1403 #define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1404 
1405 #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1406 
1407 #define S_ALMOSTEMPTY    0
1408 #define M_ALMOSTEMPTY    0xffff
1409 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1410 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1411 
1412 #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1413 
1414 #define S_ALMOSTFULL    0
1415 #define M_ALMOSTFULL    0xffff
1416 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1417 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1418 
1419 #define A_ESPI_CALENDAR_LENGTH 0x898
1420 #define A_PORT_CONFIG 0x89c
1421 
1422 #define S_RX_NPORTS    0
1423 #define M_RX_NPORTS    0xff
1424 #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1425 #define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
1426 
1427 #define S_TX_NPORTS    8
1428 #define M_TX_NPORTS    0xff
1429 #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1430 #define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
1431 
1432 #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
1433 
1434 #define S_RXSTATUSENABLE    0
1435 #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
1436 #define F_RXSTATUSENABLE    V_RXSTATUSENABLE(1U)
1437 
1438 #define S_TXDROPENABLE    1
1439 #define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1440 #define F_TXDROPENABLE    V_TXDROPENABLE(1U)
1441 
1442 #define S_RXENDIANMODE    2
1443 #define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1444 #define F_RXENDIANMODE    V_RXENDIANMODE(1U)
1445 
1446 #define S_TXENDIANMODE    3
1447 #define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)
1448 #define F_TXENDIANMODE    V_TXENDIANMODE(1U)
1449 
1450 #define S_INTEL1010MODE    4
1451 #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
1452 #define F_INTEL1010MODE    V_INTEL1010MODE(1U)
1453 
1454 #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
1455 #define A_ESPI_TRAIN 0x8ac
1456 
1457 #define S_MAXTRAINALPHA    0
1458 #define M_MAXTRAINALPHA    0xffff
1459 #define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)
1460 #define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)
1461 
1462 #define S_MAXTRAINDATA    16
1463 #define M_MAXTRAINDATA    0xffff
1464 #define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)
1465 #define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)
1466 
1467 #define A_RAM_STATUS 0x8b0
1468 
1469 #define S_RXFIFOPARITYERROR    0
1470 #define M_RXFIFOPARITYERROR    0x3ff
1471 #define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)
1472 #define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)
1473 
1474 #define S_TXFIFOPARITYERROR    10
1475 #define M_TXFIFOPARITYERROR    0x3ff
1476 #define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)
1477 #define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)
1478 
1479 #define S_RXFIFOOVERFLOW    20
1480 #define M_RXFIFOOVERFLOW    0x3ff
1481 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
1482 #define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)
1483 
1484 #define A_TX_DROP_COUNT0 0x8b4
1485 
1486 #define S_TXPORT0DROPCNT    0
1487 #define M_TXPORT0DROPCNT    0xffff
1488 #define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)
1489 #define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)
1490 
1491 #define S_TXPORT1DROPCNT    16
1492 #define M_TXPORT1DROPCNT    0xffff
1493 #define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)
1494 #define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)
1495 
1496 #define A_TX_DROP_COUNT1 0x8b8
1497 
1498 #define S_TXPORT2DROPCNT    0
1499 #define M_TXPORT2DROPCNT    0xffff
1500 #define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)
1501 #define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)
1502 
1503 #define S_TXPORT3DROPCNT    16
1504 #define M_TXPORT3DROPCNT    0xffff
1505 #define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)
1506 #define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)
1507 
1508 #define A_RX_DROP_COUNT0 0x8bc
1509 
1510 #define S_RXPORT0DROPCNT    0
1511 #define M_RXPORT0DROPCNT    0xffff
1512 #define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)
1513 #define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)
1514 
1515 #define S_RXPORT1DROPCNT    16
1516 #define M_RXPORT1DROPCNT    0xffff
1517 #define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)
1518 #define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)
1519 
1520 #define A_RX_DROP_COUNT1 0x8c0
1521 
1522 #define S_RXPORT2DROPCNT    0
1523 #define M_RXPORT2DROPCNT    0xffff
1524 #define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)
1525 #define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)
1526 
1527 #define S_RXPORT3DROPCNT    16
1528 #define M_RXPORT3DROPCNT    0xffff
1529 #define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)
1530 #define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)
1531 
1532 #define A_DIP4_ERROR_COUNT 0x8c4
1533 
1534 #define S_DIP4ERRORCNT    0
1535 #define M_DIP4ERRORCNT    0xfff
1536 #define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)
1537 #define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)
1538 
1539 #define S_DIP4ERRORCNTSHADOW    12
1540 #define M_DIP4ERRORCNTSHADOW    0xfff
1541 #define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)
1542 #define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)
1543 
1544 #define S_TRICN_RX_TRAIN_ERR    24
1545 #define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)
1546 #define F_TRICN_RX_TRAIN_ERR    V_TRICN_RX_TRAIN_ERR(1U)
1547 
1548 #define S_TRICN_RX_TRAINING    25
1549 #define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)
1550 #define F_TRICN_RX_TRAINING    V_TRICN_RX_TRAINING(1U)
1551 
1552 #define S_TRICN_RX_TRAIN_OK    26
1553 #define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)
1554 #define F_TRICN_RX_TRAIN_OK    V_TRICN_RX_TRAIN_OK(1U)
1555 
1556 #define A_ESPI_INTR_STATUS 0x8c8
1557 
1558 #define S_DIP2PARITYERR    5
1559 #define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
1560 #define F_DIP2PARITYERR    V_DIP2PARITYERR(1U)
1561 
1562 #define A_ESPI_INTR_ENABLE 0x8cc
1563 #define A_RX_DROP_THRESHOLD 0x8d0
1564 #define A_ESPI_RX_RESET 0x8ec
1565 
1566 #define S_ESPI_RX_LNK_RST    0
1567 #define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)
1568 #define F_ESPI_RX_LNK_RST    V_ESPI_RX_LNK_RST(1U)
1569 
1570 #define S_ESPI_RX_CORE_RST    1
1571 #define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)
1572 #define F_ESPI_RX_CORE_RST    V_ESPI_RX_CORE_RST(1U)
1573 
1574 #define S_RX_CLK_STATUS    2
1575 #define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)
1576 #define F_RX_CLK_STATUS    V_RX_CLK_STATUS(1U)
1577 
1578 #define A_ESPI_MISC_CONTROL 0x8f0
1579 
1580 #define S_OUT_OF_SYNC_COUNT    0
1581 #define M_OUT_OF_SYNC_COUNT    0xf
1582 #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
1583 #define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)
1584 
1585 #define S_DIP2_COUNT_MODE_ENABLE    4
1586 #define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)
1587 #define F_DIP2_COUNT_MODE_ENABLE    V_DIP2_COUNT_MODE_ENABLE(1U)
1588 
1589 #define S_DIP2_PARITY_ERR_THRES    5
1590 #define M_DIP2_PARITY_ERR_THRES    0xf
1591 #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
1592 #define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)
1593 
1594 #define S_DIP4_THRES    9
1595 #define M_DIP4_THRES    0xfff
1596 #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
1597 #define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)
1598 
1599 #define S_DIP4_THRES_ENABLE    21
1600 #define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)
1601 #define F_DIP4_THRES_ENABLE    V_DIP4_THRES_ENABLE(1U)
1602 
1603 #define S_FORCE_DISABLE_STATUS    22
1604 #define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)
1605 #define F_FORCE_DISABLE_STATUS    V_FORCE_DISABLE_STATUS(1U)
1606 
1607 #define S_DYNAMIC_DESKEW    23
1608 #define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)
1609 #define F_DYNAMIC_DESKEW    V_DYNAMIC_DESKEW(1U)
1610 
1611 #define S_MONITORED_PORT_NUM    25
1612 #define M_MONITORED_PORT_NUM    0x3
1613 #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
1614 #define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)
1615 
1616 #define S_MONITORED_DIRECTION    27
1617 #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
1618 #define F_MONITORED_DIRECTION    V_MONITORED_DIRECTION(1U)
1619 
1620 #define S_MONITORED_INTERFACE    28
1621 #define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
1622 #define F_MONITORED_INTERFACE    V_MONITORED_INTERFACE(1U)
1623 
1624 #define A_ESPI_DIP2_ERR_COUNT 0x8f4
1625 
1626 #define S_DIP2_ERR_CNT    0
1627 #define M_DIP2_ERR_CNT    0xf
1628 #define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)
1629 #define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)
1630 
1631 #define A_ESPI_CMD_ADDR 0x8f8
1632 
1633 #define S_WRITE_DATA    0
1634 #define M_WRITE_DATA    0xff
1635 #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
1636 #define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)
1637 
1638 #define S_REGISTER_OFFSET    8
1639 #define M_REGISTER_OFFSET    0xf
1640 #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
1641 #define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)
1642 
1643 #define S_CHANNEL_ADDR    12
1644 #define M_CHANNEL_ADDR    0xf
1645 #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
1646 #define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)
1647 
1648 #define S_MODULE_ADDR    16
1649 #define M_MODULE_ADDR    0x3
1650 #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
1651 #define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)
1652 
1653 #define S_BUNDLE_ADDR    20
1654 #define M_BUNDLE_ADDR    0x3
1655 #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
1656 #define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)
1657 
1658 #define S_SPI4_COMMAND    24
1659 #define M_SPI4_COMMAND    0xff
1660 #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
1661 #define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)
1662 
1663 #define A_ESPI_GOSTAT 0x8fc
1664 
1665 #define S_READ_DATA    0
1666 #define M_READ_DATA    0xff
1667 #define V_READ_DATA(x) ((x) << S_READ_DATA)
1668 #define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)
1669 
1670 #define S_ESPI_CMD_BUSY    8
1671 #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
1672 #define F_ESPI_CMD_BUSY    V_ESPI_CMD_BUSY(1U)
1673 
1674 #define S_ERROR_ACK    9
1675 #define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)
1676 #define F_ERROR_ACK    V_ERROR_ACK(1U)
1677 
1678 #define S_UNMAPPED_ERR    10
1679 #define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)
1680 #define F_UNMAPPED_ERR    V_UNMAPPED_ERR(1U)
1681 
1682 #define S_TRANSACTION_TIMER    16
1683 #define M_TRANSACTION_TIMER    0xff
1684 #define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)
1685 #define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)
1686 
1687 
1688 /* ULP registers */
1689 #define A_ULP_ULIMIT 0x980
1690 #define A_ULP_TAGMASK 0x984
1691 #define A_ULP_HREG_INDEX 0x988
1692 #define A_ULP_HREG_DATA 0x98c
1693 #define A_ULP_INT_ENABLE 0x990
1694 #define A_ULP_INT_CAUSE 0x994
1695 
1696 #define S_HREG_PAR_ERR    0
1697 #define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)
1698 #define F_HREG_PAR_ERR    V_HREG_PAR_ERR(1U)
1699 
1700 #define S_EGRS_DATA_PAR_ERR    1
1701 #define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)
1702 #define F_EGRS_DATA_PAR_ERR    V_EGRS_DATA_PAR_ERR(1U)
1703 
1704 #define S_INGRS_DATA_PAR_ERR    2
1705 #define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)
1706 #define F_INGRS_DATA_PAR_ERR    V_INGRS_DATA_PAR_ERR(1U)
1707 
1708 #define S_PM_INTR    3
1709 #define V_PM_INTR(x) ((x) << S_PM_INTR)
1710 #define F_PM_INTR    V_PM_INTR(1U)
1711 
1712 #define S_PM_E2C_SYNC_ERR    4
1713 #define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)
1714 #define F_PM_E2C_SYNC_ERR    V_PM_E2C_SYNC_ERR(1U)
1715 
1716 #define S_PM_C2E_SYNC_ERR    5
1717 #define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)
1718 #define F_PM_C2E_SYNC_ERR    V_PM_C2E_SYNC_ERR(1U)
1719 
1720 #define S_PM_E2C_EMPTY_ERR    6
1721 #define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)
1722 #define F_PM_E2C_EMPTY_ERR    V_PM_E2C_EMPTY_ERR(1U)
1723 
1724 #define S_PM_C2E_EMPTY_ERR    7
1725 #define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)
1726 #define F_PM_C2E_EMPTY_ERR    V_PM_C2E_EMPTY_ERR(1U)
1727 
1728 #define S_PM_PAR_ERR    8
1729 #define M_PM_PAR_ERR    0xffff
1730 #define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)
1731 #define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)
1732 
1733 #define S_PM_E2C_WRT_FULL    24
1734 #define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)
1735 #define F_PM_E2C_WRT_FULL    V_PM_E2C_WRT_FULL(1U)
1736 
1737 #define S_PM_C2E_WRT_FULL    25
1738 #define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)
1739 #define F_PM_C2E_WRT_FULL    V_PM_C2E_WRT_FULL(1U)
1740 
1741 #define A_ULP_PIO_CTRL 0x998
1742 
1743 /* PL registers */
1744 #define A_PL_ENABLE 0xa00
1745 
1746 #define S_PL_INTR_SGE_ERR    0
1747 #define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
1748 #define F_PL_INTR_SGE_ERR    V_PL_INTR_SGE_ERR(1U)
1749 
1750 #define S_PL_INTR_SGE_DATA    1
1751 #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
1752 #define F_PL_INTR_SGE_DATA    V_PL_INTR_SGE_DATA(1U)
1753 
1754 #define S_PL_INTR_MC3    2
1755 #define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)
1756 #define F_PL_INTR_MC3    V_PL_INTR_MC3(1U)
1757 
1758 #define S_PL_INTR_MC4    3
1759 #define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)
1760 #define F_PL_INTR_MC4    V_PL_INTR_MC4(1U)
1761 
1762 #define S_PL_INTR_MC5    4
1763 #define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)
1764 #define F_PL_INTR_MC5    V_PL_INTR_MC5(1U)
1765 
1766 #define S_PL_INTR_RAT    5
1767 #define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)
1768 #define F_PL_INTR_RAT    V_PL_INTR_RAT(1U)
1769 
1770 #define S_PL_INTR_TP    6
1771 #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
1772 #define F_PL_INTR_TP    V_PL_INTR_TP(1U)
1773 
1774 #define S_PL_INTR_ULP    7
1775 #define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)
1776 #define F_PL_INTR_ULP    V_PL_INTR_ULP(1U)
1777 
1778 #define S_PL_INTR_ESPI    8
1779 #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
1780 #define F_PL_INTR_ESPI    V_PL_INTR_ESPI(1U)
1781 
1782 #define S_PL_INTR_CSPI    9
1783 #define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)
1784 #define F_PL_INTR_CSPI    V_PL_INTR_CSPI(1U)
1785 
1786 #define S_PL_INTR_PCIX    10
1787 #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
1788 #define F_PL_INTR_PCIX    V_PL_INTR_PCIX(1U)
1789 
1790 #define S_PL_INTR_EXT    11
1791 #define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
1792 #define F_PL_INTR_EXT    V_PL_INTR_EXT(1U)
1793 
1794 #define A_PL_CAUSE 0xa04
1795 
1796 /* MC5 registers */
1797 #define A_MC5_CONFIG 0xc04
1798 
1799 #define S_MODE    0
1800 #define V_MODE(x) ((x) << S_MODE)
1801 #define F_MODE    V_MODE(1U)
1802 
1803 #define S_TCAM_RESET    1
1804 #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
1805 #define F_TCAM_RESET    V_TCAM_RESET(1U)
1806 
1807 #define S_TCAM_READY    2
1808 #define V_TCAM_READY(x) ((x) << S_TCAM_READY)
1809 #define F_TCAM_READY    V_TCAM_READY(1U)
1810 
1811 #define S_DBGI_ENABLE    4
1812 #define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)
1813 #define F_DBGI_ENABLE    V_DBGI_ENABLE(1U)
1814 
1815 #define S_M_BUS_ENABLE    5
1816 #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
1817 #define F_M_BUS_ENABLE    V_M_BUS_ENABLE(1U)
1818 
1819 #define S_PARITY_ENABLE    6
1820 #define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)
1821 #define F_PARITY_ENABLE    V_PARITY_ENABLE(1U)
1822 
1823 #define S_SYN_ISSUE_MODE    7
1824 #define M_SYN_ISSUE_MODE    0x3
1825 #define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)
1826 #define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)
1827 
1828 #define S_BUILD    16
1829 #define V_BUILD(x) ((x) << S_BUILD)
1830 #define F_BUILD    V_BUILD(1U)
1831 
1832 #define S_COMPRESSION_ENABLE    17
1833 #define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)
1834 #define F_COMPRESSION_ENABLE    V_COMPRESSION_ENABLE(1U)
1835 
1836 #define S_NUM_LIP    18
1837 #define M_NUM_LIP    0x3f
1838 #define V_NUM_LIP(x) ((x) << S_NUM_LIP)
1839 #define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)
1840 
1841 #define S_TCAM_PART_CNT    24
1842 #define M_TCAM_PART_CNT    0x3
1843 #define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)
1844 #define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)
1845 
1846 #define S_TCAM_PART_TYPE    26
1847 #define M_TCAM_PART_TYPE    0x3
1848 #define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)
1849 #define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)
1850 
1851 #define S_TCAM_PART_SIZE    28
1852 #define M_TCAM_PART_SIZE    0x3
1853 #define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)
1854 #define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)
1855 
1856 #define S_TCAM_PART_TYPE_HI    30
1857 #define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)
1858 #define F_TCAM_PART_TYPE_HI    V_TCAM_PART_TYPE_HI(1U)
1859 
1860 #define A_MC5_SIZE 0xc08
1861 
1862 #define S_SIZE    0
1863 #define M_SIZE    0x3fffff
1864 #define V_SIZE(x) ((x) << S_SIZE)
1865 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1866 
1867 #define A_MC5_ROUTING_TABLE_INDEX 0xc0c
1868 
1869 #define S_START_OF_ROUTING_TABLE    0
1870 #define M_START_OF_ROUTING_TABLE    0x3fffff
1871 #define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)
1872 #define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)
1873 
1874 #define A_MC5_SERVER_INDEX 0xc14
1875 
1876 #define S_START_OF_SERVER_INDEX    0
1877 #define M_START_OF_SERVER_INDEX    0x3fffff
1878 #define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)
1879 #define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)
1880 
1881 #define A_MC5_LIP_RAM_ADDR 0xc18
1882 
1883 #define S_LOCAL_IP_RAM_ADDR    0
1884 #define M_LOCAL_IP_RAM_ADDR    0x3f
1885 #define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)
1886 #define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)
1887 
1888 #define S_RAM_WRITE_ENABLE    8
1889 #define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)
1890 #define F_RAM_WRITE_ENABLE    V_RAM_WRITE_ENABLE(1U)
1891 
1892 #define A_MC5_LIP_RAM_DATA 0xc1c
1893 #define A_MC5_RSP_LATENCY 0xc20
1894 
1895 #define S_SEARCH_RESPONSE_LATENCY    0
1896 #define M_SEARCH_RESPONSE_LATENCY    0x1f
1897 #define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)
1898 #define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
1899 
1900 #define S_LEARN_RESPONSE_LATENCY    8
1901 #define M_LEARN_RESPONSE_LATENCY    0x1f
1902 #define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)
1903 #define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)
1904 
1905 #define A_MC5_PARITY_LATENCY 0xc24
1906 
1907 #define S_SRCHLAT    0
1908 #define M_SRCHLAT    0x1f
1909 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1910 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
1911 
1912 #define S_PARLAT    8
1913 #define M_PARLAT    0x1f
1914 #define V_PARLAT(x) ((x) << S_PARLAT)
1915 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
1916 
1917 #define A_MC5_WR_LRN_VERIFY 0xc28
1918 
1919 #define S_POVEREN    0
1920 #define V_POVEREN(x) ((x) << S_POVEREN)
1921 #define F_POVEREN    V_POVEREN(1U)
1922 
1923 #define S_LRNVEREN    1
1924 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
1925 #define F_LRNVEREN    V_LRNVEREN(1U)
1926 
1927 #define S_VWVEREN    2
1928 #define V_VWVEREN(x) ((x) << S_VWVEREN)
1929 #define F_VWVEREN    V_VWVEREN(1U)
1930 
1931 #define A_MC5_PART_ID_INDEX 0xc2c
1932 
1933 #define S_IDINDEX    0
1934 #define M_IDINDEX    0xf
1935 #define V_IDINDEX(x) ((x) << S_IDINDEX)
1936 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
1937 
1938 #define A_MC5_RESET_MAX 0xc30
1939 
1940 #define S_RSTMAX    0
1941 #define M_RSTMAX    0x1ff
1942 #define V_RSTMAX(x) ((x) << S_RSTMAX)
1943 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
1944 
1945 #define A_MC5_INT_ENABLE 0xc40
1946 
1947 #define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR    0
1948 #define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)
1949 #define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR    V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)
1950 
1951 #define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR    1
1952 #define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)
1953 #define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR    V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)
1954 
1955 #define S_MC5_INT_HIT_IN_RT_REGION_ERR    2
1956 #define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)
1957 #define F_MC5_INT_HIT_IN_RT_REGION_ERR    V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)
1958 
1959 #define S_MC5_INT_MISS_ERR    3
1960 #define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)
1961 #define F_MC5_INT_MISS_ERR    V_MC5_INT_MISS_ERR(1U)
1962 
1963 #define S_MC5_INT_LIP0_ERR    4
1964 #define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)
1965 #define F_MC5_INT_LIP0_ERR    V_MC5_INT_LIP0_ERR(1U)
1966 
1967 #define S_MC5_INT_LIP_MISS_ERR    5
1968 #define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)
1969 #define F_MC5_INT_LIP_MISS_ERR    V_MC5_INT_LIP_MISS_ERR(1U)
1970 
1971 #define S_MC5_INT_PARITY_ERR    6
1972 #define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)
1973 #define F_MC5_INT_PARITY_ERR    V_MC5_INT_PARITY_ERR(1U)
1974 
1975 #define S_MC5_INT_ACTIVE_REGION_FULL    7
1976 #define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)
1977 #define F_MC5_INT_ACTIVE_REGION_FULL    V_MC5_INT_ACTIVE_REGION_FULL(1U)
1978 
1979 #define S_MC5_INT_NFA_SRCH_ERR    8
1980 #define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)
1981 #define F_MC5_INT_NFA_SRCH_ERR    V_MC5_INT_NFA_SRCH_ERR(1U)
1982 
1983 #define S_MC5_INT_SYN_COOKIE    9
1984 #define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)
1985 #define F_MC5_INT_SYN_COOKIE    V_MC5_INT_SYN_COOKIE(1U)
1986 
1987 #define S_MC5_INT_SYN_COOKIE_BAD    10
1988 #define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)
1989 #define F_MC5_INT_SYN_COOKIE_BAD    V_MC5_INT_SYN_COOKIE_BAD(1U)
1990 
1991 #define S_MC5_INT_SYN_COOKIE_OFF    11
1992 #define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)
1993 #define F_MC5_INT_SYN_COOKIE_OFF    V_MC5_INT_SYN_COOKIE_OFF(1U)
1994 
1995 #define S_MC5_INT_UNKNOWN_CMD    15
1996 #define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)
1997 #define F_MC5_INT_UNKNOWN_CMD    V_MC5_INT_UNKNOWN_CMD(1U)
1998 
1999 #define S_MC5_INT_REQUESTQ_PARITY_ERR    16
2000 #define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)
2001 #define F_MC5_INT_REQUESTQ_PARITY_ERR    V_MC5_INT_REQUESTQ_PARITY_ERR(1U)
2002 
2003 #define S_MC5_INT_DISPATCHQ_PARITY_ERR    17
2004 #define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)
2005 #define F_MC5_INT_DISPATCHQ_PARITY_ERR    V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)
2006 
2007 #define S_MC5_INT_DEL_ACT_EMPTY    18
2008 #define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)
2009 #define F_MC5_INT_DEL_ACT_EMPTY    V_MC5_INT_DEL_ACT_EMPTY(1U)
2010 
2011 #define A_MC5_INT_CAUSE 0xc44
2012 #define A_MC5_INT_TID 0xc48
2013 #define A_MC5_INT_PTID 0xc4c
2014 #define A_MC5_DBGI_CONFIG 0xc74
2015 #define A_MC5_DBGI_REQ_CMD 0xc78
2016 
2017 #define S_CMDMODE    0
2018 #define M_CMDMODE    0x7
2019 #define V_CMDMODE(x) ((x) << S_CMDMODE)
2020 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
2021 
2022 #define S_SADRSEL    4
2023 #define V_SADRSEL(x) ((x) << S_SADRSEL)
2024 #define F_SADRSEL    V_SADRSEL(1U)
2025 
2026 #define S_WRITE_BURST_SIZE    22
2027 #define M_WRITE_BURST_SIZE    0x3ff
2028 #define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)
2029 #define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)
2030 
2031 #define A_MC5_DBGI_REQ_ADDR0 0xc7c
2032 #define A_MC5_DBGI_REQ_ADDR1 0xc80
2033 #define A_MC5_DBGI_REQ_ADDR2 0xc84
2034 #define A_MC5_DBGI_REQ_DATA0 0xc88
2035 #define A_MC5_DBGI_REQ_DATA1 0xc8c
2036 #define A_MC5_DBGI_REQ_DATA2 0xc90
2037 #define A_MC5_DBGI_REQ_DATA3 0xc94
2038 #define A_MC5_DBGI_REQ_DATA4 0xc98
2039 #define A_MC5_DBGI_REQ_MASK0 0xc9c
2040 #define A_MC5_DBGI_REQ_MASK1 0xca0
2041 #define A_MC5_DBGI_REQ_MASK2 0xca4
2042 #define A_MC5_DBGI_REQ_MASK3 0xca8
2043 #define A_MC5_DBGI_REQ_MASK4 0xcac
2044 #define A_MC5_DBGI_RSP_STATUS 0xcb0
2045 
2046 #define S_DBGI_RSP_VALID    0
2047 #define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)
2048 #define F_DBGI_RSP_VALID    V_DBGI_RSP_VALID(1U)
2049 
2050 #define S_DBGI_RSP_HIT    1
2051 #define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)
2052 #define F_DBGI_RSP_HIT    V_DBGI_RSP_HIT(1U)
2053 
2054 #define S_DBGI_RSP_ERR    2
2055 #define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)
2056 #define F_DBGI_RSP_ERR    V_DBGI_RSP_ERR(1U)
2057 
2058 #define S_DBGI_RSP_ERR_REASON    8
2059 #define M_DBGI_RSP_ERR_REASON    0x7
2060 #define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)
2061 #define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)
2062 
2063 #define A_MC5_DBGI_RSP_DATA0 0xcb4
2064 #define A_MC5_DBGI_RSP_DATA1 0xcb8
2065 #define A_MC5_DBGI_RSP_DATA2 0xcbc
2066 #define A_MC5_DBGI_RSP_DATA3 0xcc0
2067 #define A_MC5_DBGI_RSP_DATA4 0xcc4
2068 #define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2069 #define A_MC5_POPEN_DATA_WR_CMD 0xccc
2070 #define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2071 #define A_MC5_AOPEN_SRCH_CMD 0xcd4
2072 #define A_MC5_AOPEN_LRN_CMD 0xcd8
2073 #define A_MC5_SYN_SRCH_CMD 0xcdc
2074 #define A_MC5_SYN_LRN_CMD 0xce0
2075 #define A_MC5_ACK_SRCH_CMD 0xce4
2076 #define A_MC5_ACK_LRN_CMD 0xce8
2077 #define A_MC5_ILOOKUP_CMD 0xcec
2078 #define A_MC5_ELOOKUP_CMD 0xcf0
2079 #define A_MC5_DATA_WRITE_CMD 0xcf4
2080 #define A_MC5_DATA_READ_CMD 0xcf8
2081 #define A_MC5_MASK_WRITE_CMD 0xcfc
2082 
2083 /* PCICFG registers */
2084 #define A_PCICFG_PM_CSR 0x44
2085 #define A_PCICFG_VPD_ADDR 0x4a
2086 
2087 #define S_VPD_ADDR    0
2088 #define M_VPD_ADDR    0x7fff
2089 #define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)
2090 #define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)
2091 
2092 #define S_VPD_OP_FLAG    15
2093 #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
2094 #define F_VPD_OP_FLAG    V_VPD_OP_FLAG(1U)
2095 
2096 #define A_PCICFG_VPD_DATA 0x4c
2097 #define A_PCICFG_PCIX_CMD 0x60
2098 #define A_PCICFG_INTR_ENABLE 0xf4
2099 
2100 #define S_MASTER_PARITY_ERR    0
2101 #define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)
2102 #define F_MASTER_PARITY_ERR    V_MASTER_PARITY_ERR(1U)
2103 
2104 #define S_SIG_TARGET_ABORT    1
2105 #define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)
2106 #define F_SIG_TARGET_ABORT    V_SIG_TARGET_ABORT(1U)
2107 
2108 #define S_RCV_TARGET_ABORT    2
2109 #define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)
2110 #define F_RCV_TARGET_ABORT    V_RCV_TARGET_ABORT(1U)
2111 
2112 #define S_RCV_MASTER_ABORT    3
2113 #define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)
2114 #define F_RCV_MASTER_ABORT    V_RCV_MASTER_ABORT(1U)
2115 
2116 #define S_SIG_SYS_ERR    4
2117 #define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)
2118 #define F_SIG_SYS_ERR    V_SIG_SYS_ERR(1U)
2119 
2120 #define S_DET_PARITY_ERR    5
2121 #define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)
2122 #define F_DET_PARITY_ERR    V_DET_PARITY_ERR(1U)
2123 
2124 #define S_PIO_PARITY_ERR    6
2125 #define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)
2126 #define F_PIO_PARITY_ERR    V_PIO_PARITY_ERR(1U)
2127 
2128 #define S_WF_PARITY_ERR    7
2129 #define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)
2130 #define F_WF_PARITY_ERR    V_WF_PARITY_ERR(1U)
2131 
2132 #define S_RF_PARITY_ERR    8
2133 #define M_RF_PARITY_ERR    0x3
2134 #define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)
2135 #define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)
2136 
2137 #define S_CF_PARITY_ERR    10
2138 #define M_CF_PARITY_ERR    0x3
2139 #define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)
2140 #define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)
2141 
2142 #define A_PCICFG_INTR_CAUSE 0xf8
2143 #define A_PCICFG_MODE 0xfc
2144 
2145 #define S_PCI_MODE_64BIT    0
2146 #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
2147 #define F_PCI_MODE_64BIT    V_PCI_MODE_64BIT(1U)
2148 
2149 #define S_PCI_MODE_66MHZ    1
2150 #define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)
2151 #define F_PCI_MODE_66MHZ    V_PCI_MODE_66MHZ(1U)
2152 
2153 #define S_PCI_MODE_PCIX_INITPAT    2
2154 #define M_PCI_MODE_PCIX_INITPAT    0x7
2155 #define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)
2156 #define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)
2157 
2158 #define S_PCI_MODE_PCIX    5
2159 #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
2160 #define F_PCI_MODE_PCIX    V_PCI_MODE_PCIX(1U)
2161 
2162 #define S_PCI_MODE_CLK    6
2163 #define M_PCI_MODE_CLK    0x3
2164 #define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)
2165 #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
2166 
2167 #endif /* _CXGB_REGS_H_ */
2168