1 // SPDX-License-Identifier: GPL-2.0-only
2 /*****************************************************************************
3  *                                                                           *
4  * File: pm3393.c                                                            *
5  * $Revision: 1.16 $                                                         *
6  * $Date: 2005/05/14 00:59:32 $                                              *
7  * Description:                                                              *
8  *  PMC/SIERRA (pm3393) MAC-PHY functionality.                               *
9  *  part of the Chelsio 10Gb Ethernet Driver.                                *
10  *                                                                           *
11  *                                                                           *
12  * http://www.chelsio.com                                                    *
13  *                                                                           *
14  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
15  * All rights reserved.                                                      *
16  *                                                                           *
17  * Maintainers: maintainers@chelsio.com                                      *
18  *                                                                           *
19  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
20  *          Tina Yang               <tainay@chelsio.com>                     *
21  *          Felix Marti             <felix@chelsio.com>                      *
22  *          Scott Bardone           <sbardone@chelsio.com>                   *
23  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
24  *          Frank DiMambro          <frank@chelsio.com>                      *
25  *                                                                           *
26  * History:                                                                  *
27  *                                                                           *
28  ****************************************************************************/
29 
30 #include "common.h"
31 #include "regs.h"
32 #include "gmac.h"
33 #include "elmer0.h"
34 #include "suni1x10gexp_regs.h"
35 
36 #include <linux/crc32.h>
37 #include <linux/slab.h>
38 
39 #define OFFSET(REG_ADDR)    ((REG_ADDR) << 2)
40 
41 #define IPG 12
42 #define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \
43 	SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \
44 	SUNI1x10GEXP_BITMSK_TXXG_PADEN)
45 #define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
46 	SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP)
47 
48 /* Update statistics every 15 minutes */
49 #define STATS_TICK_SECS (15 * 60)
50 
51 enum {                     /* RMON registers */
52 	RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW,
53 	RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW,
54 	RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW,
55 	RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW,
56 	RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW,
57 	RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW,
58 	RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW,
59 	RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW,
60 	RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW,
61 	RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW,
62 	RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
63 	RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
64 	RxUndersizedFrames =  SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
65 	RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
66 	RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
67 
68 	TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
69 	TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
70 	TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW,
71 	TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
72 	TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
73 	TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
74 	TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
75 	TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
76 	TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
77 };
78 
79 struct _cmac_instance {
80 	u8 enabled;
81 	u8 fc;
82 	u8 mac_addr[6];
83 };
84 
85 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
86 {
87 	t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
88 	return 0;
89 }
90 
91 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
92 {
93 	t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
94 	return 0;
95 }
96 
97 /* Port reset. */
98 static int pm3393_reset(struct cmac *cmac)
99 {
100 	return 0;
101 }
102 
103 /*
104  * Enable interrupts for the PM3393
105  *
106  *	1. Enable PM3393 BLOCK interrupts.
107  *	2. Enable PM3393 Master Interrupt bit(INTE)
108  *	3. Enable ELMER's PM3393 bit.
109  *	4. Enable Terminator external interrupt.
110  */
111 static int pm3393_interrupt_enable(struct cmac *cmac)
112 {
113 	u32 pl_intr;
114 
115 	/* PM3393 - Enabling all hardware block interrupts.
116 	 */
117 	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
118 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
119 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
120 	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
121 
122 	/* Don't interrupt on statistics overflow, we are polling */
123 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
124 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
125 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
126 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
127 
128 	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
129 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
130 	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
131 	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
132 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
133 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
134 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
135 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
136 	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
137 
138 	/* PM3393 - Global interrupt enable
139 	 */
140 	/* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */
141 	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
142 		0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ );
143 
144 	/* TERMINATOR - PL_INTERUPTS_EXT */
145 	pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
146 	pl_intr |= F_PL_INTR_EXT;
147 	writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
148 	return 0;
149 }
150 
151 static int pm3393_interrupt_disable(struct cmac *cmac)
152 {
153 	u32 elmer;
154 
155 	/* PM3393 - Enabling HW interrupt blocks. */
156 	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
157 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
158 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
159 	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
160 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
161 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
162 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
163 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
164 	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
165 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
166 	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
167 	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
168 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
169 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
170 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
171 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
172 	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
173 
174 	/* PM3393 - Global interrupt enable */
175 	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
176 
177 	/* ELMER - External chip interrupts. */
178 	t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
179 	elmer &= ~ELMER0_GP_BIT1;
180 	t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
181 
182 	/* TERMINATOR - PL_INTERUPTS_EXT */
183 	/* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP
184 	 * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.
185 	 */
186 
187 	return 0;
188 }
189 
190 static int pm3393_interrupt_clear(struct cmac *cmac)
191 {
192 	u32 elmer;
193 	u32 pl_intr;
194 	u32 val32;
195 
196 	/* PM3393 - Clearing HW interrupt blocks. Note, this assumes
197 	 *          bit WCIMODE=0 for a clear-on-read.
198 	 */
199 	pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
200 	pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
201 	pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
202 	pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
203 	pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
204 	pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
205 	pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
206 	pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
207 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
208 	pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
209 	pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
210 	pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
211 	       &val32);
212 	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
213 	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
214 
215 	/* PM3393 - Global interrupt status
216 	 */
217 	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
218 
219 	/* ELMER - External chip interrupts.
220 	 */
221 	t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
222 	elmer |= ELMER0_GP_BIT1;
223 	t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
224 
225 	/* TERMINATOR - PL_INTERUPTS_EXT
226 	 */
227 	pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
228 	pl_intr |= F_PL_INTR_EXT;
229 	writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
230 
231 	return 0;
232 }
233 
234 /* Interrupt handler */
235 static int pm3393_interrupt_handler(struct cmac *cmac)
236 {
237 	u32 master_intr_status;
238 
239 	/* Read the master interrupt status register. */
240 	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
241 	       &master_intr_status);
242 	if (netif_msg_intr(cmac->adapter))
243 		dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",
244 			master_intr_status);
245 
246 	/* TBD XXX Lets just clear everything for now */
247 	pm3393_interrupt_clear(cmac);
248 
249 	return 0;
250 }
251 
252 static int pm3393_enable(struct cmac *cmac, int which)
253 {
254 	if (which & MAC_DIRECTION_RX)
255 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
256 			(RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN));
257 
258 	if (which & MAC_DIRECTION_TX) {
259 		u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0;
260 
261 		if (cmac->instance->fc & PAUSE_RX)
262 			val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX;
263 		if (cmac->instance->fc & PAUSE_TX)
264 			val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX;
265 		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
266 	}
267 
268 	cmac->instance->enabled |= which;
269 	return 0;
270 }
271 
272 static int pm3393_enable_port(struct cmac *cmac, int which)
273 {
274 	/* Clear port statistics */
275 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
276 		SUNI1x10GEXP_BITMSK_MSTAT_CLEAR);
277 	udelay(2);
278 	memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
279 
280 	pm3393_enable(cmac, which);
281 
282 	/*
283 	 * XXX This should be done by the PHY and preferably not at all.
284 	 * The PHY doesn't give us link status indication on its own so have
285 	 * the link management code query it instead.
286 	 */
287 	t1_link_changed(cmac->adapter, 0);
288 	return 0;
289 }
290 
291 static int pm3393_disable(struct cmac *cmac, int which)
292 {
293 	if (which & MAC_DIRECTION_RX)
294 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
295 	if (which & MAC_DIRECTION_TX)
296 		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
297 
298 	/*
299 	 * The disable is graceful. Give the PM3393 time.  Can't wait very
300 	 * long here, we may be holding locks.
301 	 */
302 	udelay(20);
303 
304 	cmac->instance->enabled &= ~which;
305 	return 0;
306 }
307 
308 static int pm3393_loopback_enable(struct cmac *cmac)
309 {
310 	return 0;
311 }
312 
313 static int pm3393_loopback_disable(struct cmac *cmac)
314 {
315 	return 0;
316 }
317 
318 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
319 {
320 	int enabled = cmac->instance->enabled;
321 
322 	mtu += ETH_HLEN + ETH_FCS_LEN;
323 
324 	/* Disable Rx/Tx MAC before configuring it. */
325 	if (enabled)
326 		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
327 
328 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
329 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
330 
331 	if (enabled)
332 		pm3393_enable(cmac, enabled);
333 	return 0;
334 }
335 
336 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
337 {
338 	int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
339 	u32 rx_mode;
340 
341 	/* Disable MAC RX before reconfiguring it */
342 	if (enabled)
343 		pm3393_disable(cmac, MAC_DIRECTION_RX);
344 
345 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
346 	rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE |
347 		     SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN);
348 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
349 		(u16)rx_mode);
350 
351 	if (t1_rx_mode_promisc(rm)) {
352 		/* Promiscuous mode. */
353 		rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE;
354 	}
355 	if (t1_rx_mode_allmulti(rm)) {
356 		/* Accept all multicast. */
357 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
358 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
359 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
360 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
361 		rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
362 	} else if (t1_rx_mode_mc_cnt(rm)) {
363 		/* Accept one or more multicast(s). */
364 		struct netdev_hw_addr *ha;
365 		int bit;
366 		u16 mc_filter[4] = { 0, };
367 
368 		netdev_for_each_mc_addr(ha, t1_get_netdev(rm)) {
369 			/* bit[23:28] */
370 			bit = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x3f;
371 			mc_filter[bit >> 4] |= 1 << (bit & 0xf);
372 		}
373 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
374 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
375 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
376 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
377 		rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
378 	}
379 
380 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
381 
382 	if (enabled)
383 		pm3393_enable(cmac, MAC_DIRECTION_RX);
384 
385 	return 0;
386 }
387 
388 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
389 				      int *duplex, int *fc)
390 {
391 	if (speed)
392 		*speed = SPEED_10000;
393 	if (duplex)
394 		*duplex = DUPLEX_FULL;
395 	if (fc)
396 		*fc = cmac->instance->fc;
397 	return 0;
398 }
399 
400 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
401 				      int fc)
402 {
403 	if (speed >= 0 && speed != SPEED_10000)
404 		return -1;
405 	if (duplex >= 0 && duplex != DUPLEX_FULL)
406 		return -1;
407 	if (fc & ~(PAUSE_TX | PAUSE_RX))
408 		return -1;
409 
410 	if (fc != cmac->instance->fc) {
411 		cmac->instance->fc = (u8) fc;
412 		if (cmac->instance->enabled & MAC_DIRECTION_TX)
413 			pm3393_enable(cmac, MAC_DIRECTION_TX);
414 	}
415 	return 0;
416 }
417 
418 #define RMON_UPDATE(mac, name, stat_name) \
419 { \
420 	t1_tpi_read((mac)->adapter, OFFSET(name), &val0);     \
421 	t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \
422 	t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \
423 	(mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
424 				 ((u64)(val1 & 0xffff) << 16) | \
425 				 ((u64)(val2 & 0xff) << 32) | \
426 				 ((mac)->stats.stat_name & \
427 					0xffffff0000000000ULL); \
428 	if (ro & \
429 	    (1ULL << ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2))) \
430 		(mac)->stats.stat_name += 1ULL << 40; \
431 }
432 
433 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
434 							      int flag)
435 {
436 	u64	ro;
437 	u32	val0, val1, val2, val3;
438 
439 	/* Snap the counters */
440 	pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
441 		SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
442 
443 	/* Counter rollover, clear on read */
444 	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
445 	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1);
446 	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2);
447 	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3);
448 	ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
449 		(((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
450 
451 	/* Rx stats */
452 	RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK);
453 	RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK);
454 	RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK);
455 	RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK);
456 	RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames);
457 	RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors);
458 	RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors,
459 				RxInternalMACRcvError);
460 	RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
461 	RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors);
462 	RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors);
463 	RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
464 	RMON_UPDATE(mac, RxFragments, RxRuntErrors);
465 	RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
466 	RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
467 	RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
468 
469 	/* Tx stats */
470 	RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
471 	RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError,
472 				TxInternalMACXmitError);
473 	RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors);
474 	RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK);
475 	RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
476 	RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
477 	RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
478 	RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
479 	RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
480 
481 	return &mac->stats;
482 }
483 
484 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
485 {
486 	memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);
487 	return 0;
488 }
489 
490 static int pm3393_macaddress_set(struct cmac *cmac, const u8 ma[6])
491 {
492 	u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
493 
494 	/*
495 	 * MAC addr: 00:07:43:00:13:09
496 	 *
497 	 * ma[5] = 0x09
498 	 * ma[4] = 0x13
499 	 * ma[3] = 0x00
500 	 * ma[2] = 0x43
501 	 * ma[1] = 0x07
502 	 * ma[0] = 0x00
503 	 *
504 	 * The PM3393 requires byte swapping and reverse order entry
505 	 * when programming MAC addresses:
506 	 *
507 	 * low_bits[15:0]    = ma[1]:ma[0]
508 	 * mid_bits[31:16]   = ma[3]:ma[2]
509 	 * high_bits[47:32]  = ma[5]:ma[4]
510 	 */
511 
512 	/* Store local copy */
513 	memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);
514 
515 	lo  = ((u32) ma[1] << 8) | (u32) ma[0];
516 	mid = ((u32) ma[3] << 8) | (u32) ma[2];
517 	hi  = ((u32) ma[5] << 8) | (u32) ma[4];
518 
519 	/* Disable Rx/Tx MAC before configuring it. */
520 	if (enabled)
521 		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
522 
523 	/* Set RXXG Station Address */
524 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
525 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
526 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
527 
528 	/* Set TXXG Station Address */
529 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
530 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
531 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
532 
533 	/* Setup Exact Match Filter 1 with our MAC address
534 	 *
535 	 * Must disable exact match filter before configuring it.
536 	 */
537 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
538 	val &= 0xff0f;
539 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
540 
541 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
542 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
543 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
544 
545 	val |= 0x0090;
546 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
547 
548 	if (enabled)
549 		pm3393_enable(cmac, enabled);
550 	return 0;
551 }
552 
553 static void pm3393_destroy(struct cmac *cmac)
554 {
555 	kfree(cmac);
556 }
557 
558 static const struct cmac_ops pm3393_ops = {
559 	.destroy                 = pm3393_destroy,
560 	.reset                   = pm3393_reset,
561 	.interrupt_enable        = pm3393_interrupt_enable,
562 	.interrupt_disable       = pm3393_interrupt_disable,
563 	.interrupt_clear         = pm3393_interrupt_clear,
564 	.interrupt_handler       = pm3393_interrupt_handler,
565 	.enable                  = pm3393_enable_port,
566 	.disable                 = pm3393_disable,
567 	.loopback_enable         = pm3393_loopback_enable,
568 	.loopback_disable        = pm3393_loopback_disable,
569 	.set_mtu                 = pm3393_set_mtu,
570 	.set_rx_mode             = pm3393_set_rx_mode,
571 	.get_speed_duplex_fc     = pm3393_get_speed_duplex_fc,
572 	.set_speed_duplex_fc     = pm3393_set_speed_duplex_fc,
573 	.statistics_update       = pm3393_update_statistics,
574 	.macaddress_get          = pm3393_macaddress_get,
575 	.macaddress_set          = pm3393_macaddress_set
576 };
577 
578 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
579 {
580 	struct cmac *cmac;
581 
582 	cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
583 	if (!cmac)
584 		return NULL;
585 
586 	cmac->ops = &pm3393_ops;
587 	cmac->instance = (cmac_instance *) (cmac + 1);
588 	cmac->adapter = adapter;
589 	cmac->instance->fc = PAUSE_TX | PAUSE_RX;
590 
591 	t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
592 	t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
593 	t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
594 	t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001);   /* PL4IO Enable */
595 	t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
596 	t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
597 	t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
598 	t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
599 	t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
600 	t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
601 	t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
602 	t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
603 	t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
604 	t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
605 	t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
606 	t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
607 	t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
608 	t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
609 	t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
610 	t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
611 	t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
612 	t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202);	/* PL4IO Calendar Repetitions */
613 
614 	t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080);	/* EFLX Enable */
615 	t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000);	/* EFLX Channel Deprovision */
616 	t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000);	/* EFLX Low Limit */
617 	t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040);	/* EFLX High Limit */
618 	t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc);	/* EFLX Almost Full */
619 	t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199);	/* EFLX Almost Empty */
620 	t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240);	/* EFLX Cut Through Threshold */
621 	t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000);	/* EFLX Indirect Register Update */
622 	t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001);	/* EFLX Channel Provision */
623 	t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff);	/* EFLX Undocumented */
624 	t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff);	/* EFLX Undocumented */
625 	t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff);	/* EFLX enable overflow interrupt The other bit are undocumented */
626 	t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff);	/* EFLX Undocumented */
627 
628 	t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000);	/* IFLX Configuration - enable */
629 	t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000);	/* IFLX Channel Deprovision */
630 	t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000);	/* IFLX Low Limit */
631 	t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100);	/* IFLX High Limit */
632 	t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00);	/* IFLX Almost Full Limit */
633 	t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599);	/* IFLX Almost Empty Limit */
634 	t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000);	/* IFLX Indirect Register Update */
635 	t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001);	/* IFLX Channel Provision */
636 	t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff);	/* IFLX Undocumented */
637 	t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff);	/* IFLX Undocumented */
638 	t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff);	/* IFLX Enable overflow interrupt.  The other bit are undocumented */
639 
640 	t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe);	/* PL4MOS Undocumented */
641 	t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff);	/* PL4MOS Undocumented */
642 	t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008);	/* PL4MOS Starving Burst Size */
643 	t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008);	/* PL4MOS Hungry Burst Size */
644 	t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008);	/* PL4MOS Transfer Size */
645 	t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005);	/* PL4MOS Disable */
646 
647 	t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103);	/* PL4ODP Training Repeat and SOP rule */
648 	t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000);	/* PL4ODP MAX_T setting */
649 
650 	t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087);	/* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
651 	t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f);	/* PL4IDU Enable Dip4 check error interrupts */
652 
653 	t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32);	/* # TXXG Config */
654 	/* For T1 use timer based Mac flow control. */
655 	t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
656 	t1_tpi_write(adapter, OFFSET(0x2040), 0x059c);	/* # RXXG Config */
657 	t1_tpi_write(adapter, OFFSET(0x2049), 0x0001);	/* # RXXG Cut Through */
658 	t1_tpi_write(adapter, OFFSET(0x2070), 0x0000);	/* # Disable promiscuous mode */
659 
660 	/* Setup Exact Match Filter 0 to allow broadcast packets.
661 	 */
662 	t1_tpi_write(adapter, OFFSET(0x206e), 0x0000);	/* # Disable Match Enable bit */
663 	t1_tpi_write(adapter, OFFSET(0x204a), 0xffff);	/* # low addr */
664 	t1_tpi_write(adapter, OFFSET(0x204b), 0xffff);	/* # mid addr */
665 	t1_tpi_write(adapter, OFFSET(0x204c), 0xffff);	/* # high addr */
666 	t1_tpi_write(adapter, OFFSET(0x206e), 0x0009);	/* # Enable Match Enable bit */
667 
668 	t1_tpi_write(adapter, OFFSET(0x0003), 0x0000);	/* # NO SOP/ PAD_EN setup */
669 	t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0);	/* # RXEQB disabled */
670 	t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f);	/* # No Preemphasis */
671 
672 	return cmac;
673 }
674 
675 static int pm3393_mac_reset(adapter_t * adapter)
676 {
677 	u32 val;
678 	u32 x;
679 	u32 is_pl4_reset_finished;
680 	u32 is_pl4_outof_lock;
681 	u32 is_xaui_mabc_pll_locked;
682 	u32 successful_reset;
683 	int i;
684 
685 	/* The following steps are required to properly reset
686 	 * the PM3393. This information is provided in the
687 	 * PM3393 datasheet (Issue 2: November 2002)
688 	 * section 13.1 -- Device Reset.
689 	 *
690 	 * The PM3393 has three types of components that are
691 	 * individually reset:
692 	 *
693 	 * DRESETB      - Digital circuitry
694 	 * PL4_ARESETB  - PL4 analog circuitry
695 	 * XAUI_ARESETB - XAUI bus analog circuitry
696 	 *
697 	 * Steps to reset PM3393 using RSTB pin:
698 	 *
699 	 * 1. Assert RSTB pin low ( write 0 )
700 	 * 2. Wait at least 1ms to initiate a complete initialization of device.
701 	 * 3. Wait until all external clocks and REFSEL are stable.
702 	 * 4. Wait minimum of 1ms. (after external clocks and REFEL are stable)
703 	 * 5. De-assert RSTB ( write 1 )
704 	 * 6. Wait until internal timers to expires after ~14ms.
705 	 *    - Allows analog clock synthesizer(PL4CSU) to stabilize to
706 	 *      selected reference frequency before allowing the digital
707 	 *      portion of the device to operate.
708 	 * 7. Wait at least 200us for XAUI interface to stabilize.
709 	 * 8. Verify the PM3393 came out of reset successfully.
710 	 *    Set successful reset flag if everything worked else try again
711 	 *    a few more times.
712 	 */
713 
714 	successful_reset = 0;
715 	for (i = 0; i < 3 && !successful_reset; i++) {
716 		/* 1 */
717 		t1_tpi_read(adapter, A_ELMER0_GPO, &val);
718 		val &= ~1;
719 		t1_tpi_write(adapter, A_ELMER0_GPO, val);
720 
721 		/* 2 */
722 		msleep(1);
723 
724 		/* 3 */
725 		msleep(1);
726 
727 		/* 4 */
728 		msleep(2 /*1 extra ms for safety */ );
729 
730 		/* 5 */
731 		val |= 1;
732 		t1_tpi_write(adapter, A_ELMER0_GPO, val);
733 
734 		/* 6 */
735 		msleep(15 /*1 extra ms for safety */ );
736 
737 		/* 7 */
738 		msleep(1);
739 
740 		/* 8 */
741 
742 		/* Has PL4 analog block come out of reset correctly? */
743 		t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);
744 		is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED);
745 
746 		/* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence
747 		 *         figure out why? */
748 
749 		/* Have all PL4 block clocks locked? */
750 		x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL
751 		     /*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */  |
752 		     SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL |
753 		     SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL |
754 		     SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL);
755 		is_pl4_outof_lock = (val & x);
756 
757 		/* ??? If this fails, might be able to software reset the XAUI part
758 		 *     and try to recover... thus saving us from doing another HW reset */
759 		/* Has the XAUI MABC PLL circuitry stablized? */
760 		is_xaui_mabc_pll_locked =
761 		    (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED);
762 
763 		successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
764 				    && is_xaui_mabc_pll_locked);
765 
766 		if (netif_msg_hw(adapter))
767 			dev_dbg(&adapter->pdev->dev,
768 				"PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
769 				"is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
770 				i, is_pl4_reset_finished, val,
771 				is_pl4_outof_lock, is_xaui_mabc_pll_locked);
772 	}
773 	return successful_reset ? 0 : 1;
774 }
775 
776 const struct gmac t1_pm3393_ops = {
777 	.stats_update_period = STATS_TICK_SECS,
778 	.create              = pm3393_mac_create,
779 	.reset               = pm3393_mac_reset,
780 };
781