1 /*****************************************************************************
2  *                                                                           *
3  * File: elmer0.h                                                            *
4  * $Revision: 1.6 $                                                          *
5  * $Date: 2005/06/21 22:49:43 $                                              *
6  * Description:                                                              *
7  *  part of the Chelsio 10Gb Ethernet Driver.                                *
8  *                                                                           *
9  * This program is free software; you can redistribute it and/or modify      *
10  * it under the terms of the GNU General Public License, version 2, as       *
11  * published by the Free Software Foundation.                                *
12  *                                                                           *
13  * You should have received a copy of the GNU General Public License along   *
14  * with this program; if not, see <http://www.gnu.org/licenses/>.            *
15  *                                                                           *
16  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
17  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
19  *                                                                           *
20  * http://www.chelsio.com                                                    *
21  *                                                                           *
22  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
23  * All rights reserved.                                                      *
24  *                                                                           *
25  * Maintainers: maintainers@chelsio.com                                      *
26  *                                                                           *
27  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
28  *          Tina Yang               <tainay@chelsio.com>                     *
29  *          Felix Marti             <felix@chelsio.com>                      *
30  *          Scott Bardone           <sbardone@chelsio.com>                   *
31  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
32  *          Frank DiMambro          <frank@chelsio.com>                      *
33  *                                                                           *
34  * History:                                                                  *
35  *                                                                           *
36  ****************************************************************************/
37 
38 #ifndef _CXGB_ELMER0_H_
39 #define _CXGB_ELMER0_H_
40 
41 /* ELMER0 flavors */
42 enum {
43 	ELMER0_XC2S300E_6FT256_C,
44 	ELMER0_XC2S100E_6TQ144_C
45 };
46 
47 /* ELMER0 registers */
48 #define A_ELMER0_VERSION	0x100000
49 #define A_ELMER0_PHY_CFG	0x100004
50 #define A_ELMER0_INT_ENABLE	0x100008
51 #define A_ELMER0_INT_CAUSE	0x10000c
52 #define A_ELMER0_GPI_CFG	0x100010
53 #define A_ELMER0_GPI_STAT	0x100014
54 #define A_ELMER0_GPO		0x100018
55 #define A_ELMER0_PORT0_MI1_CFG	0x400000
56 
57 #define S_MI1_MDI_ENABLE    0
58 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
59 #define F_MI1_MDI_ENABLE    V_MI1_MDI_ENABLE(1U)
60 
61 #define S_MI1_MDI_INVERT    1
62 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
63 #define F_MI1_MDI_INVERT    V_MI1_MDI_INVERT(1U)
64 
65 #define S_MI1_PREAMBLE_ENABLE    2
66 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
67 #define F_MI1_PREAMBLE_ENABLE    V_MI1_PREAMBLE_ENABLE(1U)
68 
69 #define S_MI1_SOF    3
70 #define M_MI1_SOF    0x3
71 #define V_MI1_SOF(x) ((x) << S_MI1_SOF)
72 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
73 
74 #define S_MI1_CLK_DIV    5
75 #define M_MI1_CLK_DIV    0xff
76 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
77 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
78 
79 #define A_ELMER0_PORT0_MI1_ADDR 0x400004
80 
81 #define S_MI1_REG_ADDR    0
82 #define M_MI1_REG_ADDR    0x1f
83 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
84 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
85 
86 #define S_MI1_PHY_ADDR    5
87 #define M_MI1_PHY_ADDR    0x1f
88 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
89 #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
90 
91 #define A_ELMER0_PORT0_MI1_DATA 0x400008
92 
93 #define S_MI1_DATA    0
94 #define M_MI1_DATA    0xffff
95 #define V_MI1_DATA(x) ((x) << S_MI1_DATA)
96 #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
97 
98 #define A_ELMER0_PORT0_MI1_OP 0x40000c
99 
100 #define S_MI1_OP    0
101 #define M_MI1_OP    0x3
102 #define V_MI1_OP(x) ((x) << S_MI1_OP)
103 #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
104 
105 #define S_MI1_ADDR_AUTOINC    2
106 #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
107 #define F_MI1_ADDR_AUTOINC    V_MI1_ADDR_AUTOINC(1U)
108 
109 #define S_MI1_OP_BUSY    31
110 #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
111 #define F_MI1_OP_BUSY    V_MI1_OP_BUSY(1U)
112 
113 #define A_ELMER0_PORT1_MI1_CFG	0x500000
114 #define A_ELMER0_PORT1_MI1_ADDR	0x500004
115 #define A_ELMER0_PORT1_MI1_DATA	0x500008
116 #define A_ELMER0_PORT1_MI1_OP	0x50000c
117 #define A_ELMER0_PORT2_MI1_CFG	0x600000
118 #define A_ELMER0_PORT2_MI1_ADDR	0x600004
119 #define A_ELMER0_PORT2_MI1_DATA	0x600008
120 #define A_ELMER0_PORT2_MI1_OP	0x60000c
121 #define A_ELMER0_PORT3_MI1_CFG	0x700000
122 #define A_ELMER0_PORT3_MI1_ADDR	0x700004
123 #define A_ELMER0_PORT3_MI1_DATA	0x700008
124 #define A_ELMER0_PORT3_MI1_OP	0x70000c
125 
126 /* Simple bit definition for GPI and GP0 registers. */
127 #define     ELMER0_GP_BIT0              0x0001
128 #define     ELMER0_GP_BIT1              0x0002
129 #define     ELMER0_GP_BIT2              0x0004
130 #define     ELMER0_GP_BIT3              0x0008
131 #define     ELMER0_GP_BIT4              0x0010
132 #define     ELMER0_GP_BIT5              0x0020
133 #define     ELMER0_GP_BIT6              0x0040
134 #define     ELMER0_GP_BIT7              0x0080
135 #define     ELMER0_GP_BIT8              0x0100
136 #define     ELMER0_GP_BIT9              0x0200
137 #define     ELMER0_GP_BIT10             0x0400
138 #define     ELMER0_GP_BIT11             0x0800
139 #define     ELMER0_GP_BIT12             0x1000
140 #define     ELMER0_GP_BIT13             0x2000
141 #define     ELMER0_GP_BIT14             0x4000
142 #define     ELMER0_GP_BIT15             0x8000
143 #define     ELMER0_GP_BIT16             0x10000
144 #define     ELMER0_GP_BIT17             0x20000
145 #define     ELMER0_GP_BIT18             0x40000
146 #define     ELMER0_GP_BIT19             0x80000
147 
148 #define MI1_OP_DIRECT_WRITE 1
149 #define MI1_OP_DIRECT_READ  2
150 
151 #define MI1_OP_INDIRECT_ADDRESS  0
152 #define MI1_OP_INDIRECT_WRITE    1
153 #define MI1_OP_INDIRECT_READ_INC 2
154 #define MI1_OP_INDIRECT_READ     3
155 
156 #endif /* _CXGB_ELMER0_H_ */
157 
158