1 /*****************************************************************************
2  *                                                                           *
3  * File: cpl5_cmd.h                                                          *
4  * $Revision: 1.6 $                                                          *
5  * $Date: 2005/06/21 18:29:47 $                                              *
6  * Description:                                                              *
7  *  part of the Chelsio 10Gb Ethernet Driver.                                *
8  *                                                                           *
9  * This program is free software; you can redistribute it and/or modify      *
10  * it under the terms of the GNU General Public License, version 2, as       *
11  * published by the Free Software Foundation.                                *
12  *                                                                           *
13  * You should have received a copy of the GNU General Public License along   *
14  * with this program; if not, see <http://www.gnu.org/licenses/>.            *
15  *                                                                           *
16  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
17  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
19  *                                                                           *
20  * http://www.chelsio.com                                                    *
21  *                                                                           *
22  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
23  * All rights reserved.                                                      *
24  *                                                                           *
25  * Maintainers: maintainers@chelsio.com                                      *
26  *                                                                           *
27  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
28  *          Tina Yang               <tainay@chelsio.com>                     *
29  *          Felix Marti             <felix@chelsio.com>                      *
30  *          Scott Bardone           <sbardone@chelsio.com>                   *
31  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
32  *          Frank DiMambro          <frank@chelsio.com>                      *
33  *                                                                           *
34  * History:                                                                  *
35  *                                                                           *
36  ****************************************************************************/
37 
38 #ifndef _CXGB_CPL5_CMD_H_
39 #define _CXGB_CPL5_CMD_H_
40 
41 #include <asm/byteorder.h>
42 
43 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
44 #error "Adjust your <asm/byteorder.h> defines"
45 #endif
46 
47 enum CPL_opcode {
48 	CPL_PASS_OPEN_REQ     = 0x1,
49 	CPL_PASS_OPEN_RPL     = 0x2,
50 	CPL_PASS_ESTABLISH    = 0x3,
51 	CPL_PASS_ACCEPT_REQ   = 0xE,
52 	CPL_PASS_ACCEPT_RPL   = 0x4,
53 	CPL_ACT_OPEN_REQ      = 0x5,
54 	CPL_ACT_OPEN_RPL      = 0x6,
55 	CPL_CLOSE_CON_REQ     = 0x7,
56 	CPL_CLOSE_CON_RPL     = 0x8,
57 	CPL_CLOSE_LISTSRV_REQ = 0x9,
58 	CPL_CLOSE_LISTSRV_RPL = 0xA,
59 	CPL_ABORT_REQ         = 0xB,
60 	CPL_ABORT_RPL         = 0xC,
61 	CPL_PEER_CLOSE        = 0xD,
62 	CPL_ACT_ESTABLISH     = 0x17,
63 
64 	CPL_GET_TCB           = 0x24,
65 	CPL_GET_TCB_RPL       = 0x25,
66 	CPL_SET_TCB           = 0x26,
67 	CPL_SET_TCB_FIELD     = 0x27,
68 	CPL_SET_TCB_RPL       = 0x28,
69 	CPL_PCMD              = 0x29,
70 
71 	CPL_PCMD_READ         = 0x31,
72 	CPL_PCMD_READ_RPL     = 0x32,
73 
74 
75 	CPL_RX_DATA           = 0xA0,
76 	CPL_RX_DATA_DDP       = 0xA1,
77 	CPL_RX_DATA_ACK       = 0xA3,
78 	CPL_RX_PKT            = 0xAD,
79 	CPL_RX_ISCSI_HDR      = 0xAF,
80 	CPL_TX_DATA_ACK       = 0xB0,
81 	CPL_TX_DATA           = 0xB1,
82 	CPL_TX_PKT            = 0xB2,
83 	CPL_TX_PKT_LSO        = 0xB6,
84 
85 	CPL_RTE_DELETE_REQ    = 0xC0,
86 	CPL_RTE_DELETE_RPL    = 0xC1,
87 	CPL_RTE_WRITE_REQ     = 0xC2,
88 	CPL_RTE_WRITE_RPL     = 0xD3,
89 	CPL_RTE_READ_REQ      = 0xC3,
90 	CPL_RTE_READ_RPL      = 0xC4,
91 	CPL_L2T_WRITE_REQ     = 0xC5,
92 	CPL_L2T_WRITE_RPL     = 0xD4,
93 	CPL_L2T_READ_REQ      = 0xC6,
94 	CPL_L2T_READ_RPL      = 0xC7,
95 	CPL_SMT_WRITE_REQ     = 0xC8,
96 	CPL_SMT_WRITE_RPL     = 0xD5,
97 	CPL_SMT_READ_REQ      = 0xC9,
98 	CPL_SMT_READ_RPL      = 0xCA,
99 	CPL_ARP_MISS_REQ      = 0xCD,
100 	CPL_ARP_MISS_RPL      = 0xCE,
101 	CPL_MIGRATE_C2T_REQ   = 0xDC,
102 	CPL_MIGRATE_C2T_RPL   = 0xDD,
103 	CPL_ERROR             = 0xD7,
104 
105 	/* internal: driver -> TOM */
106 	CPL_MSS_CHANGE        = 0xE1
107 };
108 
109 #define NUM_CPL_CMDS 256
110 
111 enum CPL_error {
112 	CPL_ERR_NONE               = 0,
113 	CPL_ERR_TCAM_PARITY        = 1,
114 	CPL_ERR_TCAM_FULL          = 3,
115 	CPL_ERR_CONN_RESET         = 20,
116 	CPL_ERR_CONN_EXIST         = 22,
117 	CPL_ERR_ARP_MISS           = 23,
118 	CPL_ERR_BAD_SYN            = 24,
119 	CPL_ERR_CONN_TIMEDOUT      = 30,
120 	CPL_ERR_XMIT_TIMEDOUT      = 31,
121 	CPL_ERR_PERSIST_TIMEDOUT   = 32,
122 	CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
123 	CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
124 	CPL_ERR_ABORT_FAILED       = 42,
125 	CPL_ERR_GENERAL            = 99
126 };
127 
128 enum {
129 	CPL_CONN_POLICY_AUTO = 0,
130 	CPL_CONN_POLICY_ASK  = 1,
131 	CPL_CONN_POLICY_DENY = 3
132 };
133 
134 enum {
135 	ULP_MODE_NONE   = 0,
136 	ULP_MODE_TCPDDP = 1,
137 	ULP_MODE_ISCSI  = 2,
138 	ULP_MODE_IWARP  = 3,
139 	ULP_MODE_SSL    = 4
140 };
141 
142 enum {
143 	CPL_PASS_OPEN_ACCEPT,
144 	CPL_PASS_OPEN_REJECT
145 };
146 
147 enum {
148 	CPL_ABORT_SEND_RST = 0,
149 	CPL_ABORT_NO_RST,
150 	CPL_ABORT_POST_CLOSE_REQ = 2
151 };
152 
153 enum {                // TX_PKT_LSO ethernet types
154 	CPL_ETH_II,
155 	CPL_ETH_II_VLAN,
156 	CPL_ETH_802_3,
157 	CPL_ETH_802_3_VLAN
158 };
159 
160 union opcode_tid {
161 	u32 opcode_tid;
162 	u8 opcode;
163 };
164 
165 #define S_OPCODE 24
166 #define V_OPCODE(x) ((x) << S_OPCODE)
167 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
168 #define G_TID(x)    ((x) & 0xFFFFFF)
169 
170 /* tid is assumed to be 24-bits */
171 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
172 
173 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
174 
175 /* extract the TID from a CPL command */
176 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
177 
178 struct tcp_options {
179 	u16 mss;
180 	u8 wsf;
181 #if defined(__LITTLE_ENDIAN_BITFIELD)
182 	u8 rsvd:4;
183 	u8 ecn:1;
184 	u8 sack:1;
185 	u8 tstamp:1;
186 #else
187 	u8 tstamp:1;
188 	u8 sack:1;
189 	u8 ecn:1;
190 	u8 rsvd:4;
191 #endif
192 };
193 
194 struct cpl_pass_open_req {
195 	union opcode_tid ot;
196 	u16 local_port;
197 	u16 peer_port;
198 	u32 local_ip;
199 	u32 peer_ip;
200 	u32 opt0h;
201 	u32 opt0l;
202 	u32 peer_netmask;
203 	u32 opt1;
204 };
205 
206 struct cpl_pass_open_rpl {
207 	union opcode_tid ot;
208 	u16 local_port;
209 	u16 peer_port;
210 	u32 local_ip;
211 	u32 peer_ip;
212 	u8 resvd[7];
213 	u8 status;
214 };
215 
216 struct cpl_pass_establish {
217 	union opcode_tid ot;
218 	u16 local_port;
219 	u16 peer_port;
220 	u32 local_ip;
221 	u32 peer_ip;
222 	u32 tos_tid;
223 	u8  l2t_idx;
224 	u8  rsvd[3];
225 	u32 snd_isn;
226 	u32 rcv_isn;
227 };
228 
229 struct cpl_pass_accept_req {
230 	union opcode_tid ot;
231 	u16 local_port;
232 	u16 peer_port;
233 	u32 local_ip;
234 	u32 peer_ip;
235 	u32 tos_tid;
236 	struct tcp_options tcp_options;
237 	u8  dst_mac[6];
238 	u16 vlan_tag;
239 	u8  src_mac[6];
240 	u8  rsvd[2];
241 	u32 rcv_isn;
242 	u32 unknown_tcp_options;
243 };
244 
245 struct cpl_pass_accept_rpl {
246 	union opcode_tid ot;
247 	u32 rsvd0;
248 	u32 rsvd1;
249 	u32 peer_ip;
250 	u32 opt0h;
251 	union {
252 		u32 opt0l;
253 		struct {
254 		    u8 rsvd[3];
255 		    u8 status;
256 		};
257 	};
258 };
259 
260 struct cpl_act_open_req {
261 	union opcode_tid ot;
262 	u16 local_port;
263 	u16 peer_port;
264 	u32 local_ip;
265 	u32 peer_ip;
266 	u32 opt0h;
267 	u32 opt0l;
268 	u32 iff_vlantag;
269 	u32 rsvd;
270 };
271 
272 struct cpl_act_open_rpl {
273 	union opcode_tid ot;
274 	u16 local_port;
275 	u16 peer_port;
276 	u32 local_ip;
277 	u32 peer_ip;
278 	u32 new_tid;
279 	u8  rsvd[3];
280 	u8  status;
281 };
282 
283 struct cpl_act_establish {
284 	union opcode_tid ot;
285 	u16 local_port;
286 	u16 peer_port;
287 	u32 local_ip;
288 	u32 peer_ip;
289 	u32 tos_tid;
290 	u32 rsvd;
291 	u32 snd_isn;
292 	u32 rcv_isn;
293 };
294 
295 struct cpl_get_tcb {
296 	union opcode_tid ot;
297 	u32 rsvd;
298 };
299 
300 struct cpl_get_tcb_rpl {
301 	union opcode_tid ot;
302 	u16 len;
303 	u8 rsvd;
304 	u8 status;
305 };
306 
307 struct cpl_set_tcb {
308 	union opcode_tid ot;
309 	u16 len;
310 	u16 rsvd;
311 };
312 
313 struct cpl_set_tcb_field {
314 	union opcode_tid ot;
315 	u8 rsvd[3];
316 	u8 offset;
317 	u32 mask;
318 	u32 val;
319 };
320 
321 struct cpl_set_tcb_rpl {
322 	union opcode_tid ot;
323 	u8 rsvd[3];
324 	u8 status;
325 };
326 
327 struct cpl_pcmd {
328 	union opcode_tid ot;
329 	u16 dlen_in;
330 	u16 dlen_out;
331 	u32 pcmd_parm[2];
332 };
333 
334 struct cpl_pcmd_read {
335 	union opcode_tid ot;
336 	u32 rsvd1;
337 	u16 rsvd2;
338 	u32 addr;
339 	u16 len;
340 };
341 
342 struct cpl_pcmd_read_rpl {
343 	union opcode_tid ot;
344 	u16 len;
345 };
346 
347 struct cpl_close_con_req {
348 	union opcode_tid ot;
349 	u32 rsvd;
350 };
351 
352 struct cpl_close_con_rpl {
353 	union opcode_tid ot;
354 	u8 rsvd[3];
355 	u8 status;
356 	u32 snd_nxt;
357 	u32 rcv_nxt;
358 };
359 
360 struct cpl_close_listserv_req {
361 	union opcode_tid ot;
362 	u32 rsvd;
363 };
364 
365 struct cpl_close_listserv_rpl {
366 	union opcode_tid ot;
367 	u8 rsvd[3];
368 	u8 status;
369 };
370 
371 struct cpl_abort_req {
372 	union opcode_tid ot;
373 	u32 rsvd0;
374 	u8  rsvd1;
375 	u8  cmd;
376 	u8  rsvd2[6];
377 };
378 
379 struct cpl_abort_rpl {
380 	union opcode_tid ot;
381 	u32 rsvd0;
382 	u8  rsvd1;
383 	u8  status;
384 	u8  rsvd2[6];
385 };
386 
387 struct cpl_peer_close {
388 	union opcode_tid ot;
389 	u32 rsvd;
390 };
391 
392 struct cpl_tx_data {
393 	union opcode_tid ot;
394 	u32 len;
395 	u32 rsvd0;
396 	u16 urg;
397 	u16 flags;
398 };
399 
400 struct cpl_tx_data_ack {
401 	union opcode_tid ot;
402 	u32 ack_seq;
403 };
404 
405 struct cpl_rx_data {
406 	union opcode_tid ot;
407 	u32 len;
408 	u32 seq;
409 	u16 urg;
410 	u8  rsvd;
411 	u8  status;
412 };
413 
414 struct cpl_rx_data_ack {
415 	union opcode_tid ot;
416 	u32 credit;
417 };
418 
419 struct cpl_rx_data_ddp {
420 	union opcode_tid ot;
421 	u32 len;
422 	u32 seq;
423 	u32 nxt_seq;
424 	u32 ulp_crc;
425 	u16 ddp_status;
426 	u8  rsvd;
427 	u8  status;
428 };
429 
430 /*
431  * We want this header's alignment to be no more stringent than 2-byte aligned.
432  * All fields are u8 or u16 except for the length.  However that field is not
433  * used so we break it into 2 16-bit parts to easily meet our alignment needs.
434  */
435 struct cpl_tx_pkt {
436 	u8 opcode;
437 #if defined(__LITTLE_ENDIAN_BITFIELD)
438 	u8 iff:4;
439 	u8 ip_csum_dis:1;
440 	u8 l4_csum_dis:1;
441 	u8 vlan_valid:1;
442 	u8 rsvd:1;
443 #else
444 	u8 rsvd:1;
445 	u8 vlan_valid:1;
446 	u8 l4_csum_dis:1;
447 	u8 ip_csum_dis:1;
448 	u8 iff:4;
449 #endif
450 	u16 vlan;
451 	u16 len_hi;
452 	u16 len_lo;
453 };
454 
455 struct cpl_tx_pkt_lso {
456 	u8 opcode;
457 #if defined(__LITTLE_ENDIAN_BITFIELD)
458 	u8 iff:4;
459 	u8 ip_csum_dis:1;
460 	u8 l4_csum_dis:1;
461 	u8 vlan_valid:1;
462 	u8 :1;
463 #else
464 	u8 :1;
465 	u8 vlan_valid:1;
466 	u8 l4_csum_dis:1;
467 	u8 ip_csum_dis:1;
468 	u8 iff:4;
469 #endif
470 	u16 vlan;
471 	__be32 len;
472 
473 	u8 rsvd[5];
474 #if defined(__LITTLE_ENDIAN_BITFIELD)
475 	u8 tcp_hdr_words:4;
476 	u8 ip_hdr_words:4;
477 #else
478 	u8 ip_hdr_words:4;
479 	u8 tcp_hdr_words:4;
480 #endif
481 	__be16 eth_type_mss;
482 };
483 
484 struct cpl_rx_pkt {
485 	u8 opcode;
486 #if defined(__LITTLE_ENDIAN_BITFIELD)
487 	u8 iff:4;
488 	u8 csum_valid:1;
489 	u8 bad_pkt:1;
490 	u8 vlan_valid:1;
491 	u8 rsvd:1;
492 #else
493 	u8 rsvd:1;
494 	u8 vlan_valid:1;
495 	u8 bad_pkt:1;
496 	u8 csum_valid:1;
497 	u8 iff:4;
498 #endif
499 	u16 csum;
500 	u16 vlan;
501 	u16 len;
502 };
503 
504 struct cpl_l2t_write_req {
505 	union opcode_tid ot;
506 	u32 params;
507 	u8 rsvd1[2];
508 	u8 dst_mac[6];
509 };
510 
511 struct cpl_l2t_write_rpl {
512 	union opcode_tid ot;
513 	u8 status;
514 	u8 rsvd[3];
515 };
516 
517 struct cpl_l2t_read_req {
518 	union opcode_tid ot;
519 	u8 rsvd[3];
520 	u8 l2t_idx;
521 };
522 
523 struct cpl_l2t_read_rpl {
524 	union opcode_tid ot;
525 	u32 params;
526 	u8 rsvd1[2];
527 	u8 dst_mac[6];
528 };
529 
530 struct cpl_smt_write_req {
531 	union opcode_tid ot;
532 	u8 rsvd0;
533 #if defined(__LITTLE_ENDIAN_BITFIELD)
534 	u8 rsvd1:1;
535 	u8 mtu_idx:3;
536 	u8 iff:4;
537 #else
538 	u8 iff:4;
539 	u8 mtu_idx:3;
540 	u8 rsvd1:1;
541 #endif
542 	u16 rsvd2;
543 	u16 rsvd3;
544 	u8  src_mac1[6];
545 	u16 rsvd4;
546 	u8  src_mac0[6];
547 };
548 
549 struct cpl_smt_write_rpl {
550 	union opcode_tid ot;
551 	u8 status;
552 	u8 rsvd[3];
553 };
554 
555 struct cpl_smt_read_req {
556 	union opcode_tid ot;
557 	u8 rsvd0;
558 #if defined(__LITTLE_ENDIAN_BITFIELD)
559 	u8 rsvd1:4;
560 	u8 iff:4;
561 #else
562 	u8 iff:4;
563 	u8 rsvd1:4;
564 #endif
565 	u16 rsvd2;
566 };
567 
568 struct cpl_smt_read_rpl {
569 	union opcode_tid ot;
570 	u8 status;
571 #if defined(__LITTLE_ENDIAN_BITFIELD)
572 	u8 rsvd1:1;
573 	u8 mtu_idx:3;
574 	u8 rsvd0:4;
575 #else
576 	u8 rsvd0:4;
577 	u8 mtu_idx:3;
578 	u8 rsvd1:1;
579 #endif
580 	u16 rsvd2;
581 	u16 rsvd3;
582 	u8  src_mac1[6];
583 	u16 rsvd4;
584 	u8  src_mac0[6];
585 };
586 
587 struct cpl_rte_delete_req {
588 	union opcode_tid ot;
589 	u32 params;
590 };
591 
592 struct cpl_rte_delete_rpl {
593 	union opcode_tid ot;
594 	u8 status;
595 	u8 rsvd[3];
596 };
597 
598 struct cpl_rte_write_req {
599 	union opcode_tid ot;
600 	u32 params;
601 	u32 netmask;
602 	u32 faddr;
603 };
604 
605 struct cpl_rte_write_rpl {
606 	union opcode_tid ot;
607 	u8 status;
608 	u8 rsvd[3];
609 };
610 
611 struct cpl_rte_read_req {
612 	union opcode_tid ot;
613 	u32 params;
614 };
615 
616 struct cpl_rte_read_rpl {
617 	union opcode_tid ot;
618 	u8 status;
619 	u8 rsvd0[2];
620 	u8 l2t_idx;
621 #if defined(__LITTLE_ENDIAN_BITFIELD)
622 	u8 rsvd1:7;
623 	u8 select:1;
624 #else
625 	u8 select:1;
626 	u8 rsvd1:7;
627 #endif
628 	u8 rsvd2[3];
629 	u32 addr;
630 };
631 
632 struct cpl_mss_change {
633 	union opcode_tid ot;
634 	u32 mss;
635 };
636 
637 #endif /* _CXGB_CPL5_CMD_H_ */
638 
639