1 /***************************************************************************** 2 * * 3 * File: common.h * 4 * $Revision: 1.21 $ * 5 * $Date: 2005/06/22 00:43:25 $ * 6 * Description: * 7 * part of the Chelsio 10Gb Ethernet Driver. * 8 * * 9 * This program is free software; you can redistribute it and/or modify * 10 * it under the terms of the GNU General Public License, version 2, as * 11 * published by the Free Software Foundation. * 12 * * 13 * You should have received a copy of the GNU General Public License along * 14 * with this program; if not, see <http://www.gnu.org/licenses/>. * 15 * * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * 17 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * 19 * * 20 * http://www.chelsio.com * 21 * * 22 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * 23 * All rights reserved. * 24 * * 25 * Maintainers: maintainers@chelsio.com * 26 * * 27 * Authors: Dimitrios Michailidis <dm@chelsio.com> * 28 * Tina Yang <tainay@chelsio.com> * 29 * Felix Marti <felix@chelsio.com> * 30 * Scott Bardone <sbardone@chelsio.com> * 31 * Kurt Ottaway <kottaway@chelsio.com> * 32 * Frank DiMambro <frank@chelsio.com> * 33 * * 34 * History: * 35 * * 36 ****************************************************************************/ 37 38 #define pr_fmt(fmt) "cxgb: " fmt 39 40 #ifndef _CXGB_COMMON_H_ 41 #define _CXGB_COMMON_H_ 42 43 #include <linux/module.h> 44 #include <linux/netdevice.h> 45 #include <linux/types.h> 46 #include <linux/delay.h> 47 #include <linux/pci.h> 48 #include <linux/ethtool.h> 49 #include <linux/if_vlan.h> 50 #include <linux/mdio.h> 51 #include <linux/crc32.h> 52 #include <linux/slab.h> 53 #include <asm/io.h> 54 #include <linux/pci_ids.h> 55 56 #define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver" 57 #define DRV_NAME "cxgb" 58 #define DRV_VERSION "2.2" 59 60 #define CH_DEVICE(devid, ssid, idx) \ 61 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx } 62 63 #define SUPPORTED_PAUSE (1 << 13) 64 #define SUPPORTED_LOOPBACK (1 << 15) 65 66 #define ADVERTISED_PAUSE (1 << 13) 67 #define ADVERTISED_ASYM_PAUSE (1 << 14) 68 69 typedef struct adapter adapter_t; 70 71 struct t1_rx_mode { 72 struct net_device *dev; 73 }; 74 75 #define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC) 76 #define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI) 77 #define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev)) 78 #define t1_get_netdev(rm) (rm->dev) 79 80 #define MAX_NPORTS 4 81 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 82 #define NMTUS 8 83 #define TCB_SIZE 128 84 85 #define SPEED_INVALID 0xffff 86 #define DUPLEX_INVALID 0xff 87 88 /* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */ 89 #define PM3393_MAX_FRAME_SIZE 9600 90 91 #define VSC7326_MAX_MTU 9600 92 93 enum { 94 CHBT_BOARD_N110, 95 CHBT_BOARD_N210, 96 CHBT_BOARD_7500, 97 CHBT_BOARD_8000, 98 CHBT_BOARD_CHT101, 99 CHBT_BOARD_CHT110, 100 CHBT_BOARD_CHT210, 101 CHBT_BOARD_CHT204, 102 CHBT_BOARD_CHT204V, 103 CHBT_BOARD_CHT204E, 104 CHBT_BOARD_CHN204, 105 CHBT_BOARD_COUGAR, 106 CHBT_BOARD_6800, 107 CHBT_BOARD_SIMUL, 108 }; 109 110 enum { 111 CHBT_TERM_FPGA, 112 CHBT_TERM_T1, 113 CHBT_TERM_T2, 114 CHBT_TERM_T3 115 }; 116 117 enum { 118 CHBT_MAC_CHELSIO_A, 119 CHBT_MAC_IXF1010, 120 CHBT_MAC_PM3393, 121 CHBT_MAC_VSC7321, 122 CHBT_MAC_DUMMY 123 }; 124 125 enum { 126 CHBT_PHY_88E1041, 127 CHBT_PHY_88E1111, 128 CHBT_PHY_88X2010, 129 CHBT_PHY_XPAK, 130 CHBT_PHY_MY3126, 131 CHBT_PHY_8244, 132 CHBT_PHY_DUMMY 133 }; 134 135 enum { 136 PAUSE_RX = 1 << 0, 137 PAUSE_TX = 1 << 1, 138 PAUSE_AUTONEG = 1 << 2 139 }; 140 141 /* Revisions of T1 chip */ 142 enum { 143 TERM_T1A = 0, 144 TERM_T1B = 1, 145 TERM_T2 = 3 146 }; 147 148 struct sge_params { 149 unsigned int cmdQ_size[2]; 150 unsigned int freelQ_size[2]; 151 unsigned int large_buf_capacity; 152 unsigned int rx_coalesce_usecs; 153 unsigned int last_rx_coalesce_raw; 154 unsigned int default_rx_coalesce_usecs; 155 unsigned int sample_interval_usecs; 156 unsigned int coalesce_enable; 157 unsigned int polling; 158 }; 159 160 struct chelsio_pci_params { 161 unsigned short speed; 162 unsigned char width; 163 unsigned char is_pcix; 164 }; 165 166 struct tp_params { 167 unsigned int pm_size; 168 unsigned int cm_size; 169 unsigned int pm_rx_base; 170 unsigned int pm_tx_base; 171 unsigned int pm_rx_pg_size; 172 unsigned int pm_tx_pg_size; 173 unsigned int pm_rx_num_pgs; 174 unsigned int pm_tx_num_pgs; 175 unsigned int rx_coalescing_size; 176 unsigned int use_5tuple_mode; 177 }; 178 179 struct mc5_params { 180 unsigned int mode; /* selects MC5 width */ 181 unsigned int nservers; /* size of server region */ 182 unsigned int nroutes; /* size of routing region */ 183 }; 184 185 /* Default MC5 region sizes */ 186 #define DEFAULT_SERVER_REGION_LEN 256 187 #define DEFAULT_RT_REGION_LEN 1024 188 189 struct adapter_params { 190 struct sge_params sge; 191 struct mc5_params mc5; 192 struct tp_params tp; 193 struct chelsio_pci_params pci; 194 195 const struct board_info *brd_info; 196 197 unsigned short mtus[NMTUS]; 198 unsigned int nports; /* # of ethernet ports */ 199 unsigned int stats_update_period; 200 unsigned short chip_revision; 201 unsigned char chip_version; 202 unsigned char is_asic; 203 unsigned char has_msi; 204 }; 205 206 struct link_config { 207 unsigned int supported; /* link capabilities */ 208 unsigned int advertising; /* advertised capabilities */ 209 unsigned short requested_speed; /* speed user has requested */ 210 unsigned short speed; /* actual link speed */ 211 unsigned char requested_duplex; /* duplex user has requested */ 212 unsigned char duplex; /* actual link duplex */ 213 unsigned char requested_fc; /* flow control user has requested */ 214 unsigned char fc; /* actual link flow control */ 215 unsigned char autoneg; /* autonegotiating? */ 216 }; 217 218 struct cmac; 219 struct cphy; 220 221 struct port_info { 222 struct net_device *dev; 223 struct cmac *mac; 224 struct cphy *phy; 225 struct link_config link_config; 226 }; 227 228 struct sge; 229 struct peespi; 230 231 struct adapter { 232 u8 __iomem *regs; 233 struct pci_dev *pdev; 234 unsigned long registered_device_map; 235 unsigned long open_device_map; 236 unsigned long flags; 237 238 const char *name; 239 int msg_enable; 240 u32 mmio_len; 241 242 struct work_struct ext_intr_handler_task; 243 struct adapter_params params; 244 245 /* Terminator modules. */ 246 struct sge *sge; 247 struct peespi *espi; 248 struct petp *tp; 249 250 struct napi_struct napi; 251 struct port_info port[MAX_NPORTS]; 252 struct delayed_work stats_update_task; 253 struct timer_list stats_update_timer; 254 255 spinlock_t tpi_lock; 256 spinlock_t work_lock; 257 spinlock_t mac_lock; 258 259 /* guards async operations */ 260 spinlock_t async_lock ____cacheline_aligned; 261 u32 slow_intr_mask; 262 int t1powersave; 263 }; 264 265 enum { /* adapter flags */ 266 FULL_INIT_DONE = 1 << 0, 267 }; 268 269 struct mdio_ops; 270 struct gmac; 271 struct gphy; 272 273 struct board_info { 274 unsigned char board; 275 unsigned char port_number; 276 unsigned long caps; 277 unsigned char chip_term; 278 unsigned char chip_mac; 279 unsigned char chip_phy; 280 unsigned int clock_core; 281 unsigned int clock_mc3; 282 unsigned int clock_mc4; 283 unsigned int espi_nports; 284 unsigned int clock_elmer0; 285 unsigned char mdio_mdien; 286 unsigned char mdio_mdiinv; 287 unsigned char mdio_mdc; 288 unsigned char mdio_phybaseaddr; 289 const struct gmac *gmac; 290 const struct gphy *gphy; 291 const struct mdio_ops *mdio_ops; 292 const char *desc; 293 }; 294 295 static inline int t1_is_asic(const adapter_t *adapter) 296 { 297 return adapter->params.is_asic; 298 } 299 300 extern const struct pci_device_id t1_pci_tbl[]; 301 302 static inline int adapter_matches_type(const adapter_t *adapter, 303 int version, int revision) 304 { 305 return adapter->params.chip_version == version && 306 adapter->params.chip_revision == revision; 307 } 308 309 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B) 310 #define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2) 311 312 /* Returns true if an adapter supports VLAN acceleration and TSO */ 313 static inline int vlan_tso_capable(const adapter_t *adapter) 314 { 315 return !t1_is_T1B(adapter); 316 } 317 318 #define for_each_port(adapter, iter) \ 319 for (iter = 0; iter < (adapter)->params.nports; ++iter) 320 321 #define board_info(adapter) ((adapter)->params.brd_info) 322 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full) 323 324 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 325 { 326 return board_info(adap)->clock_core / 1000000; 327 } 328 329 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp); 330 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); 331 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value); 332 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value); 333 334 void t1_interrupts_enable(adapter_t *adapter); 335 void t1_interrupts_disable(adapter_t *adapter); 336 void t1_interrupts_clear(adapter_t *adapter); 337 int t1_elmer0_ext_intr_handler(adapter_t *adapter); 338 void t1_elmer0_ext_intr(adapter_t *adapter); 339 int t1_slow_intr_handler(adapter_t *adapter); 340 341 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 342 const struct board_info *t1_get_board_info(unsigned int board_id); 343 const struct board_info *t1_get_board_info_from_ids(unsigned int devid, 344 unsigned short ssid); 345 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data); 346 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi, 347 struct adapter_params *p); 348 int t1_init_hw_modules(adapter_t *adapter); 349 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi); 350 void t1_free_sw_modules(adapter_t *adapter); 351 void t1_fatal_err(adapter_t *adapter); 352 void t1_link_changed(adapter_t *adapter, int port_id); 353 void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat, 354 int speed, int duplex, int pause); 355 #endif /* _CXGB_COMMON_H_ */ 356