1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef THUNDER_BGX_H 10 #define THUNDER_BGX_H 11 12 /* PCI device ID */ 13 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 14 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054 15 16 /* Subsystem device IDs */ 17 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126 18 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226 19 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326 20 21 #define MAX_BGX_THUNDER 8 /* Max 2 nodes, 4 per node */ 22 #define MAX_BGX_PER_CN88XX 2 23 #define MAX_BGX_PER_CN81XX 3 /* 2 BGXs + 1 RGX */ 24 #define MAX_BGX_PER_CN83XX 4 25 #define MAX_BGX_PER_NODE 4 26 #define MAX_LMAC_PER_BGX 4 27 #define MAX_BGX_CHANS_PER_LMAC 16 28 #define MAX_DMAC_PER_LMAC 8 29 #define MAX_FRAME_SIZE 9216 30 31 #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 32 33 /* Registers */ 34 #define BGX_CMRX_CFG 0x00 35 #define CMR_PKT_TX_EN BIT_ULL(13) 36 #define CMR_PKT_RX_EN BIT_ULL(14) 37 #define CMR_EN BIT_ULL(15) 38 #define BGX_CMR_GLOBAL_CFG 0x08 39 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6) 40 #define BGX_CMRX_RX_ID_MAP 0x60 41 #define BGX_CMRX_RX_STAT0 0x70 42 #define BGX_CMRX_RX_STAT1 0x78 43 #define BGX_CMRX_RX_STAT2 0x80 44 #define BGX_CMRX_RX_STAT3 0x88 45 #define BGX_CMRX_RX_STAT4 0x90 46 #define BGX_CMRX_RX_STAT5 0x98 47 #define BGX_CMRX_RX_STAT6 0xA0 48 #define BGX_CMRX_RX_STAT7 0xA8 49 #define BGX_CMRX_RX_STAT8 0xB0 50 #define BGX_CMRX_RX_STAT9 0xB8 51 #define BGX_CMRX_RX_STAT10 0xC0 52 #define BGX_CMRX_RX_BP_DROP 0xC8 53 #define BGX_CMRX_RX_DMAC_CTL 0x0E8 54 #define BGX_CMRX_RX_FIFO_LEN 0x108 55 #define BGX_CMR_RX_DMACX_CAM 0x200 56 #define RX_DMACX_CAM_EN BIT_ULL(48) 57 #define RX_DMACX_CAM_LMACID(x) (x << 49) 58 #define RX_DMAC_COUNT 32 59 #define BGX_CMR_RX_STREERING 0x300 60 #define RX_TRAFFIC_STEER_RULE_COUNT 8 61 #define BGX_CMR_CHAN_MSK_AND 0x450 62 #define BGX_CMR_BIST_STATUS 0x460 63 #define BGX_CMR_RX_LMACS 0x468 64 #define BGX_CMRX_TX_FIFO_LEN 0x518 65 #define BGX_CMRX_TX_STAT0 0x600 66 #define BGX_CMRX_TX_STAT1 0x608 67 #define BGX_CMRX_TX_STAT2 0x610 68 #define BGX_CMRX_TX_STAT3 0x618 69 #define BGX_CMRX_TX_STAT4 0x620 70 #define BGX_CMRX_TX_STAT5 0x628 71 #define BGX_CMRX_TX_STAT6 0x630 72 #define BGX_CMRX_TX_STAT7 0x638 73 #define BGX_CMRX_TX_STAT8 0x640 74 #define BGX_CMRX_TX_STAT9 0x648 75 #define BGX_CMRX_TX_STAT10 0x650 76 #define BGX_CMRX_TX_STAT11 0x658 77 #define BGX_CMRX_TX_STAT12 0x660 78 #define BGX_CMRX_TX_STAT13 0x668 79 #define BGX_CMRX_TX_STAT14 0x670 80 #define BGX_CMRX_TX_STAT15 0x678 81 #define BGX_CMRX_TX_STAT16 0x680 82 #define BGX_CMRX_TX_STAT17 0x688 83 #define BGX_CMR_TX_LMACS 0x1000 84 85 #define BGX_SPUX_CONTROL1 0x10000 86 #define SPU_CTL_LOW_POWER BIT_ULL(11) 87 #define SPU_CTL_LOOPBACK BIT_ULL(14) 88 #define SPU_CTL_RESET BIT_ULL(15) 89 #define BGX_SPUX_STATUS1 0x10008 90 #define SPU_STATUS1_RCV_LNK BIT_ULL(2) 91 #define BGX_SPUX_STATUS2 0x10020 92 #define SPU_STATUS2_RCVFLT BIT_ULL(10) 93 #define BGX_SPUX_BX_STATUS 0x10028 94 #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12) 95 #define BGX_SPUX_BR_STATUS1 0x10030 96 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0) 97 #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12) 98 #define BGX_SPUX_BR_PMD_CRTL 0x10068 99 #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1) 100 #define BGX_SPUX_BR_PMD_LP_CUP 0x10078 101 #define BGX_SPUX_BR_PMD_LD_CUP 0x10088 102 #define BGX_SPUX_BR_PMD_LD_REP 0x10090 103 #define BGX_SPUX_FEC_CONTROL 0x100A0 104 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0) 105 #define SPU_FEC_CTL_ERR_EN BIT_ULL(1) 106 #define BGX_SPUX_AN_CONTROL 0x100C8 107 #define SPU_AN_CTL_AN_EN BIT_ULL(12) 108 #define SPU_AN_CTL_XNP_EN BIT_ULL(13) 109 #define BGX_SPUX_AN_ADV 0x100D8 110 #define BGX_SPUX_MISC_CONTROL 0x10218 111 #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10) 112 #define SPU_MISC_CTL_RX_DIS BIT_ULL(12) 113 #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */ 114 #define BGX_SPUX_INT_W1S 0x10228 115 #define BGX_SPUX_INT_ENA_W1C 0x10230 116 #define BGX_SPUX_INT_ENA_W1S 0x10238 117 #define BGX_SPU_DBG_CONTROL 0x10300 118 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18) 119 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29) 120 121 #define BGX_SMUX_RX_INT 0x20000 122 #define BGX_SMUX_RX_JABBER 0x20030 123 #define BGX_SMUX_RX_CTL 0x20048 124 #define SMU_RX_CTL_STATUS (3ull << 0) 125 #define BGX_SMUX_TX_APPEND 0x20100 126 #define SMU_TX_APPEND_FCS_D BIT_ULL(2) 127 #define BGX_SMUX_TX_MIN_PKT 0x20118 128 #define BGX_SMUX_TX_INT 0x20140 129 #define BGX_SMUX_TX_CTL 0x20178 130 #define SMU_TX_CTL_DIC_EN BIT_ULL(0) 131 #define SMU_TX_CTL_UNI_EN BIT_ULL(1) 132 #define SMU_TX_CTL_LNK_STATUS (3ull << 4) 133 #define BGX_SMUX_TX_THRESH 0x20180 134 #define BGX_SMUX_CTL 0x20200 135 #define SMU_CTL_RX_IDLE BIT_ULL(0) 136 #define SMU_CTL_TX_IDLE BIT_ULL(1) 137 138 #define BGX_GMP_PCS_MRX_CTL 0x30000 139 #define PCS_MRX_CTL_RST_AN BIT_ULL(9) 140 #define PCS_MRX_CTL_PWR_DN BIT_ULL(11) 141 #define PCS_MRX_CTL_AN_EN BIT_ULL(12) 142 #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14) 143 #define PCS_MRX_CTL_RESET BIT_ULL(15) 144 #define BGX_GMP_PCS_MRX_STATUS 0x30008 145 #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5) 146 #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020 147 #define BGX_GMP_PCS_SGM_AN_ADV 0x30068 148 #define BGX_GMP_PCS_MISCX_CTL 0x30078 149 #define PCS_MISC_CTL_DISP_EN BIT_ULL(13) 150 #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11) 151 #define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full 152 #define BGX_GMP_GMI_PRTX_CFG 0x38020 153 #define GMI_PORT_CFG_SPEED BIT_ULL(1) 154 #define GMI_PORT_CFG_DUPLEX BIT_ULL(2) 155 #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3) 156 #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8) 157 #define BGX_GMP_GMI_RXX_JABBER 0x38038 158 #define BGX_GMP_GMI_TXX_THRESH 0x38210 159 #define BGX_GMP_GMI_TXX_APPEND 0x38218 160 #define BGX_GMP_GMI_TXX_SLOT 0x38220 161 #define BGX_GMP_GMI_TXX_BURST 0x38228 162 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 163 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 164 165 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ 166 #define BGX_MSIX_VEC_0_29_CTL 0x400008 167 #define BGX_MSIX_PBA_0 0x4F0000 168 169 /* MSI-X interrupts */ 170 #define BGX_MSIX_VECTORS 30 171 #define BGX_LMAC_VEC_OFFSET 7 172 #define BGX_MSIX_VEC_SHIFT 4 173 174 #define CMRX_INT 0 175 #define SPUX_INT 1 176 #define SMUX_RX_INT 2 177 #define SMUX_TX_INT 3 178 #define GMPX_PCS_INT 4 179 #define GMPX_GMI_RX_INT 5 180 #define GMPX_GMI_TX_INT 6 181 #define CMR_MEM_INT 28 182 #define SPU_MEM_INT 29 183 184 #define LMAC_INTR_LINK_UP BIT(0) 185 #define LMAC_INTR_LINK_DOWN BIT(1) 186 187 /* RX_DMAC_CTL configuration*/ 188 enum MCAST_MODE { 189 MCAST_MODE_REJECT, 190 MCAST_MODE_ACCEPT, 191 MCAST_MODE_CAM_FILTER, 192 RSVD 193 }; 194 195 #define BCAST_ACCEPT 1 196 #define CAM_ACCEPT 1 197 198 void octeon_mdiobus_force_mod_depencency(void); 199 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable); 200 void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac); 201 unsigned bgx_get_map(int node); 202 int bgx_get_lmac_count(int node, int bgx); 203 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid); 204 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac); 205 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status); 206 void bgx_lmac_internal_loopback(int node, int bgx_idx, 207 int lmac_idx, bool enable); 208 void xcv_init_hw(void); 209 void xcv_setup_link(bool link_up, int link_speed); 210 211 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx); 212 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx); 213 #define BGX_RX_STATS_COUNT 11 214 #define BGX_TX_STATS_COUNT 18 215 216 struct bgx_stats { 217 u64 rx_stats[BGX_RX_STATS_COUNT]; 218 u64 tx_stats[BGX_TX_STATS_COUNT]; 219 }; 220 221 enum LMAC_TYPE { 222 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */ 223 BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */ 224 BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */ 225 BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */ 226 BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */ 227 BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */ 228 BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */ 229 BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */ 230 BGX_MODE_RGMII = 5, 231 BGX_MODE_QSGMII = 6, 232 BGX_MODE_INVALID = 7, 233 }; 234 235 #endif /* THUNDER_BGX_H */ 236