1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef THUNDER_BGX_H 10 #define THUNDER_BGX_H 11 12 /* PCI device ID */ 13 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 14 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054 15 16 /* Subsystem device IDs */ 17 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126 18 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226 19 #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254 20 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326 21 22 #define MAX_BGX_THUNDER 8 /* Max 2 nodes, 4 per node */ 23 #define MAX_BGX_PER_CN88XX 2 24 #define MAX_BGX_PER_CN81XX 3 /* 2 BGXs + 1 RGX */ 25 #define MAX_BGX_PER_CN83XX 4 26 #define MAX_LMAC_PER_BGX 4 27 #define MAX_BGX_CHANS_PER_LMAC 16 28 #define MAX_DMAC_PER_LMAC 8 29 #define MAX_FRAME_SIZE 9216 30 #define DEFAULT_PAUSE_TIME 0xFFFF 31 32 #define BGX_ID_MASK 0x3 33 34 #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 35 36 /* Registers */ 37 #define BGX_CMRX_CFG 0x00 38 #define CMR_PKT_TX_EN BIT_ULL(13) 39 #define CMR_PKT_RX_EN BIT_ULL(14) 40 #define CMR_EN BIT_ULL(15) 41 #define BGX_CMR_GLOBAL_CFG 0x08 42 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6) 43 #define BGX_CMRX_RX_ID_MAP 0x60 44 #define BGX_CMRX_RX_STAT0 0x70 45 #define BGX_CMRX_RX_STAT1 0x78 46 #define BGX_CMRX_RX_STAT2 0x80 47 #define BGX_CMRX_RX_STAT3 0x88 48 #define BGX_CMRX_RX_STAT4 0x90 49 #define BGX_CMRX_RX_STAT5 0x98 50 #define BGX_CMRX_RX_STAT6 0xA0 51 #define BGX_CMRX_RX_STAT7 0xA8 52 #define BGX_CMRX_RX_STAT8 0xB0 53 #define BGX_CMRX_RX_STAT9 0xB8 54 #define BGX_CMRX_RX_STAT10 0xC0 55 #define BGX_CMRX_RX_BP_DROP 0xC8 56 #define BGX_CMRX_RX_DMAC_CTL 0x0E8 57 #define BGX_CMRX_RX_FIFO_LEN 0x108 58 #define BGX_CMR_RX_DMACX_CAM 0x200 59 #define RX_DMACX_CAM_EN BIT_ULL(48) 60 #define RX_DMACX_CAM_LMACID(x) (x << 49) 61 #define RX_DMAC_COUNT 32 62 #define BGX_CMR_RX_STREERING 0x300 63 #define RX_TRAFFIC_STEER_RULE_COUNT 8 64 #define BGX_CMR_CHAN_MSK_AND 0x450 65 #define BGX_CMR_BIST_STATUS 0x460 66 #define BGX_CMR_RX_LMACS 0x468 67 #define BGX_CMRX_TX_FIFO_LEN 0x518 68 #define BGX_CMRX_TX_STAT0 0x600 69 #define BGX_CMRX_TX_STAT1 0x608 70 #define BGX_CMRX_TX_STAT2 0x610 71 #define BGX_CMRX_TX_STAT3 0x618 72 #define BGX_CMRX_TX_STAT4 0x620 73 #define BGX_CMRX_TX_STAT5 0x628 74 #define BGX_CMRX_TX_STAT6 0x630 75 #define BGX_CMRX_TX_STAT7 0x638 76 #define BGX_CMRX_TX_STAT8 0x640 77 #define BGX_CMRX_TX_STAT9 0x648 78 #define BGX_CMRX_TX_STAT10 0x650 79 #define BGX_CMRX_TX_STAT11 0x658 80 #define BGX_CMRX_TX_STAT12 0x660 81 #define BGX_CMRX_TX_STAT13 0x668 82 #define BGX_CMRX_TX_STAT14 0x670 83 #define BGX_CMRX_TX_STAT15 0x678 84 #define BGX_CMRX_TX_STAT16 0x680 85 #define BGX_CMRX_TX_STAT17 0x688 86 #define BGX_CMR_TX_LMACS 0x1000 87 88 #define BGX_SPUX_CONTROL1 0x10000 89 #define SPU_CTL_LOW_POWER BIT_ULL(11) 90 #define SPU_CTL_LOOPBACK BIT_ULL(14) 91 #define SPU_CTL_RESET BIT_ULL(15) 92 #define BGX_SPUX_STATUS1 0x10008 93 #define SPU_STATUS1_RCV_LNK BIT_ULL(2) 94 #define BGX_SPUX_STATUS2 0x10020 95 #define SPU_STATUS2_RCVFLT BIT_ULL(10) 96 #define BGX_SPUX_BX_STATUS 0x10028 97 #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12) 98 #define BGX_SPUX_BR_STATUS1 0x10030 99 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0) 100 #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12) 101 #define BGX_SPUX_BR_PMD_CRTL 0x10068 102 #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1) 103 #define BGX_SPUX_BR_PMD_LP_CUP 0x10078 104 #define BGX_SPUX_BR_PMD_LD_CUP 0x10088 105 #define BGX_SPUX_BR_PMD_LD_REP 0x10090 106 #define BGX_SPUX_FEC_CONTROL 0x100A0 107 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0) 108 #define SPU_FEC_CTL_ERR_EN BIT_ULL(1) 109 #define BGX_SPUX_AN_CONTROL 0x100C8 110 #define SPU_AN_CTL_AN_EN BIT_ULL(12) 111 #define SPU_AN_CTL_XNP_EN BIT_ULL(13) 112 #define BGX_SPUX_AN_ADV 0x100D8 113 #define BGX_SPUX_MISC_CONTROL 0x10218 114 #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10) 115 #define SPU_MISC_CTL_RX_DIS BIT_ULL(12) 116 #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */ 117 #define BGX_SPUX_INT_W1S 0x10228 118 #define BGX_SPUX_INT_ENA_W1C 0x10230 119 #define BGX_SPUX_INT_ENA_W1S 0x10238 120 #define BGX_SPU_DBG_CONTROL 0x10300 121 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18) 122 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29) 123 124 #define BGX_SMUX_RX_INT 0x20000 125 #define BGX_SMUX_RX_FRM_CTL 0x20020 126 #define BGX_PKT_RX_PTP_EN BIT_ULL(12) 127 #define BGX_SMUX_RX_JABBER 0x20030 128 #define BGX_SMUX_RX_CTL 0x20048 129 #define SMU_RX_CTL_STATUS (3ull << 0) 130 #define BGX_SMUX_TX_APPEND 0x20100 131 #define SMU_TX_APPEND_FCS_D BIT_ULL(2) 132 #define BGX_SMUX_TX_PAUSE_PKT_TIME 0x20110 133 #define BGX_SMUX_TX_MIN_PKT 0x20118 134 #define BGX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120 135 #define BGX_SMUX_TX_PAUSE_ZERO 0x20138 136 #define BGX_SMUX_TX_INT 0x20140 137 #define BGX_SMUX_TX_CTL 0x20178 138 #define SMU_TX_CTL_DIC_EN BIT_ULL(0) 139 #define SMU_TX_CTL_UNI_EN BIT_ULL(1) 140 #define SMU_TX_CTL_LNK_STATUS (3ull << 4) 141 #define BGX_SMUX_TX_THRESH 0x20180 142 #define BGX_SMUX_CTL 0x20200 143 #define SMU_CTL_RX_IDLE BIT_ULL(0) 144 #define SMU_CTL_TX_IDLE BIT_ULL(1) 145 #define BGX_SMUX_CBFC_CTL 0x20218 146 #define RX_EN BIT_ULL(0) 147 #define TX_EN BIT_ULL(1) 148 #define BCK_EN BIT_ULL(2) 149 #define DRP_EN BIT_ULL(3) 150 151 #define BGX_GMP_PCS_MRX_CTL 0x30000 152 #define PCS_MRX_CTL_RST_AN BIT_ULL(9) 153 #define PCS_MRX_CTL_PWR_DN BIT_ULL(11) 154 #define PCS_MRX_CTL_AN_EN BIT_ULL(12) 155 #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14) 156 #define PCS_MRX_CTL_RESET BIT_ULL(15) 157 #define BGX_GMP_PCS_MRX_STATUS 0x30008 158 #define PCS_MRX_STATUS_LINK BIT_ULL(2) 159 #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5) 160 #define BGX_GMP_PCS_ANX_ADV 0x30010 161 #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020 162 #define BGX_GMP_PCS_LINKX_TIMER 0x30040 163 #define PCS_LINKX_TIMER_COUNT 0x1E84 164 #define BGX_GMP_PCS_SGM_AN_ADV 0x30068 165 #define BGX_GMP_PCS_MISCX_CTL 0x30078 166 #define PCS_MISC_CTL_MODE BIT_ULL(8) 167 #define PCS_MISC_CTL_DISP_EN BIT_ULL(13) 168 #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11) 169 #define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full 170 #define BGX_GMP_GMI_PRTX_CFG 0x38020 171 #define GMI_PORT_CFG_SPEED BIT_ULL(1) 172 #define GMI_PORT_CFG_DUPLEX BIT_ULL(2) 173 #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3) 174 #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8) 175 #define GMI_PORT_CFG_RX_IDLE BIT_ULL(12) 176 #define GMI_PORT_CFG_TX_IDLE BIT_ULL(13) 177 #define BGX_GMP_GMI_RXX_FRM_CTL 0x38028 178 #define BGX_GMP_GMI_RXX_JABBER 0x38038 179 #define BGX_GMP_GMI_TXX_THRESH 0x38210 180 #define BGX_GMP_GMI_TXX_APPEND 0x38218 181 #define BGX_GMP_GMI_TXX_SLOT 0x38220 182 #define BGX_GMP_GMI_TXX_BURST 0x38228 183 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 184 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 185 186 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ 187 #define BGX_MSIX_VEC_0_29_CTL 0x400008 188 #define BGX_MSIX_PBA_0 0x4F0000 189 190 /* MSI-X interrupts */ 191 #define BGX_MSIX_VECTORS 30 192 #define BGX_LMAC_VEC_OFFSET 7 193 #define BGX_MSIX_VEC_SHIFT 4 194 195 #define CMRX_INT 0 196 #define SPUX_INT 1 197 #define SMUX_RX_INT 2 198 #define SMUX_TX_INT 3 199 #define GMPX_PCS_INT 4 200 #define GMPX_GMI_RX_INT 5 201 #define GMPX_GMI_TX_INT 6 202 #define CMR_MEM_INT 28 203 #define SPU_MEM_INT 29 204 205 #define LMAC_INTR_LINK_UP BIT(0) 206 #define LMAC_INTR_LINK_DOWN BIT(1) 207 208 /* RX_DMAC_CTL configuration*/ 209 enum MCAST_MODE { 210 MCAST_MODE_REJECT, 211 MCAST_MODE_ACCEPT, 212 MCAST_MODE_CAM_FILTER, 213 RSVD 214 }; 215 216 #define BCAST_ACCEPT 1 217 #define CAM_ACCEPT 1 218 219 void octeon_mdiobus_force_mod_depencency(void); 220 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable); 221 void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac); 222 unsigned bgx_get_map(int node); 223 int bgx_get_lmac_count(int node, int bgx); 224 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid); 225 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac); 226 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status); 227 void bgx_lmac_internal_loopback(int node, int bgx_idx, 228 int lmac_idx, bool enable); 229 void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable); 230 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause); 231 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause); 232 233 void xcv_init_hw(void); 234 void xcv_setup_link(bool link_up, int link_speed); 235 236 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx); 237 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx); 238 #define BGX_RX_STATS_COUNT 11 239 #define BGX_TX_STATS_COUNT 18 240 241 struct bgx_stats { 242 u64 rx_stats[BGX_RX_STATS_COUNT]; 243 u64 tx_stats[BGX_TX_STATS_COUNT]; 244 }; 245 246 enum LMAC_TYPE { 247 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */ 248 BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */ 249 BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */ 250 BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */ 251 BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */ 252 BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */ 253 BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */ 254 BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */ 255 BGX_MODE_RGMII = 5, 256 BGX_MODE_QSGMII = 6, 257 BGX_MODE_INVALID = 7, 258 }; 259 260 #endif /* THUNDER_BGX_H */ 261