14863dea3SSunil Goutham /* 24863dea3SSunil Goutham * Copyright (C) 2015 Cavium, Inc. 34863dea3SSunil Goutham * 44863dea3SSunil Goutham * This program is free software; you can redistribute it and/or modify it 54863dea3SSunil Goutham * under the terms of version 2 of the GNU General Public License 64863dea3SSunil Goutham * as published by the Free Software Foundation. 74863dea3SSunil Goutham */ 84863dea3SSunil Goutham 94863dea3SSunil Goutham #ifndef THUNDER_BGX_H 104863dea3SSunil Goutham #define THUNDER_BGX_H 114863dea3SSunil Goutham 124863dea3SSunil Goutham #define MAX_BGX_THUNDER 8 /* Max 4 nodes, 2 per node */ 134863dea3SSunil Goutham #define MAX_BGX_PER_CN88XX 2 144863dea3SSunil Goutham #define MAX_LMAC_PER_BGX 4 154863dea3SSunil Goutham #define MAX_BGX_CHANS_PER_LMAC 16 164863dea3SSunil Goutham #define MAX_DMAC_PER_LMAC 8 174863dea3SSunil Goutham #define MAX_FRAME_SIZE 9216 184863dea3SSunil Goutham 194863dea3SSunil Goutham #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 204863dea3SSunil Goutham 214863dea3SSunil Goutham #define MAX_LMAC (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX) 224863dea3SSunil Goutham 234863dea3SSunil Goutham /* Registers */ 244863dea3SSunil Goutham #define BGX_CMRX_CFG 0x00 254863dea3SSunil Goutham #define CMR_PKT_TX_EN BIT_ULL(13) 264863dea3SSunil Goutham #define CMR_PKT_RX_EN BIT_ULL(14) 274863dea3SSunil Goutham #define CMR_EN BIT_ULL(15) 284863dea3SSunil Goutham #define BGX_CMR_GLOBAL_CFG 0x08 294863dea3SSunil Goutham #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6) 304863dea3SSunil Goutham #define BGX_CMRX_RX_ID_MAP 0x60 314863dea3SSunil Goutham #define BGX_CMRX_RX_STAT0 0x70 324863dea3SSunil Goutham #define BGX_CMRX_RX_STAT1 0x78 334863dea3SSunil Goutham #define BGX_CMRX_RX_STAT2 0x80 344863dea3SSunil Goutham #define BGX_CMRX_RX_STAT3 0x88 354863dea3SSunil Goutham #define BGX_CMRX_RX_STAT4 0x90 364863dea3SSunil Goutham #define BGX_CMRX_RX_STAT5 0x98 374863dea3SSunil Goutham #define BGX_CMRX_RX_STAT6 0xA0 384863dea3SSunil Goutham #define BGX_CMRX_RX_STAT7 0xA8 394863dea3SSunil Goutham #define BGX_CMRX_RX_STAT8 0xB0 404863dea3SSunil Goutham #define BGX_CMRX_RX_STAT9 0xB8 414863dea3SSunil Goutham #define BGX_CMRX_RX_STAT10 0xC0 424863dea3SSunil Goutham #define BGX_CMRX_RX_BP_DROP 0xC8 434863dea3SSunil Goutham #define BGX_CMRX_RX_DMAC_CTL 0x0E8 444863dea3SSunil Goutham #define BGX_CMR_RX_DMACX_CAM 0x200 454863dea3SSunil Goutham #define RX_DMACX_CAM_EN BIT_ULL(48) 464863dea3SSunil Goutham #define RX_DMACX_CAM_LMACID(x) (x << 49) 474863dea3SSunil Goutham #define RX_DMAC_COUNT 32 484863dea3SSunil Goutham #define BGX_CMR_RX_STREERING 0x300 494863dea3SSunil Goutham #define RX_TRAFFIC_STEER_RULE_COUNT 8 504863dea3SSunil Goutham #define BGX_CMR_CHAN_MSK_AND 0x450 514863dea3SSunil Goutham #define BGX_CMR_BIST_STATUS 0x460 524863dea3SSunil Goutham #define BGX_CMR_RX_LMACS 0x468 534863dea3SSunil Goutham #define BGX_CMRX_TX_STAT0 0x600 544863dea3SSunil Goutham #define BGX_CMRX_TX_STAT1 0x608 554863dea3SSunil Goutham #define BGX_CMRX_TX_STAT2 0x610 564863dea3SSunil Goutham #define BGX_CMRX_TX_STAT3 0x618 574863dea3SSunil Goutham #define BGX_CMRX_TX_STAT4 0x620 584863dea3SSunil Goutham #define BGX_CMRX_TX_STAT5 0x628 594863dea3SSunil Goutham #define BGX_CMRX_TX_STAT6 0x630 604863dea3SSunil Goutham #define BGX_CMRX_TX_STAT7 0x638 614863dea3SSunil Goutham #define BGX_CMRX_TX_STAT8 0x640 624863dea3SSunil Goutham #define BGX_CMRX_TX_STAT9 0x648 634863dea3SSunil Goutham #define BGX_CMRX_TX_STAT10 0x650 644863dea3SSunil Goutham #define BGX_CMRX_TX_STAT11 0x658 654863dea3SSunil Goutham #define BGX_CMRX_TX_STAT12 0x660 664863dea3SSunil Goutham #define BGX_CMRX_TX_STAT13 0x668 674863dea3SSunil Goutham #define BGX_CMRX_TX_STAT14 0x670 684863dea3SSunil Goutham #define BGX_CMRX_TX_STAT15 0x678 694863dea3SSunil Goutham #define BGX_CMRX_TX_STAT16 0x680 704863dea3SSunil Goutham #define BGX_CMRX_TX_STAT17 0x688 714863dea3SSunil Goutham #define BGX_CMR_TX_LMACS 0x1000 724863dea3SSunil Goutham 734863dea3SSunil Goutham #define BGX_SPUX_CONTROL1 0x10000 744863dea3SSunil Goutham #define SPU_CTL_LOW_POWER BIT_ULL(11) 754863dea3SSunil Goutham #define SPU_CTL_RESET BIT_ULL(15) 764863dea3SSunil Goutham #define BGX_SPUX_STATUS1 0x10008 774863dea3SSunil Goutham #define SPU_STATUS1_RCV_LNK BIT_ULL(2) 784863dea3SSunil Goutham #define BGX_SPUX_STATUS2 0x10020 794863dea3SSunil Goutham #define SPU_STATUS2_RCVFLT BIT_ULL(10) 804863dea3SSunil Goutham #define BGX_SPUX_BX_STATUS 0x10028 814863dea3SSunil Goutham #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12) 824863dea3SSunil Goutham #define BGX_SPUX_BR_STATUS1 0x10030 834863dea3SSunil Goutham #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0) 844863dea3SSunil Goutham #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12) 854863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_CRTL 0x10068 864863dea3SSunil Goutham #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1) 874863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_LP_CUP 0x10078 884863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_LD_CUP 0x10088 894863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_LD_REP 0x10090 904863dea3SSunil Goutham #define BGX_SPUX_FEC_CONTROL 0x100A0 914863dea3SSunil Goutham #define SPU_FEC_CTL_FEC_EN BIT_ULL(0) 924863dea3SSunil Goutham #define SPU_FEC_CTL_ERR_EN BIT_ULL(1) 934863dea3SSunil Goutham #define BGX_SPUX_AN_CONTROL 0x100C8 944863dea3SSunil Goutham #define SPU_AN_CTL_AN_EN BIT_ULL(12) 954863dea3SSunil Goutham #define SPU_AN_CTL_XNP_EN BIT_ULL(13) 964863dea3SSunil Goutham #define BGX_SPUX_AN_ADV 0x100D8 974863dea3SSunil Goutham #define BGX_SPUX_MISC_CONTROL 0x10218 984863dea3SSunil Goutham #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10) 994863dea3SSunil Goutham #define SPU_MISC_CTL_RX_DIS BIT_ULL(12) 1004863dea3SSunil Goutham #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */ 1014863dea3SSunil Goutham #define BGX_SPUX_INT_W1S 0x10228 1024863dea3SSunil Goutham #define BGX_SPUX_INT_ENA_W1C 0x10230 1034863dea3SSunil Goutham #define BGX_SPUX_INT_ENA_W1S 0x10238 1044863dea3SSunil Goutham #define BGX_SPU_DBG_CONTROL 0x10300 1054863dea3SSunil Goutham #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18) 1064863dea3SSunil Goutham #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29) 1074863dea3SSunil Goutham 1084863dea3SSunil Goutham #define BGX_SMUX_RX_INT 0x20000 1094863dea3SSunil Goutham #define BGX_SMUX_RX_JABBER 0x20030 1104863dea3SSunil Goutham #define BGX_SMUX_RX_CTL 0x20048 1114863dea3SSunil Goutham #define SMU_RX_CTL_STATUS (3ull << 0) 1124863dea3SSunil Goutham #define BGX_SMUX_TX_APPEND 0x20100 1134863dea3SSunil Goutham #define SMU_TX_APPEND_FCS_D BIT_ULL(2) 1144863dea3SSunil Goutham #define BGX_SMUX_TX_MIN_PKT 0x20118 1154863dea3SSunil Goutham #define BGX_SMUX_TX_INT 0x20140 1164863dea3SSunil Goutham #define BGX_SMUX_TX_CTL 0x20178 1174863dea3SSunil Goutham #define SMU_TX_CTL_DIC_EN BIT_ULL(0) 1184863dea3SSunil Goutham #define SMU_TX_CTL_UNI_EN BIT_ULL(1) 1194863dea3SSunil Goutham #define SMU_TX_CTL_LNK_STATUS (3ull << 4) 1204863dea3SSunil Goutham #define BGX_SMUX_TX_THRESH 0x20180 1214863dea3SSunil Goutham #define BGX_SMUX_CTL 0x20200 1224863dea3SSunil Goutham #define SMU_CTL_RX_IDLE BIT_ULL(0) 1234863dea3SSunil Goutham #define SMU_CTL_TX_IDLE BIT_ULL(1) 1244863dea3SSunil Goutham 1254863dea3SSunil Goutham #define BGX_GMP_PCS_MRX_CTL 0x30000 1264863dea3SSunil Goutham #define PCS_MRX_CTL_RST_AN BIT_ULL(9) 1274863dea3SSunil Goutham #define PCS_MRX_CTL_PWR_DN BIT_ULL(11) 1284863dea3SSunil Goutham #define PCS_MRX_CTL_AN_EN BIT_ULL(12) 1294863dea3SSunil Goutham #define PCS_MRX_CTL_RESET BIT_ULL(15) 1304863dea3SSunil Goutham #define BGX_GMP_PCS_MRX_STATUS 0x30008 1314863dea3SSunil Goutham #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5) 1324863dea3SSunil Goutham #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020 1334863dea3SSunil Goutham #define BGX_GMP_PCS_SGM_AN_ADV 0x30068 1344863dea3SSunil Goutham #define BGX_GMP_PCS_MISCX_CTL 0x30078 1354863dea3SSunil Goutham #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11) 1364863dea3SSunil Goutham #define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full 1374863dea3SSunil Goutham #define BGX_GMP_GMI_PRTX_CFG 0x38020 1384863dea3SSunil Goutham #define GMI_PORT_CFG_SPEED BIT_ULL(1) 1394863dea3SSunil Goutham #define GMI_PORT_CFG_DUPLEX BIT_ULL(2) 1404863dea3SSunil Goutham #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3) 1414863dea3SSunil Goutham #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8) 1424863dea3SSunil Goutham #define BGX_GMP_GMI_RXX_JABBER 0x38038 1434863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_THRESH 0x38210 1444863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_APPEND 0x38218 1454863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_SLOT 0x38220 1464863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_BURST 0x38228 1474863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 1484863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 1494863dea3SSunil Goutham 1504863dea3SSunil Goutham #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ 1514863dea3SSunil Goutham #define BGX_MSIX_VEC_0_29_CTL 0x400008 1524863dea3SSunil Goutham #define BGX_MSIX_PBA_0 0x4F0000 1534863dea3SSunil Goutham 1544863dea3SSunil Goutham /* MSI-X interrupts */ 1554863dea3SSunil Goutham #define BGX_MSIX_VECTORS 30 1564863dea3SSunil Goutham #define BGX_LMAC_VEC_OFFSET 7 1574863dea3SSunil Goutham #define BGX_MSIX_VEC_SHIFT 4 1584863dea3SSunil Goutham 1594863dea3SSunil Goutham #define CMRX_INT 0 1604863dea3SSunil Goutham #define SPUX_INT 1 1614863dea3SSunil Goutham #define SMUX_RX_INT 2 1624863dea3SSunil Goutham #define SMUX_TX_INT 3 1634863dea3SSunil Goutham #define GMPX_PCS_INT 4 1644863dea3SSunil Goutham #define GMPX_GMI_RX_INT 5 1654863dea3SSunil Goutham #define GMPX_GMI_TX_INT 6 1664863dea3SSunil Goutham #define CMR_MEM_INT 28 1674863dea3SSunil Goutham #define SPU_MEM_INT 29 1684863dea3SSunil Goutham 1694863dea3SSunil Goutham #define LMAC_INTR_LINK_UP BIT(0) 1704863dea3SSunil Goutham #define LMAC_INTR_LINK_DOWN BIT(1) 1714863dea3SSunil Goutham 1724863dea3SSunil Goutham /* RX_DMAC_CTL configuration*/ 1734863dea3SSunil Goutham enum MCAST_MODE { 1744863dea3SSunil Goutham MCAST_MODE_REJECT, 1754863dea3SSunil Goutham MCAST_MODE_ACCEPT, 1764863dea3SSunil Goutham MCAST_MODE_CAM_FILTER, 1774863dea3SSunil Goutham RSVD 1784863dea3SSunil Goutham }; 1794863dea3SSunil Goutham 1804863dea3SSunil Goutham #define BCAST_ACCEPT 1 1814863dea3SSunil Goutham #define CAM_ACCEPT 1 1824863dea3SSunil Goutham 1834863dea3SSunil Goutham void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac); 1844863dea3SSunil Goutham unsigned bgx_get_map(int node); 1854863dea3SSunil Goutham int bgx_get_lmac_count(int node, int bgx); 186e610cb32SAleksey Makarov const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid); 187e610cb32SAleksey Makarov void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac); 1884863dea3SSunil Goutham void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status); 1894863dea3SSunil Goutham u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx); 1904863dea3SSunil Goutham u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx); 1914863dea3SSunil Goutham #define BGX_RX_STATS_COUNT 11 1924863dea3SSunil Goutham #define BGX_TX_STATS_COUNT 18 1934863dea3SSunil Goutham 1944863dea3SSunil Goutham struct bgx_stats { 1954863dea3SSunil Goutham u64 rx_stats[BGX_RX_STATS_COUNT]; 1964863dea3SSunil Goutham u64 tx_stats[BGX_TX_STATS_COUNT]; 1974863dea3SSunil Goutham }; 1984863dea3SSunil Goutham 1994863dea3SSunil Goutham enum LMAC_TYPE { 2004863dea3SSunil Goutham BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */ 2014863dea3SSunil Goutham BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */ 2024863dea3SSunil Goutham BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */ 2034863dea3SSunil Goutham BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */ 2044863dea3SSunil Goutham BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */ 2054863dea3SSunil Goutham BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */ 2064863dea3SSunil Goutham BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */ 2074863dea3SSunil Goutham BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */ 2084863dea3SSunil Goutham }; 2094863dea3SSunil Goutham 2104863dea3SSunil Goutham enum qlm_mode { 2114863dea3SSunil Goutham QLM_MODE_SGMII, /* SGMII, each lane independent */ 2124863dea3SSunil Goutham QLM_MODE_XAUI_1X4, /* 1 XAUI or DXAUI, 4 lanes */ 2134863dea3SSunil Goutham QLM_MODE_RXAUI_2X2, /* 2 RXAUI, 2 lanes each */ 2144863dea3SSunil Goutham QLM_MODE_XFI_4X1, /* 4 XFI, 1 lane each */ 2154863dea3SSunil Goutham QLM_MODE_XLAUI_1X4, /* 1 XLAUI, 4 lanes each */ 2164863dea3SSunil Goutham QLM_MODE_10G_KR_4X1, /* 4 10GBASE-KR, 1 lane each */ 2174863dea3SSunil Goutham QLM_MODE_40G_KR4_1X4, /* 1 40GBASE-KR4, 4 lanes each */ 2184863dea3SSunil Goutham }; 2194863dea3SSunil Goutham 2204863dea3SSunil Goutham #endif /* THUNDER_BGX_H */ 221