14863dea3SSunil Goutham /* 24863dea3SSunil Goutham * Copyright (C) 2015 Cavium, Inc. 34863dea3SSunil Goutham * 44863dea3SSunil Goutham * This program is free software; you can redistribute it and/or modify it 54863dea3SSunil Goutham * under the terms of version 2 of the GNU General Public License 64863dea3SSunil Goutham * as published by the Free Software Foundation. 74863dea3SSunil Goutham */ 84863dea3SSunil Goutham 94863dea3SSunil Goutham #ifndef THUNDER_BGX_H 104863dea3SSunil Goutham #define THUNDER_BGX_H 114863dea3SSunil Goutham 1257aaf63cSSunil Goutham /* PCI device ID */ 1357aaf63cSSunil Goutham #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 146465859aSSunil Goutham #define PCI_DEVICE_ID_THUNDER_RGX 0xA054 1557aaf63cSSunil Goutham 1657aaf63cSSunil Goutham /* Subsystem device IDs */ 1757aaf63cSSunil Goutham #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126 1857aaf63cSSunil Goutham #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226 19b47a57a2SGeorge Cherian #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254 2057aaf63cSSunil Goutham #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326 2157aaf63cSSunil Goutham 2209de3917SSunil Goutham #define MAX_BGX_THUNDER 8 /* Max 2 nodes, 4 per node */ 234863dea3SSunil Goutham #define MAX_BGX_PER_CN88XX 2 246465859aSSunil Goutham #define MAX_BGX_PER_CN81XX 3 /* 2 BGXs + 1 RGX */ 250025d93eSSunil Goutham #define MAX_BGX_PER_CN83XX 4 264863dea3SSunil Goutham #define MAX_LMAC_PER_BGX 4 274863dea3SSunil Goutham #define MAX_BGX_CHANS_PER_LMAC 16 284863dea3SSunil Goutham #define MAX_DMAC_PER_LMAC 8 294863dea3SSunil Goutham #define MAX_FRAME_SIZE 9216 30430da208SSunil Goutham #define DEFAULT_PAUSE_TIME 0xFFFF 314863dea3SSunil Goutham 32612e94bdSRadha Mohan Chintakuntla #define BGX_ID_MASK 0x3 33612e94bdSRadha Mohan Chintakuntla 344863dea3SSunil Goutham #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 354863dea3SSunil Goutham 364863dea3SSunil Goutham /* Registers */ 374863dea3SSunil Goutham #define BGX_CMRX_CFG 0x00 384863dea3SSunil Goutham #define CMR_PKT_TX_EN BIT_ULL(13) 394863dea3SSunil Goutham #define CMR_PKT_RX_EN BIT_ULL(14) 404863dea3SSunil Goutham #define CMR_EN BIT_ULL(15) 414863dea3SSunil Goutham #define BGX_CMR_GLOBAL_CFG 0x08 424863dea3SSunil Goutham #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6) 434863dea3SSunil Goutham #define BGX_CMRX_RX_ID_MAP 0x60 444863dea3SSunil Goutham #define BGX_CMRX_RX_STAT0 0x70 454863dea3SSunil Goutham #define BGX_CMRX_RX_STAT1 0x78 464863dea3SSunil Goutham #define BGX_CMRX_RX_STAT2 0x80 474863dea3SSunil Goutham #define BGX_CMRX_RX_STAT3 0x88 484863dea3SSunil Goutham #define BGX_CMRX_RX_STAT4 0x90 494863dea3SSunil Goutham #define BGX_CMRX_RX_STAT5 0x98 504863dea3SSunil Goutham #define BGX_CMRX_RX_STAT6 0xA0 514863dea3SSunil Goutham #define BGX_CMRX_RX_STAT7 0xA8 524863dea3SSunil Goutham #define BGX_CMRX_RX_STAT8 0xB0 534863dea3SSunil Goutham #define BGX_CMRX_RX_STAT9 0xB8 544863dea3SSunil Goutham #define BGX_CMRX_RX_STAT10 0xC0 554863dea3SSunil Goutham #define BGX_CMRX_RX_BP_DROP 0xC8 564863dea3SSunil Goutham #define BGX_CMRX_RX_DMAC_CTL 0x0E8 573f4c68cfSSunil Goutham #define BGX_CMRX_RX_FIFO_LEN 0x108 584863dea3SSunil Goutham #define BGX_CMR_RX_DMACX_CAM 0x200 594863dea3SSunil Goutham #define RX_DMACX_CAM_EN BIT_ULL(48) 604863dea3SSunil Goutham #define RX_DMACX_CAM_LMACID(x) (x << 49) 614863dea3SSunil Goutham #define RX_DMAC_COUNT 32 624863dea3SSunil Goutham #define BGX_CMR_RX_STREERING 0x300 634863dea3SSunil Goutham #define RX_TRAFFIC_STEER_RULE_COUNT 8 644863dea3SSunil Goutham #define BGX_CMR_CHAN_MSK_AND 0x450 654863dea3SSunil Goutham #define BGX_CMR_BIST_STATUS 0x460 664863dea3SSunil Goutham #define BGX_CMR_RX_LMACS 0x468 673f4c68cfSSunil Goutham #define BGX_CMRX_TX_FIFO_LEN 0x518 684863dea3SSunil Goutham #define BGX_CMRX_TX_STAT0 0x600 694863dea3SSunil Goutham #define BGX_CMRX_TX_STAT1 0x608 704863dea3SSunil Goutham #define BGX_CMRX_TX_STAT2 0x610 714863dea3SSunil Goutham #define BGX_CMRX_TX_STAT3 0x618 724863dea3SSunil Goutham #define BGX_CMRX_TX_STAT4 0x620 734863dea3SSunil Goutham #define BGX_CMRX_TX_STAT5 0x628 744863dea3SSunil Goutham #define BGX_CMRX_TX_STAT6 0x630 754863dea3SSunil Goutham #define BGX_CMRX_TX_STAT7 0x638 764863dea3SSunil Goutham #define BGX_CMRX_TX_STAT8 0x640 774863dea3SSunil Goutham #define BGX_CMRX_TX_STAT9 0x648 784863dea3SSunil Goutham #define BGX_CMRX_TX_STAT10 0x650 794863dea3SSunil Goutham #define BGX_CMRX_TX_STAT11 0x658 804863dea3SSunil Goutham #define BGX_CMRX_TX_STAT12 0x660 814863dea3SSunil Goutham #define BGX_CMRX_TX_STAT13 0x668 824863dea3SSunil Goutham #define BGX_CMRX_TX_STAT14 0x670 834863dea3SSunil Goutham #define BGX_CMRX_TX_STAT15 0x678 844863dea3SSunil Goutham #define BGX_CMRX_TX_STAT16 0x680 854863dea3SSunil Goutham #define BGX_CMRX_TX_STAT17 0x688 864863dea3SSunil Goutham #define BGX_CMR_TX_LMACS 0x1000 874863dea3SSunil Goutham 884863dea3SSunil Goutham #define BGX_SPUX_CONTROL1 0x10000 894863dea3SSunil Goutham #define SPU_CTL_LOW_POWER BIT_ULL(11) 90d77a2384SSunil Goutham #define SPU_CTL_LOOPBACK BIT_ULL(14) 914863dea3SSunil Goutham #define SPU_CTL_RESET BIT_ULL(15) 924863dea3SSunil Goutham #define BGX_SPUX_STATUS1 0x10008 934863dea3SSunil Goutham #define SPU_STATUS1_RCV_LNK BIT_ULL(2) 944863dea3SSunil Goutham #define BGX_SPUX_STATUS2 0x10020 954863dea3SSunil Goutham #define SPU_STATUS2_RCVFLT BIT_ULL(10) 964863dea3SSunil Goutham #define BGX_SPUX_BX_STATUS 0x10028 974863dea3SSunil Goutham #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12) 984863dea3SSunil Goutham #define BGX_SPUX_BR_STATUS1 0x10030 994863dea3SSunil Goutham #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0) 1004863dea3SSunil Goutham #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12) 1014863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_CRTL 0x10068 1024863dea3SSunil Goutham #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1) 1034863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_LP_CUP 0x10078 1044863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_LD_CUP 0x10088 1054863dea3SSunil Goutham #define BGX_SPUX_BR_PMD_LD_REP 0x10090 1064863dea3SSunil Goutham #define BGX_SPUX_FEC_CONTROL 0x100A0 1074863dea3SSunil Goutham #define SPU_FEC_CTL_FEC_EN BIT_ULL(0) 1084863dea3SSunil Goutham #define SPU_FEC_CTL_ERR_EN BIT_ULL(1) 1094863dea3SSunil Goutham #define BGX_SPUX_AN_CONTROL 0x100C8 1104863dea3SSunil Goutham #define SPU_AN_CTL_AN_EN BIT_ULL(12) 1114863dea3SSunil Goutham #define SPU_AN_CTL_XNP_EN BIT_ULL(13) 1124863dea3SSunil Goutham #define BGX_SPUX_AN_ADV 0x100D8 1134863dea3SSunil Goutham #define BGX_SPUX_MISC_CONTROL 0x10218 1144863dea3SSunil Goutham #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10) 1154863dea3SSunil Goutham #define SPU_MISC_CTL_RX_DIS BIT_ULL(12) 1164863dea3SSunil Goutham #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */ 1174863dea3SSunil Goutham #define BGX_SPUX_INT_W1S 0x10228 1184863dea3SSunil Goutham #define BGX_SPUX_INT_ENA_W1C 0x10230 1194863dea3SSunil Goutham #define BGX_SPUX_INT_ENA_W1S 0x10238 1204863dea3SSunil Goutham #define BGX_SPU_DBG_CONTROL 0x10300 1214863dea3SSunil Goutham #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18) 1224863dea3SSunil Goutham #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29) 1234863dea3SSunil Goutham 1244863dea3SSunil Goutham #define BGX_SMUX_RX_INT 0x20000 1254a875509SSunil Goutham #define BGX_SMUX_RX_FRM_CTL 0x20020 1264a875509SSunil Goutham #define BGX_PKT_RX_PTP_EN BIT_ULL(12) 1274863dea3SSunil Goutham #define BGX_SMUX_RX_JABBER 0x20030 1284863dea3SSunil Goutham #define BGX_SMUX_RX_CTL 0x20048 1294863dea3SSunil Goutham #define SMU_RX_CTL_STATUS (3ull << 0) 1304863dea3SSunil Goutham #define BGX_SMUX_TX_APPEND 0x20100 1314863dea3SSunil Goutham #define SMU_TX_APPEND_FCS_D BIT_ULL(2) 132430da208SSunil Goutham #define BGX_SMUX_TX_PAUSE_PKT_TIME 0x20110 1334863dea3SSunil Goutham #define BGX_SMUX_TX_MIN_PKT 0x20118 134430da208SSunil Goutham #define BGX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120 135430da208SSunil Goutham #define BGX_SMUX_TX_PAUSE_ZERO 0x20138 1364863dea3SSunil Goutham #define BGX_SMUX_TX_INT 0x20140 1374863dea3SSunil Goutham #define BGX_SMUX_TX_CTL 0x20178 1384863dea3SSunil Goutham #define SMU_TX_CTL_DIC_EN BIT_ULL(0) 1394863dea3SSunil Goutham #define SMU_TX_CTL_UNI_EN BIT_ULL(1) 1404863dea3SSunil Goutham #define SMU_TX_CTL_LNK_STATUS (3ull << 4) 1414863dea3SSunil Goutham #define BGX_SMUX_TX_THRESH 0x20180 1424863dea3SSunil Goutham #define BGX_SMUX_CTL 0x20200 1434863dea3SSunil Goutham #define SMU_CTL_RX_IDLE BIT_ULL(0) 1444863dea3SSunil Goutham #define SMU_CTL_TX_IDLE BIT_ULL(1) 145430da208SSunil Goutham #define BGX_SMUX_CBFC_CTL 0x20218 146430da208SSunil Goutham #define RX_EN BIT_ULL(0) 147430da208SSunil Goutham #define TX_EN BIT_ULL(1) 148430da208SSunil Goutham #define BCK_EN BIT_ULL(2) 149430da208SSunil Goutham #define DRP_EN BIT_ULL(3) 1504863dea3SSunil Goutham 1514863dea3SSunil Goutham #define BGX_GMP_PCS_MRX_CTL 0x30000 1524863dea3SSunil Goutham #define PCS_MRX_CTL_RST_AN BIT_ULL(9) 1534863dea3SSunil Goutham #define PCS_MRX_CTL_PWR_DN BIT_ULL(11) 1544863dea3SSunil Goutham #define PCS_MRX_CTL_AN_EN BIT_ULL(12) 155d77a2384SSunil Goutham #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14) 1564863dea3SSunil Goutham #define PCS_MRX_CTL_RESET BIT_ULL(15) 1574863dea3SSunil Goutham #define BGX_GMP_PCS_MRX_STATUS 0x30008 158075ad765SThanneeru Srinivasulu #define PCS_MRX_STATUS_LINK BIT_ULL(2) 1594863dea3SSunil Goutham #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5) 160075ad765SThanneeru Srinivasulu #define BGX_GMP_PCS_ANX_ADV 0x30010 1614863dea3SSunil Goutham #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020 162075ad765SThanneeru Srinivasulu #define BGX_GMP_PCS_LINKX_TIMER 0x30040 163075ad765SThanneeru Srinivasulu #define PCS_LINKX_TIMER_COUNT 0x1E84 1644863dea3SSunil Goutham #define BGX_GMP_PCS_SGM_AN_ADV 0x30068 1654863dea3SSunil Goutham #define BGX_GMP_PCS_MISCX_CTL 0x30078 166075ad765SThanneeru Srinivasulu #define PCS_MISC_CTL_MODE BIT_ULL(8) 1673f8057cfSSunil Goutham #define PCS_MISC_CTL_DISP_EN BIT_ULL(13) 1684863dea3SSunil Goutham #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11) 1694863dea3SSunil Goutham #define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full 1704863dea3SSunil Goutham #define BGX_GMP_GMI_PRTX_CFG 0x38020 1714863dea3SSunil Goutham #define GMI_PORT_CFG_SPEED BIT_ULL(1) 1724863dea3SSunil Goutham #define GMI_PORT_CFG_DUPLEX BIT_ULL(2) 1734863dea3SSunil Goutham #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3) 1744863dea3SSunil Goutham #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8) 175500268e9SSunil Goutham #define GMI_PORT_CFG_RX_IDLE BIT_ULL(12) 176500268e9SSunil Goutham #define GMI_PORT_CFG_TX_IDLE BIT_ULL(13) 1774a875509SSunil Goutham #define BGX_GMP_GMI_RXX_FRM_CTL 0x38028 1784863dea3SSunil Goutham #define BGX_GMP_GMI_RXX_JABBER 0x38038 1794863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_THRESH 0x38210 1804863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_APPEND 0x38218 1814863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_SLOT 0x38220 1824863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_BURST 0x38228 1834863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 1844863dea3SSunil Goutham #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 1854863dea3SSunil Goutham 1864863dea3SSunil Goutham #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ 1874863dea3SSunil Goutham #define BGX_MSIX_VEC_0_29_CTL 0x400008 1884863dea3SSunil Goutham #define BGX_MSIX_PBA_0 0x4F0000 1894863dea3SSunil Goutham 1904863dea3SSunil Goutham /* MSI-X interrupts */ 1914863dea3SSunil Goutham #define BGX_MSIX_VECTORS 30 1924863dea3SSunil Goutham #define BGX_LMAC_VEC_OFFSET 7 1934863dea3SSunil Goutham #define BGX_MSIX_VEC_SHIFT 4 1944863dea3SSunil Goutham 1954863dea3SSunil Goutham #define CMRX_INT 0 1964863dea3SSunil Goutham #define SPUX_INT 1 1974863dea3SSunil Goutham #define SMUX_RX_INT 2 1984863dea3SSunil Goutham #define SMUX_TX_INT 3 1994863dea3SSunil Goutham #define GMPX_PCS_INT 4 2004863dea3SSunil Goutham #define GMPX_GMI_RX_INT 5 2014863dea3SSunil Goutham #define GMPX_GMI_TX_INT 6 2024863dea3SSunil Goutham #define CMR_MEM_INT 28 2034863dea3SSunil Goutham #define SPU_MEM_INT 29 2044863dea3SSunil Goutham 2054863dea3SSunil Goutham #define LMAC_INTR_LINK_UP BIT(0) 2064863dea3SSunil Goutham #define LMAC_INTR_LINK_DOWN BIT(1) 2074863dea3SSunil Goutham 2084863dea3SSunil Goutham /* RX_DMAC_CTL configuration*/ 2094863dea3SSunil Goutham enum MCAST_MODE { 2104863dea3SSunil Goutham MCAST_MODE_REJECT, 2114863dea3SSunil Goutham MCAST_MODE_ACCEPT, 2124863dea3SSunil Goutham MCAST_MODE_CAM_FILTER, 2134863dea3SSunil Goutham RSVD 2144863dea3SSunil Goutham }; 2154863dea3SSunil Goutham 2164863dea3SSunil Goutham #define BCAST_ACCEPT 1 2174863dea3SSunil Goutham #define CAM_ACCEPT 1 2184863dea3SSunil Goutham 219723cda5bSThanneeru Srinivasulu void octeon_mdiobus_force_mod_depencency(void); 220bc69fdfcSSunil Goutham void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable); 2214863dea3SSunil Goutham void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac); 2224863dea3SSunil Goutham unsigned bgx_get_map(int node); 2234863dea3SSunil Goutham int bgx_get_lmac_count(int node, int bgx); 224e610cb32SAleksey Makarov const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid); 225e610cb32SAleksey Makarov void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac); 2264863dea3SSunil Goutham void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status); 227d77a2384SSunil Goutham void bgx_lmac_internal_loopback(int node, int bgx_idx, 228d77a2384SSunil Goutham int lmac_idx, bool enable); 2294a875509SSunil Goutham void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable); 230430da208SSunil Goutham void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause); 231430da208SSunil Goutham void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause); 232430da208SSunil Goutham 2336465859aSSunil Goutham void xcv_init_hw(void); 2346465859aSSunil Goutham void xcv_setup_link(bool link_up, int link_speed); 2356465859aSSunil Goutham 2364863dea3SSunil Goutham u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx); 2374863dea3SSunil Goutham u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx); 2384863dea3SSunil Goutham #define BGX_RX_STATS_COUNT 11 2394863dea3SSunil Goutham #define BGX_TX_STATS_COUNT 18 2404863dea3SSunil Goutham 2414863dea3SSunil Goutham struct bgx_stats { 2424863dea3SSunil Goutham u64 rx_stats[BGX_RX_STATS_COUNT]; 2434863dea3SSunil Goutham u64 tx_stats[BGX_TX_STATS_COUNT]; 2444863dea3SSunil Goutham }; 2454863dea3SSunil Goutham 2464863dea3SSunil Goutham enum LMAC_TYPE { 2474863dea3SSunil Goutham BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */ 2484863dea3SSunil Goutham BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */ 2494863dea3SSunil Goutham BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */ 2504863dea3SSunil Goutham BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */ 2514863dea3SSunil Goutham BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */ 2524863dea3SSunil Goutham BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */ 2534863dea3SSunil Goutham BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */ 2544863dea3SSunil Goutham BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */ 25557aaf63cSSunil Goutham BGX_MODE_RGMII = 5, 25657aaf63cSSunil Goutham BGX_MODE_QSGMII = 6, 25757aaf63cSSunil Goutham BGX_MODE_INVALID = 7, 2584863dea3SSunil Goutham }; 2594863dea3SSunil Goutham 2604863dea3SSunil Goutham #endif /* THUNDER_BGX_H */ 261