1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/phy.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 20 #include "nic_reg.h" 21 #include "nic.h" 22 #include "thunder_bgx.h" 23 24 #define DRV_NAME "thunder-BGX" 25 #define DRV_VERSION "1.0" 26 27 struct lmac { 28 struct bgx *bgx; 29 int dmac; 30 u8 mac[ETH_ALEN]; 31 u8 lmac_type; 32 u8 lane_to_sds; 33 bool use_training; 34 bool autoneg; 35 bool link_up; 36 int lmacid; /* ID within BGX */ 37 int lmacid_bd; /* ID on board */ 38 struct net_device netdev; 39 struct phy_device *phydev; 40 unsigned int last_duplex; 41 unsigned int last_link; 42 unsigned int last_speed; 43 bool is_sgmii; 44 struct delayed_work dwork; 45 struct workqueue_struct *check_link; 46 }; 47 48 struct bgx { 49 u8 bgx_id; 50 struct lmac lmac[MAX_LMAC_PER_BGX]; 51 u8 lmac_count; 52 u8 max_lmac; 53 u8 acpi_lmac_idx; 54 void __iomem *reg_base; 55 struct pci_dev *pdev; 56 bool is_dlm; 57 bool is_rgx; 58 }; 59 60 static struct bgx *bgx_vnic[MAX_BGX_THUNDER]; 61 static int lmac_count; /* Total no of LMACs in system */ 62 63 static int bgx_xaui_check_link(struct lmac *lmac); 64 65 /* Supported devices */ 66 static const struct pci_device_id bgx_id_table[] = { 67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) }, 68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) }, 69 { 0, } /* end of table */ 70 }; 71 72 MODULE_AUTHOR("Cavium Inc"); 73 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver"); 74 MODULE_LICENSE("GPL v2"); 75 MODULE_VERSION(DRV_VERSION); 76 MODULE_DEVICE_TABLE(pci, bgx_id_table); 77 78 /* The Cavium ThunderX network controller can *only* be found in SoCs 79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 80 * registers on this platform are implicitly strongly ordered with respect 81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 82 * with no memory barriers in this driver. The readq()/writeq() functions add 83 * explicit ordering operation which in this case are redundant, and only 84 * add overhead. 85 */ 86 87 /* Register read/write APIs */ 88 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset) 89 { 90 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 91 92 return readq_relaxed(addr); 93 } 94 95 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 96 { 97 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 98 99 writeq_relaxed(val, addr); 100 } 101 102 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 103 { 104 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 105 106 writeq_relaxed(val | readq_relaxed(addr), addr); 107 } 108 109 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero) 110 { 111 int timeout = 100; 112 u64 reg_val; 113 114 while (timeout) { 115 reg_val = bgx_reg_read(bgx, lmac, reg); 116 if (zero && !(reg_val & mask)) 117 return 0; 118 if (!zero && (reg_val & mask)) 119 return 0; 120 usleep_range(1000, 2000); 121 timeout--; 122 } 123 return 1; 124 } 125 126 /* Return number of BGX present in HW */ 127 unsigned bgx_get_map(int node) 128 { 129 int i; 130 unsigned map = 0; 131 132 for (i = 0; i < MAX_BGX_PER_NODE; i++) { 133 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i]) 134 map |= (1 << i); 135 } 136 137 return map; 138 } 139 EXPORT_SYMBOL(bgx_get_map); 140 141 /* Return number of LMAC configured for this BGX */ 142 int bgx_get_lmac_count(int node, int bgx_idx) 143 { 144 struct bgx *bgx; 145 146 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 147 if (bgx) 148 return bgx->lmac_count; 149 150 return 0; 151 } 152 EXPORT_SYMBOL(bgx_get_lmac_count); 153 154 /* Returns the current link status of LMAC */ 155 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status) 156 { 157 struct bgx_link_status *link = (struct bgx_link_status *)status; 158 struct bgx *bgx; 159 struct lmac *lmac; 160 161 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 162 if (!bgx) 163 return; 164 165 lmac = &bgx->lmac[lmacid]; 166 link->mac_type = lmac->lmac_type; 167 link->link_up = lmac->link_up; 168 link->duplex = lmac->last_duplex; 169 link->speed = lmac->last_speed; 170 } 171 EXPORT_SYMBOL(bgx_get_lmac_link_state); 172 173 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid) 174 { 175 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 176 177 if (bgx) 178 return bgx->lmac[lmacid].mac; 179 180 return NULL; 181 } 182 EXPORT_SYMBOL(bgx_get_lmac_mac); 183 184 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac) 185 { 186 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 187 188 if (!bgx) 189 return; 190 191 ether_addr_copy(bgx->lmac[lmacid].mac, mac); 192 } 193 EXPORT_SYMBOL(bgx_set_lmac_mac); 194 195 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable) 196 { 197 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 198 struct lmac *lmac; 199 u64 cfg; 200 201 if (!bgx) 202 return; 203 lmac = &bgx->lmac[lmacid]; 204 205 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 206 if (enable) 207 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN; 208 else 209 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN); 210 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 211 212 if (bgx->is_rgx) 213 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed); 214 } 215 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable); 216 217 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause) 218 { 219 struct pfc *pfc = (struct pfc *)pause; 220 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 221 struct lmac *lmac; 222 u64 cfg; 223 224 if (!bgx) 225 return; 226 lmac = &bgx->lmac[lmacid]; 227 if (lmac->is_sgmii) 228 return; 229 230 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL); 231 pfc->fc_rx = cfg & RX_EN; 232 pfc->fc_tx = cfg & TX_EN; 233 pfc->autoneg = 0; 234 } 235 EXPORT_SYMBOL(bgx_lmac_get_pfc); 236 237 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause) 238 { 239 struct pfc *pfc = (struct pfc *)pause; 240 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 241 struct lmac *lmac; 242 u64 cfg; 243 244 if (!bgx) 245 return; 246 lmac = &bgx->lmac[lmacid]; 247 if (lmac->is_sgmii) 248 return; 249 250 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL); 251 cfg &= ~(RX_EN | TX_EN); 252 cfg |= (pfc->fc_rx ? RX_EN : 0x00); 253 cfg |= (pfc->fc_tx ? TX_EN : 0x00); 254 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg); 255 } 256 EXPORT_SYMBOL(bgx_lmac_set_pfc); 257 258 static void bgx_sgmii_change_link_state(struct lmac *lmac) 259 { 260 struct bgx *bgx = lmac->bgx; 261 u64 cmr_cfg; 262 u64 port_cfg = 0; 263 u64 misc_ctl = 0; 264 265 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG); 266 cmr_cfg &= ~CMR_EN; 267 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 268 269 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 270 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL); 271 272 if (lmac->link_up) { 273 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO; 274 port_cfg &= ~GMI_PORT_CFG_DUPLEX; 275 port_cfg |= (lmac->last_duplex << 2); 276 } else { 277 misc_ctl |= PCS_MISC_CTL_GMX_ENO; 278 } 279 280 switch (lmac->last_speed) { 281 case 10: 282 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 283 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */ 284 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 285 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 286 misc_ctl |= 50; /* samp_pt */ 287 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 288 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 289 break; 290 case 100: 291 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 292 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 293 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 294 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 295 misc_ctl |= 5; /* samp_pt */ 296 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 297 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 298 break; 299 case 1000: 300 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */ 301 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 302 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */ 303 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 304 misc_ctl |= 1; /* samp_pt */ 305 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512); 306 if (lmac->last_duplex) 307 bgx_reg_write(bgx, lmac->lmacid, 308 BGX_GMP_GMI_TXX_BURST, 0); 309 else 310 bgx_reg_write(bgx, lmac->lmacid, 311 BGX_GMP_GMI_TXX_BURST, 8192); 312 break; 313 default: 314 break; 315 } 316 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl); 317 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg); 318 319 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 320 321 /* Re-enable lmac */ 322 cmr_cfg |= CMR_EN; 323 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 324 325 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN))) 326 xcv_setup_link(lmac->link_up, lmac->last_speed); 327 } 328 329 static void bgx_lmac_handler(struct net_device *netdev) 330 { 331 struct lmac *lmac = container_of(netdev, struct lmac, netdev); 332 struct phy_device *phydev; 333 int link_changed = 0; 334 335 if (!lmac) 336 return; 337 338 phydev = lmac->phydev; 339 340 if (!phydev->link && lmac->last_link) 341 link_changed = -1; 342 343 if (phydev->link && 344 (lmac->last_duplex != phydev->duplex || 345 lmac->last_link != phydev->link || 346 lmac->last_speed != phydev->speed)) { 347 link_changed = 1; 348 } 349 350 lmac->last_link = phydev->link; 351 lmac->last_speed = phydev->speed; 352 lmac->last_duplex = phydev->duplex; 353 354 if (!link_changed) 355 return; 356 357 if (link_changed > 0) 358 lmac->link_up = true; 359 else 360 lmac->link_up = false; 361 362 if (lmac->is_sgmii) 363 bgx_sgmii_change_link_state(lmac); 364 else 365 bgx_xaui_check_link(lmac); 366 } 367 368 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx) 369 { 370 struct bgx *bgx; 371 372 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 373 if (!bgx) 374 return 0; 375 376 if (idx > 8) 377 lmac = 0; 378 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8)); 379 } 380 EXPORT_SYMBOL(bgx_get_rx_stats); 381 382 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx) 383 { 384 struct bgx *bgx; 385 386 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 387 if (!bgx) 388 return 0; 389 390 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8)); 391 } 392 EXPORT_SYMBOL(bgx_get_tx_stats); 393 394 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac) 395 { 396 u64 offset; 397 398 while (bgx->lmac[lmac].dmac > 0) { 399 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) + 400 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64)); 401 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0); 402 bgx->lmac[lmac].dmac--; 403 } 404 } 405 406 /* Configure BGX LMAC in internal loopback mode */ 407 void bgx_lmac_internal_loopback(int node, int bgx_idx, 408 int lmac_idx, bool enable) 409 { 410 struct bgx *bgx; 411 struct lmac *lmac; 412 u64 cfg; 413 414 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx]; 415 if (!bgx) 416 return; 417 418 lmac = &bgx->lmac[lmac_idx]; 419 if (lmac->is_sgmii) { 420 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL); 421 if (enable) 422 cfg |= PCS_MRX_CTL_LOOPBACK1; 423 else 424 cfg &= ~PCS_MRX_CTL_LOOPBACK1; 425 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg); 426 } else { 427 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1); 428 if (enable) 429 cfg |= SPU_CTL_LOOPBACK; 430 else 431 cfg &= ~SPU_CTL_LOOPBACK; 432 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg); 433 } 434 } 435 EXPORT_SYMBOL(bgx_lmac_internal_loopback); 436 437 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac) 438 { 439 int lmacid = lmac->lmacid; 440 u64 cfg; 441 442 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30); 443 /* max packet size */ 444 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE); 445 446 /* Disable frame alignment if using preamble */ 447 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 448 if (cfg & 1) 449 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0); 450 451 /* Enable lmac */ 452 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 453 454 /* PCS reset */ 455 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET); 456 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, 457 PCS_MRX_CTL_RESET, true)) { 458 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n"); 459 return -1; 460 } 461 462 /* power down, reset autoneg, autoneg enable */ 463 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL); 464 cfg &= ~PCS_MRX_CTL_PWR_DN; 465 cfg |= PCS_MRX_CTL_RST_AN; 466 if (lmac->phydev) { 467 cfg |= PCS_MRX_CTL_AN_EN; 468 } else { 469 /* In scenarios where PHY driver is not present or it's a 470 * non-standard PHY, FW sets AN_EN to inform Linux driver 471 * to do auto-neg and link polling or not. 472 */ 473 if (cfg & PCS_MRX_CTL_AN_EN) 474 lmac->autoneg = true; 475 } 476 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg); 477 478 if (lmac->lmac_type == BGX_MODE_QSGMII) { 479 /* Disable disparity check for QSGMII */ 480 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL); 481 cfg &= ~PCS_MISC_CTL_DISP_EN; 482 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg); 483 return 0; 484 } 485 486 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) { 487 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS, 488 PCS_MRX_STATUS_AN_CPT, false)) { 489 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n"); 490 return -1; 491 } 492 } 493 494 return 0; 495 } 496 497 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac) 498 { 499 u64 cfg; 500 int lmacid = lmac->lmacid; 501 502 /* Reset SPU */ 503 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET); 504 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 505 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 506 return -1; 507 } 508 509 /* Disable LMAC */ 510 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 511 cfg &= ~CMR_EN; 512 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 513 514 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); 515 /* Set interleaved running disparity for RXAUI */ 516 if (lmac->lmac_type == BGX_MODE_RXAUI) 517 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, 518 SPU_MISC_CTL_INTLV_RDISP); 519 520 /* Clear receive packet disable */ 521 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL); 522 cfg &= ~SPU_MISC_CTL_RX_DIS; 523 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg); 524 525 /* clear all interrupts */ 526 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT); 527 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg); 528 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT); 529 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg); 530 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 531 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 532 533 if (lmac->use_training) { 534 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00); 535 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00); 536 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00); 537 /* training enable */ 538 bgx_reg_modify(bgx, lmacid, 539 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN); 540 } 541 542 /* Append FCS to each packet */ 543 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D); 544 545 /* Disable forward error correction */ 546 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL); 547 cfg &= ~SPU_FEC_CTL_FEC_EN; 548 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg); 549 550 /* Disable autoneg */ 551 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL); 552 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN); 553 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg); 554 555 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV); 556 if (lmac->lmac_type == BGX_MODE_10G_KR) 557 cfg |= (1 << 23); 558 else if (lmac->lmac_type == BGX_MODE_40G_KR) 559 cfg |= (1 << 24); 560 else 561 cfg &= ~((1 << 23) | (1 << 24)); 562 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12))); 563 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg); 564 565 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL); 566 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN; 567 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg); 568 569 /* Enable lmac */ 570 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 571 572 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1); 573 cfg &= ~SPU_CTL_LOW_POWER; 574 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg); 575 576 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL); 577 cfg &= ~SMU_TX_CTL_UNI_EN; 578 cfg |= SMU_TX_CTL_DIC_EN; 579 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg); 580 581 /* Enable receive and transmission of pause frames */ 582 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) | 583 BCK_EN | DRP_EN | TX_EN | RX_EN)); 584 /* Configure pause time and interval */ 585 bgx_reg_write(bgx, lmacid, 586 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME); 587 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL); 588 cfg &= ~0xFFFFull; 589 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL, 590 cfg | (DEFAULT_PAUSE_TIME - 0x1000)); 591 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01); 592 593 /* take lmac_count into account */ 594 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1)); 595 /* max packet size */ 596 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE); 597 598 return 0; 599 } 600 601 static int bgx_xaui_check_link(struct lmac *lmac) 602 { 603 struct bgx *bgx = lmac->bgx; 604 int lmacid = lmac->lmacid; 605 int lmac_type = lmac->lmac_type; 606 u64 cfg; 607 608 if (lmac->use_training) { 609 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 610 if (!(cfg & (1ull << 13))) { 611 cfg = (1ull << 13) | (1ull << 14); 612 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 613 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL); 614 cfg |= (1ull << 0); 615 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg); 616 return -1; 617 } 618 } 619 620 /* wait for PCS to come out of reset */ 621 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 622 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 623 return -1; 624 } 625 626 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) || 627 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) { 628 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1, 629 SPU_BR_STATUS_BLK_LOCK, false)) { 630 dev_err(&bgx->pdev->dev, 631 "SPU_BR_STATUS_BLK_LOCK not completed\n"); 632 return -1; 633 } 634 } else { 635 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS, 636 SPU_BX_STATUS_RX_ALIGN, false)) { 637 dev_err(&bgx->pdev->dev, 638 "SPU_BX_STATUS_RX_ALIGN not completed\n"); 639 return -1; 640 } 641 } 642 643 /* Clear rcvflt bit (latching high) and read it back */ 644 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) 645 bgx_reg_modify(bgx, lmacid, 646 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT); 647 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { 648 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n"); 649 if (lmac->use_training) { 650 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 651 if (!(cfg & (1ull << 13))) { 652 cfg = (1ull << 13) | (1ull << 14); 653 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 654 cfg = bgx_reg_read(bgx, lmacid, 655 BGX_SPUX_BR_PMD_CRTL); 656 cfg |= (1ull << 0); 657 bgx_reg_write(bgx, lmacid, 658 BGX_SPUX_BR_PMD_CRTL, cfg); 659 return -1; 660 } 661 } 662 return -1; 663 } 664 665 /* Wait for BGX RX to be idle */ 666 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) { 667 dev_err(&bgx->pdev->dev, "SMU RX not idle\n"); 668 return -1; 669 } 670 671 /* Wait for BGX TX to be idle */ 672 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) { 673 dev_err(&bgx->pdev->dev, "SMU TX not idle\n"); 674 return -1; 675 } 676 677 /* Check for MAC RX faults */ 678 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL); 679 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */ 680 cfg &= SMU_RX_CTL_STATUS; 681 if (!cfg) 682 return 0; 683 684 /* Rx local/remote fault seen. 685 * Do lmac reinit to see if condition recovers 686 */ 687 bgx_lmac_xaui_init(bgx, lmac); 688 689 return -1; 690 } 691 692 static void bgx_poll_for_sgmii_link(struct lmac *lmac) 693 { 694 u64 pcs_link, an_result; 695 u8 speed; 696 697 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid, 698 BGX_GMP_PCS_MRX_STATUS); 699 700 /*Link state bit is sticky, read it again*/ 701 if (!(pcs_link & PCS_MRX_STATUS_LINK)) 702 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid, 703 BGX_GMP_PCS_MRX_STATUS); 704 705 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS, 706 PCS_MRX_STATUS_AN_CPT, false)) { 707 lmac->link_up = false; 708 lmac->last_speed = SPEED_UNKNOWN; 709 lmac->last_duplex = DUPLEX_UNKNOWN; 710 goto next_poll; 711 } 712 713 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false; 714 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid, 715 BGX_GMP_PCS_ANX_AN_RESULTS); 716 717 speed = (an_result >> 3) & 0x3; 718 lmac->last_duplex = (an_result >> 1) & 0x1; 719 switch (speed) { 720 case 0: 721 lmac->last_speed = 10; 722 break; 723 case 1: 724 lmac->last_speed = 100; 725 break; 726 case 2: 727 lmac->last_speed = 1000; 728 break; 729 default: 730 lmac->link_up = false; 731 lmac->last_speed = SPEED_UNKNOWN; 732 lmac->last_duplex = DUPLEX_UNKNOWN; 733 break; 734 } 735 736 next_poll: 737 738 if (lmac->last_link != lmac->link_up) { 739 if (lmac->link_up) 740 bgx_sgmii_change_link_state(lmac); 741 lmac->last_link = lmac->link_up; 742 } 743 744 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3); 745 } 746 747 static void bgx_poll_for_link(struct work_struct *work) 748 { 749 struct lmac *lmac; 750 u64 spu_link, smu_link; 751 752 lmac = container_of(work, struct lmac, dwork.work); 753 if (lmac->is_sgmii) { 754 bgx_poll_for_sgmii_link(lmac); 755 return; 756 } 757 758 /* Receive link is latching low. Force it high and verify it */ 759 bgx_reg_modify(lmac->bgx, lmac->lmacid, 760 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); 761 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1, 762 SPU_STATUS1_RCV_LNK, false); 763 764 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1); 765 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL); 766 767 if ((spu_link & SPU_STATUS1_RCV_LNK) && 768 !(smu_link & SMU_RX_CTL_STATUS)) { 769 lmac->link_up = 1; 770 if (lmac->lmac_type == BGX_MODE_XLAUI) 771 lmac->last_speed = 40000; 772 else 773 lmac->last_speed = 10000; 774 lmac->last_duplex = 1; 775 } else { 776 lmac->link_up = 0; 777 lmac->last_speed = SPEED_UNKNOWN; 778 lmac->last_duplex = DUPLEX_UNKNOWN; 779 } 780 781 if (lmac->last_link != lmac->link_up) { 782 if (lmac->link_up) { 783 if (bgx_xaui_check_link(lmac)) { 784 /* Errors, clear link_up state */ 785 lmac->link_up = 0; 786 lmac->last_speed = SPEED_UNKNOWN; 787 lmac->last_duplex = DUPLEX_UNKNOWN; 788 } 789 } 790 lmac->last_link = lmac->link_up; 791 } 792 793 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2); 794 } 795 796 static int phy_interface_mode(u8 lmac_type) 797 { 798 if (lmac_type == BGX_MODE_QSGMII) 799 return PHY_INTERFACE_MODE_QSGMII; 800 if (lmac_type == BGX_MODE_RGMII) 801 return PHY_INTERFACE_MODE_RGMII; 802 803 return PHY_INTERFACE_MODE_SGMII; 804 } 805 806 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid) 807 { 808 struct lmac *lmac; 809 u64 cfg; 810 811 lmac = &bgx->lmac[lmacid]; 812 lmac->bgx = bgx; 813 814 if ((lmac->lmac_type == BGX_MODE_SGMII) || 815 (lmac->lmac_type == BGX_MODE_QSGMII) || 816 (lmac->lmac_type == BGX_MODE_RGMII)) { 817 lmac->is_sgmii = 1; 818 if (bgx_lmac_sgmii_init(bgx, lmac)) 819 return -1; 820 } else { 821 lmac->is_sgmii = 0; 822 if (bgx_lmac_xaui_init(bgx, lmac)) 823 return -1; 824 } 825 826 if (lmac->is_sgmii) { 827 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 828 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 829 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg); 830 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1); 831 } else { 832 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND); 833 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 834 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg); 835 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4); 836 } 837 838 /* Enable lmac */ 839 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 840 841 /* Restore default cfg, incase low level firmware changed it */ 842 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03); 843 844 if ((lmac->lmac_type != BGX_MODE_XFI) && 845 (lmac->lmac_type != BGX_MODE_XLAUI) && 846 (lmac->lmac_type != BGX_MODE_40G_KR) && 847 (lmac->lmac_type != BGX_MODE_10G_KR)) { 848 if (!lmac->phydev) { 849 if (lmac->autoneg) { 850 bgx_reg_write(bgx, lmacid, 851 BGX_GMP_PCS_LINKX_TIMER, 852 PCS_LINKX_TIMER_COUNT); 853 goto poll; 854 } else { 855 /* Default to below link speed and duplex */ 856 lmac->link_up = true; 857 lmac->last_speed = 1000; 858 lmac->last_duplex = 1; 859 bgx_sgmii_change_link_state(lmac); 860 return 0; 861 } 862 } 863 lmac->phydev->dev_flags = 0; 864 865 if (phy_connect_direct(&lmac->netdev, lmac->phydev, 866 bgx_lmac_handler, 867 phy_interface_mode(lmac->lmac_type))) 868 return -ENODEV; 869 870 phy_start_aneg(lmac->phydev); 871 return 0; 872 } 873 874 poll: 875 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND | 876 WQ_MEM_RECLAIM, 1); 877 if (!lmac->check_link) 878 return -ENOMEM; 879 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link); 880 queue_delayed_work(lmac->check_link, &lmac->dwork, 0); 881 882 return 0; 883 } 884 885 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid) 886 { 887 struct lmac *lmac; 888 u64 cfg; 889 890 lmac = &bgx->lmac[lmacid]; 891 if (lmac->check_link) { 892 /* Destroy work queue */ 893 cancel_delayed_work_sync(&lmac->dwork); 894 destroy_workqueue(lmac->check_link); 895 } 896 897 /* Disable packet reception */ 898 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 899 cfg &= ~CMR_PKT_RX_EN; 900 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 901 902 /* Give chance for Rx/Tx FIFO to get drained */ 903 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true); 904 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true); 905 906 /* Disable packet transmission */ 907 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 908 cfg &= ~CMR_PKT_TX_EN; 909 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 910 911 /* Disable serdes lanes */ 912 if (!lmac->is_sgmii) 913 bgx_reg_modify(bgx, lmacid, 914 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); 915 else 916 bgx_reg_modify(bgx, lmacid, 917 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN); 918 919 /* Disable LMAC */ 920 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 921 cfg &= ~CMR_EN; 922 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 923 924 bgx_flush_dmac_addrs(bgx, lmacid); 925 926 if ((lmac->lmac_type != BGX_MODE_XFI) && 927 (lmac->lmac_type != BGX_MODE_XLAUI) && 928 (lmac->lmac_type != BGX_MODE_40G_KR) && 929 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev) 930 phy_disconnect(lmac->phydev); 931 932 lmac->phydev = NULL; 933 } 934 935 static void bgx_init_hw(struct bgx *bgx) 936 { 937 int i; 938 struct lmac *lmac; 939 940 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP); 941 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS)) 942 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id); 943 944 /* Set lmac type and lane2serdes mapping */ 945 for (i = 0; i < bgx->lmac_count; i++) { 946 lmac = &bgx->lmac[i]; 947 bgx_reg_write(bgx, i, BGX_CMRX_CFG, 948 (lmac->lmac_type << 8) | lmac->lane_to_sds); 949 bgx->lmac[i].lmacid_bd = lmac_count; 950 lmac_count++; 951 } 952 953 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count); 954 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count); 955 956 /* Set the backpressure AND mask */ 957 for (i = 0; i < bgx->lmac_count; i++) 958 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND, 959 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) << 960 (i * MAX_BGX_CHANS_PER_LMAC)); 961 962 /* Disable all MAC filtering */ 963 for (i = 0; i < RX_DMAC_COUNT; i++) 964 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00); 965 966 /* Disable MAC steering (NCSI traffic) */ 967 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++) 968 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00); 969 } 970 971 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac) 972 { 973 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF); 974 } 975 976 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid) 977 { 978 struct device *dev = &bgx->pdev->dev; 979 struct lmac *lmac; 980 char str[20]; 981 982 if (!bgx->is_dlm && lmacid) 983 return; 984 985 lmac = &bgx->lmac[lmacid]; 986 if (!bgx->is_dlm) 987 sprintf(str, "BGX%d QLM mode", bgx->bgx_id); 988 else 989 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid); 990 991 switch (lmac->lmac_type) { 992 case BGX_MODE_SGMII: 993 dev_info(dev, "%s: SGMII\n", (char *)str); 994 break; 995 case BGX_MODE_XAUI: 996 dev_info(dev, "%s: XAUI\n", (char *)str); 997 break; 998 case BGX_MODE_RXAUI: 999 dev_info(dev, "%s: RXAUI\n", (char *)str); 1000 break; 1001 case BGX_MODE_XFI: 1002 if (!lmac->use_training) 1003 dev_info(dev, "%s: XFI\n", (char *)str); 1004 else 1005 dev_info(dev, "%s: 10G_KR\n", (char *)str); 1006 break; 1007 case BGX_MODE_XLAUI: 1008 if (!lmac->use_training) 1009 dev_info(dev, "%s: XLAUI\n", (char *)str); 1010 else 1011 dev_info(dev, "%s: 40G_KR4\n", (char *)str); 1012 break; 1013 case BGX_MODE_QSGMII: 1014 if ((lmacid == 0) && 1015 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid)) 1016 return; 1017 if ((lmacid == 2) && 1018 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid)) 1019 return; 1020 dev_info(dev, "%s: QSGMII\n", (char *)str); 1021 break; 1022 case BGX_MODE_RGMII: 1023 dev_info(dev, "%s: RGMII\n", (char *)str); 1024 break; 1025 case BGX_MODE_INVALID: 1026 /* Nothing to do */ 1027 break; 1028 } 1029 } 1030 1031 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac) 1032 { 1033 switch (lmac->lmac_type) { 1034 case BGX_MODE_SGMII: 1035 case BGX_MODE_XFI: 1036 lmac->lane_to_sds = lmac->lmacid; 1037 break; 1038 case BGX_MODE_XAUI: 1039 case BGX_MODE_XLAUI: 1040 case BGX_MODE_RGMII: 1041 lmac->lane_to_sds = 0xE4; 1042 break; 1043 case BGX_MODE_RXAUI: 1044 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4; 1045 break; 1046 case BGX_MODE_QSGMII: 1047 /* There is no way to determine if DLM0/2 is QSGMII or 1048 * DLM1/3 is configured to QSGMII as bootloader will 1049 * configure all LMACs, so take whatever is configured 1050 * by low level firmware. 1051 */ 1052 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac); 1053 break; 1054 default: 1055 lmac->lane_to_sds = 0; 1056 break; 1057 } 1058 } 1059 1060 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid) 1061 { 1062 if ((lmac->lmac_type != BGX_MODE_10G_KR) && 1063 (lmac->lmac_type != BGX_MODE_40G_KR)) { 1064 lmac->use_training = 0; 1065 return; 1066 } 1067 1068 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) & 1069 SPU_PMD_CRTL_TRAIN_EN; 1070 } 1071 1072 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx) 1073 { 1074 struct lmac *lmac; 1075 u64 cmr_cfg; 1076 u8 lmac_type; 1077 u8 lane_to_sds; 1078 1079 lmac = &bgx->lmac[idx]; 1080 1081 if (!bgx->is_dlm || bgx->is_rgx) { 1082 /* Read LMAC0 type to figure out QLM mode 1083 * This is configured by low level firmware 1084 */ 1085 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG); 1086 lmac->lmac_type = (cmr_cfg >> 8) & 0x07; 1087 if (bgx->is_rgx) 1088 lmac->lmac_type = BGX_MODE_RGMII; 1089 lmac_set_training(bgx, lmac, 0); 1090 lmac_set_lane2sds(bgx, lmac); 1091 return; 1092 } 1093 1094 /* For DLMs or SLMs on 80/81/83xx so many lane configurations 1095 * are possible and vary across boards. Also Kernel doesn't have 1096 * any way to identify board type/info and since firmware does, 1097 * just take lmac type and serdes lane config as is. 1098 */ 1099 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG); 1100 lmac_type = (u8)((cmr_cfg >> 8) & 0x07); 1101 lane_to_sds = (u8)(cmr_cfg & 0xFF); 1102 /* Check if config is reset value */ 1103 if ((lmac_type == 0) && (lane_to_sds == 0xE4)) 1104 lmac->lmac_type = BGX_MODE_INVALID; 1105 else 1106 lmac->lmac_type = lmac_type; 1107 lmac->lane_to_sds = lane_to_sds; 1108 lmac_set_training(bgx, lmac, lmac->lmacid); 1109 } 1110 1111 static void bgx_get_qlm_mode(struct bgx *bgx) 1112 { 1113 struct lmac *lmac; 1114 u8 idx; 1115 1116 /* Init all LMAC's type to invalid */ 1117 for (idx = 0; idx < bgx->max_lmac; idx++) { 1118 lmac = &bgx->lmac[idx]; 1119 lmac->lmacid = idx; 1120 lmac->lmac_type = BGX_MODE_INVALID; 1121 lmac->use_training = false; 1122 } 1123 1124 /* It is assumed that low level firmware sets this value */ 1125 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7; 1126 if (bgx->lmac_count > bgx->max_lmac) 1127 bgx->lmac_count = bgx->max_lmac; 1128 1129 for (idx = 0; idx < bgx->lmac_count; idx++) { 1130 bgx_set_lmac_config(bgx, idx); 1131 bgx_print_qlm_mode(bgx, idx); 1132 } 1133 } 1134 1135 #ifdef CONFIG_ACPI 1136 1137 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev, 1138 u8 *dst) 1139 { 1140 u8 mac[ETH_ALEN]; 1141 int ret; 1142 1143 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev), 1144 "mac-address", mac, ETH_ALEN); 1145 if (ret) 1146 goto out; 1147 1148 if (!is_valid_ether_addr(mac)) { 1149 dev_err(dev, "MAC address invalid: %pM\n", mac); 1150 ret = -EINVAL; 1151 goto out; 1152 } 1153 1154 dev_info(dev, "MAC address set to: %pM\n", mac); 1155 1156 memcpy(dst, mac, ETH_ALEN); 1157 out: 1158 return ret; 1159 } 1160 1161 /* Currently only sets the MAC address. */ 1162 static acpi_status bgx_acpi_register_phy(acpi_handle handle, 1163 u32 lvl, void *context, void **rv) 1164 { 1165 struct bgx *bgx = context; 1166 struct device *dev = &bgx->pdev->dev; 1167 struct acpi_device *adev; 1168 1169 if (acpi_bus_get_device(handle, &adev)) 1170 goto out; 1171 1172 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac); 1173 1174 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev); 1175 1176 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx; 1177 bgx->acpi_lmac_idx++; /* move to next LMAC */ 1178 out: 1179 return AE_OK; 1180 } 1181 1182 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl, 1183 void *context, void **ret_val) 1184 { 1185 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; 1186 struct bgx *bgx = context; 1187 char bgx_sel[5]; 1188 1189 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id); 1190 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) { 1191 pr_warn("Invalid link device\n"); 1192 return AE_OK; 1193 } 1194 1195 if (strncmp(string.pointer, bgx_sel, 4)) 1196 return AE_OK; 1197 1198 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, 1199 bgx_acpi_register_phy, NULL, bgx, NULL); 1200 1201 kfree(string.pointer); 1202 return AE_CTRL_TERMINATE; 1203 } 1204 1205 static int bgx_init_acpi_phy(struct bgx *bgx) 1206 { 1207 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL); 1208 return 0; 1209 } 1210 1211 #else 1212 1213 static int bgx_init_acpi_phy(struct bgx *bgx) 1214 { 1215 return -ENODEV; 1216 } 1217 1218 #endif /* CONFIG_ACPI */ 1219 1220 #if IS_ENABLED(CONFIG_OF_MDIO) 1221 1222 static int bgx_init_of_phy(struct bgx *bgx) 1223 { 1224 struct fwnode_handle *fwn; 1225 struct device_node *node = NULL; 1226 u8 lmac = 0; 1227 1228 device_for_each_child_node(&bgx->pdev->dev, fwn) { 1229 struct phy_device *pd; 1230 struct device_node *phy_np; 1231 const char *mac; 1232 1233 /* Should always be an OF node. But if it is not, we 1234 * cannot handle it, so exit the loop. 1235 */ 1236 node = to_of_node(fwn); 1237 if (!node) 1238 break; 1239 1240 mac = of_get_mac_address(node); 1241 if (mac) 1242 ether_addr_copy(bgx->lmac[lmac].mac, mac); 1243 1244 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev); 1245 bgx->lmac[lmac].lmacid = lmac; 1246 1247 phy_np = of_parse_phandle(node, "phy-handle", 0); 1248 /* If there is no phy or defective firmware presents 1249 * this cortina phy, for which there is no driver 1250 * support, ignore it. 1251 */ 1252 if (phy_np && 1253 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) { 1254 /* Wait until the phy drivers are available */ 1255 pd = of_phy_find_device(phy_np); 1256 if (!pd) 1257 goto defer; 1258 bgx->lmac[lmac].phydev = pd; 1259 } 1260 1261 lmac++; 1262 if (lmac == bgx->max_lmac) { 1263 of_node_put(node); 1264 break; 1265 } 1266 } 1267 return 0; 1268 1269 defer: 1270 /* We are bailing out, try not to leak device reference counts 1271 * for phy devices we may have already found. 1272 */ 1273 while (lmac) { 1274 if (bgx->lmac[lmac].phydev) { 1275 put_device(&bgx->lmac[lmac].phydev->mdio.dev); 1276 bgx->lmac[lmac].phydev = NULL; 1277 } 1278 lmac--; 1279 } 1280 of_node_put(node); 1281 return -EPROBE_DEFER; 1282 } 1283 1284 #else 1285 1286 static int bgx_init_of_phy(struct bgx *bgx) 1287 { 1288 return -ENODEV; 1289 } 1290 1291 #endif /* CONFIG_OF_MDIO */ 1292 1293 static int bgx_init_phy(struct bgx *bgx) 1294 { 1295 if (!acpi_disabled) 1296 return bgx_init_acpi_phy(bgx); 1297 1298 return bgx_init_of_phy(bgx); 1299 } 1300 1301 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1302 { 1303 int err; 1304 struct device *dev = &pdev->dev; 1305 struct bgx *bgx = NULL; 1306 u8 lmac; 1307 u16 sdevid; 1308 1309 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL); 1310 if (!bgx) 1311 return -ENOMEM; 1312 bgx->pdev = pdev; 1313 1314 pci_set_drvdata(pdev, bgx); 1315 1316 err = pci_enable_device(pdev); 1317 if (err) { 1318 dev_err(dev, "Failed to enable PCI device\n"); 1319 pci_set_drvdata(pdev, NULL); 1320 return err; 1321 } 1322 1323 err = pci_request_regions(pdev, DRV_NAME); 1324 if (err) { 1325 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1326 goto err_disable_device; 1327 } 1328 1329 /* MAP configuration registers */ 1330 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1331 if (!bgx->reg_base) { 1332 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n"); 1333 err = -ENOMEM; 1334 goto err_release_regions; 1335 } 1336 1337 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid); 1338 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) { 1339 bgx->bgx_id = (pci_resource_start(pdev, 1340 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK; 1341 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE; 1342 bgx->max_lmac = MAX_LMAC_PER_BGX; 1343 bgx_vnic[bgx->bgx_id] = bgx; 1344 } else { 1345 bgx->is_rgx = true; 1346 bgx->max_lmac = 1; 1347 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1; 1348 bgx_vnic[bgx->bgx_id] = bgx; 1349 xcv_init_hw(); 1350 } 1351 1352 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one 1353 * BGX i.e BGX2 can be split across 2 DLMs. 1354 */ 1355 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid); 1356 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) || 1357 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2))) 1358 bgx->is_dlm = true; 1359 1360 bgx_get_qlm_mode(bgx); 1361 1362 err = bgx_init_phy(bgx); 1363 if (err) 1364 goto err_enable; 1365 1366 bgx_init_hw(bgx); 1367 1368 /* Enable all LMACs */ 1369 for (lmac = 0; lmac < bgx->lmac_count; lmac++) { 1370 err = bgx_lmac_enable(bgx, lmac); 1371 if (err) { 1372 dev_err(dev, "BGX%d failed to enable lmac%d\n", 1373 bgx->bgx_id, lmac); 1374 while (lmac) 1375 bgx_lmac_disable(bgx, --lmac); 1376 goto err_enable; 1377 } 1378 } 1379 1380 return 0; 1381 1382 err_enable: 1383 bgx_vnic[bgx->bgx_id] = NULL; 1384 err_release_regions: 1385 pci_release_regions(pdev); 1386 err_disable_device: 1387 pci_disable_device(pdev); 1388 pci_set_drvdata(pdev, NULL); 1389 return err; 1390 } 1391 1392 static void bgx_remove(struct pci_dev *pdev) 1393 { 1394 struct bgx *bgx = pci_get_drvdata(pdev); 1395 u8 lmac; 1396 1397 /* Disable all LMACs */ 1398 for (lmac = 0; lmac < bgx->lmac_count; lmac++) 1399 bgx_lmac_disable(bgx, lmac); 1400 1401 bgx_vnic[bgx->bgx_id] = NULL; 1402 pci_release_regions(pdev); 1403 pci_disable_device(pdev); 1404 pci_set_drvdata(pdev, NULL); 1405 } 1406 1407 static struct pci_driver bgx_driver = { 1408 .name = DRV_NAME, 1409 .id_table = bgx_id_table, 1410 .probe = bgx_probe, 1411 .remove = bgx_remove, 1412 }; 1413 1414 static int __init bgx_init_module(void) 1415 { 1416 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1417 1418 return pci_register_driver(&bgx_driver); 1419 } 1420 1421 static void __exit bgx_cleanup_module(void) 1422 { 1423 pci_unregister_driver(&bgx_driver); 1424 } 1425 1426 module_init(bgx_init_module); 1427 module_exit(bgx_cleanup_module); 1428