1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/phy.h> 15 #include <linux/of.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 19 #include "nic_reg.h" 20 #include "nic.h" 21 #include "thunder_bgx.h" 22 23 #define DRV_NAME "thunder-BGX" 24 #define DRV_VERSION "1.0" 25 26 struct lmac { 27 struct bgx *bgx; 28 int dmac; 29 unsigned char mac[ETH_ALEN]; 30 bool link_up; 31 int lmacid; /* ID within BGX */ 32 int lmacid_bd; /* ID on board */ 33 struct net_device netdev; 34 struct phy_device *phydev; 35 unsigned int last_duplex; 36 unsigned int last_link; 37 unsigned int last_speed; 38 bool is_sgmii; 39 struct delayed_work dwork; 40 struct workqueue_struct *check_link; 41 }; 42 43 struct bgx { 44 u8 bgx_id; 45 u8 qlm_mode; 46 struct lmac lmac[MAX_LMAC_PER_BGX]; 47 int lmac_count; 48 int lmac_type; 49 int lane_to_sds; 50 int use_training; 51 void __iomem *reg_base; 52 struct pci_dev *pdev; 53 }; 54 55 static struct bgx *bgx_vnic[MAX_BGX_THUNDER]; 56 static int lmac_count; /* Total no of LMACs in system */ 57 58 static int bgx_xaui_check_link(struct lmac *lmac); 59 60 /* Supported devices */ 61 static const struct pci_device_id bgx_id_table[] = { 62 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) }, 63 { 0, } /* end of table */ 64 }; 65 66 MODULE_AUTHOR("Cavium Inc"); 67 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver"); 68 MODULE_LICENSE("GPL v2"); 69 MODULE_VERSION(DRV_VERSION); 70 MODULE_DEVICE_TABLE(pci, bgx_id_table); 71 72 /* The Cavium ThunderX network controller can *only* be found in SoCs 73 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 74 * registers on this platform are implicitly strongly ordered with respect 75 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 76 * with no memory barriers in this driver. The readq()/writeq() functions add 77 * explicit ordering operation which in this case are redundant, and only 78 * add overhead. 79 */ 80 81 /* Register read/write APIs */ 82 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset) 83 { 84 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 85 86 return readq_relaxed(addr); 87 } 88 89 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 90 { 91 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 92 93 writeq_relaxed(val, addr); 94 } 95 96 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 97 { 98 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 99 100 writeq_relaxed(val | readq_relaxed(addr), addr); 101 } 102 103 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero) 104 { 105 int timeout = 100; 106 u64 reg_val; 107 108 while (timeout) { 109 reg_val = bgx_reg_read(bgx, lmac, reg); 110 if (zero && !(reg_val & mask)) 111 return 0; 112 if (!zero && (reg_val & mask)) 113 return 0; 114 usleep_range(1000, 2000); 115 timeout--; 116 } 117 return 1; 118 } 119 120 /* Return number of BGX present in HW */ 121 unsigned bgx_get_map(int node) 122 { 123 int i; 124 unsigned map = 0; 125 126 for (i = 0; i < MAX_BGX_PER_CN88XX; i++) { 127 if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i]) 128 map |= (1 << i); 129 } 130 131 return map; 132 } 133 EXPORT_SYMBOL(bgx_get_map); 134 135 /* Return number of LMAC configured for this BGX */ 136 int bgx_get_lmac_count(int node, int bgx_idx) 137 { 138 struct bgx *bgx; 139 140 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 141 if (bgx) 142 return bgx->lmac_count; 143 144 return 0; 145 } 146 EXPORT_SYMBOL(bgx_get_lmac_count); 147 148 /* Returns the current link status of LMAC */ 149 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status) 150 { 151 struct bgx_link_status *link = (struct bgx_link_status *)status; 152 struct bgx *bgx; 153 struct lmac *lmac; 154 155 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 156 if (!bgx) 157 return; 158 159 lmac = &bgx->lmac[lmacid]; 160 link->link_up = lmac->link_up; 161 link->duplex = lmac->last_duplex; 162 link->speed = lmac->last_speed; 163 } 164 EXPORT_SYMBOL(bgx_get_lmac_link_state); 165 166 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid) 167 { 168 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 169 170 if (bgx) 171 return bgx->lmac[lmacid].mac; 172 173 return NULL; 174 } 175 EXPORT_SYMBOL(bgx_get_lmac_mac); 176 177 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac) 178 { 179 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 180 181 if (!bgx) 182 return; 183 184 ether_addr_copy(bgx->lmac[lmacid].mac, mac); 185 } 186 EXPORT_SYMBOL(bgx_set_lmac_mac); 187 188 static void bgx_sgmii_change_link_state(struct lmac *lmac) 189 { 190 struct bgx *bgx = lmac->bgx; 191 u64 cmr_cfg; 192 u64 port_cfg = 0; 193 u64 misc_ctl = 0; 194 195 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG); 196 cmr_cfg &= ~CMR_EN; 197 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 198 199 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 200 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL); 201 202 if (lmac->link_up) { 203 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO; 204 port_cfg &= ~GMI_PORT_CFG_DUPLEX; 205 port_cfg |= (lmac->last_duplex << 2); 206 } else { 207 misc_ctl |= PCS_MISC_CTL_GMX_ENO; 208 } 209 210 switch (lmac->last_speed) { 211 case 10: 212 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 213 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */ 214 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 215 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 216 misc_ctl |= 50; /* samp_pt */ 217 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 218 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 219 break; 220 case 100: 221 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 222 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 223 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 224 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 225 misc_ctl |= 5; /* samp_pt */ 226 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 227 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 228 break; 229 case 1000: 230 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */ 231 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 232 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */ 233 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 234 misc_ctl |= 1; /* samp_pt */ 235 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512); 236 if (lmac->last_duplex) 237 bgx_reg_write(bgx, lmac->lmacid, 238 BGX_GMP_GMI_TXX_BURST, 0); 239 else 240 bgx_reg_write(bgx, lmac->lmacid, 241 BGX_GMP_GMI_TXX_BURST, 8192); 242 break; 243 default: 244 break; 245 } 246 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl); 247 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg); 248 249 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 250 251 /* renable lmac */ 252 cmr_cfg |= CMR_EN; 253 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 254 } 255 256 static void bgx_lmac_handler(struct net_device *netdev) 257 { 258 struct lmac *lmac = container_of(netdev, struct lmac, netdev); 259 struct phy_device *phydev = lmac->phydev; 260 int link_changed = 0; 261 262 if (!lmac) 263 return; 264 265 if (!phydev->link && lmac->last_link) 266 link_changed = -1; 267 268 if (phydev->link && 269 (lmac->last_duplex != phydev->duplex || 270 lmac->last_link != phydev->link || 271 lmac->last_speed != phydev->speed)) { 272 link_changed = 1; 273 } 274 275 lmac->last_link = phydev->link; 276 lmac->last_speed = phydev->speed; 277 lmac->last_duplex = phydev->duplex; 278 279 if (!link_changed) 280 return; 281 282 if (link_changed > 0) 283 lmac->link_up = true; 284 else 285 lmac->link_up = false; 286 287 if (lmac->is_sgmii) 288 bgx_sgmii_change_link_state(lmac); 289 else 290 bgx_xaui_check_link(lmac); 291 } 292 293 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx) 294 { 295 struct bgx *bgx; 296 297 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 298 if (!bgx) 299 return 0; 300 301 if (idx > 8) 302 lmac = 0; 303 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8)); 304 } 305 EXPORT_SYMBOL(bgx_get_rx_stats); 306 307 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx) 308 { 309 struct bgx *bgx; 310 311 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 312 if (!bgx) 313 return 0; 314 315 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8)); 316 } 317 EXPORT_SYMBOL(bgx_get_tx_stats); 318 319 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac) 320 { 321 u64 offset; 322 323 while (bgx->lmac[lmac].dmac > 0) { 324 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) + 325 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64)); 326 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0); 327 bgx->lmac[lmac].dmac--; 328 } 329 } 330 331 static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid) 332 { 333 u64 cfg; 334 335 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30); 336 /* max packet size */ 337 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE); 338 339 /* Disable frame alignment if using preamble */ 340 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 341 if (cfg & 1) 342 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0); 343 344 /* Enable lmac */ 345 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 346 347 /* PCS reset */ 348 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET); 349 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, 350 PCS_MRX_CTL_RESET, true)) { 351 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n"); 352 return -1; 353 } 354 355 /* power down, reset autoneg, autoneg enable */ 356 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL); 357 cfg &= ~PCS_MRX_CTL_PWR_DN; 358 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN); 359 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg); 360 361 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS, 362 PCS_MRX_STATUS_AN_CPT, false)) { 363 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n"); 364 return -1; 365 } 366 367 return 0; 368 } 369 370 static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type) 371 { 372 u64 cfg; 373 374 /* Reset SPU */ 375 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET); 376 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 377 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 378 return -1; 379 } 380 381 /* Disable LMAC */ 382 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 383 cfg &= ~CMR_EN; 384 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 385 386 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); 387 /* Set interleaved running disparity for RXAUI */ 388 if (bgx->lmac_type != BGX_MODE_RXAUI) 389 bgx_reg_modify(bgx, lmacid, 390 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS); 391 else 392 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, 393 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP); 394 395 /* clear all interrupts */ 396 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT); 397 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg); 398 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT); 399 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg); 400 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 401 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 402 403 if (bgx->use_training) { 404 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00); 405 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00); 406 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00); 407 /* training enable */ 408 bgx_reg_modify(bgx, lmacid, 409 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN); 410 } 411 412 /* Append FCS to each packet */ 413 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D); 414 415 /* Disable forward error correction */ 416 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL); 417 cfg &= ~SPU_FEC_CTL_FEC_EN; 418 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg); 419 420 /* Disable autoneg */ 421 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL); 422 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN); 423 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg); 424 425 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV); 426 if (bgx->lmac_type == BGX_MODE_10G_KR) 427 cfg |= (1 << 23); 428 else if (bgx->lmac_type == BGX_MODE_40G_KR) 429 cfg |= (1 << 24); 430 else 431 cfg &= ~((1 << 23) | (1 << 24)); 432 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12))); 433 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg); 434 435 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL); 436 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN; 437 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg); 438 439 /* Enable lmac */ 440 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 441 442 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1); 443 cfg &= ~SPU_CTL_LOW_POWER; 444 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg); 445 446 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL); 447 cfg &= ~SMU_TX_CTL_UNI_EN; 448 cfg |= SMU_TX_CTL_DIC_EN; 449 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg); 450 451 /* take lmac_count into account */ 452 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1)); 453 /* max packet size */ 454 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE); 455 456 return 0; 457 } 458 459 static int bgx_xaui_check_link(struct lmac *lmac) 460 { 461 struct bgx *bgx = lmac->bgx; 462 int lmacid = lmac->lmacid; 463 int lmac_type = bgx->lmac_type; 464 u64 cfg; 465 466 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS); 467 if (bgx->use_training) { 468 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 469 if (!(cfg & (1ull << 13))) { 470 cfg = (1ull << 13) | (1ull << 14); 471 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 472 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL); 473 cfg |= (1ull << 0); 474 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg); 475 return -1; 476 } 477 } 478 479 /* wait for PCS to come out of reset */ 480 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 481 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 482 return -1; 483 } 484 485 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) || 486 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) { 487 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1, 488 SPU_BR_STATUS_BLK_LOCK, false)) { 489 dev_err(&bgx->pdev->dev, 490 "SPU_BR_STATUS_BLK_LOCK not completed\n"); 491 return -1; 492 } 493 } else { 494 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS, 495 SPU_BX_STATUS_RX_ALIGN, false)) { 496 dev_err(&bgx->pdev->dev, 497 "SPU_BX_STATUS_RX_ALIGN not completed\n"); 498 return -1; 499 } 500 } 501 502 /* Clear rcvflt bit (latching high) and read it back */ 503 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT); 504 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { 505 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n"); 506 if (bgx->use_training) { 507 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 508 if (!(cfg & (1ull << 13))) { 509 cfg = (1ull << 13) | (1ull << 14); 510 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 511 cfg = bgx_reg_read(bgx, lmacid, 512 BGX_SPUX_BR_PMD_CRTL); 513 cfg |= (1ull << 0); 514 bgx_reg_write(bgx, lmacid, 515 BGX_SPUX_BR_PMD_CRTL, cfg); 516 return -1; 517 } 518 } 519 return -1; 520 } 521 522 /* Wait for MAC RX to be ready */ 523 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL, 524 SMU_RX_CTL_STATUS, true)) { 525 dev_err(&bgx->pdev->dev, "SMU RX link not okay\n"); 526 return -1; 527 } 528 529 /* Wait for BGX RX to be idle */ 530 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) { 531 dev_err(&bgx->pdev->dev, "SMU RX not idle\n"); 532 return -1; 533 } 534 535 /* Wait for BGX TX to be idle */ 536 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) { 537 dev_err(&bgx->pdev->dev, "SMU TX not idle\n"); 538 return -1; 539 } 540 541 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { 542 dev_err(&bgx->pdev->dev, "Receive fault\n"); 543 return -1; 544 } 545 546 /* Receive link is latching low. Force it high and verify it */ 547 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); 548 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1, 549 SPU_STATUS1_RCV_LNK, false)) { 550 dev_err(&bgx->pdev->dev, "SPU receive link down\n"); 551 return -1; 552 } 553 554 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL); 555 cfg &= ~SPU_MISC_CTL_RX_DIS; 556 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg); 557 return 0; 558 } 559 560 static void bgx_poll_for_link(struct work_struct *work) 561 { 562 struct lmac *lmac; 563 u64 link; 564 565 lmac = container_of(work, struct lmac, dwork.work); 566 567 /* Receive link is latching low. Force it high and verify it */ 568 bgx_reg_modify(lmac->bgx, lmac->lmacid, 569 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); 570 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1, 571 SPU_STATUS1_RCV_LNK, false); 572 573 link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1); 574 if (link & SPU_STATUS1_RCV_LNK) { 575 lmac->link_up = 1; 576 if (lmac->bgx->lmac_type == BGX_MODE_XLAUI) 577 lmac->last_speed = 40000; 578 else 579 lmac->last_speed = 10000; 580 lmac->last_duplex = 1; 581 } else { 582 lmac->link_up = 0; 583 } 584 585 if (lmac->last_link != lmac->link_up) { 586 lmac->last_link = lmac->link_up; 587 if (lmac->link_up) 588 bgx_xaui_check_link(lmac); 589 } 590 591 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2); 592 } 593 594 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid) 595 { 596 struct lmac *lmac; 597 u64 cfg; 598 599 lmac = &bgx->lmac[lmacid]; 600 lmac->bgx = bgx; 601 602 if (bgx->lmac_type == BGX_MODE_SGMII) { 603 lmac->is_sgmii = 1; 604 if (bgx_lmac_sgmii_init(bgx, lmacid)) 605 return -1; 606 } else { 607 lmac->is_sgmii = 0; 608 if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type)) 609 return -1; 610 } 611 612 if (lmac->is_sgmii) { 613 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 614 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 615 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg); 616 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1); 617 } else { 618 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND); 619 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 620 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg); 621 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4); 622 } 623 624 /* Enable lmac */ 625 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, 626 CMR_EN | CMR_PKT_RX_EN | CMR_PKT_TX_EN); 627 628 /* Restore default cfg, incase low level firmware changed it */ 629 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03); 630 631 if ((bgx->lmac_type != BGX_MODE_XFI) && 632 (bgx->lmac_type != BGX_MODE_XLAUI) && 633 (bgx->lmac_type != BGX_MODE_40G_KR) && 634 (bgx->lmac_type != BGX_MODE_10G_KR)) { 635 if (!lmac->phydev) 636 return -ENODEV; 637 638 lmac->phydev->dev_flags = 0; 639 640 if (phy_connect_direct(&lmac->netdev, lmac->phydev, 641 bgx_lmac_handler, 642 PHY_INTERFACE_MODE_SGMII)) 643 return -ENODEV; 644 645 phy_start_aneg(lmac->phydev); 646 } else { 647 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND | 648 WQ_MEM_RECLAIM, 1); 649 if (!lmac->check_link) 650 return -ENOMEM; 651 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link); 652 queue_delayed_work(lmac->check_link, &lmac->dwork, 0); 653 } 654 655 return 0; 656 } 657 658 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid) 659 { 660 struct lmac *lmac; 661 u64 cmrx_cfg; 662 663 lmac = &bgx->lmac[lmacid]; 664 if (lmac->check_link) { 665 /* Destroy work queue */ 666 cancel_delayed_work(&lmac->dwork); 667 flush_workqueue(lmac->check_link); 668 destroy_workqueue(lmac->check_link); 669 } 670 671 cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 672 cmrx_cfg &= ~(1 << 15); 673 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg); 674 bgx_flush_dmac_addrs(bgx, lmacid); 675 676 if (lmac->phydev) 677 phy_disconnect(lmac->phydev); 678 679 lmac->phydev = NULL; 680 } 681 682 static void bgx_set_num_ports(struct bgx *bgx) 683 { 684 u64 lmac_count; 685 686 switch (bgx->qlm_mode) { 687 case QLM_MODE_SGMII: 688 bgx->lmac_count = 4; 689 bgx->lmac_type = BGX_MODE_SGMII; 690 bgx->lane_to_sds = 0; 691 break; 692 case QLM_MODE_XAUI_1X4: 693 bgx->lmac_count = 1; 694 bgx->lmac_type = BGX_MODE_XAUI; 695 bgx->lane_to_sds = 0xE4; 696 break; 697 case QLM_MODE_RXAUI_2X2: 698 bgx->lmac_count = 2; 699 bgx->lmac_type = BGX_MODE_RXAUI; 700 bgx->lane_to_sds = 0xE4; 701 break; 702 case QLM_MODE_XFI_4X1: 703 bgx->lmac_count = 4; 704 bgx->lmac_type = BGX_MODE_XFI; 705 bgx->lane_to_sds = 0; 706 break; 707 case QLM_MODE_XLAUI_1X4: 708 bgx->lmac_count = 1; 709 bgx->lmac_type = BGX_MODE_XLAUI; 710 bgx->lane_to_sds = 0xE4; 711 break; 712 case QLM_MODE_10G_KR_4X1: 713 bgx->lmac_count = 4; 714 bgx->lmac_type = BGX_MODE_10G_KR; 715 bgx->lane_to_sds = 0; 716 bgx->use_training = 1; 717 break; 718 case QLM_MODE_40G_KR4_1X4: 719 bgx->lmac_count = 1; 720 bgx->lmac_type = BGX_MODE_40G_KR; 721 bgx->lane_to_sds = 0xE4; 722 bgx->use_training = 1; 723 break; 724 default: 725 bgx->lmac_count = 0; 726 break; 727 } 728 729 /* Check if low level firmware has programmed LMAC count 730 * based on board type, if yes consider that otherwise 731 * the default static values 732 */ 733 lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7; 734 if (lmac_count != 4) 735 bgx->lmac_count = lmac_count; 736 } 737 738 static void bgx_init_hw(struct bgx *bgx) 739 { 740 int i; 741 742 bgx_set_num_ports(bgx); 743 744 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP); 745 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS)) 746 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id); 747 748 /* Set lmac type and lane2serdes mapping */ 749 for (i = 0; i < bgx->lmac_count; i++) { 750 if (bgx->lmac_type == BGX_MODE_RXAUI) { 751 if (i) 752 bgx->lane_to_sds = 0x0e; 753 else 754 bgx->lane_to_sds = 0x04; 755 bgx_reg_write(bgx, i, BGX_CMRX_CFG, 756 (bgx->lmac_type << 8) | bgx->lane_to_sds); 757 continue; 758 } 759 bgx_reg_write(bgx, i, BGX_CMRX_CFG, 760 (bgx->lmac_type << 8) | (bgx->lane_to_sds + i)); 761 bgx->lmac[i].lmacid_bd = lmac_count; 762 lmac_count++; 763 } 764 765 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count); 766 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count); 767 768 /* Set the backpressure AND mask */ 769 for (i = 0; i < bgx->lmac_count; i++) 770 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND, 771 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) << 772 (i * MAX_BGX_CHANS_PER_LMAC)); 773 774 /* Disable all MAC filtering */ 775 for (i = 0; i < RX_DMAC_COUNT; i++) 776 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00); 777 778 /* Disable MAC steering (NCSI traffic) */ 779 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++) 780 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00); 781 } 782 783 static void bgx_get_qlm_mode(struct bgx *bgx) 784 { 785 struct device *dev = &bgx->pdev->dev; 786 int lmac_type; 787 int train_en; 788 789 /* Read LMAC0 type to figure out QLM mode 790 * This is configured by low level firmware 791 */ 792 lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG); 793 lmac_type = (lmac_type >> 8) & 0x07; 794 795 train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) & 796 SPU_PMD_CRTL_TRAIN_EN; 797 798 switch (lmac_type) { 799 case BGX_MODE_SGMII: 800 bgx->qlm_mode = QLM_MODE_SGMII; 801 dev_info(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id); 802 break; 803 case BGX_MODE_XAUI: 804 bgx->qlm_mode = QLM_MODE_XAUI_1X4; 805 dev_info(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id); 806 break; 807 case BGX_MODE_RXAUI: 808 bgx->qlm_mode = QLM_MODE_RXAUI_2X2; 809 dev_info(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id); 810 break; 811 case BGX_MODE_XFI: 812 if (!train_en) { 813 bgx->qlm_mode = QLM_MODE_XFI_4X1; 814 dev_info(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id); 815 } else { 816 bgx->qlm_mode = QLM_MODE_10G_KR_4X1; 817 dev_info(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id); 818 } 819 break; 820 case BGX_MODE_XLAUI: 821 if (!train_en) { 822 bgx->qlm_mode = QLM_MODE_XLAUI_1X4; 823 dev_info(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id); 824 } else { 825 bgx->qlm_mode = QLM_MODE_40G_KR4_1X4; 826 dev_info(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id); 827 } 828 break; 829 default: 830 bgx->qlm_mode = QLM_MODE_SGMII; 831 dev_info(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id); 832 } 833 } 834 835 static void bgx_init_of(struct bgx *bgx, struct device_node *np) 836 { 837 struct device_node *np_child; 838 u8 lmac = 0; 839 840 for_each_child_of_node(np, np_child) { 841 struct device_node *phy_np; 842 const char *mac; 843 844 phy_np = of_parse_phandle(np_child, "phy-handle", 0); 845 if (phy_np) 846 bgx->lmac[lmac].phydev = of_phy_find_device(phy_np); 847 848 mac = of_get_mac_address(np_child); 849 if (mac) 850 ether_addr_copy(bgx->lmac[lmac].mac, mac); 851 852 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev); 853 bgx->lmac[lmac].lmacid = lmac; 854 lmac++; 855 if (lmac == MAX_LMAC_PER_BGX) 856 break; 857 } 858 } 859 860 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 861 { 862 int err; 863 struct device *dev = &pdev->dev; 864 struct bgx *bgx = NULL; 865 struct device_node *np; 866 char bgx_sel[5]; 867 u8 lmac; 868 869 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL); 870 if (!bgx) 871 return -ENOMEM; 872 bgx->pdev = pdev; 873 874 pci_set_drvdata(pdev, bgx); 875 876 err = pci_enable_device(pdev); 877 if (err) { 878 dev_err(dev, "Failed to enable PCI device\n"); 879 pci_set_drvdata(pdev, NULL); 880 return err; 881 } 882 883 err = pci_request_regions(pdev, DRV_NAME); 884 if (err) { 885 dev_err(dev, "PCI request regions failed 0x%x\n", err); 886 goto err_disable_device; 887 } 888 889 /* MAP configuration registers */ 890 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 891 if (!bgx->reg_base) { 892 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n"); 893 err = -ENOMEM; 894 goto err_release_regions; 895 } 896 bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1; 897 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_CN88XX; 898 899 bgx_vnic[bgx->bgx_id] = bgx; 900 bgx_get_qlm_mode(bgx); 901 902 snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id); 903 np = of_find_node_by_name(NULL, bgx_sel); 904 if (np) 905 bgx_init_of(bgx, np); 906 907 bgx_init_hw(bgx); 908 909 /* Enable all LMACs */ 910 for (lmac = 0; lmac < bgx->lmac_count; lmac++) { 911 err = bgx_lmac_enable(bgx, lmac); 912 if (err) { 913 dev_err(dev, "BGX%d failed to enable lmac%d\n", 914 bgx->bgx_id, lmac); 915 goto err_enable; 916 } 917 } 918 919 return 0; 920 921 err_enable: 922 bgx_vnic[bgx->bgx_id] = NULL; 923 err_release_regions: 924 pci_release_regions(pdev); 925 err_disable_device: 926 pci_disable_device(pdev); 927 pci_set_drvdata(pdev, NULL); 928 return err; 929 } 930 931 static void bgx_remove(struct pci_dev *pdev) 932 { 933 struct bgx *bgx = pci_get_drvdata(pdev); 934 u8 lmac; 935 936 /* Disable all LMACs */ 937 for (lmac = 0; lmac < bgx->lmac_count; lmac++) 938 bgx_lmac_disable(bgx, lmac); 939 940 bgx_vnic[bgx->bgx_id] = NULL; 941 pci_release_regions(pdev); 942 pci_disable_device(pdev); 943 pci_set_drvdata(pdev, NULL); 944 } 945 946 static struct pci_driver bgx_driver = { 947 .name = DRV_NAME, 948 .id_table = bgx_id_table, 949 .probe = bgx_probe, 950 .remove = bgx_remove, 951 }; 952 953 static int __init bgx_init_module(void) 954 { 955 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 956 957 return pci_register_driver(&bgx_driver); 958 } 959 960 static void __exit bgx_cleanup_module(void) 961 { 962 pci_unregister_driver(&bgx_driver); 963 } 964 965 module_init(bgx_init_module); 966 module_exit(bgx_cleanup_module); 967