1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/phy.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 20 #include "nic_reg.h" 21 #include "nic.h" 22 #include "thunder_bgx.h" 23 24 #define DRV_NAME "thunder-BGX" 25 #define DRV_VERSION "1.0" 26 27 struct lmac { 28 struct bgx *bgx; 29 int dmac; 30 u8 mac[ETH_ALEN]; 31 u8 lmac_type; 32 u8 lane_to_sds; 33 bool use_training; 34 bool autoneg; 35 bool link_up; 36 int lmacid; /* ID within BGX */ 37 int lmacid_bd; /* ID on board */ 38 struct net_device netdev; 39 struct phy_device *phydev; 40 unsigned int last_duplex; 41 unsigned int last_link; 42 unsigned int last_speed; 43 bool is_sgmii; 44 struct delayed_work dwork; 45 struct workqueue_struct *check_link; 46 }; 47 48 struct bgx { 49 u8 bgx_id; 50 struct lmac lmac[MAX_LMAC_PER_BGX]; 51 u8 lmac_count; 52 u8 max_lmac; 53 u8 acpi_lmac_idx; 54 void __iomem *reg_base; 55 struct pci_dev *pdev; 56 bool is_dlm; 57 bool is_rgx; 58 }; 59 60 static struct bgx *bgx_vnic[MAX_BGX_THUNDER]; 61 static int lmac_count; /* Total no of LMACs in system */ 62 63 static int bgx_xaui_check_link(struct lmac *lmac); 64 65 /* Supported devices */ 66 static const struct pci_device_id bgx_id_table[] = { 67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) }, 68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) }, 69 { 0, } /* end of table */ 70 }; 71 72 MODULE_AUTHOR("Cavium Inc"); 73 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver"); 74 MODULE_LICENSE("GPL v2"); 75 MODULE_VERSION(DRV_VERSION); 76 MODULE_DEVICE_TABLE(pci, bgx_id_table); 77 78 /* The Cavium ThunderX network controller can *only* be found in SoCs 79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 80 * registers on this platform are implicitly strongly ordered with respect 81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 82 * with no memory barriers in this driver. The readq()/writeq() functions add 83 * explicit ordering operation which in this case are redundant, and only 84 * add overhead. 85 */ 86 87 /* Register read/write APIs */ 88 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset) 89 { 90 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 91 92 return readq_relaxed(addr); 93 } 94 95 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 96 { 97 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 98 99 writeq_relaxed(val, addr); 100 } 101 102 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 103 { 104 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 105 106 writeq_relaxed(val | readq_relaxed(addr), addr); 107 } 108 109 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero) 110 { 111 int timeout = 100; 112 u64 reg_val; 113 114 while (timeout) { 115 reg_val = bgx_reg_read(bgx, lmac, reg); 116 if (zero && !(reg_val & mask)) 117 return 0; 118 if (!zero && (reg_val & mask)) 119 return 0; 120 usleep_range(1000, 2000); 121 timeout--; 122 } 123 return 1; 124 } 125 126 static int max_bgx_per_node; 127 static void set_max_bgx_per_node(struct pci_dev *pdev) 128 { 129 u16 sdevid; 130 131 if (max_bgx_per_node) 132 return; 133 134 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid); 135 switch (sdevid) { 136 case PCI_SUBSYS_DEVID_81XX_BGX: 137 case PCI_SUBSYS_DEVID_81XX_RGX: 138 max_bgx_per_node = MAX_BGX_PER_CN81XX; 139 break; 140 case PCI_SUBSYS_DEVID_83XX_BGX: 141 max_bgx_per_node = MAX_BGX_PER_CN83XX; 142 break; 143 case PCI_SUBSYS_DEVID_88XX_BGX: 144 default: 145 max_bgx_per_node = MAX_BGX_PER_CN88XX; 146 break; 147 } 148 } 149 150 static struct bgx *get_bgx(int node, int bgx_idx) 151 { 152 int idx = (node * max_bgx_per_node) + bgx_idx; 153 154 return bgx_vnic[idx]; 155 } 156 157 /* Return number of BGX present in HW */ 158 unsigned bgx_get_map(int node) 159 { 160 int i; 161 unsigned map = 0; 162 163 for (i = 0; i < max_bgx_per_node; i++) { 164 if (bgx_vnic[(node * max_bgx_per_node) + i]) 165 map |= (1 << i); 166 } 167 168 return map; 169 } 170 EXPORT_SYMBOL(bgx_get_map); 171 172 /* Return number of LMAC configured for this BGX */ 173 int bgx_get_lmac_count(int node, int bgx_idx) 174 { 175 struct bgx *bgx; 176 177 bgx = get_bgx(node, bgx_idx); 178 if (bgx) 179 return bgx->lmac_count; 180 181 return 0; 182 } 183 EXPORT_SYMBOL(bgx_get_lmac_count); 184 185 /* Returns the current link status of LMAC */ 186 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status) 187 { 188 struct bgx_link_status *link = (struct bgx_link_status *)status; 189 struct bgx *bgx; 190 struct lmac *lmac; 191 192 bgx = get_bgx(node, bgx_idx); 193 if (!bgx) 194 return; 195 196 lmac = &bgx->lmac[lmacid]; 197 link->mac_type = lmac->lmac_type; 198 link->link_up = lmac->link_up; 199 link->duplex = lmac->last_duplex; 200 link->speed = lmac->last_speed; 201 } 202 EXPORT_SYMBOL(bgx_get_lmac_link_state); 203 204 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid) 205 { 206 struct bgx *bgx = get_bgx(node, bgx_idx); 207 208 if (bgx) 209 return bgx->lmac[lmacid].mac; 210 211 return NULL; 212 } 213 EXPORT_SYMBOL(bgx_get_lmac_mac); 214 215 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac) 216 { 217 struct bgx *bgx = get_bgx(node, bgx_idx); 218 219 if (!bgx) 220 return; 221 222 ether_addr_copy(bgx->lmac[lmacid].mac, mac); 223 } 224 EXPORT_SYMBOL(bgx_set_lmac_mac); 225 226 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable) 227 { 228 struct bgx *bgx = get_bgx(node, bgx_idx); 229 struct lmac *lmac; 230 u64 cfg; 231 232 if (!bgx) 233 return; 234 lmac = &bgx->lmac[lmacid]; 235 236 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 237 if (enable) 238 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN; 239 else 240 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN); 241 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 242 243 if (bgx->is_rgx) 244 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed); 245 } 246 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable); 247 248 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause) 249 { 250 struct pfc *pfc = (struct pfc *)pause; 251 struct bgx *bgx = get_bgx(node, bgx_idx); 252 struct lmac *lmac; 253 u64 cfg; 254 255 if (!bgx) 256 return; 257 lmac = &bgx->lmac[lmacid]; 258 if (lmac->is_sgmii) 259 return; 260 261 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL); 262 pfc->fc_rx = cfg & RX_EN; 263 pfc->fc_tx = cfg & TX_EN; 264 pfc->autoneg = 0; 265 } 266 EXPORT_SYMBOL(bgx_lmac_get_pfc); 267 268 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause) 269 { 270 struct pfc *pfc = (struct pfc *)pause; 271 struct bgx *bgx = get_bgx(node, bgx_idx); 272 struct lmac *lmac; 273 u64 cfg; 274 275 if (!bgx) 276 return; 277 lmac = &bgx->lmac[lmacid]; 278 if (lmac->is_sgmii) 279 return; 280 281 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL); 282 cfg &= ~(RX_EN | TX_EN); 283 cfg |= (pfc->fc_rx ? RX_EN : 0x00); 284 cfg |= (pfc->fc_tx ? TX_EN : 0x00); 285 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg); 286 } 287 EXPORT_SYMBOL(bgx_lmac_set_pfc); 288 289 static void bgx_sgmii_change_link_state(struct lmac *lmac) 290 { 291 struct bgx *bgx = lmac->bgx; 292 u64 cmr_cfg; 293 u64 port_cfg = 0; 294 u64 misc_ctl = 0; 295 296 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG); 297 cmr_cfg &= ~CMR_EN; 298 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 299 300 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 301 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL); 302 303 if (lmac->link_up) { 304 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO; 305 port_cfg &= ~GMI_PORT_CFG_DUPLEX; 306 port_cfg |= (lmac->last_duplex << 2); 307 } else { 308 misc_ctl |= PCS_MISC_CTL_GMX_ENO; 309 } 310 311 switch (lmac->last_speed) { 312 case 10: 313 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 314 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */ 315 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 316 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 317 misc_ctl |= 50; /* samp_pt */ 318 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 319 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 320 break; 321 case 100: 322 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 323 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 324 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 325 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 326 misc_ctl |= 5; /* samp_pt */ 327 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 328 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 329 break; 330 case 1000: 331 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */ 332 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 333 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */ 334 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 335 misc_ctl |= 1; /* samp_pt */ 336 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512); 337 if (lmac->last_duplex) 338 bgx_reg_write(bgx, lmac->lmacid, 339 BGX_GMP_GMI_TXX_BURST, 0); 340 else 341 bgx_reg_write(bgx, lmac->lmacid, 342 BGX_GMP_GMI_TXX_BURST, 8192); 343 break; 344 default: 345 break; 346 } 347 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl); 348 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg); 349 350 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 351 352 /* Re-enable lmac */ 353 cmr_cfg |= CMR_EN; 354 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 355 356 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN))) 357 xcv_setup_link(lmac->link_up, lmac->last_speed); 358 } 359 360 static void bgx_lmac_handler(struct net_device *netdev) 361 { 362 struct lmac *lmac = container_of(netdev, struct lmac, netdev); 363 struct phy_device *phydev; 364 int link_changed = 0; 365 366 if (!lmac) 367 return; 368 369 phydev = lmac->phydev; 370 371 if (!phydev->link && lmac->last_link) 372 link_changed = -1; 373 374 if (phydev->link && 375 (lmac->last_duplex != phydev->duplex || 376 lmac->last_link != phydev->link || 377 lmac->last_speed != phydev->speed)) { 378 link_changed = 1; 379 } 380 381 lmac->last_link = phydev->link; 382 lmac->last_speed = phydev->speed; 383 lmac->last_duplex = phydev->duplex; 384 385 if (!link_changed) 386 return; 387 388 if (link_changed > 0) 389 lmac->link_up = true; 390 else 391 lmac->link_up = false; 392 393 if (lmac->is_sgmii) 394 bgx_sgmii_change_link_state(lmac); 395 else 396 bgx_xaui_check_link(lmac); 397 } 398 399 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx) 400 { 401 struct bgx *bgx; 402 403 bgx = get_bgx(node, bgx_idx); 404 if (!bgx) 405 return 0; 406 407 if (idx > 8) 408 lmac = 0; 409 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8)); 410 } 411 EXPORT_SYMBOL(bgx_get_rx_stats); 412 413 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx) 414 { 415 struct bgx *bgx; 416 417 bgx = get_bgx(node, bgx_idx); 418 if (!bgx) 419 return 0; 420 421 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8)); 422 } 423 EXPORT_SYMBOL(bgx_get_tx_stats); 424 425 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac) 426 { 427 u64 offset; 428 429 while (bgx->lmac[lmac].dmac > 0) { 430 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) + 431 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64)); 432 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0); 433 bgx->lmac[lmac].dmac--; 434 } 435 } 436 437 /* Configure BGX LMAC in internal loopback mode */ 438 void bgx_lmac_internal_loopback(int node, int bgx_idx, 439 int lmac_idx, bool enable) 440 { 441 struct bgx *bgx; 442 struct lmac *lmac; 443 u64 cfg; 444 445 bgx = get_bgx(node, bgx_idx); 446 if (!bgx) 447 return; 448 449 lmac = &bgx->lmac[lmac_idx]; 450 if (lmac->is_sgmii) { 451 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL); 452 if (enable) 453 cfg |= PCS_MRX_CTL_LOOPBACK1; 454 else 455 cfg &= ~PCS_MRX_CTL_LOOPBACK1; 456 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg); 457 } else { 458 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1); 459 if (enable) 460 cfg |= SPU_CTL_LOOPBACK; 461 else 462 cfg &= ~SPU_CTL_LOOPBACK; 463 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg); 464 } 465 } 466 EXPORT_SYMBOL(bgx_lmac_internal_loopback); 467 468 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac) 469 { 470 int lmacid = lmac->lmacid; 471 u64 cfg; 472 473 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30); 474 /* max packet size */ 475 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE); 476 477 /* Disable frame alignment if using preamble */ 478 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 479 if (cfg & 1) 480 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0); 481 482 /* Enable lmac */ 483 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 484 485 /* PCS reset */ 486 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET); 487 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, 488 PCS_MRX_CTL_RESET, true)) { 489 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n"); 490 return -1; 491 } 492 493 /* power down, reset autoneg, autoneg enable */ 494 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL); 495 cfg &= ~PCS_MRX_CTL_PWR_DN; 496 cfg |= PCS_MRX_CTL_RST_AN; 497 if (lmac->phydev) { 498 cfg |= PCS_MRX_CTL_AN_EN; 499 } else { 500 /* In scenarios where PHY driver is not present or it's a 501 * non-standard PHY, FW sets AN_EN to inform Linux driver 502 * to do auto-neg and link polling or not. 503 */ 504 if (cfg & PCS_MRX_CTL_AN_EN) 505 lmac->autoneg = true; 506 } 507 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg); 508 509 if (lmac->lmac_type == BGX_MODE_QSGMII) { 510 /* Disable disparity check for QSGMII */ 511 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL); 512 cfg &= ~PCS_MISC_CTL_DISP_EN; 513 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg); 514 return 0; 515 } 516 517 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) { 518 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS, 519 PCS_MRX_STATUS_AN_CPT, false)) { 520 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n"); 521 return -1; 522 } 523 } 524 525 return 0; 526 } 527 528 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac) 529 { 530 u64 cfg; 531 int lmacid = lmac->lmacid; 532 533 /* Reset SPU */ 534 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET); 535 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 536 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 537 return -1; 538 } 539 540 /* Disable LMAC */ 541 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 542 cfg &= ~CMR_EN; 543 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 544 545 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); 546 /* Set interleaved running disparity for RXAUI */ 547 if (lmac->lmac_type == BGX_MODE_RXAUI) 548 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, 549 SPU_MISC_CTL_INTLV_RDISP); 550 551 /* Clear receive packet disable */ 552 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL); 553 cfg &= ~SPU_MISC_CTL_RX_DIS; 554 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg); 555 556 /* clear all interrupts */ 557 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT); 558 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg); 559 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT); 560 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg); 561 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 562 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 563 564 if (lmac->use_training) { 565 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00); 566 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00); 567 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00); 568 /* training enable */ 569 bgx_reg_modify(bgx, lmacid, 570 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN); 571 } 572 573 /* Append FCS to each packet */ 574 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D); 575 576 /* Disable forward error correction */ 577 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL); 578 cfg &= ~SPU_FEC_CTL_FEC_EN; 579 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg); 580 581 /* Disable autoneg */ 582 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL); 583 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN); 584 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg); 585 586 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV); 587 if (lmac->lmac_type == BGX_MODE_10G_KR) 588 cfg |= (1 << 23); 589 else if (lmac->lmac_type == BGX_MODE_40G_KR) 590 cfg |= (1 << 24); 591 else 592 cfg &= ~((1 << 23) | (1 << 24)); 593 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12))); 594 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg); 595 596 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL); 597 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN; 598 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg); 599 600 /* Enable lmac */ 601 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 602 603 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1); 604 cfg &= ~SPU_CTL_LOW_POWER; 605 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg); 606 607 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL); 608 cfg &= ~SMU_TX_CTL_UNI_EN; 609 cfg |= SMU_TX_CTL_DIC_EN; 610 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg); 611 612 /* Enable receive and transmission of pause frames */ 613 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) | 614 BCK_EN | DRP_EN | TX_EN | RX_EN)); 615 /* Configure pause time and interval */ 616 bgx_reg_write(bgx, lmacid, 617 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME); 618 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL); 619 cfg &= ~0xFFFFull; 620 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL, 621 cfg | (DEFAULT_PAUSE_TIME - 0x1000)); 622 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01); 623 624 /* take lmac_count into account */ 625 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1)); 626 /* max packet size */ 627 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE); 628 629 return 0; 630 } 631 632 static int bgx_xaui_check_link(struct lmac *lmac) 633 { 634 struct bgx *bgx = lmac->bgx; 635 int lmacid = lmac->lmacid; 636 int lmac_type = lmac->lmac_type; 637 u64 cfg; 638 639 if (lmac->use_training) { 640 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 641 if (!(cfg & (1ull << 13))) { 642 cfg = (1ull << 13) | (1ull << 14); 643 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 644 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL); 645 cfg |= (1ull << 0); 646 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg); 647 return -1; 648 } 649 } 650 651 /* wait for PCS to come out of reset */ 652 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 653 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 654 return -1; 655 } 656 657 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) || 658 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) { 659 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1, 660 SPU_BR_STATUS_BLK_LOCK, false)) { 661 dev_err(&bgx->pdev->dev, 662 "SPU_BR_STATUS_BLK_LOCK not completed\n"); 663 return -1; 664 } 665 } else { 666 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS, 667 SPU_BX_STATUS_RX_ALIGN, false)) { 668 dev_err(&bgx->pdev->dev, 669 "SPU_BX_STATUS_RX_ALIGN not completed\n"); 670 return -1; 671 } 672 } 673 674 /* Clear rcvflt bit (latching high) and read it back */ 675 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) 676 bgx_reg_modify(bgx, lmacid, 677 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT); 678 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { 679 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n"); 680 if (lmac->use_training) { 681 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 682 if (!(cfg & (1ull << 13))) { 683 cfg = (1ull << 13) | (1ull << 14); 684 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 685 cfg = bgx_reg_read(bgx, lmacid, 686 BGX_SPUX_BR_PMD_CRTL); 687 cfg |= (1ull << 0); 688 bgx_reg_write(bgx, lmacid, 689 BGX_SPUX_BR_PMD_CRTL, cfg); 690 return -1; 691 } 692 } 693 return -1; 694 } 695 696 /* Wait for BGX RX to be idle */ 697 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) { 698 dev_err(&bgx->pdev->dev, "SMU RX not idle\n"); 699 return -1; 700 } 701 702 /* Wait for BGX TX to be idle */ 703 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) { 704 dev_err(&bgx->pdev->dev, "SMU TX not idle\n"); 705 return -1; 706 } 707 708 /* Check for MAC RX faults */ 709 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL); 710 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */ 711 cfg &= SMU_RX_CTL_STATUS; 712 if (!cfg) 713 return 0; 714 715 /* Rx local/remote fault seen. 716 * Do lmac reinit to see if condition recovers 717 */ 718 bgx_lmac_xaui_init(bgx, lmac); 719 720 return -1; 721 } 722 723 static void bgx_poll_for_sgmii_link(struct lmac *lmac) 724 { 725 u64 pcs_link, an_result; 726 u8 speed; 727 728 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid, 729 BGX_GMP_PCS_MRX_STATUS); 730 731 /*Link state bit is sticky, read it again*/ 732 if (!(pcs_link & PCS_MRX_STATUS_LINK)) 733 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid, 734 BGX_GMP_PCS_MRX_STATUS); 735 736 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS, 737 PCS_MRX_STATUS_AN_CPT, false)) { 738 lmac->link_up = false; 739 lmac->last_speed = SPEED_UNKNOWN; 740 lmac->last_duplex = DUPLEX_UNKNOWN; 741 goto next_poll; 742 } 743 744 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false; 745 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid, 746 BGX_GMP_PCS_ANX_AN_RESULTS); 747 748 speed = (an_result >> 3) & 0x3; 749 lmac->last_duplex = (an_result >> 1) & 0x1; 750 switch (speed) { 751 case 0: 752 lmac->last_speed = 10; 753 break; 754 case 1: 755 lmac->last_speed = 100; 756 break; 757 case 2: 758 lmac->last_speed = 1000; 759 break; 760 default: 761 lmac->link_up = false; 762 lmac->last_speed = SPEED_UNKNOWN; 763 lmac->last_duplex = DUPLEX_UNKNOWN; 764 break; 765 } 766 767 next_poll: 768 769 if (lmac->last_link != lmac->link_up) { 770 if (lmac->link_up) 771 bgx_sgmii_change_link_state(lmac); 772 lmac->last_link = lmac->link_up; 773 } 774 775 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3); 776 } 777 778 static void bgx_poll_for_link(struct work_struct *work) 779 { 780 struct lmac *lmac; 781 u64 spu_link, smu_link; 782 783 lmac = container_of(work, struct lmac, dwork.work); 784 if (lmac->is_sgmii) { 785 bgx_poll_for_sgmii_link(lmac); 786 return; 787 } 788 789 /* Receive link is latching low. Force it high and verify it */ 790 bgx_reg_modify(lmac->bgx, lmac->lmacid, 791 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); 792 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1, 793 SPU_STATUS1_RCV_LNK, false); 794 795 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1); 796 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL); 797 798 if ((spu_link & SPU_STATUS1_RCV_LNK) && 799 !(smu_link & SMU_RX_CTL_STATUS)) { 800 lmac->link_up = 1; 801 if (lmac->lmac_type == BGX_MODE_XLAUI) 802 lmac->last_speed = 40000; 803 else 804 lmac->last_speed = 10000; 805 lmac->last_duplex = 1; 806 } else { 807 lmac->link_up = 0; 808 lmac->last_speed = SPEED_UNKNOWN; 809 lmac->last_duplex = DUPLEX_UNKNOWN; 810 } 811 812 if (lmac->last_link != lmac->link_up) { 813 if (lmac->link_up) { 814 if (bgx_xaui_check_link(lmac)) { 815 /* Errors, clear link_up state */ 816 lmac->link_up = 0; 817 lmac->last_speed = SPEED_UNKNOWN; 818 lmac->last_duplex = DUPLEX_UNKNOWN; 819 } 820 } 821 lmac->last_link = lmac->link_up; 822 } 823 824 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2); 825 } 826 827 static int phy_interface_mode(u8 lmac_type) 828 { 829 if (lmac_type == BGX_MODE_QSGMII) 830 return PHY_INTERFACE_MODE_QSGMII; 831 if (lmac_type == BGX_MODE_RGMII) 832 return PHY_INTERFACE_MODE_RGMII; 833 834 return PHY_INTERFACE_MODE_SGMII; 835 } 836 837 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid) 838 { 839 struct lmac *lmac; 840 u64 cfg; 841 842 lmac = &bgx->lmac[lmacid]; 843 lmac->bgx = bgx; 844 845 if ((lmac->lmac_type == BGX_MODE_SGMII) || 846 (lmac->lmac_type == BGX_MODE_QSGMII) || 847 (lmac->lmac_type == BGX_MODE_RGMII)) { 848 lmac->is_sgmii = 1; 849 if (bgx_lmac_sgmii_init(bgx, lmac)) 850 return -1; 851 } else { 852 lmac->is_sgmii = 0; 853 if (bgx_lmac_xaui_init(bgx, lmac)) 854 return -1; 855 } 856 857 if (lmac->is_sgmii) { 858 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 859 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 860 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg); 861 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1); 862 } else { 863 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND); 864 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 865 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg); 866 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4); 867 } 868 869 /* Enable lmac */ 870 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 871 872 /* Restore default cfg, incase low level firmware changed it */ 873 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03); 874 875 if ((lmac->lmac_type != BGX_MODE_XFI) && 876 (lmac->lmac_type != BGX_MODE_XLAUI) && 877 (lmac->lmac_type != BGX_MODE_40G_KR) && 878 (lmac->lmac_type != BGX_MODE_10G_KR)) { 879 if (!lmac->phydev) { 880 if (lmac->autoneg) { 881 bgx_reg_write(bgx, lmacid, 882 BGX_GMP_PCS_LINKX_TIMER, 883 PCS_LINKX_TIMER_COUNT); 884 goto poll; 885 } else { 886 /* Default to below link speed and duplex */ 887 lmac->link_up = true; 888 lmac->last_speed = 1000; 889 lmac->last_duplex = 1; 890 bgx_sgmii_change_link_state(lmac); 891 return 0; 892 } 893 } 894 lmac->phydev->dev_flags = 0; 895 896 if (phy_connect_direct(&lmac->netdev, lmac->phydev, 897 bgx_lmac_handler, 898 phy_interface_mode(lmac->lmac_type))) 899 return -ENODEV; 900 901 phy_start_aneg(lmac->phydev); 902 return 0; 903 } 904 905 poll: 906 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND | 907 WQ_MEM_RECLAIM, 1); 908 if (!lmac->check_link) 909 return -ENOMEM; 910 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link); 911 queue_delayed_work(lmac->check_link, &lmac->dwork, 0); 912 913 return 0; 914 } 915 916 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid) 917 { 918 struct lmac *lmac; 919 u64 cfg; 920 921 lmac = &bgx->lmac[lmacid]; 922 if (lmac->check_link) { 923 /* Destroy work queue */ 924 cancel_delayed_work_sync(&lmac->dwork); 925 destroy_workqueue(lmac->check_link); 926 } 927 928 /* Disable packet reception */ 929 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 930 cfg &= ~CMR_PKT_RX_EN; 931 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 932 933 /* Give chance for Rx/Tx FIFO to get drained */ 934 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true); 935 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true); 936 937 /* Disable packet transmission */ 938 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 939 cfg &= ~CMR_PKT_TX_EN; 940 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 941 942 /* Disable serdes lanes */ 943 if (!lmac->is_sgmii) 944 bgx_reg_modify(bgx, lmacid, 945 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); 946 else 947 bgx_reg_modify(bgx, lmacid, 948 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN); 949 950 /* Disable LMAC */ 951 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 952 cfg &= ~CMR_EN; 953 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 954 955 bgx_flush_dmac_addrs(bgx, lmacid); 956 957 if ((lmac->lmac_type != BGX_MODE_XFI) && 958 (lmac->lmac_type != BGX_MODE_XLAUI) && 959 (lmac->lmac_type != BGX_MODE_40G_KR) && 960 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev) 961 phy_disconnect(lmac->phydev); 962 963 lmac->phydev = NULL; 964 } 965 966 static void bgx_init_hw(struct bgx *bgx) 967 { 968 int i; 969 struct lmac *lmac; 970 971 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP); 972 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS)) 973 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id); 974 975 /* Set lmac type and lane2serdes mapping */ 976 for (i = 0; i < bgx->lmac_count; i++) { 977 lmac = &bgx->lmac[i]; 978 bgx_reg_write(bgx, i, BGX_CMRX_CFG, 979 (lmac->lmac_type << 8) | lmac->lane_to_sds); 980 bgx->lmac[i].lmacid_bd = lmac_count; 981 lmac_count++; 982 } 983 984 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count); 985 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count); 986 987 /* Set the backpressure AND mask */ 988 for (i = 0; i < bgx->lmac_count; i++) 989 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND, 990 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) << 991 (i * MAX_BGX_CHANS_PER_LMAC)); 992 993 /* Disable all MAC filtering */ 994 for (i = 0; i < RX_DMAC_COUNT; i++) 995 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00); 996 997 /* Disable MAC steering (NCSI traffic) */ 998 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++) 999 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00); 1000 } 1001 1002 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac) 1003 { 1004 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF); 1005 } 1006 1007 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid) 1008 { 1009 struct device *dev = &bgx->pdev->dev; 1010 struct lmac *lmac; 1011 char str[20]; 1012 1013 if (!bgx->is_dlm && lmacid) 1014 return; 1015 1016 lmac = &bgx->lmac[lmacid]; 1017 if (!bgx->is_dlm) 1018 sprintf(str, "BGX%d QLM mode", bgx->bgx_id); 1019 else 1020 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid); 1021 1022 switch (lmac->lmac_type) { 1023 case BGX_MODE_SGMII: 1024 dev_info(dev, "%s: SGMII\n", (char *)str); 1025 break; 1026 case BGX_MODE_XAUI: 1027 dev_info(dev, "%s: XAUI\n", (char *)str); 1028 break; 1029 case BGX_MODE_RXAUI: 1030 dev_info(dev, "%s: RXAUI\n", (char *)str); 1031 break; 1032 case BGX_MODE_XFI: 1033 if (!lmac->use_training) 1034 dev_info(dev, "%s: XFI\n", (char *)str); 1035 else 1036 dev_info(dev, "%s: 10G_KR\n", (char *)str); 1037 break; 1038 case BGX_MODE_XLAUI: 1039 if (!lmac->use_training) 1040 dev_info(dev, "%s: XLAUI\n", (char *)str); 1041 else 1042 dev_info(dev, "%s: 40G_KR4\n", (char *)str); 1043 break; 1044 case BGX_MODE_QSGMII: 1045 dev_info(dev, "%s: QSGMII\n", (char *)str); 1046 break; 1047 case BGX_MODE_RGMII: 1048 dev_info(dev, "%s: RGMII\n", (char *)str); 1049 break; 1050 case BGX_MODE_INVALID: 1051 /* Nothing to do */ 1052 break; 1053 } 1054 } 1055 1056 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac) 1057 { 1058 switch (lmac->lmac_type) { 1059 case BGX_MODE_SGMII: 1060 case BGX_MODE_XFI: 1061 lmac->lane_to_sds = lmac->lmacid; 1062 break; 1063 case BGX_MODE_XAUI: 1064 case BGX_MODE_XLAUI: 1065 case BGX_MODE_RGMII: 1066 lmac->lane_to_sds = 0xE4; 1067 break; 1068 case BGX_MODE_RXAUI: 1069 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4; 1070 break; 1071 case BGX_MODE_QSGMII: 1072 /* There is no way to determine if DLM0/2 is QSGMII or 1073 * DLM1/3 is configured to QSGMII as bootloader will 1074 * configure all LMACs, so take whatever is configured 1075 * by low level firmware. 1076 */ 1077 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac); 1078 break; 1079 default: 1080 lmac->lane_to_sds = 0; 1081 break; 1082 } 1083 } 1084 1085 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid) 1086 { 1087 if ((lmac->lmac_type != BGX_MODE_10G_KR) && 1088 (lmac->lmac_type != BGX_MODE_40G_KR)) { 1089 lmac->use_training = 0; 1090 return; 1091 } 1092 1093 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) & 1094 SPU_PMD_CRTL_TRAIN_EN; 1095 } 1096 1097 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx) 1098 { 1099 struct lmac *lmac; 1100 u64 cmr_cfg; 1101 u8 lmac_type; 1102 u8 lane_to_sds; 1103 1104 lmac = &bgx->lmac[idx]; 1105 1106 if (!bgx->is_dlm || bgx->is_rgx) { 1107 /* Read LMAC0 type to figure out QLM mode 1108 * This is configured by low level firmware 1109 */ 1110 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG); 1111 lmac->lmac_type = (cmr_cfg >> 8) & 0x07; 1112 if (bgx->is_rgx) 1113 lmac->lmac_type = BGX_MODE_RGMII; 1114 lmac_set_training(bgx, lmac, 0); 1115 lmac_set_lane2sds(bgx, lmac); 1116 return; 1117 } 1118 1119 /* For DLMs or SLMs on 80/81/83xx so many lane configurations 1120 * are possible and vary across boards. Also Kernel doesn't have 1121 * any way to identify board type/info and since firmware does, 1122 * just take lmac type and serdes lane config as is. 1123 */ 1124 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG); 1125 lmac_type = (u8)((cmr_cfg >> 8) & 0x07); 1126 lane_to_sds = (u8)(cmr_cfg & 0xFF); 1127 /* Check if config is reset value */ 1128 if ((lmac_type == 0) && (lane_to_sds == 0xE4)) 1129 lmac->lmac_type = BGX_MODE_INVALID; 1130 else 1131 lmac->lmac_type = lmac_type; 1132 lmac->lane_to_sds = lane_to_sds; 1133 lmac_set_training(bgx, lmac, lmac->lmacid); 1134 } 1135 1136 static void bgx_get_qlm_mode(struct bgx *bgx) 1137 { 1138 struct lmac *lmac; 1139 u8 idx; 1140 1141 /* Init all LMAC's type to invalid */ 1142 for (idx = 0; idx < bgx->max_lmac; idx++) { 1143 lmac = &bgx->lmac[idx]; 1144 lmac->lmacid = idx; 1145 lmac->lmac_type = BGX_MODE_INVALID; 1146 lmac->use_training = false; 1147 } 1148 1149 /* It is assumed that low level firmware sets this value */ 1150 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7; 1151 if (bgx->lmac_count > bgx->max_lmac) 1152 bgx->lmac_count = bgx->max_lmac; 1153 1154 for (idx = 0; idx < bgx->lmac_count; idx++) { 1155 bgx_set_lmac_config(bgx, idx); 1156 bgx_print_qlm_mode(bgx, idx); 1157 } 1158 } 1159 1160 #ifdef CONFIG_ACPI 1161 1162 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev, 1163 u8 *dst) 1164 { 1165 u8 mac[ETH_ALEN]; 1166 int ret; 1167 1168 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev), 1169 "mac-address", mac, ETH_ALEN); 1170 if (ret) 1171 goto out; 1172 1173 if (!is_valid_ether_addr(mac)) { 1174 dev_err(dev, "MAC address invalid: %pM\n", mac); 1175 ret = -EINVAL; 1176 goto out; 1177 } 1178 1179 dev_info(dev, "MAC address set to: %pM\n", mac); 1180 1181 memcpy(dst, mac, ETH_ALEN); 1182 out: 1183 return ret; 1184 } 1185 1186 /* Currently only sets the MAC address. */ 1187 static acpi_status bgx_acpi_register_phy(acpi_handle handle, 1188 u32 lvl, void *context, void **rv) 1189 { 1190 struct bgx *bgx = context; 1191 struct device *dev = &bgx->pdev->dev; 1192 struct acpi_device *adev; 1193 1194 if (acpi_bus_get_device(handle, &adev)) 1195 goto out; 1196 1197 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac); 1198 1199 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev); 1200 1201 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx; 1202 bgx->acpi_lmac_idx++; /* move to next LMAC */ 1203 out: 1204 return AE_OK; 1205 } 1206 1207 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl, 1208 void *context, void **ret_val) 1209 { 1210 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; 1211 struct bgx *bgx = context; 1212 char bgx_sel[5]; 1213 1214 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id); 1215 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) { 1216 pr_warn("Invalid link device\n"); 1217 return AE_OK; 1218 } 1219 1220 if (strncmp(string.pointer, bgx_sel, 4)) 1221 return AE_OK; 1222 1223 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, 1224 bgx_acpi_register_phy, NULL, bgx, NULL); 1225 1226 kfree(string.pointer); 1227 return AE_CTRL_TERMINATE; 1228 } 1229 1230 static int bgx_init_acpi_phy(struct bgx *bgx) 1231 { 1232 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL); 1233 return 0; 1234 } 1235 1236 #else 1237 1238 static int bgx_init_acpi_phy(struct bgx *bgx) 1239 { 1240 return -ENODEV; 1241 } 1242 1243 #endif /* CONFIG_ACPI */ 1244 1245 #if IS_ENABLED(CONFIG_OF_MDIO) 1246 1247 static int bgx_init_of_phy(struct bgx *bgx) 1248 { 1249 struct fwnode_handle *fwn; 1250 struct device_node *node = NULL; 1251 u8 lmac = 0; 1252 1253 device_for_each_child_node(&bgx->pdev->dev, fwn) { 1254 struct phy_device *pd; 1255 struct device_node *phy_np; 1256 const char *mac; 1257 1258 /* Should always be an OF node. But if it is not, we 1259 * cannot handle it, so exit the loop. 1260 */ 1261 node = to_of_node(fwn); 1262 if (!node) 1263 break; 1264 1265 mac = of_get_mac_address(node); 1266 if (mac) 1267 ether_addr_copy(bgx->lmac[lmac].mac, mac); 1268 1269 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev); 1270 bgx->lmac[lmac].lmacid = lmac; 1271 1272 phy_np = of_parse_phandle(node, "phy-handle", 0); 1273 /* If there is no phy or defective firmware presents 1274 * this cortina phy, for which there is no driver 1275 * support, ignore it. 1276 */ 1277 if (phy_np && 1278 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) { 1279 /* Wait until the phy drivers are available */ 1280 pd = of_phy_find_device(phy_np); 1281 if (!pd) 1282 goto defer; 1283 bgx->lmac[lmac].phydev = pd; 1284 } 1285 1286 lmac++; 1287 if (lmac == bgx->max_lmac) { 1288 of_node_put(node); 1289 break; 1290 } 1291 } 1292 return 0; 1293 1294 defer: 1295 /* We are bailing out, try not to leak device reference counts 1296 * for phy devices we may have already found. 1297 */ 1298 while (lmac) { 1299 if (bgx->lmac[lmac].phydev) { 1300 put_device(&bgx->lmac[lmac].phydev->mdio.dev); 1301 bgx->lmac[lmac].phydev = NULL; 1302 } 1303 lmac--; 1304 } 1305 of_node_put(node); 1306 return -EPROBE_DEFER; 1307 } 1308 1309 #else 1310 1311 static int bgx_init_of_phy(struct bgx *bgx) 1312 { 1313 return -ENODEV; 1314 } 1315 1316 #endif /* CONFIG_OF_MDIO */ 1317 1318 static int bgx_init_phy(struct bgx *bgx) 1319 { 1320 if (!acpi_disabled) 1321 return bgx_init_acpi_phy(bgx); 1322 1323 return bgx_init_of_phy(bgx); 1324 } 1325 1326 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1327 { 1328 int err; 1329 struct device *dev = &pdev->dev; 1330 struct bgx *bgx = NULL; 1331 u8 lmac; 1332 u16 sdevid; 1333 1334 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL); 1335 if (!bgx) 1336 return -ENOMEM; 1337 bgx->pdev = pdev; 1338 1339 pci_set_drvdata(pdev, bgx); 1340 1341 err = pci_enable_device(pdev); 1342 if (err) { 1343 dev_err(dev, "Failed to enable PCI device\n"); 1344 pci_set_drvdata(pdev, NULL); 1345 return err; 1346 } 1347 1348 err = pci_request_regions(pdev, DRV_NAME); 1349 if (err) { 1350 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1351 goto err_disable_device; 1352 } 1353 1354 /* MAP configuration registers */ 1355 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1356 if (!bgx->reg_base) { 1357 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n"); 1358 err = -ENOMEM; 1359 goto err_release_regions; 1360 } 1361 1362 set_max_bgx_per_node(pdev); 1363 1364 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid); 1365 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) { 1366 bgx->bgx_id = (pci_resource_start(pdev, 1367 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK; 1368 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node; 1369 bgx->max_lmac = MAX_LMAC_PER_BGX; 1370 bgx_vnic[bgx->bgx_id] = bgx; 1371 } else { 1372 bgx->is_rgx = true; 1373 bgx->max_lmac = 1; 1374 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1; 1375 bgx_vnic[bgx->bgx_id] = bgx; 1376 xcv_init_hw(); 1377 } 1378 1379 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one 1380 * BGX i.e BGX2 can be split across 2 DLMs. 1381 */ 1382 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid); 1383 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) || 1384 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2))) 1385 bgx->is_dlm = true; 1386 1387 bgx_get_qlm_mode(bgx); 1388 1389 err = bgx_init_phy(bgx); 1390 if (err) 1391 goto err_enable; 1392 1393 bgx_init_hw(bgx); 1394 1395 /* Enable all LMACs */ 1396 for (lmac = 0; lmac < bgx->lmac_count; lmac++) { 1397 err = bgx_lmac_enable(bgx, lmac); 1398 if (err) { 1399 dev_err(dev, "BGX%d failed to enable lmac%d\n", 1400 bgx->bgx_id, lmac); 1401 while (lmac) 1402 bgx_lmac_disable(bgx, --lmac); 1403 goto err_enable; 1404 } 1405 } 1406 1407 return 0; 1408 1409 err_enable: 1410 bgx_vnic[bgx->bgx_id] = NULL; 1411 err_release_regions: 1412 pci_release_regions(pdev); 1413 err_disable_device: 1414 pci_disable_device(pdev); 1415 pci_set_drvdata(pdev, NULL); 1416 return err; 1417 } 1418 1419 static void bgx_remove(struct pci_dev *pdev) 1420 { 1421 struct bgx *bgx = pci_get_drvdata(pdev); 1422 u8 lmac; 1423 1424 /* Disable all LMACs */ 1425 for (lmac = 0; lmac < bgx->lmac_count; lmac++) 1426 bgx_lmac_disable(bgx, lmac); 1427 1428 bgx_vnic[bgx->bgx_id] = NULL; 1429 pci_release_regions(pdev); 1430 pci_disable_device(pdev); 1431 pci_set_drvdata(pdev, NULL); 1432 } 1433 1434 static struct pci_driver bgx_driver = { 1435 .name = DRV_NAME, 1436 .id_table = bgx_id_table, 1437 .probe = bgx_probe, 1438 .remove = bgx_remove, 1439 }; 1440 1441 static int __init bgx_init_module(void) 1442 { 1443 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1444 1445 return pci_register_driver(&bgx_driver); 1446 } 1447 1448 static void __exit bgx_cleanup_module(void) 1449 { 1450 pci_unregister_driver(&bgx_driver); 1451 } 1452 1453 module_init(bgx_init_module); 1454 module_exit(bgx_cleanup_module); 1455