14863dea3SSunil Goutham /* 24863dea3SSunil Goutham * Copyright (C) 2015 Cavium, Inc. 34863dea3SSunil Goutham * 44863dea3SSunil Goutham * This program is free software; you can redistribute it and/or modify it 54863dea3SSunil Goutham * under the terms of version 2 of the GNU General Public License 64863dea3SSunil Goutham * as published by the Free Software Foundation. 74863dea3SSunil Goutham */ 84863dea3SSunil Goutham 94863dea3SSunil Goutham #include <linux/module.h> 104863dea3SSunil Goutham #include <linux/interrupt.h> 114863dea3SSunil Goutham #include <linux/pci.h> 124863dea3SSunil Goutham #include <linux/netdevice.h> 134863dea3SSunil Goutham #include <linux/etherdevice.h> 144863dea3SSunil Goutham #include <linux/phy.h> 154863dea3SSunil Goutham #include <linux/of.h> 164863dea3SSunil Goutham #include <linux/of_mdio.h> 174863dea3SSunil Goutham #include <linux/of_net.h> 184863dea3SSunil Goutham 194863dea3SSunil Goutham #include "nic_reg.h" 204863dea3SSunil Goutham #include "nic.h" 214863dea3SSunil Goutham #include "thunder_bgx.h" 224863dea3SSunil Goutham 234863dea3SSunil Goutham #define DRV_NAME "thunder-BGX" 244863dea3SSunil Goutham #define DRV_VERSION "1.0" 254863dea3SSunil Goutham 264863dea3SSunil Goutham struct lmac { 274863dea3SSunil Goutham struct bgx *bgx; 284863dea3SSunil Goutham int dmac; 294863dea3SSunil Goutham unsigned char mac[ETH_ALEN]; 304863dea3SSunil Goutham bool link_up; 314863dea3SSunil Goutham int lmacid; /* ID within BGX */ 324863dea3SSunil Goutham int lmacid_bd; /* ID on board */ 334863dea3SSunil Goutham struct net_device netdev; 344863dea3SSunil Goutham struct phy_device *phydev; 354863dea3SSunil Goutham unsigned int last_duplex; 364863dea3SSunil Goutham unsigned int last_link; 374863dea3SSunil Goutham unsigned int last_speed; 384863dea3SSunil Goutham bool is_sgmii; 394863dea3SSunil Goutham struct delayed_work dwork; 404863dea3SSunil Goutham struct workqueue_struct *check_link; 414863dea3SSunil Goutham } lmac; 424863dea3SSunil Goutham 434863dea3SSunil Goutham struct bgx { 444863dea3SSunil Goutham u8 bgx_id; 454863dea3SSunil Goutham u8 qlm_mode; 464863dea3SSunil Goutham struct lmac lmac[MAX_LMAC_PER_BGX]; 474863dea3SSunil Goutham int lmac_count; 484863dea3SSunil Goutham int lmac_type; 494863dea3SSunil Goutham int lane_to_sds; 504863dea3SSunil Goutham int use_training; 514863dea3SSunil Goutham void __iomem *reg_base; 524863dea3SSunil Goutham struct pci_dev *pdev; 534863dea3SSunil Goutham } bgx; 544863dea3SSunil Goutham 554863dea3SSunil Goutham struct bgx *bgx_vnic[MAX_BGX_THUNDER]; 564863dea3SSunil Goutham static int lmac_count; /* Total no of LMACs in system */ 574863dea3SSunil Goutham 584863dea3SSunil Goutham static int bgx_xaui_check_link(struct lmac *lmac); 594863dea3SSunil Goutham 604863dea3SSunil Goutham /* Supported devices */ 614863dea3SSunil Goutham static const struct pci_device_id bgx_id_table[] = { 624863dea3SSunil Goutham { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) }, 634863dea3SSunil Goutham { 0, } /* end of table */ 644863dea3SSunil Goutham }; 654863dea3SSunil Goutham 664863dea3SSunil Goutham MODULE_AUTHOR("Cavium Inc"); 674863dea3SSunil Goutham MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver"); 684863dea3SSunil Goutham MODULE_LICENSE("GPL v2"); 694863dea3SSunil Goutham MODULE_VERSION(DRV_VERSION); 704863dea3SSunil Goutham MODULE_DEVICE_TABLE(pci, bgx_id_table); 714863dea3SSunil Goutham 724863dea3SSunil Goutham /* The Cavium ThunderX network controller can *only* be found in SoCs 734863dea3SSunil Goutham * containing the ThunderX ARM64 CPU implementation. All accesses to the device 744863dea3SSunil Goutham * registers on this platform are implicitly strongly ordered with respect 754863dea3SSunil Goutham * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 764863dea3SSunil Goutham * with no memory barriers in this driver. The readq()/writeq() functions add 774863dea3SSunil Goutham * explicit ordering operation which in this case are redundant, and only 784863dea3SSunil Goutham * add overhead. 794863dea3SSunil Goutham */ 804863dea3SSunil Goutham 814863dea3SSunil Goutham /* Register read/write APIs */ 824863dea3SSunil Goutham static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset) 834863dea3SSunil Goutham { 844863dea3SSunil Goutham void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 854863dea3SSunil Goutham 864863dea3SSunil Goutham return readq_relaxed(addr); 874863dea3SSunil Goutham } 884863dea3SSunil Goutham 894863dea3SSunil Goutham static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 904863dea3SSunil Goutham { 914863dea3SSunil Goutham void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 924863dea3SSunil Goutham 934863dea3SSunil Goutham writeq_relaxed(val, addr); 944863dea3SSunil Goutham } 954863dea3SSunil Goutham 964863dea3SSunil Goutham static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val) 974863dea3SSunil Goutham { 984863dea3SSunil Goutham void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; 994863dea3SSunil Goutham 1004863dea3SSunil Goutham writeq_relaxed(val | readq_relaxed(addr), addr); 1014863dea3SSunil Goutham } 1024863dea3SSunil Goutham 1034863dea3SSunil Goutham static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero) 1044863dea3SSunil Goutham { 1054863dea3SSunil Goutham int timeout = 100; 1064863dea3SSunil Goutham u64 reg_val; 1074863dea3SSunil Goutham 1084863dea3SSunil Goutham while (timeout) { 1094863dea3SSunil Goutham reg_val = bgx_reg_read(bgx, lmac, reg); 1104863dea3SSunil Goutham if (zero && !(reg_val & mask)) 1114863dea3SSunil Goutham return 0; 1124863dea3SSunil Goutham if (!zero && (reg_val & mask)) 1134863dea3SSunil Goutham return 0; 1144863dea3SSunil Goutham usleep_range(1000, 2000); 1154863dea3SSunil Goutham timeout--; 1164863dea3SSunil Goutham } 1174863dea3SSunil Goutham return 1; 1184863dea3SSunil Goutham } 1194863dea3SSunil Goutham 1204863dea3SSunil Goutham /* Return number of BGX present in HW */ 1214863dea3SSunil Goutham unsigned bgx_get_map(int node) 1224863dea3SSunil Goutham { 1234863dea3SSunil Goutham int i; 1244863dea3SSunil Goutham unsigned map = 0; 1254863dea3SSunil Goutham 1264863dea3SSunil Goutham for (i = 0; i < MAX_BGX_PER_CN88XX; i++) { 1274863dea3SSunil Goutham if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i]) 1284863dea3SSunil Goutham map |= (1 << i); 1294863dea3SSunil Goutham } 1304863dea3SSunil Goutham 1314863dea3SSunil Goutham return map; 1324863dea3SSunil Goutham } 1334863dea3SSunil Goutham EXPORT_SYMBOL(bgx_get_map); 1344863dea3SSunil Goutham 1354863dea3SSunil Goutham /* Return number of LMAC configured for this BGX */ 1364863dea3SSunil Goutham int bgx_get_lmac_count(int node, int bgx_idx) 1374863dea3SSunil Goutham { 1384863dea3SSunil Goutham struct bgx *bgx; 1394863dea3SSunil Goutham 1404863dea3SSunil Goutham bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 1414863dea3SSunil Goutham if (bgx) 1424863dea3SSunil Goutham return bgx->lmac_count; 1434863dea3SSunil Goutham 1444863dea3SSunil Goutham return 0; 1454863dea3SSunil Goutham } 1464863dea3SSunil Goutham EXPORT_SYMBOL(bgx_get_lmac_count); 1474863dea3SSunil Goutham 1484863dea3SSunil Goutham /* Returns the current link status of LMAC */ 1494863dea3SSunil Goutham void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status) 1504863dea3SSunil Goutham { 1514863dea3SSunil Goutham struct bgx_link_status *link = (struct bgx_link_status *)status; 1524863dea3SSunil Goutham struct bgx *bgx; 1534863dea3SSunil Goutham struct lmac *lmac; 1544863dea3SSunil Goutham 1554863dea3SSunil Goutham bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 1564863dea3SSunil Goutham if (!bgx) 1574863dea3SSunil Goutham return; 1584863dea3SSunil Goutham 1594863dea3SSunil Goutham lmac = &bgx->lmac[lmacid]; 1604863dea3SSunil Goutham link->link_up = lmac->link_up; 1614863dea3SSunil Goutham link->duplex = lmac->last_duplex; 1624863dea3SSunil Goutham link->speed = lmac->last_speed; 1634863dea3SSunil Goutham } 1644863dea3SSunil Goutham EXPORT_SYMBOL(bgx_get_lmac_link_state); 1654863dea3SSunil Goutham 1664863dea3SSunil Goutham const char *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid) 1674863dea3SSunil Goutham { 1684863dea3SSunil Goutham struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 1694863dea3SSunil Goutham 1704863dea3SSunil Goutham if (bgx) 1714863dea3SSunil Goutham return bgx->lmac[lmacid].mac; 1724863dea3SSunil Goutham 1734863dea3SSunil Goutham return NULL; 1744863dea3SSunil Goutham } 1754863dea3SSunil Goutham EXPORT_SYMBOL(bgx_get_lmac_mac); 1764863dea3SSunil Goutham 1774863dea3SSunil Goutham void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const char *mac) 1784863dea3SSunil Goutham { 1794863dea3SSunil Goutham struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 1804863dea3SSunil Goutham 1814863dea3SSunil Goutham if (!bgx) 1824863dea3SSunil Goutham return; 1834863dea3SSunil Goutham 1844863dea3SSunil Goutham ether_addr_copy(bgx->lmac[lmacid].mac, mac); 1854863dea3SSunil Goutham } 1864863dea3SSunil Goutham EXPORT_SYMBOL(bgx_set_lmac_mac); 1874863dea3SSunil Goutham 1884863dea3SSunil Goutham static void bgx_sgmii_change_link_state(struct lmac *lmac) 1894863dea3SSunil Goutham { 1904863dea3SSunil Goutham struct bgx *bgx = lmac->bgx; 1914863dea3SSunil Goutham u64 cmr_cfg; 1924863dea3SSunil Goutham u64 port_cfg = 0; 1934863dea3SSunil Goutham u64 misc_ctl = 0; 1944863dea3SSunil Goutham 1954863dea3SSunil Goutham cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG); 1964863dea3SSunil Goutham cmr_cfg &= ~CMR_EN; 1974863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 1984863dea3SSunil Goutham 1994863dea3SSunil Goutham port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 2004863dea3SSunil Goutham misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL); 2014863dea3SSunil Goutham 2024863dea3SSunil Goutham if (lmac->link_up) { 2034863dea3SSunil Goutham misc_ctl &= ~PCS_MISC_CTL_GMX_ENO; 2044863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_DUPLEX; 2054863dea3SSunil Goutham port_cfg |= (lmac->last_duplex << 2); 2064863dea3SSunil Goutham } else { 2074863dea3SSunil Goutham misc_ctl |= PCS_MISC_CTL_GMX_ENO; 2084863dea3SSunil Goutham } 2094863dea3SSunil Goutham 2104863dea3SSunil Goutham switch (lmac->last_speed) { 2114863dea3SSunil Goutham case 10: 2124863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 2134863dea3SSunil Goutham port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */ 2144863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 2154863dea3SSunil Goutham misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 2164863dea3SSunil Goutham misc_ctl |= 50; /* samp_pt */ 2174863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 2184863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 2194863dea3SSunil Goutham break; 2204863dea3SSunil Goutham case 100: 2214863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */ 2224863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 2234863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */ 2244863dea3SSunil Goutham misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 2254863dea3SSunil Goutham misc_ctl |= 5; /* samp_pt */ 2264863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64); 2274863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0); 2284863dea3SSunil Goutham break; 2294863dea3SSunil Goutham case 1000: 2304863dea3SSunil Goutham port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */ 2314863dea3SSunil Goutham port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */ 2324863dea3SSunil Goutham port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */ 2334863dea3SSunil Goutham misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK; 2344863dea3SSunil Goutham misc_ctl |= 1; /* samp_pt */ 2354863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512); 2364863dea3SSunil Goutham if (lmac->last_duplex) 2374863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, 2384863dea3SSunil Goutham BGX_GMP_GMI_TXX_BURST, 0); 2394863dea3SSunil Goutham else 2404863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, 2414863dea3SSunil Goutham BGX_GMP_GMI_TXX_BURST, 8192); 2424863dea3SSunil Goutham break; 2434863dea3SSunil Goutham default: 2444863dea3SSunil Goutham break; 2454863dea3SSunil Goutham } 2464863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl); 2474863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg); 2484863dea3SSunil Goutham 2494863dea3SSunil Goutham port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG); 2504863dea3SSunil Goutham 2514863dea3SSunil Goutham /* renable lmac */ 2524863dea3SSunil Goutham cmr_cfg |= CMR_EN; 2534863dea3SSunil Goutham bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg); 2544863dea3SSunil Goutham } 2554863dea3SSunil Goutham 2564863dea3SSunil Goutham void bgx_lmac_handler(struct net_device *netdev) 2574863dea3SSunil Goutham { 2584863dea3SSunil Goutham struct lmac *lmac = container_of(netdev, struct lmac, netdev); 2594863dea3SSunil Goutham struct phy_device *phydev = lmac->phydev; 2604863dea3SSunil Goutham int link_changed = 0; 2614863dea3SSunil Goutham 2624863dea3SSunil Goutham if (!lmac) 2634863dea3SSunil Goutham return; 2644863dea3SSunil Goutham 2654863dea3SSunil Goutham if (!phydev->link && lmac->last_link) 2664863dea3SSunil Goutham link_changed = -1; 2674863dea3SSunil Goutham 2684863dea3SSunil Goutham if (phydev->link && 2694863dea3SSunil Goutham (lmac->last_duplex != phydev->duplex || 2704863dea3SSunil Goutham lmac->last_link != phydev->link || 2714863dea3SSunil Goutham lmac->last_speed != phydev->speed)) { 2724863dea3SSunil Goutham link_changed = 1; 2734863dea3SSunil Goutham } 2744863dea3SSunil Goutham 2754863dea3SSunil Goutham lmac->last_link = phydev->link; 2764863dea3SSunil Goutham lmac->last_speed = phydev->speed; 2774863dea3SSunil Goutham lmac->last_duplex = phydev->duplex; 2784863dea3SSunil Goutham 2794863dea3SSunil Goutham if (!link_changed) 2804863dea3SSunil Goutham return; 2814863dea3SSunil Goutham 2824863dea3SSunil Goutham if (link_changed > 0) 2834863dea3SSunil Goutham lmac->link_up = true; 2844863dea3SSunil Goutham else 2854863dea3SSunil Goutham lmac->link_up = false; 2864863dea3SSunil Goutham 2874863dea3SSunil Goutham if (lmac->is_sgmii) 2884863dea3SSunil Goutham bgx_sgmii_change_link_state(lmac); 2894863dea3SSunil Goutham else 2904863dea3SSunil Goutham bgx_xaui_check_link(lmac); 2914863dea3SSunil Goutham } 2924863dea3SSunil Goutham 2934863dea3SSunil Goutham u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx) 2944863dea3SSunil Goutham { 2954863dea3SSunil Goutham struct bgx *bgx; 2964863dea3SSunil Goutham 2974863dea3SSunil Goutham bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 2984863dea3SSunil Goutham if (!bgx) 2994863dea3SSunil Goutham return 0; 3004863dea3SSunil Goutham 3014863dea3SSunil Goutham if (idx > 8) 3024863dea3SSunil Goutham lmac = 0; 3034863dea3SSunil Goutham return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8)); 3044863dea3SSunil Goutham } 3054863dea3SSunil Goutham EXPORT_SYMBOL(bgx_get_rx_stats); 3064863dea3SSunil Goutham 3074863dea3SSunil Goutham u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx) 3084863dea3SSunil Goutham { 3094863dea3SSunil Goutham struct bgx *bgx; 3104863dea3SSunil Goutham 3114863dea3SSunil Goutham bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx]; 3124863dea3SSunil Goutham if (!bgx) 3134863dea3SSunil Goutham return 0; 3144863dea3SSunil Goutham 3154863dea3SSunil Goutham return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8)); 3164863dea3SSunil Goutham } 3174863dea3SSunil Goutham EXPORT_SYMBOL(bgx_get_tx_stats); 3184863dea3SSunil Goutham 3194863dea3SSunil Goutham static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac) 3204863dea3SSunil Goutham { 3214863dea3SSunil Goutham u64 offset; 3224863dea3SSunil Goutham 3234863dea3SSunil Goutham while (bgx->lmac[lmac].dmac > 0) { 3244863dea3SSunil Goutham offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) + 3254863dea3SSunil Goutham (lmac * MAX_DMAC_PER_LMAC * sizeof(u64)); 3264863dea3SSunil Goutham bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0); 3274863dea3SSunil Goutham bgx->lmac[lmac].dmac--; 3284863dea3SSunil Goutham } 3294863dea3SSunil Goutham } 3304863dea3SSunil Goutham 3314863dea3SSunil Goutham static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid) 3324863dea3SSunil Goutham { 3334863dea3SSunil Goutham u64 cfg; 3344863dea3SSunil Goutham 3354863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30); 3364863dea3SSunil Goutham /* max packet size */ 3374863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE); 3384863dea3SSunil Goutham 3394863dea3SSunil Goutham /* Disable frame alignment if using preamble */ 3404863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 3414863dea3SSunil Goutham if (cfg & 1) 3424863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0); 3434863dea3SSunil Goutham 3444863dea3SSunil Goutham /* Enable lmac */ 3454863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 3464863dea3SSunil Goutham 3474863dea3SSunil Goutham /* PCS reset */ 3484863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET); 3494863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, 3504863dea3SSunil Goutham PCS_MRX_CTL_RESET, true)) { 3514863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n"); 3524863dea3SSunil Goutham return -1; 3534863dea3SSunil Goutham } 3544863dea3SSunil Goutham 3554863dea3SSunil Goutham /* power down, reset autoneg, autoneg enable */ 3564863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL); 3574863dea3SSunil Goutham cfg &= ~PCS_MRX_CTL_PWR_DN; 3584863dea3SSunil Goutham cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN); 3594863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg); 3604863dea3SSunil Goutham 3614863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS, 3624863dea3SSunil Goutham PCS_MRX_STATUS_AN_CPT, false)) { 3634863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n"); 3644863dea3SSunil Goutham return -1; 3654863dea3SSunil Goutham } 3664863dea3SSunil Goutham 3674863dea3SSunil Goutham return 0; 3684863dea3SSunil Goutham } 3694863dea3SSunil Goutham 3704863dea3SSunil Goutham static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type) 3714863dea3SSunil Goutham { 3724863dea3SSunil Goutham u64 cfg; 3734863dea3SSunil Goutham 3744863dea3SSunil Goutham /* Reset SPU */ 3754863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET); 3764863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 3774863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 3784863dea3SSunil Goutham return -1; 3794863dea3SSunil Goutham } 3804863dea3SSunil Goutham 3814863dea3SSunil Goutham /* Disable LMAC */ 3824863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 3834863dea3SSunil Goutham cfg &= ~CMR_EN; 3844863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); 3854863dea3SSunil Goutham 3864863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER); 3874863dea3SSunil Goutham /* Set interleaved running disparity for RXAUI */ 3884863dea3SSunil Goutham if (bgx->lmac_type != BGX_MODE_RXAUI) 3894863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, 3904863dea3SSunil Goutham BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS); 3914863dea3SSunil Goutham else 3924863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, 3934863dea3SSunil Goutham SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP); 3944863dea3SSunil Goutham 3954863dea3SSunil Goutham /* clear all interrupts */ 3964863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT); 3974863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg); 3984863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT); 3994863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg); 4004863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 4014863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 4024863dea3SSunil Goutham 4034863dea3SSunil Goutham if (bgx->use_training) { 4044863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00); 4054863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00); 4064863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00); 4074863dea3SSunil Goutham /* training enable */ 4084863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, 4094863dea3SSunil Goutham BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN); 4104863dea3SSunil Goutham } 4114863dea3SSunil Goutham 4124863dea3SSunil Goutham /* Append FCS to each packet */ 4134863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D); 4144863dea3SSunil Goutham 4154863dea3SSunil Goutham /* Disable forward error correction */ 4164863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL); 4174863dea3SSunil Goutham cfg &= ~SPU_FEC_CTL_FEC_EN; 4184863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg); 4194863dea3SSunil Goutham 4204863dea3SSunil Goutham /* Disable autoneg */ 4214863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL); 4224863dea3SSunil Goutham cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN); 4234863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg); 4244863dea3SSunil Goutham 4254863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV); 4264863dea3SSunil Goutham if (bgx->lmac_type == BGX_MODE_10G_KR) 4274863dea3SSunil Goutham cfg |= (1 << 23); 4284863dea3SSunil Goutham else if (bgx->lmac_type == BGX_MODE_40G_KR) 4294863dea3SSunil Goutham cfg |= (1 << 24); 4304863dea3SSunil Goutham else 4314863dea3SSunil Goutham cfg &= ~((1 << 23) | (1 << 24)); 4324863dea3SSunil Goutham cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12))); 4334863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg); 4344863dea3SSunil Goutham 4354863dea3SSunil Goutham cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL); 4364863dea3SSunil Goutham cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN; 4374863dea3SSunil Goutham bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg); 4384863dea3SSunil Goutham 4394863dea3SSunil Goutham /* Enable lmac */ 4404863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN); 4414863dea3SSunil Goutham 4424863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1); 4434863dea3SSunil Goutham cfg &= ~SPU_CTL_LOW_POWER; 4444863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg); 4454863dea3SSunil Goutham 4464863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL); 4474863dea3SSunil Goutham cfg &= ~SMU_TX_CTL_UNI_EN; 4484863dea3SSunil Goutham cfg |= SMU_TX_CTL_DIC_EN; 4494863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg); 4504863dea3SSunil Goutham 4514863dea3SSunil Goutham /* take lmac_count into account */ 4524863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1)); 4534863dea3SSunil Goutham /* max packet size */ 4544863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE); 4554863dea3SSunil Goutham 4564863dea3SSunil Goutham return 0; 4574863dea3SSunil Goutham } 4584863dea3SSunil Goutham 4594863dea3SSunil Goutham static int bgx_xaui_check_link(struct lmac *lmac) 4604863dea3SSunil Goutham { 4614863dea3SSunil Goutham struct bgx *bgx = lmac->bgx; 4624863dea3SSunil Goutham int lmacid = lmac->lmacid; 4634863dea3SSunil Goutham int lmac_type = bgx->lmac_type; 4644863dea3SSunil Goutham u64 cfg; 4654863dea3SSunil Goutham 4664863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS); 4674863dea3SSunil Goutham if (bgx->use_training) { 4684863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 4694863dea3SSunil Goutham if (!(cfg & (1ull << 13))) { 4704863dea3SSunil Goutham cfg = (1ull << 13) | (1ull << 14); 4714863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 4724863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL); 4734863dea3SSunil Goutham cfg |= (1ull << 0); 4744863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg); 4754863dea3SSunil Goutham return -1; 4764863dea3SSunil Goutham } 4774863dea3SSunil Goutham } 4784863dea3SSunil Goutham 4794863dea3SSunil Goutham /* wait for PCS to come out of reset */ 4804863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) { 4814863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n"); 4824863dea3SSunil Goutham return -1; 4834863dea3SSunil Goutham } 4844863dea3SSunil Goutham 4854863dea3SSunil Goutham if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) || 4864863dea3SSunil Goutham (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) { 4874863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1, 4884863dea3SSunil Goutham SPU_BR_STATUS_BLK_LOCK, false)) { 4894863dea3SSunil Goutham dev_err(&bgx->pdev->dev, 4904863dea3SSunil Goutham "SPU_BR_STATUS_BLK_LOCK not completed\n"); 4914863dea3SSunil Goutham return -1; 4924863dea3SSunil Goutham } 4934863dea3SSunil Goutham } else { 4944863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS, 4954863dea3SSunil Goutham SPU_BX_STATUS_RX_ALIGN, false)) { 4964863dea3SSunil Goutham dev_err(&bgx->pdev->dev, 4974863dea3SSunil Goutham "SPU_BX_STATUS_RX_ALIGN not completed\n"); 4984863dea3SSunil Goutham return -1; 4994863dea3SSunil Goutham } 5004863dea3SSunil Goutham } 5014863dea3SSunil Goutham 5024863dea3SSunil Goutham /* Clear rcvflt bit (latching high) and read it back */ 5034863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT); 5044863dea3SSunil Goutham if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { 5054863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "Receive fault, retry training\n"); 5064863dea3SSunil Goutham if (bgx->use_training) { 5074863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT); 5084863dea3SSunil Goutham if (!(cfg & (1ull << 13))) { 5094863dea3SSunil Goutham cfg = (1ull << 13) | (1ull << 14); 5104863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg); 5114863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, 5124863dea3SSunil Goutham BGX_SPUX_BR_PMD_CRTL); 5134863dea3SSunil Goutham cfg |= (1ull << 0); 5144863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, 5154863dea3SSunil Goutham BGX_SPUX_BR_PMD_CRTL, cfg); 5164863dea3SSunil Goutham return -1; 5174863dea3SSunil Goutham } 5184863dea3SSunil Goutham } 5194863dea3SSunil Goutham return -1; 5204863dea3SSunil Goutham } 5214863dea3SSunil Goutham 5224863dea3SSunil Goutham /* Wait for MAC RX to be ready */ 5234863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL, 5244863dea3SSunil Goutham SMU_RX_CTL_STATUS, true)) { 5254863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "SMU RX link not okay\n"); 5264863dea3SSunil Goutham return -1; 5274863dea3SSunil Goutham } 5284863dea3SSunil Goutham 5294863dea3SSunil Goutham /* Wait for BGX RX to be idle */ 5304863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) { 5314863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "SMU RX not idle\n"); 5324863dea3SSunil Goutham return -1; 5334863dea3SSunil Goutham } 5344863dea3SSunil Goutham 5354863dea3SSunil Goutham /* Wait for BGX TX to be idle */ 5364863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) { 5374863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "SMU TX not idle\n"); 5384863dea3SSunil Goutham return -1; 5394863dea3SSunil Goutham } 5404863dea3SSunil Goutham 5414863dea3SSunil Goutham if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) { 5424863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "Receive fault\n"); 5434863dea3SSunil Goutham return -1; 5444863dea3SSunil Goutham } 5454863dea3SSunil Goutham 5464863dea3SSunil Goutham /* Receive link is latching low. Force it high and verify it */ 5474863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); 5484863dea3SSunil Goutham if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1, 5494863dea3SSunil Goutham SPU_STATUS1_RCV_LNK, false)) { 5504863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "SPU receive link down\n"); 5514863dea3SSunil Goutham return -1; 5524863dea3SSunil Goutham } 5534863dea3SSunil Goutham 5544863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL); 5554863dea3SSunil Goutham cfg &= ~SPU_MISC_CTL_RX_DIS; 5564863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg); 5574863dea3SSunil Goutham return 0; 5584863dea3SSunil Goutham } 5594863dea3SSunil Goutham 5604863dea3SSunil Goutham static void bgx_poll_for_link(struct work_struct *work) 5614863dea3SSunil Goutham { 5624863dea3SSunil Goutham struct lmac *lmac; 5634863dea3SSunil Goutham u64 link; 5644863dea3SSunil Goutham 5654863dea3SSunil Goutham lmac = container_of(work, struct lmac, dwork.work); 5664863dea3SSunil Goutham 5674863dea3SSunil Goutham /* Receive link is latching low. Force it high and verify it */ 5684863dea3SSunil Goutham bgx_reg_modify(lmac->bgx, lmac->lmacid, 5694863dea3SSunil Goutham BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK); 5704863dea3SSunil Goutham bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1, 5714863dea3SSunil Goutham SPU_STATUS1_RCV_LNK, false); 5724863dea3SSunil Goutham 5734863dea3SSunil Goutham link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1); 5744863dea3SSunil Goutham if (link & SPU_STATUS1_RCV_LNK) { 5754863dea3SSunil Goutham lmac->link_up = 1; 5764863dea3SSunil Goutham if (lmac->bgx->lmac_type == BGX_MODE_XLAUI) 5774863dea3SSunil Goutham lmac->last_speed = 40000; 5784863dea3SSunil Goutham else 5794863dea3SSunil Goutham lmac->last_speed = 10000; 5804863dea3SSunil Goutham lmac->last_duplex = 1; 5814863dea3SSunil Goutham } else { 5824863dea3SSunil Goutham lmac->link_up = 0; 5834863dea3SSunil Goutham } 5844863dea3SSunil Goutham 5854863dea3SSunil Goutham if (lmac->last_link != lmac->link_up) { 5864863dea3SSunil Goutham lmac->last_link = lmac->link_up; 5874863dea3SSunil Goutham if (lmac->link_up) 5884863dea3SSunil Goutham bgx_xaui_check_link(lmac); 5894863dea3SSunil Goutham } 5904863dea3SSunil Goutham 5914863dea3SSunil Goutham queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2); 5924863dea3SSunil Goutham } 5934863dea3SSunil Goutham 5944863dea3SSunil Goutham static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid) 5954863dea3SSunil Goutham { 5964863dea3SSunil Goutham struct lmac *lmac; 5974863dea3SSunil Goutham u64 cfg; 5984863dea3SSunil Goutham 5994863dea3SSunil Goutham lmac = &bgx->lmac[lmacid]; 6004863dea3SSunil Goutham lmac->bgx = bgx; 6014863dea3SSunil Goutham 6024863dea3SSunil Goutham if (bgx->lmac_type == BGX_MODE_SGMII) { 6034863dea3SSunil Goutham lmac->is_sgmii = 1; 6044863dea3SSunil Goutham if (bgx_lmac_sgmii_init(bgx, lmacid)) 6054863dea3SSunil Goutham return -1; 6064863dea3SSunil Goutham } else { 6074863dea3SSunil Goutham lmac->is_sgmii = 0; 6084863dea3SSunil Goutham if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type)) 6094863dea3SSunil Goutham return -1; 6104863dea3SSunil Goutham } 6114863dea3SSunil Goutham 6124863dea3SSunil Goutham if (lmac->is_sgmii) { 6134863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND); 6144863dea3SSunil Goutham cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 6154863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg); 6164863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1); 6174863dea3SSunil Goutham } else { 6184863dea3SSunil Goutham cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND); 6194863dea3SSunil Goutham cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */ 6204863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg); 6214863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4); 6224863dea3SSunil Goutham } 6234863dea3SSunil Goutham 6244863dea3SSunil Goutham /* Enable lmac */ 6254863dea3SSunil Goutham bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, 6264863dea3SSunil Goutham CMR_EN | CMR_PKT_RX_EN | CMR_PKT_TX_EN); 6274863dea3SSunil Goutham 6284863dea3SSunil Goutham /* Restore default cfg, incase low level firmware changed it */ 6294863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03); 6304863dea3SSunil Goutham 6314863dea3SSunil Goutham if ((bgx->lmac_type != BGX_MODE_XFI) && 6324863dea3SSunil Goutham (bgx->lmac_type != BGX_MODE_XLAUI) && 6334863dea3SSunil Goutham (bgx->lmac_type != BGX_MODE_40G_KR) && 6344863dea3SSunil Goutham (bgx->lmac_type != BGX_MODE_10G_KR)) { 6354863dea3SSunil Goutham if (!lmac->phydev) 6364863dea3SSunil Goutham return -ENODEV; 6374863dea3SSunil Goutham 6384863dea3SSunil Goutham lmac->phydev->dev_flags = 0; 6394863dea3SSunil Goutham 6404863dea3SSunil Goutham if (phy_connect_direct(&lmac->netdev, lmac->phydev, 6414863dea3SSunil Goutham bgx_lmac_handler, 6424863dea3SSunil Goutham PHY_INTERFACE_MODE_SGMII)) 6434863dea3SSunil Goutham return -ENODEV; 6444863dea3SSunil Goutham 6454863dea3SSunil Goutham phy_start_aneg(lmac->phydev); 6464863dea3SSunil Goutham } else { 6474863dea3SSunil Goutham lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND | 6484863dea3SSunil Goutham WQ_MEM_RECLAIM, 1); 6494863dea3SSunil Goutham if (!lmac->check_link) 6504863dea3SSunil Goutham return -ENOMEM; 6514863dea3SSunil Goutham INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link); 6524863dea3SSunil Goutham queue_delayed_work(lmac->check_link, &lmac->dwork, 0); 6534863dea3SSunil Goutham } 6544863dea3SSunil Goutham 6554863dea3SSunil Goutham return 0; 6564863dea3SSunil Goutham } 6574863dea3SSunil Goutham 6584863dea3SSunil Goutham void bgx_lmac_disable(struct bgx *bgx, u8 lmacid) 6594863dea3SSunil Goutham { 6604863dea3SSunil Goutham struct lmac *lmac; 6614863dea3SSunil Goutham u64 cmrx_cfg; 6624863dea3SSunil Goutham 6634863dea3SSunil Goutham lmac = &bgx->lmac[lmacid]; 6644863dea3SSunil Goutham if (lmac->check_link) { 6654863dea3SSunil Goutham /* Destroy work queue */ 6664863dea3SSunil Goutham cancel_delayed_work(&lmac->dwork); 6674863dea3SSunil Goutham flush_workqueue(lmac->check_link); 6684863dea3SSunil Goutham destroy_workqueue(lmac->check_link); 6694863dea3SSunil Goutham } 6704863dea3SSunil Goutham 6714863dea3SSunil Goutham cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); 6724863dea3SSunil Goutham cmrx_cfg &= ~(1 << 15); 6734863dea3SSunil Goutham bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg); 6744863dea3SSunil Goutham bgx_flush_dmac_addrs(bgx, lmacid); 6754863dea3SSunil Goutham 6764863dea3SSunil Goutham if (lmac->phydev) 6774863dea3SSunil Goutham phy_disconnect(lmac->phydev); 6784863dea3SSunil Goutham 6794863dea3SSunil Goutham lmac->phydev = NULL; 6804863dea3SSunil Goutham } 6814863dea3SSunil Goutham 6824863dea3SSunil Goutham static void bgx_set_num_ports(struct bgx *bgx) 6834863dea3SSunil Goutham { 6844863dea3SSunil Goutham u64 lmac_count; 6854863dea3SSunil Goutham 6864863dea3SSunil Goutham switch (bgx->qlm_mode) { 6874863dea3SSunil Goutham case QLM_MODE_SGMII: 6884863dea3SSunil Goutham bgx->lmac_count = 4; 6894863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_SGMII; 6904863dea3SSunil Goutham bgx->lane_to_sds = 0; 6914863dea3SSunil Goutham break; 6924863dea3SSunil Goutham case QLM_MODE_XAUI_1X4: 6934863dea3SSunil Goutham bgx->lmac_count = 1; 6944863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_XAUI; 6954863dea3SSunil Goutham bgx->lane_to_sds = 0xE4; 6964863dea3SSunil Goutham break; 6974863dea3SSunil Goutham case QLM_MODE_RXAUI_2X2: 6984863dea3SSunil Goutham bgx->lmac_count = 2; 6994863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_RXAUI; 7004863dea3SSunil Goutham bgx->lane_to_sds = 0xE4; 7014863dea3SSunil Goutham break; 7024863dea3SSunil Goutham case QLM_MODE_XFI_4X1: 7034863dea3SSunil Goutham bgx->lmac_count = 4; 7044863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_XFI; 7054863dea3SSunil Goutham bgx->lane_to_sds = 0; 7064863dea3SSunil Goutham break; 7074863dea3SSunil Goutham case QLM_MODE_XLAUI_1X4: 7084863dea3SSunil Goutham bgx->lmac_count = 1; 7094863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_XLAUI; 7104863dea3SSunil Goutham bgx->lane_to_sds = 0xE4; 7114863dea3SSunil Goutham break; 7124863dea3SSunil Goutham case QLM_MODE_10G_KR_4X1: 7134863dea3SSunil Goutham bgx->lmac_count = 4; 7144863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_10G_KR; 7154863dea3SSunil Goutham bgx->lane_to_sds = 0; 7164863dea3SSunil Goutham bgx->use_training = 1; 7174863dea3SSunil Goutham break; 7184863dea3SSunil Goutham case QLM_MODE_40G_KR4_1X4: 7194863dea3SSunil Goutham bgx->lmac_count = 1; 7204863dea3SSunil Goutham bgx->lmac_type = BGX_MODE_40G_KR; 7214863dea3SSunil Goutham bgx->lane_to_sds = 0xE4; 7224863dea3SSunil Goutham bgx->use_training = 1; 7234863dea3SSunil Goutham break; 7244863dea3SSunil Goutham default: 7254863dea3SSunil Goutham bgx->lmac_count = 0; 7264863dea3SSunil Goutham break; 7274863dea3SSunil Goutham } 7284863dea3SSunil Goutham 7294863dea3SSunil Goutham /* Check if low level firmware has programmed LMAC count 7304863dea3SSunil Goutham * based on board type, if yes consider that otherwise 7314863dea3SSunil Goutham * the default static values 7324863dea3SSunil Goutham */ 7334863dea3SSunil Goutham lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7; 7344863dea3SSunil Goutham if (lmac_count != 4) 7354863dea3SSunil Goutham bgx->lmac_count = lmac_count; 7364863dea3SSunil Goutham } 7374863dea3SSunil Goutham 7384863dea3SSunil Goutham static void bgx_init_hw(struct bgx *bgx) 7394863dea3SSunil Goutham { 7404863dea3SSunil Goutham int i; 7414863dea3SSunil Goutham 7424863dea3SSunil Goutham bgx_set_num_ports(bgx); 7434863dea3SSunil Goutham 7444863dea3SSunil Goutham bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP); 7454863dea3SSunil Goutham if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS)) 7464863dea3SSunil Goutham dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id); 7474863dea3SSunil Goutham 7484863dea3SSunil Goutham /* Set lmac type and lane2serdes mapping */ 7494863dea3SSunil Goutham for (i = 0; i < bgx->lmac_count; i++) { 7504863dea3SSunil Goutham if (bgx->lmac_type == BGX_MODE_RXAUI) { 7514863dea3SSunil Goutham if (i) 7524863dea3SSunil Goutham bgx->lane_to_sds = 0x0e; 7534863dea3SSunil Goutham else 7544863dea3SSunil Goutham bgx->lane_to_sds = 0x04; 7554863dea3SSunil Goutham bgx_reg_write(bgx, i, BGX_CMRX_CFG, 7564863dea3SSunil Goutham (bgx->lmac_type << 8) | bgx->lane_to_sds); 7574863dea3SSunil Goutham continue; 7584863dea3SSunil Goutham } 7594863dea3SSunil Goutham bgx_reg_write(bgx, i, BGX_CMRX_CFG, 7604863dea3SSunil Goutham (bgx->lmac_type << 8) | (bgx->lane_to_sds + i)); 7614863dea3SSunil Goutham bgx->lmac[i].lmacid_bd = lmac_count; 7624863dea3SSunil Goutham lmac_count++; 7634863dea3SSunil Goutham } 7644863dea3SSunil Goutham 7654863dea3SSunil Goutham bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count); 7664863dea3SSunil Goutham bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count); 7674863dea3SSunil Goutham 7684863dea3SSunil Goutham /* Set the backpressure AND mask */ 7694863dea3SSunil Goutham for (i = 0; i < bgx->lmac_count; i++) 7704863dea3SSunil Goutham bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND, 7714863dea3SSunil Goutham ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) << 7724863dea3SSunil Goutham (i * MAX_BGX_CHANS_PER_LMAC)); 7734863dea3SSunil Goutham 7744863dea3SSunil Goutham /* Disable all MAC filtering */ 7754863dea3SSunil Goutham for (i = 0; i < RX_DMAC_COUNT; i++) 7764863dea3SSunil Goutham bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00); 7774863dea3SSunil Goutham 7784863dea3SSunil Goutham /* Disable MAC steering (NCSI traffic) */ 7794863dea3SSunil Goutham for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++) 7804863dea3SSunil Goutham bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00); 7814863dea3SSunil Goutham } 7824863dea3SSunil Goutham 7834863dea3SSunil Goutham static void bgx_get_qlm_mode(struct bgx *bgx) 7844863dea3SSunil Goutham { 7854863dea3SSunil Goutham struct device *dev = &bgx->pdev->dev; 7864863dea3SSunil Goutham int lmac_type; 7874863dea3SSunil Goutham int train_en; 7884863dea3SSunil Goutham 7894863dea3SSunil Goutham /* Read LMAC0 type to figure out QLM mode 7904863dea3SSunil Goutham * This is configured by low level firmware 7914863dea3SSunil Goutham */ 7924863dea3SSunil Goutham lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG); 7934863dea3SSunil Goutham lmac_type = (lmac_type >> 8) & 0x07; 7944863dea3SSunil Goutham 7954863dea3SSunil Goutham train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) & 7964863dea3SSunil Goutham SPU_PMD_CRTL_TRAIN_EN; 7974863dea3SSunil Goutham 7984863dea3SSunil Goutham switch (lmac_type) { 7994863dea3SSunil Goutham case BGX_MODE_SGMII: 8004863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_SGMII; 8014863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id); 8024863dea3SSunil Goutham break; 8034863dea3SSunil Goutham case BGX_MODE_XAUI: 8044863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_XAUI_1X4; 8054863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id); 8064863dea3SSunil Goutham break; 8074863dea3SSunil Goutham case BGX_MODE_RXAUI: 8084863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_RXAUI_2X2; 8094863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id); 8104863dea3SSunil Goutham break; 8114863dea3SSunil Goutham case BGX_MODE_XFI: 8124863dea3SSunil Goutham if (!train_en) { 8134863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_XFI_4X1; 8144863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id); 8154863dea3SSunil Goutham } else { 8164863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_10G_KR_4X1; 8174863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id); 8184863dea3SSunil Goutham } 8194863dea3SSunil Goutham break; 8204863dea3SSunil Goutham case BGX_MODE_XLAUI: 8214863dea3SSunil Goutham if (!train_en) { 8224863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_XLAUI_1X4; 8234863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id); 8244863dea3SSunil Goutham } else { 8254863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_40G_KR4_1X4; 8264863dea3SSunil Goutham dev_info(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id); 8274863dea3SSunil Goutham } 8284863dea3SSunil Goutham break; 8294863dea3SSunil Goutham default: 8304863dea3SSunil Goutham bgx->qlm_mode = QLM_MODE_SGMII; 8314863dea3SSunil Goutham dev_info(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id); 8324863dea3SSunil Goutham } 8334863dea3SSunil Goutham } 8344863dea3SSunil Goutham 8354863dea3SSunil Goutham static void bgx_init_of(struct bgx *bgx, struct device_node *np) 8364863dea3SSunil Goutham { 8374863dea3SSunil Goutham struct device_node *np_child; 8384863dea3SSunil Goutham u8 lmac = 0; 8394863dea3SSunil Goutham 8404863dea3SSunil Goutham for_each_child_of_node(np, np_child) { 8414863dea3SSunil Goutham struct device_node *phy_np; 8424863dea3SSunil Goutham const char *mac; 8434863dea3SSunil Goutham 8444863dea3SSunil Goutham phy_np = of_parse_phandle(np_child, "phy-handle", 0); 8454863dea3SSunil Goutham if (phy_np) 8464863dea3SSunil Goutham bgx->lmac[lmac].phydev = of_phy_find_device(phy_np); 8474863dea3SSunil Goutham 8484863dea3SSunil Goutham mac = of_get_mac_address(np_child); 8494863dea3SSunil Goutham if (mac) 8504863dea3SSunil Goutham ether_addr_copy(bgx->lmac[lmac].mac, mac); 8514863dea3SSunil Goutham 8524863dea3SSunil Goutham SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev); 8534863dea3SSunil Goutham bgx->lmac[lmac].lmacid = lmac; 8544863dea3SSunil Goutham lmac++; 8554863dea3SSunil Goutham if (lmac == MAX_LMAC_PER_BGX) 8564863dea3SSunil Goutham break; 8574863dea3SSunil Goutham } 8584863dea3SSunil Goutham } 8594863dea3SSunil Goutham 8604863dea3SSunil Goutham static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8614863dea3SSunil Goutham { 8624863dea3SSunil Goutham int err; 8634863dea3SSunil Goutham struct device *dev = &pdev->dev; 8644863dea3SSunil Goutham struct bgx *bgx = NULL; 8654863dea3SSunil Goutham struct device_node *np; 8664863dea3SSunil Goutham char bgx_sel[5]; 8674863dea3SSunil Goutham u8 lmac; 8684863dea3SSunil Goutham 8694863dea3SSunil Goutham bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL); 8704863dea3SSunil Goutham if (!bgx) 8714863dea3SSunil Goutham return -ENOMEM; 8724863dea3SSunil Goutham bgx->pdev = pdev; 8734863dea3SSunil Goutham 8744863dea3SSunil Goutham pci_set_drvdata(pdev, bgx); 8754863dea3SSunil Goutham 8764863dea3SSunil Goutham err = pci_enable_device(pdev); 8774863dea3SSunil Goutham if (err) { 8784863dea3SSunil Goutham dev_err(dev, "Failed to enable PCI device\n"); 8794863dea3SSunil Goutham pci_set_drvdata(pdev, NULL); 8804863dea3SSunil Goutham return err; 8814863dea3SSunil Goutham } 8824863dea3SSunil Goutham 8834863dea3SSunil Goutham err = pci_request_regions(pdev, DRV_NAME); 8844863dea3SSunil Goutham if (err) { 8854863dea3SSunil Goutham dev_err(dev, "PCI request regions failed 0x%x\n", err); 8864863dea3SSunil Goutham goto err_disable_device; 8874863dea3SSunil Goutham } 8884863dea3SSunil Goutham 8894863dea3SSunil Goutham /* MAP configuration registers */ 8904863dea3SSunil Goutham bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 8914863dea3SSunil Goutham if (!bgx->reg_base) { 8924863dea3SSunil Goutham dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n"); 8934863dea3SSunil Goutham err = -ENOMEM; 8944863dea3SSunil Goutham goto err_release_regions; 8954863dea3SSunil Goutham } 8964863dea3SSunil Goutham bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1; 8974863dea3SSunil Goutham bgx->bgx_id += NODE_ID(pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM)) 8984863dea3SSunil Goutham * MAX_BGX_PER_CN88XX; 8994863dea3SSunil Goutham bgx_vnic[bgx->bgx_id] = bgx; 9004863dea3SSunil Goutham bgx_get_qlm_mode(bgx); 9014863dea3SSunil Goutham 9024863dea3SSunil Goutham snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id); 9034863dea3SSunil Goutham np = of_find_node_by_name(NULL, bgx_sel); 9044863dea3SSunil Goutham if (np) 9054863dea3SSunil Goutham bgx_init_of(bgx, np); 9064863dea3SSunil Goutham 9074863dea3SSunil Goutham bgx_init_hw(bgx); 9084863dea3SSunil Goutham 9094863dea3SSunil Goutham /* Enable all LMACs */ 9104863dea3SSunil Goutham for (lmac = 0; lmac < bgx->lmac_count; lmac++) { 9114863dea3SSunil Goutham err = bgx_lmac_enable(bgx, lmac); 9124863dea3SSunil Goutham if (err) { 9134863dea3SSunil Goutham dev_err(dev, "BGX%d failed to enable lmac%d\n", 9144863dea3SSunil Goutham bgx->bgx_id, lmac); 9154863dea3SSunil Goutham goto err_enable; 9164863dea3SSunil Goutham } 9174863dea3SSunil Goutham } 9184863dea3SSunil Goutham 9194863dea3SSunil Goutham return 0; 9204863dea3SSunil Goutham 9214863dea3SSunil Goutham err_enable: 9224863dea3SSunil Goutham bgx_vnic[bgx->bgx_id] = NULL; 9234863dea3SSunil Goutham err_release_regions: 9244863dea3SSunil Goutham pci_release_regions(pdev); 9254863dea3SSunil Goutham err_disable_device: 9264863dea3SSunil Goutham pci_disable_device(pdev); 9274863dea3SSunil Goutham pci_set_drvdata(pdev, NULL); 9284863dea3SSunil Goutham return err; 9294863dea3SSunil Goutham } 9304863dea3SSunil Goutham 9314863dea3SSunil Goutham static void bgx_remove(struct pci_dev *pdev) 9324863dea3SSunil Goutham { 9334863dea3SSunil Goutham struct bgx *bgx = pci_get_drvdata(pdev); 9344863dea3SSunil Goutham u8 lmac; 9354863dea3SSunil Goutham 9364863dea3SSunil Goutham /* Disable all LMACs */ 9374863dea3SSunil Goutham for (lmac = 0; lmac < bgx->lmac_count; lmac++) 9384863dea3SSunil Goutham bgx_lmac_disable(bgx, lmac); 9394863dea3SSunil Goutham 9404863dea3SSunil Goutham bgx_vnic[bgx->bgx_id] = NULL; 9414863dea3SSunil Goutham pci_release_regions(pdev); 9424863dea3SSunil Goutham pci_disable_device(pdev); 9434863dea3SSunil Goutham pci_set_drvdata(pdev, NULL); 9444863dea3SSunil Goutham } 9454863dea3SSunil Goutham 9464863dea3SSunil Goutham static struct pci_driver bgx_driver = { 9474863dea3SSunil Goutham .name = DRV_NAME, 9484863dea3SSunil Goutham .id_table = bgx_id_table, 9494863dea3SSunil Goutham .probe = bgx_probe, 9504863dea3SSunil Goutham .remove = bgx_remove, 9514863dea3SSunil Goutham }; 9524863dea3SSunil Goutham 9534863dea3SSunil Goutham static int __init bgx_init_module(void) 9544863dea3SSunil Goutham { 9554863dea3SSunil Goutham pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 9564863dea3SSunil Goutham 9574863dea3SSunil Goutham return pci_register_driver(&bgx_driver); 9584863dea3SSunil Goutham } 9594863dea3SSunil Goutham 9604863dea3SSunil Goutham static void __exit bgx_cleanup_module(void) 9614863dea3SSunil Goutham { 9624863dea3SSunil Goutham pci_unregister_driver(&bgx_driver); 9634863dea3SSunil Goutham } 9644863dea3SSunil Goutham 9654863dea3SSunil Goutham module_init(bgx_init_module); 9664863dea3SSunil Goutham module_exit(bgx_cleanup_module); 967