1 /* 2 * This file contains HW queue descriptor formats, config register 3 * structures etc 4 * 5 * Copyright (C) 2015 Cavium, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of version 2 of the GNU General Public License 9 * as published by the Free Software Foundation. 10 */ 11 12 #ifndef Q_STRUCT_H 13 #define Q_STRUCT_H 14 15 /* Load transaction types for reading segment bytes specified by 16 * NIC_SEND_GATHER_S[LD_TYPE]. 17 */ 18 enum nic_send_ld_type_e { 19 NIC_SEND_LD_TYPE_E_LDD = 0x0, 20 NIC_SEND_LD_TYPE_E_LDT = 0x1, 21 NIC_SEND_LD_TYPE_E_LDWB = 0x2, 22 NIC_SEND_LD_TYPE_E_ENUM_LAST = 0x3, 23 }; 24 25 enum ether_type_algorithm { 26 ETYPE_ALG_NONE = 0x0, 27 ETYPE_ALG_SKIP = 0x1, 28 ETYPE_ALG_ENDPARSE = 0x2, 29 ETYPE_ALG_VLAN = 0x3, 30 ETYPE_ALG_VLAN_STRIP = 0x4, 31 }; 32 33 enum layer3_type { 34 L3TYPE_NONE = 0x00, 35 L3TYPE_GRH = 0x01, 36 L3TYPE_IPV4 = 0x04, 37 L3TYPE_IPV4_OPTIONS = 0x05, 38 L3TYPE_IPV6 = 0x06, 39 L3TYPE_IPV6_OPTIONS = 0x07, 40 L3TYPE_ET_STOP = 0x0D, 41 L3TYPE_OTHER = 0x0E, 42 }; 43 44 enum layer4_type { 45 L4TYPE_NONE = 0x00, 46 L4TYPE_IPSEC_ESP = 0x01, 47 L4TYPE_IPFRAG = 0x02, 48 L4TYPE_IPCOMP = 0x03, 49 L4TYPE_TCP = 0x04, 50 L4TYPE_UDP = 0x05, 51 L4TYPE_SCTP = 0x06, 52 L4TYPE_GRE = 0x07, 53 L4TYPE_ROCE_BTH = 0x08, 54 L4TYPE_OTHER = 0x0E, 55 }; 56 57 /* CPI and RSSI configuration */ 58 enum cpi_algorithm_type { 59 CPI_ALG_NONE = 0x0, 60 CPI_ALG_VLAN = 0x1, 61 CPI_ALG_VLAN16 = 0x2, 62 CPI_ALG_DIFF = 0x3, 63 }; 64 65 enum rss_algorithm_type { 66 RSS_ALG_NONE = 0x00, 67 RSS_ALG_PORT = 0x01, 68 RSS_ALG_IP = 0x02, 69 RSS_ALG_TCP_IP = 0x03, 70 RSS_ALG_UDP_IP = 0x04, 71 RSS_ALG_SCTP_IP = 0x05, 72 RSS_ALG_GRE_IP = 0x06, 73 RSS_ALG_ROCE = 0x07, 74 }; 75 76 enum rss_hash_cfg { 77 RSS_HASH_L2ETC = 0x00, 78 RSS_HASH_IP = 0x01, 79 RSS_HASH_TCP = 0x02, 80 RSS_HASH_TCP_SYN_DIS = 0x03, 81 RSS_HASH_UDP = 0x04, 82 RSS_HASH_L4ETC = 0x05, 83 RSS_HASH_ROCE = 0x06, 84 RSS_L3_BIDI = 0x07, 85 RSS_L4_BIDI = 0x08, 86 }; 87 88 /* Completion queue entry types */ 89 enum cqe_type { 90 CQE_TYPE_INVALID = 0x0, 91 CQE_TYPE_RX = 0x2, 92 CQE_TYPE_RX_SPLIT = 0x3, 93 CQE_TYPE_RX_TCP = 0x4, 94 CQE_TYPE_SEND = 0x8, 95 CQE_TYPE_SEND_PTP = 0x9, 96 }; 97 98 enum cqe_rx_tcp_status { 99 CQE_RX_STATUS_VALID_TCP_CNXT = 0x00, 100 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F, 101 }; 102 103 enum cqe_send_status { 104 CQE_SEND_STATUS_GOOD = 0x00, 105 CQE_SEND_STATUS_DESC_FAULT = 0x01, 106 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11, 107 CQE_SEND_STATUS_SUBDESC_ERR = 0x12, 108 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80, 109 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81, 110 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82, 111 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83, 112 CQE_SEND_STATUS_LOCK_VIOL = 0x84, 113 CQE_SEND_STATUS_LOCK_UFLOW = 0x85, 114 CQE_SEND_STATUS_DATA_FAULT = 0x86, 115 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87, 116 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88, 117 CQE_SEND_STATUS_MEM_FAULT = 0x89, 118 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A, 119 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B, 120 }; 121 122 enum cqe_rx_tcp_end_reason { 123 CQE_RX_TCP_END_FIN_FLAG_DET = 0, 124 CQE_RX_TCP_END_INVALID_FLAG = 1, 125 CQE_RX_TCP_END_TIMEOUT = 2, 126 CQE_RX_TCP_END_OUT_OF_SEQ = 3, 127 CQE_RX_TCP_END_PKT_ERR = 4, 128 CQE_RX_TCP_END_QS_DISABLED = 0x0F, 129 }; 130 131 /* Packet protocol level error enumeration */ 132 enum cqe_rx_err_level { 133 CQE_RX_ERRLVL_RE = 0x0, 134 CQE_RX_ERRLVL_L2 = 0x1, 135 CQE_RX_ERRLVL_L3 = 0x2, 136 CQE_RX_ERRLVL_L4 = 0x3, 137 }; 138 139 /* Packet protocol level error type enumeration */ 140 enum cqe_rx_err_opcode { 141 CQE_RX_ERR_RE_NONE = 0x0, 142 CQE_RX_ERR_RE_PARTIAL = 0x1, 143 CQE_RX_ERR_RE_JABBER = 0x2, 144 CQE_RX_ERR_RE_FCS = 0x7, 145 CQE_RX_ERR_RE_TERMINATE = 0x9, 146 CQE_RX_ERR_RE_RX_CTL = 0xb, 147 CQE_RX_ERR_PREL2_ERR = 0x1f, 148 CQE_RX_ERR_L2_FRAGMENT = 0x20, 149 CQE_RX_ERR_L2_OVERRUN = 0x21, 150 CQE_RX_ERR_L2_PFCS = 0x22, 151 CQE_RX_ERR_L2_PUNY = 0x23, 152 CQE_RX_ERR_L2_MAL = 0x24, 153 CQE_RX_ERR_L2_OVERSIZE = 0x25, 154 CQE_RX_ERR_L2_UNDERSIZE = 0x26, 155 CQE_RX_ERR_L2_LENMISM = 0x27, 156 CQE_RX_ERR_L2_PCLP = 0x28, 157 CQE_RX_ERR_IP_NOT = 0x41, 158 CQE_RX_ERR_IP_CHK = 0x42, 159 CQE_RX_ERR_IP_MAL = 0x43, 160 CQE_RX_ERR_IP_MALD = 0x44, 161 CQE_RX_ERR_IP_HOP = 0x45, 162 CQE_RX_ERR_L3_ICRC = 0x46, 163 CQE_RX_ERR_L3_PCLP = 0x47, 164 CQE_RX_ERR_L4_MAL = 0x61, 165 CQE_RX_ERR_L4_CHK = 0x62, 166 CQE_RX_ERR_UDP_LEN = 0x63, 167 CQE_RX_ERR_L4_PORT = 0x64, 168 CQE_RX_ERR_TCP_FLAG = 0x65, 169 CQE_RX_ERR_TCP_OFFSET = 0x66, 170 CQE_RX_ERR_L4_PCLP = 0x67, 171 CQE_RX_ERR_RBDR_TRUNC = 0x70, 172 }; 173 174 struct cqe_rx_t { 175 #if defined(__BIG_ENDIAN_BITFIELD) 176 u64 cqe_type:4; /* W0 */ 177 u64 stdn_fault:1; 178 u64 rsvd0:1; 179 u64 rq_qs:7; 180 u64 rq_idx:3; 181 u64 rsvd1:12; 182 u64 rss_alg:4; 183 u64 rsvd2:4; 184 u64 rb_cnt:4; 185 u64 vlan_found:1; 186 u64 vlan_stripped:1; 187 u64 vlan2_found:1; 188 u64 vlan2_stripped:1; 189 u64 l4_type:4; 190 u64 l3_type:4; 191 u64 l2_present:1; 192 u64 err_level:3; 193 u64 err_opcode:8; 194 195 u64 pkt_len:16; /* W1 */ 196 u64 l2_ptr:8; 197 u64 l3_ptr:8; 198 u64 l4_ptr:8; 199 u64 cq_pkt_len:8; 200 u64 align_pad:3; 201 u64 rsvd3:1; 202 u64 chan:12; 203 204 u64 rss_tag:32; /* W2 */ 205 u64 vlan_tci:16; 206 u64 vlan_ptr:8; 207 u64 vlan2_ptr:8; 208 209 u64 rb3_sz:16; /* W3 */ 210 u64 rb2_sz:16; 211 u64 rb1_sz:16; 212 u64 rb0_sz:16; 213 214 u64 rb7_sz:16; /* W4 */ 215 u64 rb6_sz:16; 216 u64 rb5_sz:16; 217 u64 rb4_sz:16; 218 219 u64 rb11_sz:16; /* W5 */ 220 u64 rb10_sz:16; 221 u64 rb9_sz:16; 222 u64 rb8_sz:16; 223 #elif defined(__LITTLE_ENDIAN_BITFIELD) 224 u64 err_opcode:8; 225 u64 err_level:3; 226 u64 l2_present:1; 227 u64 l3_type:4; 228 u64 l4_type:4; 229 u64 vlan2_stripped:1; 230 u64 vlan2_found:1; 231 u64 vlan_stripped:1; 232 u64 vlan_found:1; 233 u64 rb_cnt:4; 234 u64 rsvd2:4; 235 u64 rss_alg:4; 236 u64 rsvd1:12; 237 u64 rq_idx:3; 238 u64 rq_qs:7; 239 u64 rsvd0:1; 240 u64 stdn_fault:1; 241 u64 cqe_type:4; /* W0 */ 242 u64 chan:12; 243 u64 rsvd3:1; 244 u64 align_pad:3; 245 u64 cq_pkt_len:8; 246 u64 l4_ptr:8; 247 u64 l3_ptr:8; 248 u64 l2_ptr:8; 249 u64 pkt_len:16; /* W1 */ 250 u64 vlan2_ptr:8; 251 u64 vlan_ptr:8; 252 u64 vlan_tci:16; 253 u64 rss_tag:32; /* W2 */ 254 u64 rb0_sz:16; 255 u64 rb1_sz:16; 256 u64 rb2_sz:16; 257 u64 rb3_sz:16; /* W3 */ 258 u64 rb4_sz:16; 259 u64 rb5_sz:16; 260 u64 rb6_sz:16; 261 u64 rb7_sz:16; /* W4 */ 262 u64 rb8_sz:16; 263 u64 rb9_sz:16; 264 u64 rb10_sz:16; 265 u64 rb11_sz:16; /* W5 */ 266 #endif 267 u64 rb0_ptr:64; 268 u64 rb1_ptr:64; 269 u64 rb2_ptr:64; 270 u64 rb3_ptr:64; 271 u64 rb4_ptr:64; 272 u64 rb5_ptr:64; 273 u64 rb6_ptr:64; 274 u64 rb7_ptr:64; 275 u64 rb8_ptr:64; 276 u64 rb9_ptr:64; 277 u64 rb10_ptr:64; 278 u64 rb11_ptr:64; 279 }; 280 281 struct cqe_rx_tcp_err_t { 282 #if defined(__BIG_ENDIAN_BITFIELD) 283 u64 cqe_type:4; /* W0 */ 284 u64 rsvd0:60; 285 286 u64 rsvd1:4; /* W1 */ 287 u64 partial_first:1; 288 u64 rsvd2:27; 289 u64 rbdr_bytes:8; 290 u64 rsvd3:24; 291 #elif defined(__LITTLE_ENDIAN_BITFIELD) 292 u64 rsvd0:60; 293 u64 cqe_type:4; 294 295 u64 rsvd3:24; 296 u64 rbdr_bytes:8; 297 u64 rsvd2:27; 298 u64 partial_first:1; 299 u64 rsvd1:4; 300 #endif 301 }; 302 303 struct cqe_rx_tcp_t { 304 #if defined(__BIG_ENDIAN_BITFIELD) 305 u64 cqe_type:4; /* W0 */ 306 u64 rsvd0:52; 307 u64 cq_tcp_status:8; 308 309 u64 rsvd1:32; /* W1 */ 310 u64 tcp_cntx_bytes:8; 311 u64 rsvd2:8; 312 u64 tcp_err_bytes:16; 313 #elif defined(__LITTLE_ENDIAN_BITFIELD) 314 u64 cq_tcp_status:8; 315 u64 rsvd0:52; 316 u64 cqe_type:4; /* W0 */ 317 318 u64 tcp_err_bytes:16; 319 u64 rsvd2:8; 320 u64 tcp_cntx_bytes:8; 321 u64 rsvd1:32; /* W1 */ 322 #endif 323 }; 324 325 struct cqe_send_t { 326 #if defined(__BIG_ENDIAN_BITFIELD) 327 u64 cqe_type:4; /* W0 */ 328 u64 rsvd0:4; 329 u64 sqe_ptr:16; 330 u64 rsvd1:4; 331 u64 rsvd2:10; 332 u64 sq_qs:7; 333 u64 sq_idx:3; 334 u64 rsvd3:8; 335 u64 send_status:8; 336 337 u64 ptp_timestamp:64; /* W1 */ 338 #elif defined(__LITTLE_ENDIAN_BITFIELD) 339 u64 send_status:8; 340 u64 rsvd3:8; 341 u64 sq_idx:3; 342 u64 sq_qs:7; 343 u64 rsvd2:10; 344 u64 rsvd1:4; 345 u64 sqe_ptr:16; 346 u64 rsvd0:4; 347 u64 cqe_type:4; /* W0 */ 348 349 u64 ptp_timestamp:64; /* W1 */ 350 #endif 351 }; 352 353 union cq_desc_t { 354 u64 u[64]; 355 struct cqe_send_t snd_hdr; 356 struct cqe_rx_t rx_hdr; 357 struct cqe_rx_tcp_t rx_tcp_hdr; 358 struct cqe_rx_tcp_err_t rx_tcp_err_hdr; 359 }; 360 361 struct rbdr_entry_t { 362 #if defined(__BIG_ENDIAN_BITFIELD) 363 u64 rsvd0:15; 364 u64 buf_addr:42; 365 u64 cache_align:7; 366 #elif defined(__LITTLE_ENDIAN_BITFIELD) 367 u64 cache_align:7; 368 u64 buf_addr:42; 369 u64 rsvd0:15; 370 #endif 371 }; 372 373 /* TCP reassembly context */ 374 struct rbe_tcp_cnxt_t { 375 #if defined(__BIG_ENDIAN_BITFIELD) 376 u64 tcp_pkt_cnt:12; 377 u64 rsvd1:4; 378 u64 align_hdr_bytes:4; 379 u64 align_ptr_bytes:4; 380 u64 ptr_bytes:16; 381 u64 rsvd2:24; 382 u64 cqe_type:4; 383 u64 rsvd0:54; 384 u64 tcp_end_reason:2; 385 u64 tcp_status:4; 386 #elif defined(__LITTLE_ENDIAN_BITFIELD) 387 u64 tcp_status:4; 388 u64 tcp_end_reason:2; 389 u64 rsvd0:54; 390 u64 cqe_type:4; 391 u64 rsvd2:24; 392 u64 ptr_bytes:16; 393 u64 align_ptr_bytes:4; 394 u64 align_hdr_bytes:4; 395 u64 rsvd1:4; 396 u64 tcp_pkt_cnt:12; 397 #endif 398 }; 399 400 /* Always Big endian */ 401 struct rx_hdr_t { 402 u64 opaque:32; 403 u64 rss_flow:8; 404 u64 skip_length:6; 405 u64 disable_rss:1; 406 u64 disable_tcp_reassembly:1; 407 u64 nodrop:1; 408 u64 dest_alg:2; 409 u64 rsvd0:2; 410 u64 dest_rq:11; 411 }; 412 413 enum send_l4_csum_type { 414 SEND_L4_CSUM_DISABLE = 0x00, 415 SEND_L4_CSUM_UDP = 0x01, 416 SEND_L4_CSUM_TCP = 0x02, 417 SEND_L4_CSUM_SCTP = 0x03, 418 }; 419 420 enum send_crc_alg { 421 SEND_CRCALG_CRC32 = 0x00, 422 SEND_CRCALG_CRC32C = 0x01, 423 SEND_CRCALG_ICRC = 0x02, 424 }; 425 426 enum send_load_type { 427 SEND_LD_TYPE_LDD = 0x00, 428 SEND_LD_TYPE_LDT = 0x01, 429 SEND_LD_TYPE_LDWB = 0x02, 430 }; 431 432 enum send_mem_alg_type { 433 SEND_MEMALG_SET = 0x00, 434 SEND_MEMALG_ADD = 0x08, 435 SEND_MEMALG_SUB = 0x09, 436 SEND_MEMALG_ADDLEN = 0x0A, 437 SEND_MEMALG_SUBLEN = 0x0B, 438 }; 439 440 enum send_mem_dsz_type { 441 SEND_MEMDSZ_B64 = 0x00, 442 SEND_MEMDSZ_B32 = 0x01, 443 SEND_MEMDSZ_B8 = 0x03, 444 }; 445 446 enum sq_subdesc_type { 447 SQ_DESC_TYPE_INVALID = 0x00, 448 SQ_DESC_TYPE_HEADER = 0x01, 449 SQ_DESC_TYPE_CRC = 0x02, 450 SQ_DESC_TYPE_IMMEDIATE = 0x03, 451 SQ_DESC_TYPE_GATHER = 0x04, 452 SQ_DESC_TYPE_MEMORY = 0x05, 453 }; 454 455 struct sq_crc_subdesc { 456 #if defined(__BIG_ENDIAN_BITFIELD) 457 u64 rsvd1:32; 458 u64 crc_ival:32; 459 u64 subdesc_type:4; 460 u64 crc_alg:2; 461 u64 rsvd0:10; 462 u64 crc_insert_pos:16; 463 u64 hdr_start:16; 464 u64 crc_len:16; 465 #elif defined(__LITTLE_ENDIAN_BITFIELD) 466 u64 crc_len:16; 467 u64 hdr_start:16; 468 u64 crc_insert_pos:16; 469 u64 rsvd0:10; 470 u64 crc_alg:2; 471 u64 subdesc_type:4; 472 u64 crc_ival:32; 473 u64 rsvd1:32; 474 #endif 475 }; 476 477 struct sq_gather_subdesc { 478 #if defined(__BIG_ENDIAN_BITFIELD) 479 u64 subdesc_type:4; /* W0 */ 480 u64 ld_type:2; 481 u64 rsvd0:42; 482 u64 size:16; 483 484 u64 rsvd1:15; /* W1 */ 485 u64 addr:49; 486 #elif defined(__LITTLE_ENDIAN_BITFIELD) 487 u64 size:16; 488 u64 rsvd0:42; 489 u64 ld_type:2; 490 u64 subdesc_type:4; /* W0 */ 491 492 u64 addr:49; 493 u64 rsvd1:15; /* W1 */ 494 #endif 495 }; 496 497 /* SQ immediate subdescriptor */ 498 struct sq_imm_subdesc { 499 #if defined(__BIG_ENDIAN_BITFIELD) 500 u64 subdesc_type:4; /* W0 */ 501 u64 rsvd0:46; 502 u64 len:14; 503 504 u64 data:64; /* W1 */ 505 #elif defined(__LITTLE_ENDIAN_BITFIELD) 506 u64 len:14; 507 u64 rsvd0:46; 508 u64 subdesc_type:4; /* W0 */ 509 510 u64 data:64; /* W1 */ 511 #endif 512 }; 513 514 struct sq_mem_subdesc { 515 #if defined(__BIG_ENDIAN_BITFIELD) 516 u64 subdesc_type:4; /* W0 */ 517 u64 mem_alg:4; 518 u64 mem_dsz:2; 519 u64 wmem:1; 520 u64 rsvd0:21; 521 u64 offset:32; 522 523 u64 rsvd1:15; /* W1 */ 524 u64 addr:49; 525 #elif defined(__LITTLE_ENDIAN_BITFIELD) 526 u64 offset:32; 527 u64 rsvd0:21; 528 u64 wmem:1; 529 u64 mem_dsz:2; 530 u64 mem_alg:4; 531 u64 subdesc_type:4; /* W0 */ 532 533 u64 addr:49; 534 u64 rsvd1:15; /* W1 */ 535 #endif 536 }; 537 538 struct sq_hdr_subdesc { 539 #if defined(__BIG_ENDIAN_BITFIELD) 540 u64 subdesc_type:4; 541 u64 tso:1; 542 u64 post_cqe:1; /* Post CQE on no error also */ 543 u64 dont_send:1; 544 u64 tstmp:1; 545 u64 subdesc_cnt:8; 546 u64 csum_l4:2; 547 u64 csum_l3:1; 548 u64 csum_inner_l4:2; 549 u64 csum_inner_l3:1; 550 u64 rsvd0:2; 551 u64 l4_offset:8; 552 u64 l3_offset:8; 553 u64 rsvd1:4; 554 u64 tot_len:20; /* W0 */ 555 556 u64 rsvd2:24; 557 u64 inner_l4_offset:8; 558 u64 inner_l3_offset:8; 559 u64 tso_start:8; 560 u64 rsvd3:2; 561 u64 tso_max_paysize:14; /* W1 */ 562 #elif defined(__LITTLE_ENDIAN_BITFIELD) 563 u64 tot_len:20; 564 u64 rsvd1:4; 565 u64 l3_offset:8; 566 u64 l4_offset:8; 567 u64 rsvd0:2; 568 u64 csum_inner_l3:1; 569 u64 csum_inner_l4:2; 570 u64 csum_l3:1; 571 u64 csum_l4:2; 572 u64 subdesc_cnt:8; 573 u64 tstmp:1; 574 u64 dont_send:1; 575 u64 post_cqe:1; /* Post CQE on no error also */ 576 u64 tso:1; 577 u64 subdesc_type:4; /* W0 */ 578 579 u64 tso_max_paysize:14; 580 u64 rsvd3:2; 581 u64 tso_start:8; 582 u64 inner_l3_offset:8; 583 u64 inner_l4_offset:8; 584 u64 rsvd2:24; /* W1 */ 585 #endif 586 }; 587 588 /* Queue config register formats */ 589 struct rq_cfg { 590 #if defined(__BIG_ENDIAN_BITFIELD) 591 u64 reserved_2_63:62; 592 u64 ena:1; 593 u64 tcp_ena:1; 594 #elif defined(__LITTLE_ENDIAN_BITFIELD) 595 u64 tcp_ena:1; 596 u64 ena:1; 597 u64 reserved_2_63:62; 598 #endif 599 }; 600 601 struct cq_cfg { 602 #if defined(__BIG_ENDIAN_BITFIELD) 603 u64 reserved_43_63:21; 604 u64 ena:1; 605 u64 reset:1; 606 u64 caching:1; 607 u64 reserved_35_39:5; 608 u64 qsize:3; 609 u64 reserved_25_31:7; 610 u64 avg_con:9; 611 u64 reserved_0_15:16; 612 #elif defined(__LITTLE_ENDIAN_BITFIELD) 613 u64 reserved_0_15:16; 614 u64 avg_con:9; 615 u64 reserved_25_31:7; 616 u64 qsize:3; 617 u64 reserved_35_39:5; 618 u64 caching:1; 619 u64 reset:1; 620 u64 ena:1; 621 u64 reserved_43_63:21; 622 #endif 623 }; 624 625 struct sq_cfg { 626 #if defined(__BIG_ENDIAN_BITFIELD) 627 u64 reserved_20_63:44; 628 u64 ena:1; 629 u64 reserved_18_18:1; 630 u64 reset:1; 631 u64 ldwb:1; 632 u64 reserved_11_15:5; 633 u64 qsize:3; 634 u64 reserved_3_7:5; 635 u64 tstmp_bgx_intf:3; 636 #elif defined(__LITTLE_ENDIAN_BITFIELD) 637 u64 tstmp_bgx_intf:3; 638 u64 reserved_3_7:5; 639 u64 qsize:3; 640 u64 reserved_11_15:5; 641 u64 ldwb:1; 642 u64 reset:1; 643 u64 reserved_18_18:1; 644 u64 ena:1; 645 u64 reserved_20_63:44; 646 #endif 647 }; 648 649 struct rbdr_cfg { 650 #if defined(__BIG_ENDIAN_BITFIELD) 651 u64 reserved_45_63:19; 652 u64 ena:1; 653 u64 reset:1; 654 u64 ldwb:1; 655 u64 reserved_36_41:6; 656 u64 qsize:4; 657 u64 reserved_25_31:7; 658 u64 avg_con:9; 659 u64 reserved_12_15:4; 660 u64 lines:12; 661 #elif defined(__LITTLE_ENDIAN_BITFIELD) 662 u64 lines:12; 663 u64 reserved_12_15:4; 664 u64 avg_con:9; 665 u64 reserved_25_31:7; 666 u64 qsize:4; 667 u64 reserved_36_41:6; 668 u64 ldwb:1; 669 u64 reset:1; 670 u64 ena: 1; 671 u64 reserved_45_63:19; 672 #endif 673 }; 674 675 struct qs_cfg { 676 #if defined(__BIG_ENDIAN_BITFIELD) 677 u64 reserved_32_63:32; 678 u64 ena:1; 679 u64 reserved_27_30:4; 680 u64 sq_ins_ena:1; 681 u64 sq_ins_pos:6; 682 u64 lock_ena:1; 683 u64 lock_viol_cqe_ena:1; 684 u64 send_tstmp_ena:1; 685 u64 be:1; 686 u64 reserved_7_15:9; 687 u64 vnic:7; 688 #elif defined(__LITTLE_ENDIAN_BITFIELD) 689 u64 vnic:7; 690 u64 reserved_7_15:9; 691 u64 be:1; 692 u64 send_tstmp_ena:1; 693 u64 lock_viol_cqe_ena:1; 694 u64 lock_ena:1; 695 u64 sq_ins_pos:6; 696 u64 sq_ins_ena:1; 697 u64 reserved_27_30:4; 698 u64 ena:1; 699 u64 reserved_32_63:32; 700 #endif 701 }; 702 703 #endif /* Q_STRUCT_H */ 704