1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef NICVF_QUEUES_H 10 #define NICVF_QUEUES_H 11 12 #include <linux/netdevice.h> 13 #include "q_struct.h" 14 15 #define MAX_QUEUE_SET 128 16 #define MAX_RCV_QUEUES_PER_QS 8 17 #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2 18 #define MAX_SND_QUEUES_PER_QS 8 19 #define MAX_CMP_QUEUES_PER_QS 8 20 21 /* VF's queue interrupt ranges */ 22 #define NICVF_INTR_ID_CQ 0 23 #define NICVF_INTR_ID_SQ 8 24 #define NICVF_INTR_ID_RBDR 16 25 #define NICVF_INTR_ID_MISC 18 26 #define NICVF_INTR_ID_QS_ERR 19 27 28 #define for_each_cq_irq(irq) \ 29 for (irq = NICVF_INTR_ID_CQ; irq < NICVF_INTR_ID_SQ; irq++) 30 #define for_each_sq_irq(irq) \ 31 for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_RBDR; irq++) 32 #define for_each_rbdr_irq(irq) \ 33 for (irq = NICVF_INTR_ID_RBDR; irq < NICVF_INTR_ID_MISC; irq++) 34 35 #define RBDR_SIZE0 0ULL /* 8K entries */ 36 #define RBDR_SIZE1 1ULL /* 16K entries */ 37 #define RBDR_SIZE2 2ULL /* 32K entries */ 38 #define RBDR_SIZE3 3ULL /* 64K entries */ 39 #define RBDR_SIZE4 4ULL /* 126K entries */ 40 #define RBDR_SIZE5 5ULL /* 256K entries */ 41 #define RBDR_SIZE6 6ULL /* 512K entries */ 42 43 #define SND_QUEUE_SIZE0 0ULL /* 1K entries */ 44 #define SND_QUEUE_SIZE1 1ULL /* 2K entries */ 45 #define SND_QUEUE_SIZE2 2ULL /* 4K entries */ 46 #define SND_QUEUE_SIZE3 3ULL /* 8K entries */ 47 #define SND_QUEUE_SIZE4 4ULL /* 16K entries */ 48 #define SND_QUEUE_SIZE5 5ULL /* 32K entries */ 49 #define SND_QUEUE_SIZE6 6ULL /* 64K entries */ 50 51 #define CMP_QUEUE_SIZE0 0ULL /* 1K entries */ 52 #define CMP_QUEUE_SIZE1 1ULL /* 2K entries */ 53 #define CMP_QUEUE_SIZE2 2ULL /* 4K entries */ 54 #define CMP_QUEUE_SIZE3 3ULL /* 8K entries */ 55 #define CMP_QUEUE_SIZE4 4ULL /* 16K entries */ 56 #define CMP_QUEUE_SIZE5 5ULL /* 32K entries */ 57 #define CMP_QUEUE_SIZE6 6ULL /* 64K entries */ 58 59 /* Default queue count per QS, its lengths and threshold values */ 60 #define DEFAULT_RBDR_CNT 1 61 62 #define SND_QSIZE SND_QUEUE_SIZE2 63 #define SND_QUEUE_LEN (1ULL << (SND_QSIZE + 10)) 64 #define MAX_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE6 + 10)) 65 #define SND_QUEUE_THRESH 2ULL 66 #define MIN_SQ_DESC_PER_PKT_XMIT 2 67 /* Since timestamp not enabled, otherwise 2 */ 68 #define MAX_CQE_PER_PKT_XMIT 1 69 70 /* Keep CQ and SQ sizes same, if timestamping 71 * is enabled this equation will change. 72 */ 73 #define CMP_QSIZE CMP_QUEUE_SIZE2 74 #define CMP_QUEUE_LEN (1ULL << (CMP_QSIZE + 10)) 75 #define CMP_QUEUE_CQE_THRESH (NAPI_POLL_WEIGHT / 2) 76 #define CMP_QUEUE_TIMER_THRESH 80 /* ~2usec */ 77 78 #define RBDR_SIZE RBDR_SIZE0 79 #define RCV_BUF_COUNT (1ULL << (RBDR_SIZE + 13)) 80 #define MAX_RCV_BUF_COUNT (1ULL << (RBDR_SIZE6 + 13)) 81 #define RBDR_THRESH (RCV_BUF_COUNT / 2) 82 #define DMA_BUFFER_LEN 2048 /* In multiples of 128bytes */ 83 #define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \ 84 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 85 86 #define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \ 87 MAX_CQE_PER_PKT_XMIT) 88 89 /* RED and Backpressure levels of CQ for pkt reception 90 * For CQ, level is a measure of emptiness i.e 0x0 means full 91 * eg: For CQ of size 4K, and for pass/drop levels of 160/144 92 * HW accepts pkt if unused CQE >= 2560 93 * RED accepts pkt if unused CQE < 2304 & >= 2560 94 * DROPs pkts if unused CQE < 2304 95 */ 96 #define RQ_PASS_CQ_LVL 160ULL 97 #define RQ_DROP_CQ_LVL 144ULL 98 99 /* RED and Backpressure levels of RBDR for pkt reception 100 * For RBDR, level is a measure of fullness i.e 0x0 means empty 101 * eg: For RBDR of size 8K, and for pass/drop levels of 4/0 102 * HW accepts pkt if unused RBs >= 256 103 * RED accepts pkt if unused RBs < 256 & >= 0 104 * DROPs pkts if unused RBs < 0 105 */ 106 #define RQ_PASS_RBDR_LVL 8ULL 107 #define RQ_DROP_RBDR_LVL 0ULL 108 109 /* Descriptor size in bytes */ 110 #define SND_QUEUE_DESC_SIZE 16 111 #define CMP_QUEUE_DESC_SIZE 512 112 113 /* Buffer / descriptor alignments */ 114 #define NICVF_RCV_BUF_ALIGN 7 115 #define NICVF_RCV_BUF_ALIGN_BYTES (1ULL << NICVF_RCV_BUF_ALIGN) 116 #define NICVF_CQ_BASE_ALIGN_BYTES 512 /* 9 bits */ 117 #define NICVF_SQ_BASE_ALIGN_BYTES 128 /* 7 bits */ 118 119 #define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES) 120 121 /* Queue enable/disable */ 122 #define NICVF_SQ_EN BIT_ULL(19) 123 124 /* Queue reset */ 125 #define NICVF_CQ_RESET BIT_ULL(41) 126 #define NICVF_SQ_RESET BIT_ULL(17) 127 #define NICVF_RBDR_RESET BIT_ULL(43) 128 129 enum CQ_RX_ERRLVL_E { 130 CQ_ERRLVL_MAC, 131 CQ_ERRLVL_L2, 132 CQ_ERRLVL_L3, 133 CQ_ERRLVL_L4, 134 }; 135 136 enum CQ_RX_ERROP_E { 137 CQ_RX_ERROP_RE_NONE = 0x0, 138 CQ_RX_ERROP_RE_PARTIAL = 0x1, 139 CQ_RX_ERROP_RE_JABBER = 0x2, 140 CQ_RX_ERROP_RE_FCS = 0x7, 141 CQ_RX_ERROP_RE_TERMINATE = 0x9, 142 CQ_RX_ERROP_RE_RX_CTL = 0xb, 143 CQ_RX_ERROP_PREL2_ERR = 0x1f, 144 CQ_RX_ERROP_L2_FRAGMENT = 0x20, 145 CQ_RX_ERROP_L2_OVERRUN = 0x21, 146 CQ_RX_ERROP_L2_PFCS = 0x22, 147 CQ_RX_ERROP_L2_PUNY = 0x23, 148 CQ_RX_ERROP_L2_MAL = 0x24, 149 CQ_RX_ERROP_L2_OVERSIZE = 0x25, 150 CQ_RX_ERROP_L2_UNDERSIZE = 0x26, 151 CQ_RX_ERROP_L2_LENMISM = 0x27, 152 CQ_RX_ERROP_L2_PCLP = 0x28, 153 CQ_RX_ERROP_IP_NOT = 0x41, 154 CQ_RX_ERROP_IP_CSUM_ERR = 0x42, 155 CQ_RX_ERROP_IP_MAL = 0x43, 156 CQ_RX_ERROP_IP_MALD = 0x44, 157 CQ_RX_ERROP_IP_HOP = 0x45, 158 CQ_RX_ERROP_L3_ICRC = 0x46, 159 CQ_RX_ERROP_L3_PCLP = 0x47, 160 CQ_RX_ERROP_L4_MAL = 0x61, 161 CQ_RX_ERROP_L4_CHK = 0x62, 162 CQ_RX_ERROP_UDP_LEN = 0x63, 163 CQ_RX_ERROP_L4_PORT = 0x64, 164 CQ_RX_ERROP_TCP_FLAG = 0x65, 165 CQ_RX_ERROP_TCP_OFFSET = 0x66, 166 CQ_RX_ERROP_L4_PCLP = 0x67, 167 CQ_RX_ERROP_RBDR_TRUNC = 0x70, 168 }; 169 170 enum CQ_TX_ERROP_E { 171 CQ_TX_ERROP_GOOD = 0x0, 172 CQ_TX_ERROP_DESC_FAULT = 0x10, 173 CQ_TX_ERROP_HDR_CONS_ERR = 0x11, 174 CQ_TX_ERROP_SUBDC_ERR = 0x12, 175 CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13, 176 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80, 177 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81, 178 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82, 179 CQ_TX_ERROP_LOCK_VIOL = 0x83, 180 CQ_TX_ERROP_DATA_FAULT = 0x84, 181 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85, 182 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86, 183 CQ_TX_ERROP_MEM_FAULT = 0x87, 184 CQ_TX_ERROP_CK_OVERLAP = 0x88, 185 CQ_TX_ERROP_CK_OFLOW = 0x89, 186 CQ_TX_ERROP_ENUM_LAST = 0x8a, 187 }; 188 189 enum RQ_SQ_STATS { 190 RQ_SQ_STATS_OCTS, 191 RQ_SQ_STATS_PKTS, 192 }; 193 194 struct rx_tx_queue_stats { 195 u64 bytes; 196 u64 pkts; 197 } ____cacheline_aligned_in_smp; 198 199 struct q_desc_mem { 200 dma_addr_t dma; 201 u64 size; 202 u16 q_len; 203 dma_addr_t phys_base; 204 void *base; 205 void *unalign_base; 206 }; 207 208 struct rbdr { 209 bool enable; 210 u32 dma_size; 211 u32 frag_len; 212 u32 thresh; /* Threshold level for interrupt */ 213 void *desc; 214 u32 head; 215 u32 tail; 216 struct q_desc_mem dmem; 217 } ____cacheline_aligned_in_smp; 218 219 struct rcv_queue { 220 bool enable; 221 struct rbdr *rbdr_start; 222 struct rbdr *rbdr_cont; 223 bool en_tcp_reassembly; 224 u8 cq_qs; /* CQ's QS to which this RQ is assigned */ 225 u8 cq_idx; /* CQ index (0 to 7) in the QS */ 226 u8 cont_rbdr_qs; /* Continue buffer ptrs - QS num */ 227 u8 cont_qs_rbdr_idx; /* RBDR idx in the cont QS */ 228 u8 start_rbdr_qs; /* First buffer ptrs - QS num */ 229 u8 start_qs_rbdr_idx; /* RBDR idx in the above QS */ 230 u8 caching; 231 struct rx_tx_queue_stats stats; 232 } ____cacheline_aligned_in_smp; 233 234 struct cmp_queue { 235 bool enable; 236 u16 thresh; 237 spinlock_t lock; /* lock to serialize processing CQEs */ 238 void *desc; 239 struct q_desc_mem dmem; 240 int irq; 241 } ____cacheline_aligned_in_smp; 242 243 struct snd_queue { 244 bool enable; 245 u8 cq_qs; /* CQ's QS to which this SQ is pointing */ 246 u8 cq_idx; /* CQ index (0 to 7) in the above QS */ 247 u16 thresh; 248 atomic_t free_cnt; 249 u32 head; 250 u32 tail; 251 u64 *skbuff; 252 void *desc; 253 254 #define TSO_HEADER_SIZE 128 255 /* For TSO segment's header */ 256 char *tso_hdrs; 257 dma_addr_t tso_hdrs_phys; 258 259 cpumask_t affinity_mask; 260 struct q_desc_mem dmem; 261 struct rx_tx_queue_stats stats; 262 } ____cacheline_aligned_in_smp; 263 264 struct queue_set { 265 bool enable; 266 bool be_en; 267 u8 vnic_id; 268 u8 rq_cnt; 269 u8 cq_cnt; 270 u64 cq_len; 271 u8 sq_cnt; 272 u64 sq_len; 273 u8 rbdr_cnt; 274 u64 rbdr_len; 275 struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS]; 276 struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS]; 277 struct snd_queue sq[MAX_SND_QUEUES_PER_QS]; 278 struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS]; 279 } ____cacheline_aligned_in_smp; 280 281 #define GET_RBDR_DESC(RING, idx)\ 282 (&(((struct rbdr_entry_t *)((RING)->desc))[idx])) 283 #define GET_SQ_DESC(RING, idx)\ 284 (&(((struct sq_hdr_subdesc *)((RING)->desc))[idx])) 285 #define GET_CQ_DESC(RING, idx)\ 286 (&(((union cq_desc_t *)((RING)->desc))[idx])) 287 288 /* CQ status bits */ 289 #define CQ_WR_FULL BIT(26) 290 #define CQ_WR_DISABLE BIT(25) 291 #define CQ_WR_FAULT BIT(24) 292 #define CQ_CQE_COUNT (0xFFFF << 0) 293 294 #define CQ_ERR_MASK (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT) 295 296 void nicvf_config_vlan_stripping(struct nicvf *nic, 297 netdev_features_t features); 298 int nicvf_set_qset_resources(struct nicvf *nic); 299 int nicvf_config_data_transfer(struct nicvf *nic, bool enable); 300 void nicvf_qset_config(struct nicvf *nic, bool enable); 301 void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, 302 int qidx, bool enable); 303 304 void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx); 305 void nicvf_sq_disable(struct nicvf *nic, int qidx); 306 void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt); 307 void nicvf_sq_free_used_descs(struct net_device *netdev, 308 struct snd_queue *sq, int qidx); 309 int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq, 310 struct sk_buff *skb, u8 sq_num); 311 312 struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx); 313 void nicvf_rbdr_task(unsigned long data); 314 void nicvf_rbdr_work(struct work_struct *work); 315 316 void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx); 317 void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx); 318 void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx); 319 int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx); 320 321 /* Register access APIs */ 322 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val); 323 u64 nicvf_reg_read(struct nicvf *nic, u64 offset); 324 void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val); 325 u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset); 326 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset, 327 u64 qidx, u64 val); 328 u64 nicvf_queue_reg_read(struct nicvf *nic, 329 u64 offset, u64 qidx); 330 331 /* Stats */ 332 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx); 333 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx); 334 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx); 335 int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx); 336 #endif /* NICVF_QUEUES_H */ 337