1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/ip.h> 12 #include <linux/etherdevice.h> 13 #include <linux/iommu.h> 14 #include <net/ip.h> 15 #include <net/tso.h> 16 17 #include "nic_reg.h" 18 #include "nic.h" 19 #include "q_struct.h" 20 #include "nicvf_queues.h" 21 22 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry, 23 int size, u64 data); 24 static void nicvf_get_page(struct nicvf *nic) 25 { 26 if (!nic->rb_pageref || !nic->rb_page) 27 return; 28 29 page_ref_add(nic->rb_page, nic->rb_pageref); 30 nic->rb_pageref = 0; 31 } 32 33 /* Poll a register for a specific value */ 34 static int nicvf_poll_reg(struct nicvf *nic, int qidx, 35 u64 reg, int bit_pos, int bits, int val) 36 { 37 u64 bit_mask; 38 u64 reg_val; 39 int timeout = 10; 40 41 bit_mask = (1ULL << bits) - 1; 42 bit_mask = (bit_mask << bit_pos); 43 44 while (timeout) { 45 reg_val = nicvf_queue_reg_read(nic, reg, qidx); 46 if (((reg_val & bit_mask) >> bit_pos) == val) 47 return 0; 48 usleep_range(1000, 2000); 49 timeout--; 50 } 51 netdev_err(nic->netdev, "Poll on reg 0x%llx failed\n", reg); 52 return 1; 53 } 54 55 /* Allocate memory for a queue's descriptors */ 56 static int nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem, 57 int q_len, int desc_size, int align_bytes) 58 { 59 dmem->q_len = q_len; 60 dmem->size = (desc_size * q_len) + align_bytes; 61 /* Save address, need it while freeing */ 62 dmem->unalign_base = dma_zalloc_coherent(&nic->pdev->dev, dmem->size, 63 &dmem->dma, GFP_KERNEL); 64 if (!dmem->unalign_base) 65 return -ENOMEM; 66 67 /* Align memory address for 'align_bytes' */ 68 dmem->phys_base = NICVF_ALIGNED_ADDR((u64)dmem->dma, align_bytes); 69 dmem->base = dmem->unalign_base + (dmem->phys_base - dmem->dma); 70 return 0; 71 } 72 73 /* Free queue's descriptor memory */ 74 static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem) 75 { 76 if (!dmem) 77 return; 78 79 dma_free_coherent(&nic->pdev->dev, dmem->size, 80 dmem->unalign_base, dmem->dma); 81 dmem->unalign_base = NULL; 82 dmem->base = NULL; 83 } 84 85 #define XDP_PAGE_REFCNT_REFILL 256 86 87 /* Allocate a new page or recycle one if possible 88 * 89 * We cannot optimize dma mapping here, since 90 * 1. It's only one RBDR ring for 8 Rx queues. 91 * 2. CQE_RX gives address of the buffer where pkt has been DMA'ed 92 * and not idx into RBDR ring, so can't refer to saved info. 93 * 3. There are multiple receive buffers per page 94 */ 95 static inline struct pgcache *nicvf_alloc_page(struct nicvf *nic, 96 struct rbdr *rbdr, gfp_t gfp) 97 { 98 int ref_count; 99 struct page *page = NULL; 100 struct pgcache *pgcache, *next; 101 102 /* Check if page is already allocated */ 103 pgcache = &rbdr->pgcache[rbdr->pgidx]; 104 page = pgcache->page; 105 /* Check if page can be recycled */ 106 if (page) { 107 ref_count = page_ref_count(page); 108 /* Check if this page has been used once i.e 'put_page' 109 * called after packet transmission i.e internal ref_count 110 * and page's ref_count are equal i.e page can be recycled. 111 */ 112 if (rbdr->is_xdp && (ref_count == pgcache->ref_count)) 113 pgcache->ref_count--; 114 else 115 page = NULL; 116 117 /* In non-XDP mode, page's ref_count needs to be '1' for it 118 * to be recycled. 119 */ 120 if (!rbdr->is_xdp && (ref_count != 1)) 121 page = NULL; 122 } 123 124 if (!page) { 125 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, 0); 126 if (!page) 127 return NULL; 128 129 this_cpu_inc(nic->pnicvf->drv_stats->page_alloc); 130 131 /* Check for space */ 132 if (rbdr->pgalloc >= rbdr->pgcnt) { 133 /* Page can still be used */ 134 nic->rb_page = page; 135 return NULL; 136 } 137 138 /* Save the page in page cache */ 139 pgcache->page = page; 140 pgcache->dma_addr = 0; 141 pgcache->ref_count = 0; 142 rbdr->pgalloc++; 143 } 144 145 /* Take additional page references for recycling */ 146 if (rbdr->is_xdp) { 147 /* Since there is single RBDR (i.e single core doing 148 * page recycling) per 8 Rx queues, in XDP mode adjusting 149 * page references atomically is the biggest bottleneck, so 150 * take bunch of references at a time. 151 * 152 * So here, below reference counts defer by '1'. 153 */ 154 if (!pgcache->ref_count) { 155 pgcache->ref_count = XDP_PAGE_REFCNT_REFILL; 156 page_ref_add(page, XDP_PAGE_REFCNT_REFILL); 157 } 158 } else { 159 /* In non-XDP case, single 64K page is divided across multiple 160 * receive buffers, so cost of recycling is less anyway. 161 * So we can do with just one extra reference. 162 */ 163 page_ref_add(page, 1); 164 } 165 166 rbdr->pgidx++; 167 rbdr->pgidx &= (rbdr->pgcnt - 1); 168 169 /* Prefetch refcount of next page in page cache */ 170 next = &rbdr->pgcache[rbdr->pgidx]; 171 page = next->page; 172 if (page) 173 prefetch(&page->_refcount); 174 175 return pgcache; 176 } 177 178 /* Allocate buffer for packet reception */ 179 static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr, 180 gfp_t gfp, u32 buf_len, u64 *rbuf) 181 { 182 struct pgcache *pgcache = NULL; 183 184 /* Check if request can be accomodated in previous allocated page. 185 * But in XDP mode only one buffer per page is permitted. 186 */ 187 if (!rbdr->is_xdp && nic->rb_page && 188 ((nic->rb_page_offset + buf_len) <= PAGE_SIZE)) { 189 nic->rb_pageref++; 190 goto ret; 191 } 192 193 nicvf_get_page(nic); 194 nic->rb_page = NULL; 195 196 /* Get new page, either recycled or new one */ 197 pgcache = nicvf_alloc_page(nic, rbdr, gfp); 198 if (!pgcache && !nic->rb_page) { 199 this_cpu_inc(nic->pnicvf->drv_stats->rcv_buffer_alloc_failures); 200 return -ENOMEM; 201 } 202 203 nic->rb_page_offset = 0; 204 205 /* Reserve space for header modifications by BPF program */ 206 if (rbdr->is_xdp) 207 buf_len += XDP_PACKET_HEADROOM; 208 209 /* Check if it's recycled */ 210 if (pgcache) 211 nic->rb_page = pgcache->page; 212 ret: 213 if (rbdr->is_xdp && pgcache && pgcache->dma_addr) { 214 *rbuf = pgcache->dma_addr; 215 } else { 216 /* HW will ensure data coherency, CPU sync not required */ 217 *rbuf = (u64)dma_map_page_attrs(&nic->pdev->dev, nic->rb_page, 218 nic->rb_page_offset, buf_len, 219 DMA_FROM_DEVICE, 220 DMA_ATTR_SKIP_CPU_SYNC); 221 if (dma_mapping_error(&nic->pdev->dev, (dma_addr_t)*rbuf)) { 222 if (!nic->rb_page_offset) 223 __free_pages(nic->rb_page, 0); 224 nic->rb_page = NULL; 225 return -ENOMEM; 226 } 227 if (pgcache) 228 pgcache->dma_addr = *rbuf + XDP_PACKET_HEADROOM; 229 nic->rb_page_offset += buf_len; 230 } 231 232 return 0; 233 } 234 235 /* Build skb around receive buffer */ 236 static struct sk_buff *nicvf_rb_ptr_to_skb(struct nicvf *nic, 237 u64 rb_ptr, int len) 238 { 239 void *data; 240 struct sk_buff *skb; 241 242 data = phys_to_virt(rb_ptr); 243 244 /* Now build an skb to give to stack */ 245 skb = build_skb(data, RCV_FRAG_LEN); 246 if (!skb) { 247 put_page(virt_to_page(data)); 248 return NULL; 249 } 250 251 prefetch(skb->data); 252 return skb; 253 } 254 255 /* Allocate RBDR ring and populate receive buffers */ 256 static int nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr, 257 int ring_len, int buf_size) 258 { 259 int idx; 260 u64 rbuf; 261 struct rbdr_entry_t *desc; 262 int err; 263 264 err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len, 265 sizeof(struct rbdr_entry_t), 266 NICVF_RCV_BUF_ALIGN_BYTES); 267 if (err) 268 return err; 269 270 rbdr->desc = rbdr->dmem.base; 271 /* Buffer size has to be in multiples of 128 bytes */ 272 rbdr->dma_size = buf_size; 273 rbdr->enable = true; 274 rbdr->thresh = RBDR_THRESH; 275 rbdr->head = 0; 276 rbdr->tail = 0; 277 278 /* Initialize page recycling stuff. 279 * 280 * Can't use single buffer per page especially with 64K pages. 281 * On embedded platforms i.e 81xx/83xx available memory itself 282 * is low and minimum ring size of RBDR is 8K, that takes away 283 * lots of memory. 284 * 285 * But for XDP it has to be a single buffer per page. 286 */ 287 if (!nic->pnicvf->xdp_prog) { 288 rbdr->pgcnt = ring_len / (PAGE_SIZE / buf_size); 289 rbdr->is_xdp = false; 290 } else { 291 rbdr->pgcnt = ring_len; 292 rbdr->is_xdp = true; 293 } 294 rbdr->pgcnt = roundup_pow_of_two(rbdr->pgcnt); 295 rbdr->pgcache = kzalloc(sizeof(*rbdr->pgcache) * 296 rbdr->pgcnt, GFP_KERNEL); 297 if (!rbdr->pgcache) 298 return -ENOMEM; 299 rbdr->pgidx = 0; 300 rbdr->pgalloc = 0; 301 302 nic->rb_page = NULL; 303 for (idx = 0; idx < ring_len; idx++) { 304 err = nicvf_alloc_rcv_buffer(nic, rbdr, GFP_KERNEL, 305 RCV_FRAG_LEN, &rbuf); 306 if (err) { 307 /* To free already allocated and mapped ones */ 308 rbdr->tail = idx - 1; 309 return err; 310 } 311 312 desc = GET_RBDR_DESC(rbdr, idx); 313 desc->buf_addr = rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1); 314 } 315 316 nicvf_get_page(nic); 317 318 return 0; 319 } 320 321 /* Free RBDR ring and its receive buffers */ 322 static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr) 323 { 324 int head, tail; 325 u64 buf_addr, phys_addr; 326 struct pgcache *pgcache; 327 struct rbdr_entry_t *desc; 328 329 if (!rbdr) 330 return; 331 332 rbdr->enable = false; 333 if (!rbdr->dmem.base) 334 return; 335 336 head = rbdr->head; 337 tail = rbdr->tail; 338 339 /* Release page references */ 340 while (head != tail) { 341 desc = GET_RBDR_DESC(rbdr, head); 342 buf_addr = desc->buf_addr; 343 phys_addr = nicvf_iova_to_phys(nic, buf_addr); 344 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN, 345 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 346 if (phys_addr) 347 put_page(virt_to_page(phys_to_virt(phys_addr))); 348 head++; 349 head &= (rbdr->dmem.q_len - 1); 350 } 351 /* Release buffer of tail desc */ 352 desc = GET_RBDR_DESC(rbdr, tail); 353 buf_addr = desc->buf_addr; 354 phys_addr = nicvf_iova_to_phys(nic, buf_addr); 355 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN, 356 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 357 if (phys_addr) 358 put_page(virt_to_page(phys_to_virt(phys_addr))); 359 360 /* Sync page cache info */ 361 smp_rmb(); 362 363 /* Release additional page references held for recycling */ 364 head = 0; 365 while (head < rbdr->pgcnt) { 366 pgcache = &rbdr->pgcache[head]; 367 if (pgcache->page && page_ref_count(pgcache->page) != 0) { 368 if (!rbdr->is_xdp) { 369 put_page(pgcache->page); 370 continue; 371 } 372 page_ref_sub(pgcache->page, pgcache->ref_count - 1); 373 put_page(pgcache->page); 374 } 375 head++; 376 } 377 378 /* Free RBDR ring */ 379 nicvf_free_q_desc_mem(nic, &rbdr->dmem); 380 } 381 382 /* Refill receive buffer descriptors with new buffers. 383 */ 384 static void nicvf_refill_rbdr(struct nicvf *nic, gfp_t gfp) 385 { 386 struct queue_set *qs = nic->qs; 387 int rbdr_idx = qs->rbdr_cnt; 388 int tail, qcount; 389 int refill_rb_cnt; 390 struct rbdr *rbdr; 391 struct rbdr_entry_t *desc; 392 u64 rbuf; 393 int new_rb = 0; 394 395 refill: 396 if (!rbdr_idx) 397 return; 398 rbdr_idx--; 399 rbdr = &qs->rbdr[rbdr_idx]; 400 /* Check if it's enabled */ 401 if (!rbdr->enable) 402 goto next_rbdr; 403 404 /* Get no of desc's to be refilled */ 405 qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx); 406 qcount &= 0x7FFFF; 407 /* Doorbell can be ringed with a max of ring size minus 1 */ 408 if (qcount >= (qs->rbdr_len - 1)) 409 goto next_rbdr; 410 else 411 refill_rb_cnt = qs->rbdr_len - qcount - 1; 412 413 /* Sync page cache info */ 414 smp_rmb(); 415 416 /* Start filling descs from tail */ 417 tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3; 418 while (refill_rb_cnt) { 419 tail++; 420 tail &= (rbdr->dmem.q_len - 1); 421 422 if (nicvf_alloc_rcv_buffer(nic, rbdr, gfp, RCV_FRAG_LEN, &rbuf)) 423 break; 424 425 desc = GET_RBDR_DESC(rbdr, tail); 426 desc->buf_addr = rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1); 427 refill_rb_cnt--; 428 new_rb++; 429 } 430 431 nicvf_get_page(nic); 432 433 /* make sure all memory stores are done before ringing doorbell */ 434 smp_wmb(); 435 436 /* Check if buffer allocation failed */ 437 if (refill_rb_cnt) 438 nic->rb_alloc_fail = true; 439 else 440 nic->rb_alloc_fail = false; 441 442 /* Notify HW */ 443 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, 444 rbdr_idx, new_rb); 445 next_rbdr: 446 /* Re-enable RBDR interrupts only if buffer allocation is success */ 447 if (!nic->rb_alloc_fail && rbdr->enable && 448 netif_running(nic->pnicvf->netdev)) 449 nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx); 450 451 if (rbdr_idx) 452 goto refill; 453 } 454 455 /* Alloc rcv buffers in non-atomic mode for better success */ 456 void nicvf_rbdr_work(struct work_struct *work) 457 { 458 struct nicvf *nic = container_of(work, struct nicvf, rbdr_work.work); 459 460 nicvf_refill_rbdr(nic, GFP_KERNEL); 461 if (nic->rb_alloc_fail) 462 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10)); 463 else 464 nic->rb_work_scheduled = false; 465 } 466 467 /* In Softirq context, alloc rcv buffers in atomic mode */ 468 void nicvf_rbdr_task(unsigned long data) 469 { 470 struct nicvf *nic = (struct nicvf *)data; 471 472 nicvf_refill_rbdr(nic, GFP_ATOMIC); 473 if (nic->rb_alloc_fail) { 474 nic->rb_work_scheduled = true; 475 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10)); 476 } 477 } 478 479 /* Initialize completion queue */ 480 static int nicvf_init_cmp_queue(struct nicvf *nic, 481 struct cmp_queue *cq, int q_len) 482 { 483 int err; 484 485 err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE, 486 NICVF_CQ_BASE_ALIGN_BYTES); 487 if (err) 488 return err; 489 490 cq->desc = cq->dmem.base; 491 cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH; 492 nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1; 493 494 return 0; 495 } 496 497 static void nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq) 498 { 499 if (!cq) 500 return; 501 if (!cq->dmem.base) 502 return; 503 504 nicvf_free_q_desc_mem(nic, &cq->dmem); 505 } 506 507 /* Initialize transmit queue */ 508 static int nicvf_init_snd_queue(struct nicvf *nic, 509 struct snd_queue *sq, int q_len, int qidx) 510 { 511 int err; 512 513 err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE, 514 NICVF_SQ_BASE_ALIGN_BYTES); 515 if (err) 516 return err; 517 518 sq->desc = sq->dmem.base; 519 sq->skbuff = kcalloc(q_len, sizeof(u64), GFP_KERNEL); 520 if (!sq->skbuff) 521 return -ENOMEM; 522 523 sq->head = 0; 524 sq->tail = 0; 525 sq->thresh = SND_QUEUE_THRESH; 526 527 /* Check if this SQ is a XDP TX queue */ 528 if (nic->sqs_mode) 529 qidx += ((nic->sqs_id + 1) * MAX_SND_QUEUES_PER_QS); 530 if (qidx < nic->pnicvf->xdp_tx_queues) { 531 /* Alloc memory to save page pointers for XDP_TX */ 532 sq->xdp_page = kcalloc(q_len, sizeof(u64), GFP_KERNEL); 533 if (!sq->xdp_page) 534 return -ENOMEM; 535 sq->xdp_desc_cnt = 0; 536 sq->xdp_free_cnt = q_len - 1; 537 sq->is_xdp = true; 538 } else { 539 sq->xdp_page = NULL; 540 sq->xdp_desc_cnt = 0; 541 sq->xdp_free_cnt = 0; 542 sq->is_xdp = false; 543 544 atomic_set(&sq->free_cnt, q_len - 1); 545 546 /* Preallocate memory for TSO segment's header */ 547 sq->tso_hdrs = dma_alloc_coherent(&nic->pdev->dev, 548 q_len * TSO_HEADER_SIZE, 549 &sq->tso_hdrs_phys, 550 GFP_KERNEL); 551 if (!sq->tso_hdrs) 552 return -ENOMEM; 553 } 554 555 return 0; 556 } 557 558 void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq, 559 int hdr_sqe, u8 subdesc_cnt) 560 { 561 u8 idx; 562 struct sq_gather_subdesc *gather; 563 564 /* Unmap DMA mapped skb data buffers */ 565 for (idx = 0; idx < subdesc_cnt; idx++) { 566 hdr_sqe++; 567 hdr_sqe &= (sq->dmem.q_len - 1); 568 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, hdr_sqe); 569 /* HW will ensure data coherency, CPU sync not required */ 570 dma_unmap_page_attrs(&nic->pdev->dev, gather->addr, 571 gather->size, DMA_TO_DEVICE, 572 DMA_ATTR_SKIP_CPU_SYNC); 573 } 574 } 575 576 static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) 577 { 578 struct sk_buff *skb; 579 struct page *page; 580 struct sq_hdr_subdesc *hdr; 581 struct sq_hdr_subdesc *tso_sqe; 582 583 if (!sq) 584 return; 585 if (!sq->dmem.base) 586 return; 587 588 if (sq->tso_hdrs) 589 dma_free_coherent(&nic->pdev->dev, 590 sq->dmem.q_len * TSO_HEADER_SIZE, 591 sq->tso_hdrs, sq->tso_hdrs_phys); 592 593 /* Free pending skbs in the queue */ 594 smp_rmb(); 595 while (sq->head != sq->tail) { 596 skb = (struct sk_buff *)sq->skbuff[sq->head]; 597 if (!skb || !sq->xdp_page) 598 goto next; 599 600 page = (struct page *)sq->xdp_page[sq->head]; 601 if (!page) 602 goto next; 603 else 604 put_page(page); 605 606 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head); 607 /* Check for dummy descriptor used for HW TSO offload on 88xx */ 608 if (hdr->dont_send) { 609 /* Get actual TSO descriptors and unmap them */ 610 tso_sqe = 611 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2); 612 nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2, 613 tso_sqe->subdesc_cnt); 614 } else { 615 nicvf_unmap_sndq_buffers(nic, sq, sq->head, 616 hdr->subdesc_cnt); 617 } 618 if (skb) 619 dev_kfree_skb_any(skb); 620 next: 621 sq->head++; 622 sq->head &= (sq->dmem.q_len - 1); 623 } 624 kfree(sq->skbuff); 625 kfree(sq->xdp_page); 626 nicvf_free_q_desc_mem(nic, &sq->dmem); 627 } 628 629 static void nicvf_reclaim_snd_queue(struct nicvf *nic, 630 struct queue_set *qs, int qidx) 631 { 632 /* Disable send queue */ 633 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0); 634 /* Check if SQ is stopped */ 635 if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01)) 636 return; 637 /* Reset send queue */ 638 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); 639 } 640 641 static void nicvf_reclaim_rcv_queue(struct nicvf *nic, 642 struct queue_set *qs, int qidx) 643 { 644 union nic_mbx mbx = {}; 645 646 /* Make sure all packets in the pipeline are written back into mem */ 647 mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC; 648 nicvf_send_msg_to_pf(nic, &mbx); 649 } 650 651 static void nicvf_reclaim_cmp_queue(struct nicvf *nic, 652 struct queue_set *qs, int qidx) 653 { 654 /* Disable timer threshold (doesn't get reset upon CQ reset */ 655 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0); 656 /* Disable completion queue */ 657 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0); 658 /* Reset completion queue */ 659 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); 660 } 661 662 static void nicvf_reclaim_rbdr(struct nicvf *nic, 663 struct rbdr *rbdr, int qidx) 664 { 665 u64 tmp, fifo_state; 666 int timeout = 10; 667 668 /* Save head and tail pointers for feeing up buffers */ 669 rbdr->head = nicvf_queue_reg_read(nic, 670 NIC_QSET_RBDR_0_1_HEAD, 671 qidx) >> 3; 672 rbdr->tail = nicvf_queue_reg_read(nic, 673 NIC_QSET_RBDR_0_1_TAIL, 674 qidx) >> 3; 675 676 /* If RBDR FIFO is in 'FAIL' state then do a reset first 677 * before relaiming. 678 */ 679 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx); 680 if (((fifo_state >> 62) & 0x03) == 0x3) 681 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 682 qidx, NICVF_RBDR_RESET); 683 684 /* Disable RBDR */ 685 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0); 686 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) 687 return; 688 while (1) { 689 tmp = nicvf_queue_reg_read(nic, 690 NIC_QSET_RBDR_0_1_PREFETCH_STATUS, 691 qidx); 692 if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF)) 693 break; 694 usleep_range(1000, 2000); 695 timeout--; 696 if (!timeout) { 697 netdev_err(nic->netdev, 698 "Failed polling on prefetch status\n"); 699 return; 700 } 701 } 702 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 703 qidx, NICVF_RBDR_RESET); 704 705 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02)) 706 return; 707 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00); 708 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00)) 709 return; 710 } 711 712 void nicvf_config_vlan_stripping(struct nicvf *nic, netdev_features_t features) 713 { 714 u64 rq_cfg; 715 int sqs; 716 717 rq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_RQ_GEN_CFG, 0); 718 719 /* Enable first VLAN stripping */ 720 if (features & NETIF_F_HW_VLAN_CTAG_RX) 721 rq_cfg |= (1ULL << 25); 722 else 723 rq_cfg &= ~(1ULL << 25); 724 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, rq_cfg); 725 726 /* Configure Secondary Qsets, if any */ 727 for (sqs = 0; sqs < nic->sqs_count; sqs++) 728 if (nic->snicvf[sqs]) 729 nicvf_queue_reg_write(nic->snicvf[sqs], 730 NIC_QSET_RQ_GEN_CFG, 0, rq_cfg); 731 } 732 733 static void nicvf_reset_rcv_queue_stats(struct nicvf *nic) 734 { 735 union nic_mbx mbx = {}; 736 737 /* Reset all RQ/SQ and VF stats */ 738 mbx.reset_stat.msg = NIC_MBOX_MSG_RESET_STAT_COUNTER; 739 mbx.reset_stat.rx_stat_mask = 0x3FFF; 740 mbx.reset_stat.tx_stat_mask = 0x1F; 741 mbx.reset_stat.rq_stat_mask = 0xFFFF; 742 mbx.reset_stat.sq_stat_mask = 0xFFFF; 743 nicvf_send_msg_to_pf(nic, &mbx); 744 } 745 746 /* Configures receive queue */ 747 static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs, 748 int qidx, bool enable) 749 { 750 union nic_mbx mbx = {}; 751 struct rcv_queue *rq; 752 struct rq_cfg rq_cfg; 753 754 rq = &qs->rq[qidx]; 755 rq->enable = enable; 756 757 /* Disable receive queue */ 758 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0); 759 760 if (!rq->enable) { 761 nicvf_reclaim_rcv_queue(nic, qs, qidx); 762 return; 763 } 764 765 rq->cq_qs = qs->vnic_id; 766 rq->cq_idx = qidx; 767 rq->start_rbdr_qs = qs->vnic_id; 768 rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1; 769 rq->cont_rbdr_qs = qs->vnic_id; 770 rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1; 771 /* all writes of RBDR data to be loaded into L2 Cache as well*/ 772 rq->caching = 1; 773 774 /* Send a mailbox msg to PF to config RQ */ 775 mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG; 776 mbx.rq.qs_num = qs->vnic_id; 777 mbx.rq.rq_num = qidx; 778 mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) | 779 (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) | 780 (rq->cont_qs_rbdr_idx << 8) | 781 (rq->start_rbdr_qs << 1) | (rq->start_qs_rbdr_idx); 782 nicvf_send_msg_to_pf(nic, &mbx); 783 784 mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG; 785 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) | 786 (RQ_PASS_RBDR_LVL << 16) | (RQ_PASS_CQ_LVL << 8) | 787 (qs->vnic_id << 0); 788 nicvf_send_msg_to_pf(nic, &mbx); 789 790 /* RQ drop config 791 * Enable CQ drop to reserve sufficient CQEs for all tx packets 792 */ 793 mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG; 794 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) | 795 (RQ_PASS_RBDR_LVL << 40) | (RQ_DROP_RBDR_LVL << 32) | 796 (RQ_PASS_CQ_LVL << 16) | (RQ_DROP_CQ_LVL << 8); 797 nicvf_send_msg_to_pf(nic, &mbx); 798 799 if (!nic->sqs_mode && (qidx == 0)) { 800 /* Enable checking L3/L4 length and TCP/UDP checksums 801 * Also allow IPv6 pkts with zero UDP checksum. 802 */ 803 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 804 (BIT(24) | BIT(23) | BIT(21) | BIT(20))); 805 nicvf_config_vlan_stripping(nic, nic->netdev->features); 806 } 807 808 /* Enable Receive queue */ 809 memset(&rq_cfg, 0, sizeof(struct rq_cfg)); 810 rq_cfg.ena = 1; 811 rq_cfg.tcp_ena = 0; 812 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg); 813 } 814 815 /* Configures completion queue */ 816 void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, 817 int qidx, bool enable) 818 { 819 struct cmp_queue *cq; 820 struct cq_cfg cq_cfg; 821 822 cq = &qs->cq[qidx]; 823 cq->enable = enable; 824 825 if (!cq->enable) { 826 nicvf_reclaim_cmp_queue(nic, qs, qidx); 827 return; 828 } 829 830 /* Reset completion queue */ 831 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET); 832 833 if (!cq->enable) 834 return; 835 836 spin_lock_init(&cq->lock); 837 /* Set completion queue base address */ 838 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE, 839 qidx, (u64)(cq->dmem.phys_base)); 840 841 /* Enable Completion queue */ 842 memset(&cq_cfg, 0, sizeof(struct cq_cfg)); 843 cq_cfg.ena = 1; 844 cq_cfg.reset = 0; 845 cq_cfg.caching = 0; 846 cq_cfg.qsize = ilog2(qs->cq_len >> 10); 847 cq_cfg.avg_con = 0; 848 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(u64 *)&cq_cfg); 849 850 /* Set threshold value for interrupt generation */ 851 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh); 852 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, 853 qidx, CMP_QUEUE_TIMER_THRESH); 854 } 855 856 /* Configures transmit queue */ 857 static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs, 858 int qidx, bool enable) 859 { 860 union nic_mbx mbx = {}; 861 struct snd_queue *sq; 862 struct sq_cfg sq_cfg; 863 864 sq = &qs->sq[qidx]; 865 sq->enable = enable; 866 867 if (!sq->enable) { 868 nicvf_reclaim_snd_queue(nic, qs, qidx); 869 return; 870 } 871 872 /* Reset send queue */ 873 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET); 874 875 sq->cq_qs = qs->vnic_id; 876 sq->cq_idx = qidx; 877 878 /* Send a mailbox msg to PF to config SQ */ 879 mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG; 880 mbx.sq.qs_num = qs->vnic_id; 881 mbx.sq.sq_num = qidx; 882 mbx.sq.sqs_mode = nic->sqs_mode; 883 mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx; 884 nicvf_send_msg_to_pf(nic, &mbx); 885 886 /* Set queue base address */ 887 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, 888 qidx, (u64)(sq->dmem.phys_base)); 889 890 /* Enable send queue & set queue size */ 891 memset(&sq_cfg, 0, sizeof(struct sq_cfg)); 892 sq_cfg.ena = 1; 893 sq_cfg.reset = 0; 894 sq_cfg.ldwb = 0; 895 sq_cfg.qsize = ilog2(qs->sq_len >> 10); 896 sq_cfg.tstmp_bgx_intf = 0; 897 /* CQ's level at which HW will stop processing SQEs to avoid 898 * transmitting a pkt with no space in CQ to post CQE_TX. 899 */ 900 sq_cfg.cq_limit = (CMP_QUEUE_PIPELINE_RSVD * 256) / qs->cq_len; 901 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(u64 *)&sq_cfg); 902 903 /* Set threshold value for interrupt generation */ 904 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh); 905 906 /* Set queue:cpu affinity for better load distribution */ 907 if (cpu_online(qidx)) { 908 cpumask_set_cpu(qidx, &sq->affinity_mask); 909 netif_set_xps_queue(nic->netdev, 910 &sq->affinity_mask, qidx); 911 } 912 } 913 914 /* Configures receive buffer descriptor ring */ 915 static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs, 916 int qidx, bool enable) 917 { 918 struct rbdr *rbdr; 919 struct rbdr_cfg rbdr_cfg; 920 921 rbdr = &qs->rbdr[qidx]; 922 nicvf_reclaim_rbdr(nic, rbdr, qidx); 923 if (!enable) 924 return; 925 926 /* Set descriptor base address */ 927 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE, 928 qidx, (u64)(rbdr->dmem.phys_base)); 929 930 /* Enable RBDR & set queue size */ 931 /* Buffer size should be in multiples of 128 bytes */ 932 memset(&rbdr_cfg, 0, sizeof(struct rbdr_cfg)); 933 rbdr_cfg.ena = 1; 934 rbdr_cfg.reset = 0; 935 rbdr_cfg.ldwb = 0; 936 rbdr_cfg.qsize = RBDR_SIZE; 937 rbdr_cfg.avg_con = 0; 938 rbdr_cfg.lines = rbdr->dma_size / 128; 939 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, 940 qidx, *(u64 *)&rbdr_cfg); 941 942 /* Notify HW */ 943 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, 944 qidx, qs->rbdr_len - 1); 945 946 /* Set threshold value for interrupt generation */ 947 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH, 948 qidx, rbdr->thresh - 1); 949 } 950 951 /* Requests PF to assign and enable Qset */ 952 void nicvf_qset_config(struct nicvf *nic, bool enable) 953 { 954 union nic_mbx mbx = {}; 955 struct queue_set *qs = nic->qs; 956 struct qs_cfg *qs_cfg; 957 958 if (!qs) { 959 netdev_warn(nic->netdev, 960 "Qset is still not allocated, don't init queues\n"); 961 return; 962 } 963 964 qs->enable = enable; 965 qs->vnic_id = nic->vf_id; 966 967 /* Send a mailbox msg to PF to config Qset */ 968 mbx.qs.msg = NIC_MBOX_MSG_QS_CFG; 969 mbx.qs.num = qs->vnic_id; 970 mbx.qs.sqs_count = nic->sqs_count; 971 972 mbx.qs.cfg = 0; 973 qs_cfg = (struct qs_cfg *)&mbx.qs.cfg; 974 if (qs->enable) { 975 qs_cfg->ena = 1; 976 #ifdef __BIG_ENDIAN 977 qs_cfg->be = 1; 978 #endif 979 qs_cfg->vnic = qs->vnic_id; 980 } 981 nicvf_send_msg_to_pf(nic, &mbx); 982 } 983 984 static void nicvf_free_resources(struct nicvf *nic) 985 { 986 int qidx; 987 struct queue_set *qs = nic->qs; 988 989 /* Free receive buffer descriptor ring */ 990 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 991 nicvf_free_rbdr(nic, &qs->rbdr[qidx]); 992 993 /* Free completion queue */ 994 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 995 nicvf_free_cmp_queue(nic, &qs->cq[qidx]); 996 997 /* Free send queue */ 998 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 999 nicvf_free_snd_queue(nic, &qs->sq[qidx]); 1000 } 1001 1002 static int nicvf_alloc_resources(struct nicvf *nic) 1003 { 1004 int qidx; 1005 struct queue_set *qs = nic->qs; 1006 1007 /* Alloc receive buffer descriptor ring */ 1008 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1009 if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len, 1010 DMA_BUFFER_LEN)) 1011 goto alloc_fail; 1012 } 1013 1014 /* Alloc send queue */ 1015 for (qidx = 0; qidx < qs->sq_cnt; qidx++) { 1016 if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len, qidx)) 1017 goto alloc_fail; 1018 } 1019 1020 /* Alloc completion queue */ 1021 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1022 if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len)) 1023 goto alloc_fail; 1024 } 1025 1026 return 0; 1027 alloc_fail: 1028 nicvf_free_resources(nic); 1029 return -ENOMEM; 1030 } 1031 1032 int nicvf_set_qset_resources(struct nicvf *nic) 1033 { 1034 struct queue_set *qs; 1035 1036 qs = devm_kzalloc(&nic->pdev->dev, sizeof(*qs), GFP_KERNEL); 1037 if (!qs) 1038 return -ENOMEM; 1039 nic->qs = qs; 1040 1041 /* Set count of each queue */ 1042 qs->rbdr_cnt = DEFAULT_RBDR_CNT; 1043 qs->rq_cnt = min_t(u8, MAX_RCV_QUEUES_PER_QS, num_online_cpus()); 1044 qs->sq_cnt = min_t(u8, MAX_SND_QUEUES_PER_QS, num_online_cpus()); 1045 qs->cq_cnt = max_t(u8, qs->rq_cnt, qs->sq_cnt); 1046 1047 /* Set queue lengths */ 1048 qs->rbdr_len = RCV_BUF_COUNT; 1049 qs->sq_len = SND_QUEUE_LEN; 1050 qs->cq_len = CMP_QUEUE_LEN; 1051 1052 nic->rx_queues = qs->rq_cnt; 1053 nic->tx_queues = qs->sq_cnt; 1054 nic->xdp_tx_queues = 0; 1055 1056 return 0; 1057 } 1058 1059 int nicvf_config_data_transfer(struct nicvf *nic, bool enable) 1060 { 1061 bool disable = false; 1062 struct queue_set *qs = nic->qs; 1063 struct queue_set *pqs = nic->pnicvf->qs; 1064 int qidx; 1065 1066 if (!qs) 1067 return 0; 1068 1069 /* Take primary VF's queue lengths. 1070 * This is needed to take queue lengths set from ethtool 1071 * into consideration. 1072 */ 1073 if (nic->sqs_mode && pqs) { 1074 qs->cq_len = pqs->cq_len; 1075 qs->sq_len = pqs->sq_len; 1076 } 1077 1078 if (enable) { 1079 if (nicvf_alloc_resources(nic)) 1080 return -ENOMEM; 1081 1082 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1083 nicvf_snd_queue_config(nic, qs, qidx, enable); 1084 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1085 nicvf_cmp_queue_config(nic, qs, qidx, enable); 1086 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1087 nicvf_rbdr_config(nic, qs, qidx, enable); 1088 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1089 nicvf_rcv_queue_config(nic, qs, qidx, enable); 1090 } else { 1091 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1092 nicvf_rcv_queue_config(nic, qs, qidx, disable); 1093 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1094 nicvf_rbdr_config(nic, qs, qidx, disable); 1095 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1096 nicvf_snd_queue_config(nic, qs, qidx, disable); 1097 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1098 nicvf_cmp_queue_config(nic, qs, qidx, disable); 1099 1100 nicvf_free_resources(nic); 1101 } 1102 1103 /* Reset RXQ's stats. 1104 * SQ's stats will get reset automatically once SQ is reset. 1105 */ 1106 nicvf_reset_rcv_queue_stats(nic); 1107 1108 return 0; 1109 } 1110 1111 /* Get a free desc from SQ 1112 * returns descriptor ponter & descriptor number 1113 */ 1114 static inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt) 1115 { 1116 int qentry; 1117 1118 qentry = sq->tail; 1119 if (!sq->is_xdp) 1120 atomic_sub(desc_cnt, &sq->free_cnt); 1121 else 1122 sq->xdp_free_cnt -= desc_cnt; 1123 sq->tail += desc_cnt; 1124 sq->tail &= (sq->dmem.q_len - 1); 1125 1126 return qentry; 1127 } 1128 1129 /* Rollback to previous tail pointer when descriptors not used */ 1130 static inline void nicvf_rollback_sq_desc(struct snd_queue *sq, 1131 int qentry, int desc_cnt) 1132 { 1133 sq->tail = qentry; 1134 atomic_add(desc_cnt, &sq->free_cnt); 1135 } 1136 1137 /* Free descriptor back to SQ for future use */ 1138 void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt) 1139 { 1140 if (!sq->is_xdp) 1141 atomic_add(desc_cnt, &sq->free_cnt); 1142 else 1143 sq->xdp_free_cnt += desc_cnt; 1144 sq->head += desc_cnt; 1145 sq->head &= (sq->dmem.q_len - 1); 1146 } 1147 1148 static inline int nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry) 1149 { 1150 qentry++; 1151 qentry &= (sq->dmem.q_len - 1); 1152 return qentry; 1153 } 1154 1155 void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx) 1156 { 1157 u64 sq_cfg; 1158 1159 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); 1160 sq_cfg |= NICVF_SQ_EN; 1161 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); 1162 /* Ring doorbell so that H/W restarts processing SQEs */ 1163 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0); 1164 } 1165 1166 void nicvf_sq_disable(struct nicvf *nic, int qidx) 1167 { 1168 u64 sq_cfg; 1169 1170 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx); 1171 sq_cfg &= ~NICVF_SQ_EN; 1172 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg); 1173 } 1174 1175 void nicvf_sq_free_used_descs(struct net_device *netdev, struct snd_queue *sq, 1176 int qidx) 1177 { 1178 u64 head, tail; 1179 struct sk_buff *skb; 1180 struct nicvf *nic = netdev_priv(netdev); 1181 struct sq_hdr_subdesc *hdr; 1182 1183 head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4; 1184 tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4; 1185 while (sq->head != head) { 1186 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head); 1187 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) { 1188 nicvf_put_sq_desc(sq, 1); 1189 continue; 1190 } 1191 skb = (struct sk_buff *)sq->skbuff[sq->head]; 1192 if (skb) 1193 dev_kfree_skb_any(skb); 1194 atomic64_add(1, (atomic64_t *)&netdev->stats.tx_packets); 1195 atomic64_add(hdr->tot_len, 1196 (atomic64_t *)&netdev->stats.tx_bytes); 1197 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 1198 } 1199 } 1200 1201 /* XDP Transmit APIs */ 1202 void nicvf_xdp_sq_doorbell(struct nicvf *nic, 1203 struct snd_queue *sq, int sq_num) 1204 { 1205 if (!sq->xdp_desc_cnt) 1206 return; 1207 1208 /* make sure all memory stores are done before ringing doorbell */ 1209 wmb(); 1210 1211 /* Inform HW to xmit all TSO segments */ 1212 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, 1213 sq_num, sq->xdp_desc_cnt); 1214 sq->xdp_desc_cnt = 0; 1215 } 1216 1217 static inline void 1218 nicvf_xdp_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry, 1219 int subdesc_cnt, u64 data, int len) 1220 { 1221 struct sq_hdr_subdesc *hdr; 1222 1223 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1224 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1225 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1226 hdr->subdesc_cnt = subdesc_cnt; 1227 hdr->tot_len = len; 1228 hdr->post_cqe = 1; 1229 sq->xdp_page[qentry] = (u64)virt_to_page((void *)data); 1230 } 1231 1232 int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq, 1233 u64 bufaddr, u64 dma_addr, u16 len) 1234 { 1235 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT; 1236 int qentry; 1237 1238 if (subdesc_cnt > sq->xdp_free_cnt) 1239 return 0; 1240 1241 qentry = nicvf_get_sq_desc(sq, subdesc_cnt); 1242 1243 nicvf_xdp_sq_add_hdr_subdesc(sq, qentry, subdesc_cnt - 1, bufaddr, len); 1244 1245 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1246 nicvf_sq_add_gather_subdesc(sq, qentry, len, dma_addr); 1247 1248 sq->xdp_desc_cnt += subdesc_cnt; 1249 1250 return 1; 1251 } 1252 1253 /* Calculate no of SQ subdescriptors needed to transmit all 1254 * segments of this TSO packet. 1255 * Taken from 'Tilera network driver' with a minor modification. 1256 */ 1257 static int nicvf_tso_count_subdescs(struct sk_buff *skb) 1258 { 1259 struct skb_shared_info *sh = skb_shinfo(skb); 1260 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1261 unsigned int data_len = skb->len - sh_len; 1262 unsigned int p_len = sh->gso_size; 1263 long f_id = -1; /* id of the current fragment */ 1264 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */ 1265 long f_used = 0; /* bytes used from the current fragment */ 1266 long n; /* size of the current piece of payload */ 1267 int num_edescs = 0; 1268 int segment; 1269 1270 for (segment = 0; segment < sh->gso_segs; segment++) { 1271 unsigned int p_used = 0; 1272 1273 /* One edesc for header and for each piece of the payload. */ 1274 for (num_edescs++; p_used < p_len; num_edescs++) { 1275 /* Advance as needed. */ 1276 while (f_used >= f_size) { 1277 f_id++; 1278 f_size = skb_frag_size(&sh->frags[f_id]); 1279 f_used = 0; 1280 } 1281 1282 /* Use bytes from the current fragment. */ 1283 n = p_len - p_used; 1284 if (n > f_size - f_used) 1285 n = f_size - f_used; 1286 f_used += n; 1287 p_used += n; 1288 } 1289 1290 /* The last segment may be less than gso_size. */ 1291 data_len -= p_len; 1292 if (data_len < p_len) 1293 p_len = data_len; 1294 } 1295 1296 /* '+ gso_segs' for SQ_HDR_SUDESCs for each segment */ 1297 return num_edescs + sh->gso_segs; 1298 } 1299 1300 #define POST_CQE_DESC_COUNT 2 1301 1302 /* Get the number of SQ descriptors needed to xmit this skb */ 1303 static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb) 1304 { 1305 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT; 1306 1307 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) { 1308 subdesc_cnt = nicvf_tso_count_subdescs(skb); 1309 return subdesc_cnt; 1310 } 1311 1312 /* Dummy descriptors to get TSO pkt completion notification */ 1313 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size) 1314 subdesc_cnt += POST_CQE_DESC_COUNT; 1315 1316 if (skb_shinfo(skb)->nr_frags) 1317 subdesc_cnt += skb_shinfo(skb)->nr_frags; 1318 1319 return subdesc_cnt; 1320 } 1321 1322 /* Add SQ HEADER subdescriptor. 1323 * First subdescriptor for every send descriptor. 1324 */ 1325 static inline void 1326 nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry, 1327 int subdesc_cnt, struct sk_buff *skb, int len) 1328 { 1329 int proto; 1330 struct sq_hdr_subdesc *hdr; 1331 union { 1332 struct iphdr *v4; 1333 struct ipv6hdr *v6; 1334 unsigned char *hdr; 1335 } ip; 1336 1337 ip.hdr = skb_network_header(skb); 1338 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1339 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1340 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1341 1342 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size) { 1343 /* post_cqe = 0, to avoid HW posting a CQE for every TSO 1344 * segment transmitted on 88xx. 1345 */ 1346 hdr->subdesc_cnt = subdesc_cnt - POST_CQE_DESC_COUNT; 1347 } else { 1348 sq->skbuff[qentry] = (u64)skb; 1349 /* Enable notification via CQE after processing SQE */ 1350 hdr->post_cqe = 1; 1351 /* No of subdescriptors following this */ 1352 hdr->subdesc_cnt = subdesc_cnt; 1353 } 1354 hdr->tot_len = len; 1355 1356 /* Offload checksum calculation to HW */ 1357 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1358 hdr->l3_offset = skb_network_offset(skb); 1359 hdr->l4_offset = skb_transport_offset(skb); 1360 1361 proto = (ip.v4->version == 4) ? ip.v4->protocol : 1362 ip.v6->nexthdr; 1363 1364 switch (proto) { 1365 case IPPROTO_TCP: 1366 hdr->csum_l4 = SEND_L4_CSUM_TCP; 1367 break; 1368 case IPPROTO_UDP: 1369 hdr->csum_l4 = SEND_L4_CSUM_UDP; 1370 break; 1371 case IPPROTO_SCTP: 1372 hdr->csum_l4 = SEND_L4_CSUM_SCTP; 1373 break; 1374 } 1375 } 1376 1377 if (nic->hw_tso && skb_shinfo(skb)->gso_size) { 1378 hdr->tso = 1; 1379 hdr->tso_start = skb_transport_offset(skb) + tcp_hdrlen(skb); 1380 hdr->tso_max_paysize = skb_shinfo(skb)->gso_size; 1381 /* For non-tunneled pkts, point this to L2 ethertype */ 1382 hdr->inner_l3_offset = skb_network_offset(skb) - 2; 1383 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso); 1384 } 1385 } 1386 1387 /* SQ GATHER subdescriptor 1388 * Must follow HDR descriptor 1389 */ 1390 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry, 1391 int size, u64 data) 1392 { 1393 struct sq_gather_subdesc *gather; 1394 1395 qentry &= (sq->dmem.q_len - 1); 1396 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry); 1397 1398 memset(gather, 0, SND_QUEUE_DESC_SIZE); 1399 gather->subdesc_type = SQ_DESC_TYPE_GATHER; 1400 gather->ld_type = NIC_SEND_LD_TYPE_E_LDD; 1401 gather->size = size; 1402 gather->addr = data; 1403 } 1404 1405 /* Add HDR + IMMEDIATE subdescriptors right after descriptors of a TSO 1406 * packet so that a CQE is posted as a notifation for transmission of 1407 * TSO packet. 1408 */ 1409 static inline void nicvf_sq_add_cqe_subdesc(struct snd_queue *sq, int qentry, 1410 int tso_sqe, struct sk_buff *skb) 1411 { 1412 struct sq_imm_subdesc *imm; 1413 struct sq_hdr_subdesc *hdr; 1414 1415 sq->skbuff[qentry] = (u64)skb; 1416 1417 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry); 1418 memset(hdr, 0, SND_QUEUE_DESC_SIZE); 1419 hdr->subdesc_type = SQ_DESC_TYPE_HEADER; 1420 /* Enable notification via CQE after processing SQE */ 1421 hdr->post_cqe = 1; 1422 /* There is no packet to transmit here */ 1423 hdr->dont_send = 1; 1424 hdr->subdesc_cnt = POST_CQE_DESC_COUNT - 1; 1425 hdr->tot_len = 1; 1426 /* Actual TSO header SQE index, needed for cleanup */ 1427 hdr->rsvd2 = tso_sqe; 1428 1429 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1430 imm = (struct sq_imm_subdesc *)GET_SQ_DESC(sq, qentry); 1431 memset(imm, 0, SND_QUEUE_DESC_SIZE); 1432 imm->subdesc_type = SQ_DESC_TYPE_IMMEDIATE; 1433 imm->len = 1; 1434 } 1435 1436 static inline void nicvf_sq_doorbell(struct nicvf *nic, struct sk_buff *skb, 1437 int sq_num, int desc_cnt) 1438 { 1439 struct netdev_queue *txq; 1440 1441 txq = netdev_get_tx_queue(nic->pnicvf->netdev, 1442 skb_get_queue_mapping(skb)); 1443 1444 netdev_tx_sent_queue(txq, skb->len); 1445 1446 /* make sure all memory stores are done before ringing doorbell */ 1447 smp_wmb(); 1448 1449 /* Inform HW to xmit all TSO segments */ 1450 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, 1451 sq_num, desc_cnt); 1452 } 1453 1454 /* Segment a TSO packet into 'gso_size' segments and append 1455 * them to SQ for transfer 1456 */ 1457 static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq, 1458 int sq_num, int qentry, struct sk_buff *skb) 1459 { 1460 struct tso_t tso; 1461 int seg_subdescs = 0, desc_cnt = 0; 1462 int seg_len, total_len, data_left; 1463 int hdr_qentry = qentry; 1464 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1465 1466 tso_start(skb, &tso); 1467 total_len = skb->len - hdr_len; 1468 while (total_len > 0) { 1469 char *hdr; 1470 1471 /* Save Qentry for adding HDR_SUBDESC at the end */ 1472 hdr_qentry = qentry; 1473 1474 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 1475 total_len -= data_left; 1476 1477 /* Add segment's header */ 1478 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1479 hdr = sq->tso_hdrs + qentry * TSO_HEADER_SIZE; 1480 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 1481 nicvf_sq_add_gather_subdesc(sq, qentry, hdr_len, 1482 sq->tso_hdrs_phys + 1483 qentry * TSO_HEADER_SIZE); 1484 /* HDR_SUDESC + GATHER */ 1485 seg_subdescs = 2; 1486 seg_len = hdr_len; 1487 1488 /* Add segment's payload fragments */ 1489 while (data_left > 0) { 1490 int size; 1491 1492 size = min_t(int, tso.size, data_left); 1493 1494 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1495 nicvf_sq_add_gather_subdesc(sq, qentry, size, 1496 virt_to_phys(tso.data)); 1497 seg_subdescs++; 1498 seg_len += size; 1499 1500 data_left -= size; 1501 tso_build_data(skb, &tso, size); 1502 } 1503 nicvf_sq_add_hdr_subdesc(nic, sq, hdr_qentry, 1504 seg_subdescs - 1, skb, seg_len); 1505 sq->skbuff[hdr_qentry] = (u64)NULL; 1506 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1507 1508 desc_cnt += seg_subdescs; 1509 } 1510 /* Save SKB in the last segment for freeing */ 1511 sq->skbuff[hdr_qentry] = (u64)skb; 1512 1513 nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt); 1514 1515 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso); 1516 return 1; 1517 } 1518 1519 /* Append an skb to a SQ for packet transfer. */ 1520 int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq, 1521 struct sk_buff *skb, u8 sq_num) 1522 { 1523 int i, size; 1524 int subdesc_cnt, hdr_sqe = 0; 1525 int qentry; 1526 u64 dma_addr; 1527 1528 subdesc_cnt = nicvf_sq_subdesc_required(nic, skb); 1529 if (subdesc_cnt > atomic_read(&sq->free_cnt)) 1530 goto append_fail; 1531 1532 qentry = nicvf_get_sq_desc(sq, subdesc_cnt); 1533 1534 /* Check if its a TSO packet */ 1535 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) 1536 return nicvf_sq_append_tso(nic, sq, sq_num, qentry, skb); 1537 1538 /* Add SQ header subdesc */ 1539 nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1, 1540 skb, skb->len); 1541 hdr_sqe = qentry; 1542 1543 /* Add SQ gather subdescs */ 1544 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1545 size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len; 1546 /* HW will ensure data coherency, CPU sync not required */ 1547 dma_addr = dma_map_page_attrs(&nic->pdev->dev, virt_to_page(skb->data), 1548 offset_in_page(skb->data), size, 1549 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 1550 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) { 1551 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt); 1552 return 0; 1553 } 1554 1555 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr); 1556 1557 /* Check for scattered buffer */ 1558 if (!skb_is_nonlinear(skb)) 1559 goto doorbell; 1560 1561 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1562 const struct skb_frag_struct *frag; 1563 1564 frag = &skb_shinfo(skb)->frags[i]; 1565 1566 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1567 size = skb_frag_size(frag); 1568 dma_addr = dma_map_page_attrs(&nic->pdev->dev, 1569 skb_frag_page(frag), 1570 frag->page_offset, size, 1571 DMA_TO_DEVICE, 1572 DMA_ATTR_SKIP_CPU_SYNC); 1573 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) { 1574 /* Free entire chain of mapped buffers 1575 * here 'i' = frags mapped + above mapped skb->data 1576 */ 1577 nicvf_unmap_sndq_buffers(nic, sq, hdr_sqe, i); 1578 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt); 1579 return 0; 1580 } 1581 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr); 1582 } 1583 1584 doorbell: 1585 if (nic->t88 && skb_shinfo(skb)->gso_size) { 1586 qentry = nicvf_get_nxt_sqentry(sq, qentry); 1587 nicvf_sq_add_cqe_subdesc(sq, qentry, hdr_sqe, skb); 1588 } 1589 1590 nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt); 1591 1592 return 1; 1593 1594 append_fail: 1595 /* Use original PCI dev for debug log */ 1596 nic = nic->pnicvf; 1597 netdev_dbg(nic->netdev, "Not enough SQ descriptors to xmit pkt\n"); 1598 return 0; 1599 } 1600 1601 static inline unsigned frag_num(unsigned i) 1602 { 1603 #ifdef __BIG_ENDIAN 1604 return (i & ~3) + 3 - (i & 3); 1605 #else 1606 return i; 1607 #endif 1608 } 1609 1610 static void nicvf_unmap_rcv_buffer(struct nicvf *nic, u64 dma_addr, 1611 u64 buf_addr, bool xdp) 1612 { 1613 struct page *page = NULL; 1614 int len = RCV_FRAG_LEN; 1615 1616 if (xdp) { 1617 page = virt_to_page(phys_to_virt(buf_addr)); 1618 /* Check if it's a recycled page, if not 1619 * unmap the DMA mapping. 1620 * 1621 * Recycled page holds an extra reference. 1622 */ 1623 if (page_ref_count(page) != 1) 1624 return; 1625 1626 len += XDP_PACKET_HEADROOM; 1627 /* Receive buffers in XDP mode are mapped from page start */ 1628 dma_addr &= PAGE_MASK; 1629 } 1630 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, len, 1631 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 1632 } 1633 1634 /* Returns SKB for a received packet */ 1635 struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, 1636 struct cqe_rx_t *cqe_rx, bool xdp) 1637 { 1638 int frag; 1639 int payload_len = 0; 1640 struct sk_buff *skb = NULL; 1641 struct page *page; 1642 int offset; 1643 u16 *rb_lens = NULL; 1644 u64 *rb_ptrs = NULL; 1645 u64 phys_addr; 1646 1647 rb_lens = (void *)cqe_rx + (3 * sizeof(u64)); 1648 /* Except 88xx pass1 on all other chips CQE_RX2_S is added to 1649 * CQE_RX at word6, hence buffer pointers move by word 1650 * 1651 * Use existing 'hw_tso' flag which will be set for all chips 1652 * except 88xx pass1 instead of a additional cache line 1653 * access (or miss) by using pci dev's revision. 1654 */ 1655 if (!nic->hw_tso) 1656 rb_ptrs = (void *)cqe_rx + (6 * sizeof(u64)); 1657 else 1658 rb_ptrs = (void *)cqe_rx + (7 * sizeof(u64)); 1659 1660 for (frag = 0; frag < cqe_rx->rb_cnt; frag++) { 1661 payload_len = rb_lens[frag_num(frag)]; 1662 phys_addr = nicvf_iova_to_phys(nic, *rb_ptrs); 1663 if (!phys_addr) { 1664 if (skb) 1665 dev_kfree_skb_any(skb); 1666 return NULL; 1667 } 1668 1669 if (!frag) { 1670 /* First fragment */ 1671 nicvf_unmap_rcv_buffer(nic, 1672 *rb_ptrs - cqe_rx->align_pad, 1673 phys_addr, xdp); 1674 skb = nicvf_rb_ptr_to_skb(nic, 1675 phys_addr - cqe_rx->align_pad, 1676 payload_len); 1677 if (!skb) 1678 return NULL; 1679 skb_reserve(skb, cqe_rx->align_pad); 1680 skb_put(skb, payload_len); 1681 } else { 1682 /* Add fragments */ 1683 nicvf_unmap_rcv_buffer(nic, *rb_ptrs, phys_addr, xdp); 1684 page = virt_to_page(phys_to_virt(phys_addr)); 1685 offset = phys_to_virt(phys_addr) - page_address(page); 1686 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1687 offset, payload_len, RCV_FRAG_LEN); 1688 } 1689 /* Next buffer pointer */ 1690 rb_ptrs++; 1691 } 1692 return skb; 1693 } 1694 1695 static u64 nicvf_int_type_to_mask(int int_type, int q_idx) 1696 { 1697 u64 reg_val; 1698 1699 switch (int_type) { 1700 case NICVF_INTR_CQ: 1701 reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); 1702 break; 1703 case NICVF_INTR_SQ: 1704 reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); 1705 break; 1706 case NICVF_INTR_RBDR: 1707 reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); 1708 break; 1709 case NICVF_INTR_PKT_DROP: 1710 reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT); 1711 break; 1712 case NICVF_INTR_TCP_TIMER: 1713 reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); 1714 break; 1715 case NICVF_INTR_MBOX: 1716 reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT); 1717 break; 1718 case NICVF_INTR_QS_ERR: 1719 reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT); 1720 break; 1721 default: 1722 reg_val = 0; 1723 } 1724 1725 return reg_val; 1726 } 1727 1728 /* Enable interrupt */ 1729 void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx) 1730 { 1731 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1732 1733 if (!mask) { 1734 netdev_dbg(nic->netdev, 1735 "Failed to enable interrupt: unknown type\n"); 1736 return; 1737 } 1738 nicvf_reg_write(nic, NIC_VF_ENA_W1S, 1739 nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask); 1740 } 1741 1742 /* Disable interrupt */ 1743 void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx) 1744 { 1745 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1746 1747 if (!mask) { 1748 netdev_dbg(nic->netdev, 1749 "Failed to disable interrupt: unknown type\n"); 1750 return; 1751 } 1752 1753 nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask); 1754 } 1755 1756 /* Clear interrupt */ 1757 void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx) 1758 { 1759 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1760 1761 if (!mask) { 1762 netdev_dbg(nic->netdev, 1763 "Failed to clear interrupt: unknown type\n"); 1764 return; 1765 } 1766 1767 nicvf_reg_write(nic, NIC_VF_INT, mask); 1768 } 1769 1770 /* Check if interrupt is enabled */ 1771 int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx) 1772 { 1773 u64 mask = nicvf_int_type_to_mask(int_type, q_idx); 1774 /* If interrupt type is unknown, we treat it disabled. */ 1775 if (!mask) { 1776 netdev_dbg(nic->netdev, 1777 "Failed to check interrupt enable: unknown type\n"); 1778 return 0; 1779 } 1780 1781 return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S); 1782 } 1783 1784 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx) 1785 { 1786 struct rcv_queue *rq; 1787 1788 #define GET_RQ_STATS(reg) \ 1789 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\ 1790 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) 1791 1792 rq = &nic->qs->rq[rq_idx]; 1793 rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS); 1794 rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS); 1795 } 1796 1797 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx) 1798 { 1799 struct snd_queue *sq; 1800 1801 #define GET_SQ_STATS(reg) \ 1802 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\ 1803 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) 1804 1805 sq = &nic->qs->sq[sq_idx]; 1806 sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS); 1807 sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS); 1808 } 1809 1810 /* Check for errors in the receive cmp.queue entry */ 1811 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx) 1812 { 1813 netif_err(nic, rx_err, nic->netdev, 1814 "RX error CQE err_level 0x%x err_opcode 0x%x\n", 1815 cqe_rx->err_level, cqe_rx->err_opcode); 1816 1817 switch (cqe_rx->err_opcode) { 1818 case CQ_RX_ERROP_RE_PARTIAL: 1819 this_cpu_inc(nic->drv_stats->rx_bgx_truncated_pkts); 1820 break; 1821 case CQ_RX_ERROP_RE_JABBER: 1822 this_cpu_inc(nic->drv_stats->rx_jabber_errs); 1823 break; 1824 case CQ_RX_ERROP_RE_FCS: 1825 this_cpu_inc(nic->drv_stats->rx_fcs_errs); 1826 break; 1827 case CQ_RX_ERROP_RE_RX_CTL: 1828 this_cpu_inc(nic->drv_stats->rx_bgx_errs); 1829 break; 1830 case CQ_RX_ERROP_PREL2_ERR: 1831 this_cpu_inc(nic->drv_stats->rx_prel2_errs); 1832 break; 1833 case CQ_RX_ERROP_L2_MAL: 1834 this_cpu_inc(nic->drv_stats->rx_l2_hdr_malformed); 1835 break; 1836 case CQ_RX_ERROP_L2_OVERSIZE: 1837 this_cpu_inc(nic->drv_stats->rx_oversize); 1838 break; 1839 case CQ_RX_ERROP_L2_UNDERSIZE: 1840 this_cpu_inc(nic->drv_stats->rx_undersize); 1841 break; 1842 case CQ_RX_ERROP_L2_LENMISM: 1843 this_cpu_inc(nic->drv_stats->rx_l2_len_mismatch); 1844 break; 1845 case CQ_RX_ERROP_L2_PCLP: 1846 this_cpu_inc(nic->drv_stats->rx_l2_pclp); 1847 break; 1848 case CQ_RX_ERROP_IP_NOT: 1849 this_cpu_inc(nic->drv_stats->rx_ip_ver_errs); 1850 break; 1851 case CQ_RX_ERROP_IP_CSUM_ERR: 1852 this_cpu_inc(nic->drv_stats->rx_ip_csum_errs); 1853 break; 1854 case CQ_RX_ERROP_IP_MAL: 1855 this_cpu_inc(nic->drv_stats->rx_ip_hdr_malformed); 1856 break; 1857 case CQ_RX_ERROP_IP_MALD: 1858 this_cpu_inc(nic->drv_stats->rx_ip_payload_malformed); 1859 break; 1860 case CQ_RX_ERROP_IP_HOP: 1861 this_cpu_inc(nic->drv_stats->rx_ip_ttl_errs); 1862 break; 1863 case CQ_RX_ERROP_L3_PCLP: 1864 this_cpu_inc(nic->drv_stats->rx_l3_pclp); 1865 break; 1866 case CQ_RX_ERROP_L4_MAL: 1867 this_cpu_inc(nic->drv_stats->rx_l4_malformed); 1868 break; 1869 case CQ_RX_ERROP_L4_CHK: 1870 this_cpu_inc(nic->drv_stats->rx_l4_csum_errs); 1871 break; 1872 case CQ_RX_ERROP_UDP_LEN: 1873 this_cpu_inc(nic->drv_stats->rx_udp_len_errs); 1874 break; 1875 case CQ_RX_ERROP_L4_PORT: 1876 this_cpu_inc(nic->drv_stats->rx_l4_port_errs); 1877 break; 1878 case CQ_RX_ERROP_TCP_FLAG: 1879 this_cpu_inc(nic->drv_stats->rx_tcp_flag_errs); 1880 break; 1881 case CQ_RX_ERROP_TCP_OFFSET: 1882 this_cpu_inc(nic->drv_stats->rx_tcp_offset_errs); 1883 break; 1884 case CQ_RX_ERROP_L4_PCLP: 1885 this_cpu_inc(nic->drv_stats->rx_l4_pclp); 1886 break; 1887 case CQ_RX_ERROP_RBDR_TRUNC: 1888 this_cpu_inc(nic->drv_stats->rx_truncated_pkts); 1889 break; 1890 } 1891 1892 return 1; 1893 } 1894 1895 /* Check for errors in the send cmp.queue entry */ 1896 int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx) 1897 { 1898 switch (cqe_tx->send_status) { 1899 case CQ_TX_ERROP_DESC_FAULT: 1900 this_cpu_inc(nic->drv_stats->tx_desc_fault); 1901 break; 1902 case CQ_TX_ERROP_HDR_CONS_ERR: 1903 this_cpu_inc(nic->drv_stats->tx_hdr_cons_err); 1904 break; 1905 case CQ_TX_ERROP_SUBDC_ERR: 1906 this_cpu_inc(nic->drv_stats->tx_subdesc_err); 1907 break; 1908 case CQ_TX_ERROP_MAX_SIZE_VIOL: 1909 this_cpu_inc(nic->drv_stats->tx_max_size_exceeded); 1910 break; 1911 case CQ_TX_ERROP_IMM_SIZE_OFLOW: 1912 this_cpu_inc(nic->drv_stats->tx_imm_size_oflow); 1913 break; 1914 case CQ_TX_ERROP_DATA_SEQUENCE_ERR: 1915 this_cpu_inc(nic->drv_stats->tx_data_seq_err); 1916 break; 1917 case CQ_TX_ERROP_MEM_SEQUENCE_ERR: 1918 this_cpu_inc(nic->drv_stats->tx_mem_seq_err); 1919 break; 1920 case CQ_TX_ERROP_LOCK_VIOL: 1921 this_cpu_inc(nic->drv_stats->tx_lock_viol); 1922 break; 1923 case CQ_TX_ERROP_DATA_FAULT: 1924 this_cpu_inc(nic->drv_stats->tx_data_fault); 1925 break; 1926 case CQ_TX_ERROP_TSTMP_CONFLICT: 1927 this_cpu_inc(nic->drv_stats->tx_tstmp_conflict); 1928 break; 1929 case CQ_TX_ERROP_TSTMP_TIMEOUT: 1930 this_cpu_inc(nic->drv_stats->tx_tstmp_timeout); 1931 break; 1932 case CQ_TX_ERROP_MEM_FAULT: 1933 this_cpu_inc(nic->drv_stats->tx_mem_fault); 1934 break; 1935 case CQ_TX_ERROP_CK_OVERLAP: 1936 this_cpu_inc(nic->drv_stats->tx_csum_overlap); 1937 break; 1938 case CQ_TX_ERROP_CK_OFLOW: 1939 this_cpu_inc(nic->drv_stats->tx_csum_overflow); 1940 break; 1941 } 1942 1943 return 1; 1944 } 1945