1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/if_vlan.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/log2.h> 17 #include <linux/prefetch.h> 18 #include <linux/irq.h> 19 20 #include "nic_reg.h" 21 #include "nic.h" 22 #include "nicvf_queues.h" 23 #include "thunder_bgx.h" 24 25 #define DRV_NAME "thunder-nicvf" 26 #define DRV_VERSION "1.0" 27 28 /* Supported devices */ 29 static const struct pci_device_id nicvf_id_table[] = { 30 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 31 PCI_DEVICE_ID_THUNDER_NIC_VF, 32 PCI_VENDOR_ID_CAVIUM, 33 PCI_SUBSYS_DEVID_88XX_NIC_VF) }, 34 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 35 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF, 36 PCI_VENDOR_ID_CAVIUM, 37 PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF) }, 38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 39 PCI_DEVICE_ID_THUNDER_NIC_VF, 40 PCI_VENDOR_ID_CAVIUM, 41 PCI_SUBSYS_DEVID_81XX_NIC_VF) }, 42 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 43 PCI_DEVICE_ID_THUNDER_NIC_VF, 44 PCI_VENDOR_ID_CAVIUM, 45 PCI_SUBSYS_DEVID_83XX_NIC_VF) }, 46 { 0, } /* end of table */ 47 }; 48 49 MODULE_AUTHOR("Sunil Goutham"); 50 MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver"); 51 MODULE_LICENSE("GPL v2"); 52 MODULE_VERSION(DRV_VERSION); 53 MODULE_DEVICE_TABLE(pci, nicvf_id_table); 54 55 static int debug = 0x00; 56 module_param(debug, int, 0644); 57 MODULE_PARM_DESC(debug, "Debug message level bitmap"); 58 59 static int cpi_alg = CPI_ALG_NONE; 60 module_param(cpi_alg, int, S_IRUGO); 61 MODULE_PARM_DESC(cpi_alg, 62 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)"); 63 64 static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx) 65 { 66 if (nic->sqs_mode) 67 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS); 68 else 69 return qidx; 70 } 71 72 /* The Cavium ThunderX network controller can *only* be found in SoCs 73 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 74 * registers on this platform are implicitly strongly ordered with respect 75 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 76 * with no memory barriers in this driver. The readq()/writeq() functions add 77 * explicit ordering operation which in this case are redundant, and only 78 * add overhead. 79 */ 80 81 /* Register read/write APIs */ 82 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val) 83 { 84 writeq_relaxed(val, nic->reg_base + offset); 85 } 86 87 u64 nicvf_reg_read(struct nicvf *nic, u64 offset) 88 { 89 return readq_relaxed(nic->reg_base + offset); 90 } 91 92 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset, 93 u64 qidx, u64 val) 94 { 95 void __iomem *addr = nic->reg_base + offset; 96 97 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT)); 98 } 99 100 u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx) 101 { 102 void __iomem *addr = nic->reg_base + offset; 103 104 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT)); 105 } 106 107 /* VF -> PF mailbox communication */ 108 static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx) 109 { 110 u64 *msg = (u64 *)mbx; 111 112 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]); 113 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]); 114 } 115 116 int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx) 117 { 118 int timeout = NIC_MBOX_MSG_TIMEOUT; 119 int sleep = 10; 120 121 nic->pf_acked = false; 122 nic->pf_nacked = false; 123 124 nicvf_write_to_mbx(nic, mbx); 125 126 /* Wait for previous message to be acked, timeout 2sec */ 127 while (!nic->pf_acked) { 128 if (nic->pf_nacked) { 129 netdev_err(nic->netdev, 130 "PF NACK to mbox msg 0x%02x from VF%d\n", 131 (mbx->msg.msg & 0xFF), nic->vf_id); 132 return -EINVAL; 133 } 134 msleep(sleep); 135 if (nic->pf_acked) 136 break; 137 timeout -= sleep; 138 if (!timeout) { 139 netdev_err(nic->netdev, 140 "PF didn't ACK to mbox msg 0x%02x from VF%d\n", 141 (mbx->msg.msg & 0xFF), nic->vf_id); 142 return -EBUSY; 143 } 144 } 145 return 0; 146 } 147 148 /* Checks if VF is able to comminicate with PF 149 * and also gets the VNIC number this VF is associated to. 150 */ 151 static int nicvf_check_pf_ready(struct nicvf *nic) 152 { 153 union nic_mbx mbx = {}; 154 155 mbx.msg.msg = NIC_MBOX_MSG_READY; 156 if (nicvf_send_msg_to_pf(nic, &mbx)) { 157 netdev_err(nic->netdev, 158 "PF didn't respond to READY msg\n"); 159 return 0; 160 } 161 162 return 1; 163 } 164 165 static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx) 166 { 167 if (bgx->rx) 168 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats; 169 else 170 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats; 171 } 172 173 static void nicvf_handle_mbx_intr(struct nicvf *nic) 174 { 175 union nic_mbx mbx = {}; 176 u64 *mbx_data; 177 u64 mbx_addr; 178 int i; 179 180 mbx_addr = NIC_VF_PF_MAILBOX_0_1; 181 mbx_data = (u64 *)&mbx; 182 183 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 184 *mbx_data = nicvf_reg_read(nic, mbx_addr); 185 mbx_data++; 186 mbx_addr += sizeof(u64); 187 } 188 189 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg); 190 switch (mbx.msg.msg) { 191 case NIC_MBOX_MSG_READY: 192 nic->pf_acked = true; 193 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F; 194 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F; 195 nic->node = mbx.nic_cfg.node_id; 196 if (!nic->set_mac_pending) 197 ether_addr_copy(nic->netdev->dev_addr, 198 mbx.nic_cfg.mac_addr); 199 nic->sqs_mode = mbx.nic_cfg.sqs_mode; 200 nic->loopback_supported = mbx.nic_cfg.loopback_supported; 201 nic->link_up = false; 202 nic->duplex = 0; 203 nic->speed = 0; 204 break; 205 case NIC_MBOX_MSG_ACK: 206 nic->pf_acked = true; 207 break; 208 case NIC_MBOX_MSG_NACK: 209 nic->pf_nacked = true; 210 break; 211 case NIC_MBOX_MSG_RSS_SIZE: 212 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size; 213 nic->pf_acked = true; 214 break; 215 case NIC_MBOX_MSG_BGX_STATS: 216 nicvf_read_bgx_stats(nic, &mbx.bgx_stats); 217 nic->pf_acked = true; 218 break; 219 case NIC_MBOX_MSG_BGX_LINK_CHANGE: 220 nic->pf_acked = true; 221 nic->link_up = mbx.link_status.link_up; 222 nic->duplex = mbx.link_status.duplex; 223 nic->speed = mbx.link_status.speed; 224 nic->mac_type = mbx.link_status.mac_type; 225 if (nic->link_up) { 226 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n", 227 nic->netdev->name, nic->speed, 228 nic->duplex == DUPLEX_FULL ? 229 "Full duplex" : "Half duplex"); 230 netif_carrier_on(nic->netdev); 231 netif_tx_start_all_queues(nic->netdev); 232 } else { 233 netdev_info(nic->netdev, "%s: Link is Down\n", 234 nic->netdev->name); 235 netif_carrier_off(nic->netdev); 236 netif_tx_stop_all_queues(nic->netdev); 237 } 238 break; 239 case NIC_MBOX_MSG_ALLOC_SQS: 240 nic->sqs_count = mbx.sqs_alloc.qs_count; 241 nic->pf_acked = true; 242 break; 243 case NIC_MBOX_MSG_SNICVF_PTR: 244 /* Primary VF: make note of secondary VF's pointer 245 * to be used while packet transmission. 246 */ 247 nic->snicvf[mbx.nicvf.sqs_id] = 248 (struct nicvf *)mbx.nicvf.nicvf; 249 nic->pf_acked = true; 250 break; 251 case NIC_MBOX_MSG_PNICVF_PTR: 252 /* Secondary VF/Qset: make note of primary VF's pointer 253 * to be used while packet reception, to handover packet 254 * to primary VF's netdev. 255 */ 256 nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf; 257 nic->pf_acked = true; 258 break; 259 case NIC_MBOX_MSG_PFC: 260 nic->pfc.autoneg = mbx.pfc.autoneg; 261 nic->pfc.fc_rx = mbx.pfc.fc_rx; 262 nic->pfc.fc_tx = mbx.pfc.fc_tx; 263 nic->pf_acked = true; 264 break; 265 default: 266 netdev_err(nic->netdev, 267 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg); 268 break; 269 } 270 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0); 271 } 272 273 static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev) 274 { 275 union nic_mbx mbx = {}; 276 277 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC; 278 mbx.mac.vf_id = nic->vf_id; 279 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr); 280 281 return nicvf_send_msg_to_pf(nic, &mbx); 282 } 283 284 static void nicvf_config_cpi(struct nicvf *nic) 285 { 286 union nic_mbx mbx = {}; 287 288 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG; 289 mbx.cpi_cfg.vf_id = nic->vf_id; 290 mbx.cpi_cfg.cpi_alg = nic->cpi_alg; 291 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt; 292 293 nicvf_send_msg_to_pf(nic, &mbx); 294 } 295 296 static void nicvf_get_rss_size(struct nicvf *nic) 297 { 298 union nic_mbx mbx = {}; 299 300 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 301 mbx.rss_size.vf_id = nic->vf_id; 302 nicvf_send_msg_to_pf(nic, &mbx); 303 } 304 305 void nicvf_config_rss(struct nicvf *nic) 306 { 307 union nic_mbx mbx = {}; 308 struct nicvf_rss_info *rss = &nic->rss_info; 309 int ind_tbl_len = rss->rss_size; 310 int i, nextq = 0; 311 312 mbx.rss_cfg.vf_id = nic->vf_id; 313 mbx.rss_cfg.hash_bits = rss->hash_bits; 314 while (ind_tbl_len) { 315 mbx.rss_cfg.tbl_offset = nextq; 316 mbx.rss_cfg.tbl_len = min(ind_tbl_len, 317 RSS_IND_TBL_LEN_PER_MBX_MSG); 318 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ? 319 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG; 320 321 for (i = 0; i < mbx.rss_cfg.tbl_len; i++) 322 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++]; 323 324 nicvf_send_msg_to_pf(nic, &mbx); 325 326 ind_tbl_len -= mbx.rss_cfg.tbl_len; 327 } 328 } 329 330 void nicvf_set_rss_key(struct nicvf *nic) 331 { 332 struct nicvf_rss_info *rss = &nic->rss_info; 333 u64 key_addr = NIC_VNIC_RSS_KEY_0_4; 334 int idx; 335 336 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) { 337 nicvf_reg_write(nic, key_addr, rss->key[idx]); 338 key_addr += sizeof(u64); 339 } 340 } 341 342 static int nicvf_rss_init(struct nicvf *nic) 343 { 344 struct nicvf_rss_info *rss = &nic->rss_info; 345 int idx; 346 347 nicvf_get_rss_size(nic); 348 349 if (cpi_alg != CPI_ALG_NONE) { 350 rss->enable = false; 351 rss->hash_bits = 0; 352 return 0; 353 } 354 355 rss->enable = true; 356 357 netdev_rss_key_fill(rss->key, RSS_HASH_KEY_SIZE * sizeof(u64)); 358 nicvf_set_rss_key(nic); 359 360 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA; 361 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg); 362 363 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size)); 364 365 for (idx = 0; idx < rss->rss_size; idx++) 366 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx, 367 nic->rx_queues); 368 nicvf_config_rss(nic); 369 return 1; 370 } 371 372 /* Request PF to allocate additional Qsets */ 373 static void nicvf_request_sqs(struct nicvf *nic) 374 { 375 union nic_mbx mbx = {}; 376 int sqs; 377 int sqs_count = nic->sqs_count; 378 int rx_queues = 0, tx_queues = 0; 379 380 /* Only primary VF should request */ 381 if (nic->sqs_mode || !nic->sqs_count) 382 return; 383 384 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 385 mbx.sqs_alloc.vf_id = nic->vf_id; 386 mbx.sqs_alloc.qs_count = nic->sqs_count; 387 if (nicvf_send_msg_to_pf(nic, &mbx)) { 388 /* No response from PF */ 389 nic->sqs_count = 0; 390 return; 391 } 392 393 /* Return if no Secondary Qsets available */ 394 if (!nic->sqs_count) 395 return; 396 397 if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS) 398 rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS; 399 if (nic->tx_queues > MAX_SND_QUEUES_PER_QS) 400 tx_queues = nic->tx_queues - MAX_SND_QUEUES_PER_QS; 401 402 /* Set no of Rx/Tx queues in each of the SQsets */ 403 for (sqs = 0; sqs < nic->sqs_count; sqs++) { 404 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 405 mbx.nicvf.vf_id = nic->vf_id; 406 mbx.nicvf.sqs_id = sqs; 407 nicvf_send_msg_to_pf(nic, &mbx); 408 409 nic->snicvf[sqs]->sqs_id = sqs; 410 if (rx_queues > MAX_RCV_QUEUES_PER_QS) { 411 nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS; 412 rx_queues -= MAX_RCV_QUEUES_PER_QS; 413 } else { 414 nic->snicvf[sqs]->qs->rq_cnt = rx_queues; 415 rx_queues = 0; 416 } 417 418 if (tx_queues > MAX_SND_QUEUES_PER_QS) { 419 nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS; 420 tx_queues -= MAX_SND_QUEUES_PER_QS; 421 } else { 422 nic->snicvf[sqs]->qs->sq_cnt = tx_queues; 423 tx_queues = 0; 424 } 425 426 nic->snicvf[sqs]->qs->cq_cnt = 427 max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt); 428 429 /* Initialize secondary Qset's queues and its interrupts */ 430 nicvf_open(nic->snicvf[sqs]->netdev); 431 } 432 433 /* Update stack with actual Rx/Tx queue count allocated */ 434 if (sqs_count != nic->sqs_count) 435 nicvf_set_real_num_queues(nic->netdev, 436 nic->tx_queues, nic->rx_queues); 437 } 438 439 /* Send this Qset's nicvf pointer to PF. 440 * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs 441 * so that packets received by these Qsets can use primary VF's netdev 442 */ 443 static void nicvf_send_vf_struct(struct nicvf *nic) 444 { 445 union nic_mbx mbx = {}; 446 447 mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR; 448 mbx.nicvf.sqs_mode = nic->sqs_mode; 449 mbx.nicvf.nicvf = (u64)nic; 450 nicvf_send_msg_to_pf(nic, &mbx); 451 } 452 453 static void nicvf_get_primary_vf_struct(struct nicvf *nic) 454 { 455 union nic_mbx mbx = {}; 456 457 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 458 nicvf_send_msg_to_pf(nic, &mbx); 459 } 460 461 int nicvf_set_real_num_queues(struct net_device *netdev, 462 int tx_queues, int rx_queues) 463 { 464 int err = 0; 465 466 err = netif_set_real_num_tx_queues(netdev, tx_queues); 467 if (err) { 468 netdev_err(netdev, 469 "Failed to set no of Tx queues: %d\n", tx_queues); 470 return err; 471 } 472 473 err = netif_set_real_num_rx_queues(netdev, rx_queues); 474 if (err) 475 netdev_err(netdev, 476 "Failed to set no of Rx queues: %d\n", rx_queues); 477 return err; 478 } 479 480 static int nicvf_init_resources(struct nicvf *nic) 481 { 482 int err; 483 484 /* Enable Qset */ 485 nicvf_qset_config(nic, true); 486 487 /* Initialize queues and HW for data transfer */ 488 err = nicvf_config_data_transfer(nic, true); 489 if (err) { 490 netdev_err(nic->netdev, 491 "Failed to alloc/config VF's QSet resources\n"); 492 return err; 493 } 494 495 return 0; 496 } 497 498 static void nicvf_snd_pkt_handler(struct net_device *netdev, 499 struct cqe_send_t *cqe_tx, 500 int cqe_type, int budget, 501 unsigned int *tx_pkts, unsigned int *tx_bytes) 502 { 503 struct sk_buff *skb = NULL; 504 struct nicvf *nic = netdev_priv(netdev); 505 struct snd_queue *sq; 506 struct sq_hdr_subdesc *hdr; 507 struct sq_hdr_subdesc *tso_sqe; 508 509 sq = &nic->qs->sq[cqe_tx->sq_idx]; 510 511 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr); 512 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) 513 return; 514 515 netdev_dbg(nic->netdev, 516 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n", 517 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx, 518 cqe_tx->sqe_ptr, hdr->subdesc_cnt); 519 520 nicvf_check_cqe_tx_errs(nic, cqe_tx); 521 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr]; 522 if (skb) { 523 /* Check for dummy descriptor used for HW TSO offload on 88xx */ 524 if (hdr->dont_send) { 525 /* Get actual TSO descriptors and free them */ 526 tso_sqe = 527 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2); 528 nicvf_put_sq_desc(sq, tso_sqe->subdesc_cnt + 1); 529 } 530 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 531 prefetch(skb); 532 (*tx_pkts)++; 533 *tx_bytes += skb->len; 534 napi_consume_skb(skb, budget); 535 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL; 536 } else { 537 /* In case of SW TSO on 88xx, only last segment will have 538 * a SKB attached, so just free SQEs here. 539 */ 540 if (!nic->hw_tso) 541 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1); 542 } 543 } 544 545 static inline void nicvf_set_rxhash(struct net_device *netdev, 546 struct cqe_rx_t *cqe_rx, 547 struct sk_buff *skb) 548 { 549 u8 hash_type; 550 u32 hash; 551 552 if (!(netdev->features & NETIF_F_RXHASH)) 553 return; 554 555 switch (cqe_rx->rss_alg) { 556 case RSS_ALG_TCP_IP: 557 case RSS_ALG_UDP_IP: 558 hash_type = PKT_HASH_TYPE_L4; 559 hash = cqe_rx->rss_tag; 560 break; 561 case RSS_ALG_IP: 562 hash_type = PKT_HASH_TYPE_L3; 563 hash = cqe_rx->rss_tag; 564 break; 565 default: 566 hash_type = PKT_HASH_TYPE_NONE; 567 hash = 0; 568 } 569 570 skb_set_hash(skb, hash, hash_type); 571 } 572 573 static void nicvf_rcv_pkt_handler(struct net_device *netdev, 574 struct napi_struct *napi, 575 struct cqe_rx_t *cqe_rx) 576 { 577 struct sk_buff *skb; 578 struct nicvf *nic = netdev_priv(netdev); 579 int err = 0; 580 int rq_idx; 581 582 rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx); 583 584 if (nic->sqs_mode) { 585 /* Use primary VF's 'nicvf' struct */ 586 nic = nic->pnicvf; 587 netdev = nic->netdev; 588 } 589 590 /* Check for errors */ 591 err = nicvf_check_cqe_rx_errs(nic, cqe_rx); 592 if (err && !cqe_rx->rb_cnt) 593 return; 594 595 skb = nicvf_get_rcv_skb(nic, cqe_rx); 596 if (!skb) { 597 netdev_dbg(nic->netdev, "Packet not received\n"); 598 return; 599 } 600 601 if (netif_msg_pktdata(nic)) { 602 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name, 603 skb, skb->len); 604 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 605 skb->data, skb->len, true); 606 } 607 608 /* If error packet, drop it here */ 609 if (err) { 610 dev_kfree_skb_any(skb); 611 return; 612 } 613 614 nicvf_set_rxhash(netdev, cqe_rx, skb); 615 616 skb_record_rx_queue(skb, rq_idx); 617 if (netdev->hw_features & NETIF_F_RXCSUM) { 618 /* HW by default verifies TCP/UDP/SCTP checksums */ 619 skb->ip_summed = CHECKSUM_UNNECESSARY; 620 } else { 621 skb_checksum_none_assert(skb); 622 } 623 624 skb->protocol = eth_type_trans(skb, netdev); 625 626 /* Check for stripped VLAN */ 627 if (cqe_rx->vlan_found && cqe_rx->vlan_stripped) 628 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 629 ntohs((__force __be16)cqe_rx->vlan_tci)); 630 631 if (napi && (netdev->features & NETIF_F_GRO)) 632 napi_gro_receive(napi, skb); 633 else 634 netif_receive_skb(skb); 635 } 636 637 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx, 638 struct napi_struct *napi, int budget) 639 { 640 int processed_cqe, work_done = 0, tx_done = 0; 641 int cqe_count, cqe_head; 642 struct nicvf *nic = netdev_priv(netdev); 643 struct queue_set *qs = nic->qs; 644 struct cmp_queue *cq = &qs->cq[cq_idx]; 645 struct cqe_rx_t *cq_desc; 646 struct netdev_queue *txq; 647 struct snd_queue *sq; 648 unsigned int tx_pkts = 0, tx_bytes = 0; 649 650 spin_lock_bh(&cq->lock); 651 loop: 652 processed_cqe = 0; 653 /* Get no of valid CQ entries to process */ 654 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx); 655 cqe_count &= CQ_CQE_COUNT; 656 if (!cqe_count) 657 goto done; 658 659 /* Get head of the valid CQ entries */ 660 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9; 661 cqe_head &= 0xFFFF; 662 663 netdev_dbg(nic->netdev, "%s CQ%d cqe_count %d cqe_head %d\n", 664 __func__, cq_idx, cqe_count, cqe_head); 665 while (processed_cqe < cqe_count) { 666 /* Get the CQ descriptor */ 667 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); 668 cqe_head++; 669 cqe_head &= (cq->dmem.q_len - 1); 670 /* Initiate prefetch for next descriptor */ 671 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head)); 672 673 if ((work_done >= budget) && napi && 674 (cq_desc->cqe_type != CQE_TYPE_SEND)) { 675 break; 676 } 677 678 netdev_dbg(nic->netdev, "CQ%d cq_desc->cqe_type %d\n", 679 cq_idx, cq_desc->cqe_type); 680 switch (cq_desc->cqe_type) { 681 case CQE_TYPE_RX: 682 nicvf_rcv_pkt_handler(netdev, napi, cq_desc); 683 work_done++; 684 break; 685 case CQE_TYPE_SEND: 686 nicvf_snd_pkt_handler(netdev, 687 (void *)cq_desc, CQE_TYPE_SEND, 688 budget, &tx_pkts, &tx_bytes); 689 tx_done++; 690 break; 691 case CQE_TYPE_INVALID: 692 case CQE_TYPE_RX_SPLIT: 693 case CQE_TYPE_RX_TCP: 694 case CQE_TYPE_SEND_PTP: 695 /* Ignore for now */ 696 break; 697 } 698 processed_cqe++; 699 } 700 netdev_dbg(nic->netdev, 701 "%s CQ%d processed_cqe %d work_done %d budget %d\n", 702 __func__, cq_idx, processed_cqe, work_done, budget); 703 704 /* Ring doorbell to inform H/W to reuse processed CQEs */ 705 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, 706 cq_idx, processed_cqe); 707 708 if ((work_done < budget) && napi) 709 goto loop; 710 711 done: 712 /* Wakeup TXQ if its stopped earlier due to SQ full */ 713 sq = &nic->qs->sq[cq_idx]; 714 if (tx_done || 715 (atomic_read(&sq->free_cnt) >= MIN_SQ_DESC_PER_PKT_XMIT)) { 716 netdev = nic->pnicvf->netdev; 717 txq = netdev_get_tx_queue(netdev, 718 nicvf_netdev_qidx(nic, cq_idx)); 719 if (tx_pkts) 720 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 721 722 /* To read updated queue and carrier status */ 723 smp_mb(); 724 if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) { 725 netif_tx_wake_queue(txq); 726 nic = nic->pnicvf; 727 this_cpu_inc(nic->drv_stats->txq_wake); 728 if (netif_msg_tx_err(nic)) 729 netdev_warn(netdev, 730 "%s: Transmit queue wakeup SQ%d\n", 731 netdev->name, cq_idx); 732 } 733 } 734 735 spin_unlock_bh(&cq->lock); 736 return work_done; 737 } 738 739 static int nicvf_poll(struct napi_struct *napi, int budget) 740 { 741 u64 cq_head; 742 int work_done = 0; 743 struct net_device *netdev = napi->dev; 744 struct nicvf *nic = netdev_priv(netdev); 745 struct nicvf_cq_poll *cq; 746 747 cq = container_of(napi, struct nicvf_cq_poll, napi); 748 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget); 749 750 if (work_done < budget) { 751 /* Slow packet rate, exit polling */ 752 napi_complete(napi); 753 /* Re-enable interrupts */ 754 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, 755 cq->cq_idx); 756 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 757 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD, 758 cq->cq_idx, cq_head); 759 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 760 } 761 return work_done; 762 } 763 764 /* Qset error interrupt handler 765 * 766 * As of now only CQ errors are handled 767 */ 768 static void nicvf_handle_qs_err(unsigned long data) 769 { 770 struct nicvf *nic = (struct nicvf *)data; 771 struct queue_set *qs = nic->qs; 772 int qidx; 773 u64 status; 774 775 netif_tx_disable(nic->netdev); 776 777 /* Check if it is CQ err */ 778 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 779 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, 780 qidx); 781 if (!(status & CQ_ERR_MASK)) 782 continue; 783 /* Process already queued CQEs and reconfig CQ */ 784 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 785 nicvf_sq_disable(nic, qidx); 786 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0); 787 nicvf_cmp_queue_config(nic, qs, qidx, true); 788 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx); 789 nicvf_sq_enable(nic, &qs->sq[qidx], qidx); 790 791 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 792 } 793 794 netif_tx_start_all_queues(nic->netdev); 795 /* Re-enable Qset error interrupt */ 796 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 797 } 798 799 static void nicvf_dump_intr_status(struct nicvf *nic) 800 { 801 if (netif_msg_intr(nic)) 802 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n", 803 nic->netdev->name, nicvf_reg_read(nic, NIC_VF_INT)); 804 } 805 806 static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq) 807 { 808 struct nicvf *nic = (struct nicvf *)nicvf_irq; 809 u64 intr; 810 811 nicvf_dump_intr_status(nic); 812 813 intr = nicvf_reg_read(nic, NIC_VF_INT); 814 /* Check for spurious interrupt */ 815 if (!(intr & NICVF_INTR_MBOX_MASK)) 816 return IRQ_HANDLED; 817 818 nicvf_handle_mbx_intr(nic); 819 820 return IRQ_HANDLED; 821 } 822 823 static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq) 824 { 825 struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq; 826 struct nicvf *nic = cq_poll->nicvf; 827 int qidx = cq_poll->cq_idx; 828 829 nicvf_dump_intr_status(nic); 830 831 /* Disable interrupts */ 832 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 833 834 /* Schedule NAPI */ 835 napi_schedule_irqoff(&cq_poll->napi); 836 837 /* Clear interrupt */ 838 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 839 840 return IRQ_HANDLED; 841 } 842 843 static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq) 844 { 845 struct nicvf *nic = (struct nicvf *)nicvf_irq; 846 u8 qidx; 847 848 849 nicvf_dump_intr_status(nic); 850 851 /* Disable RBDR interrupt and schedule softirq */ 852 for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) { 853 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx)) 854 continue; 855 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 856 tasklet_hi_schedule(&nic->rbdr_task); 857 /* Clear interrupt */ 858 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 859 } 860 861 return IRQ_HANDLED; 862 } 863 864 static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq) 865 { 866 struct nicvf *nic = (struct nicvf *)nicvf_irq; 867 868 nicvf_dump_intr_status(nic); 869 870 /* Disable Qset err interrupt and schedule softirq */ 871 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 872 tasklet_hi_schedule(&nic->qs_err_task); 873 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 874 875 return IRQ_HANDLED; 876 } 877 878 static int nicvf_enable_msix(struct nicvf *nic) 879 { 880 int ret, vec; 881 882 nic->num_vec = NIC_VF_MSIX_VECTORS; 883 884 for (vec = 0; vec < nic->num_vec; vec++) 885 nic->msix_entries[vec].entry = vec; 886 887 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec); 888 if (ret) { 889 netdev_err(nic->netdev, 890 "Req for #%d msix vectors failed\n", nic->num_vec); 891 return 0; 892 } 893 nic->msix_enabled = 1; 894 return 1; 895 } 896 897 static void nicvf_disable_msix(struct nicvf *nic) 898 { 899 if (nic->msix_enabled) { 900 pci_disable_msix(nic->pdev); 901 nic->msix_enabled = 0; 902 nic->num_vec = 0; 903 } 904 } 905 906 static void nicvf_set_irq_affinity(struct nicvf *nic) 907 { 908 int vec, cpu; 909 int irqnum; 910 911 for (vec = 0; vec < nic->num_vec; vec++) { 912 if (!nic->irq_allocated[vec]) 913 continue; 914 915 if (!zalloc_cpumask_var(&nic->affinity_mask[vec], GFP_KERNEL)) 916 return; 917 /* CQ interrupts */ 918 if (vec < NICVF_INTR_ID_SQ) 919 /* Leave CPU0 for RBDR and other interrupts */ 920 cpu = nicvf_netdev_qidx(nic, vec) + 1; 921 else 922 cpu = 0; 923 924 cpumask_set_cpu(cpumask_local_spread(cpu, nic->node), 925 nic->affinity_mask[vec]); 926 irqnum = nic->msix_entries[vec].vector; 927 irq_set_affinity_hint(irqnum, nic->affinity_mask[vec]); 928 } 929 } 930 931 static int nicvf_register_interrupts(struct nicvf *nic) 932 { 933 int irq, ret = 0; 934 int vector; 935 936 for_each_cq_irq(irq) 937 sprintf(nic->irq_name[irq], "%s-rxtx-%d", 938 nic->pnicvf->netdev->name, 939 nicvf_netdev_qidx(nic, irq)); 940 941 for_each_sq_irq(irq) 942 sprintf(nic->irq_name[irq], "%s-sq-%d", 943 nic->pnicvf->netdev->name, 944 nicvf_netdev_qidx(nic, irq - NICVF_INTR_ID_SQ)); 945 946 for_each_rbdr_irq(irq) 947 sprintf(nic->irq_name[irq], "%s-rbdr-%d", 948 nic->pnicvf->netdev->name, 949 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 950 951 /* Register CQ interrupts */ 952 for (irq = 0; irq < nic->qs->cq_cnt; irq++) { 953 vector = nic->msix_entries[irq].vector; 954 ret = request_irq(vector, nicvf_intr_handler, 955 0, nic->irq_name[irq], nic->napi[irq]); 956 if (ret) 957 goto err; 958 nic->irq_allocated[irq] = true; 959 } 960 961 /* Register RBDR interrupt */ 962 for (irq = NICVF_INTR_ID_RBDR; 963 irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) { 964 vector = nic->msix_entries[irq].vector; 965 ret = request_irq(vector, nicvf_rbdr_intr_handler, 966 0, nic->irq_name[irq], nic); 967 if (ret) 968 goto err; 969 nic->irq_allocated[irq] = true; 970 } 971 972 /* Register QS error interrupt */ 973 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR], "%s-qset-err-%d", 974 nic->pnicvf->netdev->name, 975 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 976 irq = NICVF_INTR_ID_QS_ERR; 977 ret = request_irq(nic->msix_entries[irq].vector, 978 nicvf_qs_err_intr_handler, 979 0, nic->irq_name[irq], nic); 980 if (ret) 981 goto err; 982 983 nic->irq_allocated[irq] = true; 984 985 /* Set IRQ affinities */ 986 nicvf_set_irq_affinity(nic); 987 988 err: 989 if (ret) 990 netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq); 991 992 return ret; 993 } 994 995 static void nicvf_unregister_interrupts(struct nicvf *nic) 996 { 997 int irq; 998 999 /* Free registered interrupts */ 1000 for (irq = 0; irq < nic->num_vec; irq++) { 1001 if (!nic->irq_allocated[irq]) 1002 continue; 1003 1004 irq_set_affinity_hint(nic->msix_entries[irq].vector, NULL); 1005 free_cpumask_var(nic->affinity_mask[irq]); 1006 1007 if (irq < NICVF_INTR_ID_SQ) 1008 free_irq(nic->msix_entries[irq].vector, nic->napi[irq]); 1009 else 1010 free_irq(nic->msix_entries[irq].vector, nic); 1011 1012 nic->irq_allocated[irq] = false; 1013 } 1014 1015 /* Disable MSI-X */ 1016 nicvf_disable_msix(nic); 1017 } 1018 1019 /* Initialize MSIX vectors and register MISC interrupt. 1020 * Send READY message to PF to check if its alive 1021 */ 1022 static int nicvf_register_misc_interrupt(struct nicvf *nic) 1023 { 1024 int ret = 0; 1025 int irq = NICVF_INTR_ID_MISC; 1026 1027 /* Return if mailbox interrupt is already registered */ 1028 if (nic->msix_enabled) 1029 return 0; 1030 1031 /* Enable MSI-X */ 1032 if (!nicvf_enable_msix(nic)) 1033 return 1; 1034 1035 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF"); 1036 /* Register Misc interrupt */ 1037 ret = request_irq(nic->msix_entries[irq].vector, 1038 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic); 1039 1040 if (ret) 1041 return ret; 1042 nic->irq_allocated[irq] = true; 1043 1044 /* Enable mailbox interrupt */ 1045 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0); 1046 1047 /* Check if VF is able to communicate with PF */ 1048 if (!nicvf_check_pf_ready(nic)) { 1049 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1050 nicvf_unregister_interrupts(nic); 1051 return 1; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev) 1058 { 1059 struct nicvf *nic = netdev_priv(netdev); 1060 int qid = skb_get_queue_mapping(skb); 1061 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid); 1062 struct nicvf *snic; 1063 struct snd_queue *sq; 1064 int tmp; 1065 1066 /* Check for minimum packet length */ 1067 if (skb->len <= ETH_HLEN) { 1068 dev_kfree_skb(skb); 1069 return NETDEV_TX_OK; 1070 } 1071 1072 snic = nic; 1073 /* Get secondary Qset's SQ structure */ 1074 if (qid >= MAX_SND_QUEUES_PER_QS) { 1075 tmp = qid / MAX_SND_QUEUES_PER_QS; 1076 snic = (struct nicvf *)nic->snicvf[tmp - 1]; 1077 if (!snic) { 1078 netdev_warn(nic->netdev, 1079 "Secondary Qset#%d's ptr not initialized\n", 1080 tmp - 1); 1081 dev_kfree_skb(skb); 1082 return NETDEV_TX_OK; 1083 } 1084 qid = qid % MAX_SND_QUEUES_PER_QS; 1085 } 1086 1087 sq = &snic->qs->sq[qid]; 1088 if (!netif_tx_queue_stopped(txq) && 1089 !nicvf_sq_append_skb(snic, sq, skb, qid)) { 1090 netif_tx_stop_queue(txq); 1091 1092 /* Barrier, so that stop_queue visible to other cpus */ 1093 smp_mb(); 1094 1095 /* Check again, incase another cpu freed descriptors */ 1096 if (atomic_read(&sq->free_cnt) > MIN_SQ_DESC_PER_PKT_XMIT) { 1097 netif_tx_wake_queue(txq); 1098 } else { 1099 this_cpu_inc(nic->drv_stats->txq_stop); 1100 if (netif_msg_tx_err(nic)) 1101 netdev_warn(netdev, 1102 "%s: Transmit ring full, stopping SQ%d\n", 1103 netdev->name, qid); 1104 } 1105 return NETDEV_TX_BUSY; 1106 } 1107 1108 return NETDEV_TX_OK; 1109 } 1110 1111 static inline void nicvf_free_cq_poll(struct nicvf *nic) 1112 { 1113 struct nicvf_cq_poll *cq_poll; 1114 int qidx; 1115 1116 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1117 cq_poll = nic->napi[qidx]; 1118 if (!cq_poll) 1119 continue; 1120 nic->napi[qidx] = NULL; 1121 kfree(cq_poll); 1122 } 1123 } 1124 1125 int nicvf_stop(struct net_device *netdev) 1126 { 1127 int irq, qidx; 1128 struct nicvf *nic = netdev_priv(netdev); 1129 struct queue_set *qs = nic->qs; 1130 struct nicvf_cq_poll *cq_poll = NULL; 1131 union nic_mbx mbx = {}; 1132 1133 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN; 1134 nicvf_send_msg_to_pf(nic, &mbx); 1135 1136 netif_carrier_off(netdev); 1137 netif_tx_stop_all_queues(nic->netdev); 1138 nic->link_up = false; 1139 1140 /* Teardown secondary qsets first */ 1141 if (!nic->sqs_mode) { 1142 for (qidx = 0; qidx < nic->sqs_count; qidx++) { 1143 if (!nic->snicvf[qidx]) 1144 continue; 1145 nicvf_stop(nic->snicvf[qidx]->netdev); 1146 nic->snicvf[qidx] = NULL; 1147 } 1148 } 1149 1150 /* Disable RBDR & QS error interrupts */ 1151 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1152 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 1153 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 1154 } 1155 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 1156 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 1157 1158 /* Wait for pending IRQ handlers to finish */ 1159 for (irq = 0; irq < nic->num_vec; irq++) 1160 synchronize_irq(nic->msix_entries[irq].vector); 1161 1162 tasklet_kill(&nic->rbdr_task); 1163 tasklet_kill(&nic->qs_err_task); 1164 if (nic->rb_work_scheduled) 1165 cancel_delayed_work_sync(&nic->rbdr_work); 1166 1167 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1168 cq_poll = nic->napi[qidx]; 1169 if (!cq_poll) 1170 continue; 1171 napi_synchronize(&cq_poll->napi); 1172 /* CQ intr is enabled while napi_complete, 1173 * so disable it now 1174 */ 1175 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 1176 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 1177 napi_disable(&cq_poll->napi); 1178 netif_napi_del(&cq_poll->napi); 1179 } 1180 1181 netif_tx_disable(netdev); 1182 1183 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1184 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1185 1186 /* Free resources */ 1187 nicvf_config_data_transfer(nic, false); 1188 1189 /* Disable HW Qset */ 1190 nicvf_qset_config(nic, false); 1191 1192 /* disable mailbox interrupt */ 1193 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1194 1195 nicvf_unregister_interrupts(nic); 1196 1197 nicvf_free_cq_poll(nic); 1198 1199 /* Clear multiqset info */ 1200 nic->pnicvf = nic; 1201 1202 return 0; 1203 } 1204 1205 static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) 1206 { 1207 union nic_mbx mbx = {}; 1208 1209 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; 1210 mbx.frs.max_frs = mtu; 1211 mbx.frs.vf_id = nic->vf_id; 1212 1213 return nicvf_send_msg_to_pf(nic, &mbx); 1214 } 1215 1216 int nicvf_open(struct net_device *netdev) 1217 { 1218 int cpu, err, qidx; 1219 struct nicvf *nic = netdev_priv(netdev); 1220 struct queue_set *qs = nic->qs; 1221 struct nicvf_cq_poll *cq_poll = NULL; 1222 union nic_mbx mbx = {}; 1223 1224 netif_carrier_off(netdev); 1225 1226 err = nicvf_register_misc_interrupt(nic); 1227 if (err) 1228 return err; 1229 1230 /* Register NAPI handler for processing CQEs */ 1231 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1232 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL); 1233 if (!cq_poll) { 1234 err = -ENOMEM; 1235 goto napi_del; 1236 } 1237 cq_poll->cq_idx = qidx; 1238 cq_poll->nicvf = nic; 1239 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll, 1240 NAPI_POLL_WEIGHT); 1241 napi_enable(&cq_poll->napi); 1242 nic->napi[qidx] = cq_poll; 1243 } 1244 1245 /* Check if we got MAC address from PF or else generate a radom MAC */ 1246 if (!nic->sqs_mode && is_zero_ether_addr(netdev->dev_addr)) { 1247 eth_hw_addr_random(netdev); 1248 nicvf_hw_set_mac_addr(nic, netdev); 1249 } 1250 1251 if (nic->set_mac_pending) { 1252 nic->set_mac_pending = false; 1253 nicvf_hw_set_mac_addr(nic, netdev); 1254 } 1255 1256 /* Init tasklet for handling Qset err interrupt */ 1257 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err, 1258 (unsigned long)nic); 1259 1260 /* Init RBDR tasklet which will refill RBDR */ 1261 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task, 1262 (unsigned long)nic); 1263 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work); 1264 1265 /* Configure CPI alorithm */ 1266 nic->cpi_alg = cpi_alg; 1267 if (!nic->sqs_mode) 1268 nicvf_config_cpi(nic); 1269 1270 nicvf_request_sqs(nic); 1271 if (nic->sqs_mode) 1272 nicvf_get_primary_vf_struct(nic); 1273 1274 /* Configure receive side scaling and MTU */ 1275 if (!nic->sqs_mode) { 1276 nicvf_rss_init(nic); 1277 if (nicvf_update_hw_max_frs(nic, netdev->mtu)) 1278 goto cleanup; 1279 1280 /* Clear percpu stats */ 1281 for_each_possible_cpu(cpu) 1282 memset(per_cpu_ptr(nic->drv_stats, cpu), 0, 1283 sizeof(struct nicvf_drv_stats)); 1284 } 1285 1286 err = nicvf_register_interrupts(nic); 1287 if (err) 1288 goto cleanup; 1289 1290 /* Initialize the queues */ 1291 err = nicvf_init_resources(nic); 1292 if (err) 1293 goto cleanup; 1294 1295 /* Make sure queue initialization is written */ 1296 wmb(); 1297 1298 nicvf_reg_write(nic, NIC_VF_INT, -1); 1299 /* Enable Qset err interrupt */ 1300 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 1301 1302 /* Enable completion queue interrupt */ 1303 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1304 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 1305 1306 /* Enable RBDR threshold interrupt */ 1307 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1308 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); 1309 1310 /* Send VF config done msg to PF */ 1311 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; 1312 nicvf_write_to_mbx(nic, &mbx); 1313 1314 return 0; 1315 cleanup: 1316 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1317 nicvf_unregister_interrupts(nic); 1318 tasklet_kill(&nic->qs_err_task); 1319 tasklet_kill(&nic->rbdr_task); 1320 napi_del: 1321 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1322 cq_poll = nic->napi[qidx]; 1323 if (!cq_poll) 1324 continue; 1325 napi_disable(&cq_poll->napi); 1326 netif_napi_del(&cq_poll->napi); 1327 } 1328 nicvf_free_cq_poll(nic); 1329 return err; 1330 } 1331 1332 static int nicvf_change_mtu(struct net_device *netdev, int new_mtu) 1333 { 1334 struct nicvf *nic = netdev_priv(netdev); 1335 int orig_mtu = netdev->mtu; 1336 1337 netdev->mtu = new_mtu; 1338 1339 if (!netif_running(netdev)) 1340 return 0; 1341 1342 if (nicvf_update_hw_max_frs(nic, new_mtu)) { 1343 netdev->mtu = orig_mtu; 1344 return -EINVAL; 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int nicvf_set_mac_address(struct net_device *netdev, void *p) 1351 { 1352 struct sockaddr *addr = p; 1353 struct nicvf *nic = netdev_priv(netdev); 1354 1355 if (!is_valid_ether_addr(addr->sa_data)) 1356 return -EADDRNOTAVAIL; 1357 1358 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1359 1360 if (nic->msix_enabled) { 1361 if (nicvf_hw_set_mac_addr(nic, netdev)) 1362 return -EBUSY; 1363 } else { 1364 nic->set_mac_pending = true; 1365 } 1366 1367 return 0; 1368 } 1369 1370 void nicvf_update_lmac_stats(struct nicvf *nic) 1371 { 1372 int stat = 0; 1373 union nic_mbx mbx = {}; 1374 1375 if (!netif_running(nic->netdev)) 1376 return; 1377 1378 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 1379 mbx.bgx_stats.vf_id = nic->vf_id; 1380 /* Rx stats */ 1381 mbx.bgx_stats.rx = 1; 1382 while (stat < BGX_RX_STATS_COUNT) { 1383 mbx.bgx_stats.idx = stat; 1384 if (nicvf_send_msg_to_pf(nic, &mbx)) 1385 return; 1386 stat++; 1387 } 1388 1389 stat = 0; 1390 1391 /* Tx stats */ 1392 mbx.bgx_stats.rx = 0; 1393 while (stat < BGX_TX_STATS_COUNT) { 1394 mbx.bgx_stats.idx = stat; 1395 if (nicvf_send_msg_to_pf(nic, &mbx)) 1396 return; 1397 stat++; 1398 } 1399 } 1400 1401 void nicvf_update_stats(struct nicvf *nic) 1402 { 1403 int qidx, cpu; 1404 u64 tmp_stats = 0; 1405 struct nicvf_hw_stats *stats = &nic->hw_stats; 1406 struct nicvf_drv_stats *drv_stats; 1407 struct queue_set *qs = nic->qs; 1408 1409 #define GET_RX_STATS(reg) \ 1410 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3)) 1411 #define GET_TX_STATS(reg) \ 1412 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3)) 1413 1414 stats->rx_bytes = GET_RX_STATS(RX_OCTS); 1415 stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST); 1416 stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST); 1417 stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST); 1418 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS); 1419 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR); 1420 stats->rx_drop_red = GET_RX_STATS(RX_RED); 1421 stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS); 1422 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN); 1423 stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS); 1424 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST); 1425 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST); 1426 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); 1427 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); 1428 1429 stats->tx_bytes = GET_TX_STATS(TX_OCTS); 1430 stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST); 1431 stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST); 1432 stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST); 1433 stats->tx_drops = GET_TX_STATS(TX_DROP); 1434 1435 /* On T88 pass 2.0, the dummy SQE added for TSO notification 1436 * via CQE has 'dont_send' set. Hence HW drops the pkt pointed 1437 * pointed by dummy SQE and results in tx_drops counter being 1438 * incremented. Subtracting it from tx_tso counter will give 1439 * exact tx_drops counter. 1440 */ 1441 if (nic->t88 && nic->hw_tso) { 1442 for_each_possible_cpu(cpu) { 1443 drv_stats = per_cpu_ptr(nic->drv_stats, cpu); 1444 tmp_stats += drv_stats->tx_tso; 1445 } 1446 stats->tx_drops = tmp_stats - stats->tx_drops; 1447 } 1448 stats->tx_frames = stats->tx_ucast_frames + 1449 stats->tx_bcast_frames + 1450 stats->tx_mcast_frames; 1451 stats->rx_frames = stats->rx_ucast_frames + 1452 stats->rx_bcast_frames + 1453 stats->rx_mcast_frames; 1454 stats->rx_drops = stats->rx_drop_red + 1455 stats->rx_drop_overrun; 1456 1457 /* Update RQ and SQ stats */ 1458 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1459 nicvf_update_rq_stats(nic, qidx); 1460 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1461 nicvf_update_sq_stats(nic, qidx); 1462 } 1463 1464 static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev, 1465 struct rtnl_link_stats64 *stats) 1466 { 1467 struct nicvf *nic = netdev_priv(netdev); 1468 struct nicvf_hw_stats *hw_stats = &nic->hw_stats; 1469 1470 nicvf_update_stats(nic); 1471 1472 stats->rx_bytes = hw_stats->rx_bytes; 1473 stats->rx_packets = hw_stats->rx_frames; 1474 stats->rx_dropped = hw_stats->rx_drops; 1475 stats->multicast = hw_stats->rx_mcast_frames; 1476 1477 stats->tx_bytes = hw_stats->tx_bytes; 1478 stats->tx_packets = hw_stats->tx_frames; 1479 stats->tx_dropped = hw_stats->tx_drops; 1480 1481 return stats; 1482 } 1483 1484 static void nicvf_tx_timeout(struct net_device *dev) 1485 { 1486 struct nicvf *nic = netdev_priv(dev); 1487 1488 if (netif_msg_tx_err(nic)) 1489 netdev_warn(dev, "%s: Transmit timed out, resetting\n", 1490 dev->name); 1491 1492 this_cpu_inc(nic->drv_stats->tx_timeout); 1493 schedule_work(&nic->reset_task); 1494 } 1495 1496 static void nicvf_reset_task(struct work_struct *work) 1497 { 1498 struct nicvf *nic; 1499 1500 nic = container_of(work, struct nicvf, reset_task); 1501 1502 if (!netif_running(nic->netdev)) 1503 return; 1504 1505 nicvf_stop(nic->netdev); 1506 nicvf_open(nic->netdev); 1507 netif_trans_update(nic->netdev); 1508 } 1509 1510 static int nicvf_config_loopback(struct nicvf *nic, 1511 netdev_features_t features) 1512 { 1513 union nic_mbx mbx = {}; 1514 1515 mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK; 1516 mbx.lbk.vf_id = nic->vf_id; 1517 mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0; 1518 1519 return nicvf_send_msg_to_pf(nic, &mbx); 1520 } 1521 1522 static netdev_features_t nicvf_fix_features(struct net_device *netdev, 1523 netdev_features_t features) 1524 { 1525 struct nicvf *nic = netdev_priv(netdev); 1526 1527 if ((features & NETIF_F_LOOPBACK) && 1528 netif_running(netdev) && !nic->loopback_supported) 1529 features &= ~NETIF_F_LOOPBACK; 1530 1531 return features; 1532 } 1533 1534 static int nicvf_set_features(struct net_device *netdev, 1535 netdev_features_t features) 1536 { 1537 struct nicvf *nic = netdev_priv(netdev); 1538 netdev_features_t changed = features ^ netdev->features; 1539 1540 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 1541 nicvf_config_vlan_stripping(nic, features); 1542 1543 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1544 return nicvf_config_loopback(nic, features); 1545 1546 return 0; 1547 } 1548 1549 static const struct net_device_ops nicvf_netdev_ops = { 1550 .ndo_open = nicvf_open, 1551 .ndo_stop = nicvf_stop, 1552 .ndo_start_xmit = nicvf_xmit, 1553 .ndo_change_mtu = nicvf_change_mtu, 1554 .ndo_set_mac_address = nicvf_set_mac_address, 1555 .ndo_get_stats64 = nicvf_get_stats64, 1556 .ndo_tx_timeout = nicvf_tx_timeout, 1557 .ndo_fix_features = nicvf_fix_features, 1558 .ndo_set_features = nicvf_set_features, 1559 }; 1560 1561 static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1562 { 1563 struct device *dev = &pdev->dev; 1564 struct net_device *netdev; 1565 struct nicvf *nic; 1566 int err, qcount; 1567 u16 sdevid; 1568 1569 err = pci_enable_device(pdev); 1570 if (err) { 1571 dev_err(dev, "Failed to enable PCI device\n"); 1572 return err; 1573 } 1574 1575 err = pci_request_regions(pdev, DRV_NAME); 1576 if (err) { 1577 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1578 goto err_disable_device; 1579 } 1580 1581 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 1582 if (err) { 1583 dev_err(dev, "Unable to get usable DMA configuration\n"); 1584 goto err_release_regions; 1585 } 1586 1587 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 1588 if (err) { 1589 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n"); 1590 goto err_release_regions; 1591 } 1592 1593 qcount = netif_get_num_default_rss_queues(); 1594 1595 /* Restrict multiqset support only for host bound VFs */ 1596 if (pdev->is_virtfn) { 1597 /* Set max number of queues per VF */ 1598 qcount = min_t(int, num_online_cpus(), 1599 (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS); 1600 } 1601 1602 netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount); 1603 if (!netdev) { 1604 err = -ENOMEM; 1605 goto err_release_regions; 1606 } 1607 1608 pci_set_drvdata(pdev, netdev); 1609 1610 SET_NETDEV_DEV(netdev, &pdev->dev); 1611 1612 nic = netdev_priv(netdev); 1613 nic->netdev = netdev; 1614 nic->pdev = pdev; 1615 nic->pnicvf = nic; 1616 nic->max_queues = qcount; 1617 1618 /* MAP VF's configuration registers */ 1619 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1620 if (!nic->reg_base) { 1621 dev_err(dev, "Cannot map config register space, aborting\n"); 1622 err = -ENOMEM; 1623 goto err_free_netdev; 1624 } 1625 1626 nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats); 1627 if (!nic->drv_stats) { 1628 err = -ENOMEM; 1629 goto err_free_netdev; 1630 } 1631 1632 err = nicvf_set_qset_resources(nic); 1633 if (err) 1634 goto err_free_netdev; 1635 1636 /* Check if PF is alive and get MAC address for this VF */ 1637 err = nicvf_register_misc_interrupt(nic); 1638 if (err) 1639 goto err_free_netdev; 1640 1641 nicvf_send_vf_struct(nic); 1642 1643 if (!pass1_silicon(nic->pdev)) 1644 nic->hw_tso = true; 1645 1646 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 1647 if (sdevid == 0xA134) 1648 nic->t88 = true; 1649 1650 /* Check if this VF is in QS only mode */ 1651 if (nic->sqs_mode) 1652 return 0; 1653 1654 err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues); 1655 if (err) 1656 goto err_unregister_interrupts; 1657 1658 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 1659 NETIF_F_TSO | NETIF_F_GRO | 1660 NETIF_F_HW_VLAN_CTAG_RX); 1661 1662 netdev->hw_features |= NETIF_F_RXHASH; 1663 1664 netdev->features |= netdev->hw_features; 1665 netdev->hw_features |= NETIF_F_LOOPBACK; 1666 1667 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 1668 1669 netdev->netdev_ops = &nicvf_netdev_ops; 1670 netdev->watchdog_timeo = NICVF_TX_TIMEOUT; 1671 1672 /* MTU range: 64 - 9200 */ 1673 netdev->min_mtu = NIC_HW_MIN_FRS; 1674 netdev->max_mtu = NIC_HW_MAX_FRS; 1675 1676 INIT_WORK(&nic->reset_task, nicvf_reset_task); 1677 1678 err = register_netdev(netdev); 1679 if (err) { 1680 dev_err(dev, "Failed to register netdevice\n"); 1681 goto err_unregister_interrupts; 1682 } 1683 1684 nic->msg_enable = debug; 1685 1686 nicvf_set_ethtool_ops(netdev); 1687 1688 return 0; 1689 1690 err_unregister_interrupts: 1691 nicvf_unregister_interrupts(nic); 1692 err_free_netdev: 1693 pci_set_drvdata(pdev, NULL); 1694 if (nic->drv_stats) 1695 free_percpu(nic->drv_stats); 1696 free_netdev(netdev); 1697 err_release_regions: 1698 pci_release_regions(pdev); 1699 err_disable_device: 1700 pci_disable_device(pdev); 1701 return err; 1702 } 1703 1704 static void nicvf_remove(struct pci_dev *pdev) 1705 { 1706 struct net_device *netdev = pci_get_drvdata(pdev); 1707 struct nicvf *nic; 1708 struct net_device *pnetdev; 1709 1710 if (!netdev) 1711 return; 1712 1713 nic = netdev_priv(netdev); 1714 pnetdev = nic->pnicvf->netdev; 1715 1716 /* Check if this Qset is assigned to different VF. 1717 * If yes, clean primary and all secondary Qsets. 1718 */ 1719 if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED)) 1720 unregister_netdev(pnetdev); 1721 nicvf_unregister_interrupts(nic); 1722 pci_set_drvdata(pdev, NULL); 1723 if (nic->drv_stats) 1724 free_percpu(nic->drv_stats); 1725 free_netdev(netdev); 1726 pci_release_regions(pdev); 1727 pci_disable_device(pdev); 1728 } 1729 1730 static void nicvf_shutdown(struct pci_dev *pdev) 1731 { 1732 nicvf_remove(pdev); 1733 } 1734 1735 static struct pci_driver nicvf_driver = { 1736 .name = DRV_NAME, 1737 .id_table = nicvf_id_table, 1738 .probe = nicvf_probe, 1739 .remove = nicvf_remove, 1740 .shutdown = nicvf_shutdown, 1741 }; 1742 1743 static int __init nicvf_init_module(void) 1744 { 1745 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1746 1747 return pci_register_driver(&nicvf_driver); 1748 } 1749 1750 static void __exit nicvf_cleanup_module(void) 1751 { 1752 pci_unregister_driver(&nicvf_driver); 1753 } 1754 1755 module_init(nicvf_init_module); 1756 module_exit(nicvf_cleanup_module); 1757