1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/if_vlan.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/log2.h> 17 #include <linux/prefetch.h> 18 #include <linux/irq.h> 19 #include <linux/iommu.h> 20 #include <linux/bpf.h> 21 #include <linux/bpf_trace.h> 22 #include <linux/filter.h> 23 24 #include "nic_reg.h" 25 #include "nic.h" 26 #include "nicvf_queues.h" 27 #include "thunder_bgx.h" 28 29 #define DRV_NAME "thunder-nicvf" 30 #define DRV_VERSION "1.0" 31 32 /* Supported devices */ 33 static const struct pci_device_id nicvf_id_table[] = { 34 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 35 PCI_DEVICE_ID_THUNDER_NIC_VF, 36 PCI_VENDOR_ID_CAVIUM, 37 PCI_SUBSYS_DEVID_88XX_NIC_VF) }, 38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 39 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF, 40 PCI_VENDOR_ID_CAVIUM, 41 PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF) }, 42 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 43 PCI_DEVICE_ID_THUNDER_NIC_VF, 44 PCI_VENDOR_ID_CAVIUM, 45 PCI_SUBSYS_DEVID_81XX_NIC_VF) }, 46 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 47 PCI_DEVICE_ID_THUNDER_NIC_VF, 48 PCI_VENDOR_ID_CAVIUM, 49 PCI_SUBSYS_DEVID_83XX_NIC_VF) }, 50 { 0, } /* end of table */ 51 }; 52 53 MODULE_AUTHOR("Sunil Goutham"); 54 MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver"); 55 MODULE_LICENSE("GPL v2"); 56 MODULE_VERSION(DRV_VERSION); 57 MODULE_DEVICE_TABLE(pci, nicvf_id_table); 58 59 static int debug = 0x00; 60 module_param(debug, int, 0644); 61 MODULE_PARM_DESC(debug, "Debug message level bitmap"); 62 63 static int cpi_alg = CPI_ALG_NONE; 64 module_param(cpi_alg, int, S_IRUGO); 65 MODULE_PARM_DESC(cpi_alg, 66 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)"); 67 68 static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx) 69 { 70 if (nic->sqs_mode) 71 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS); 72 else 73 return qidx; 74 } 75 76 /* The Cavium ThunderX network controller can *only* be found in SoCs 77 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 78 * registers on this platform are implicitly strongly ordered with respect 79 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 80 * with no memory barriers in this driver. The readq()/writeq() functions add 81 * explicit ordering operation which in this case are redundant, and only 82 * add overhead. 83 */ 84 85 /* Register read/write APIs */ 86 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val) 87 { 88 writeq_relaxed(val, nic->reg_base + offset); 89 } 90 91 u64 nicvf_reg_read(struct nicvf *nic, u64 offset) 92 { 93 return readq_relaxed(nic->reg_base + offset); 94 } 95 96 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset, 97 u64 qidx, u64 val) 98 { 99 void __iomem *addr = nic->reg_base + offset; 100 101 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT)); 102 } 103 104 u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx) 105 { 106 void __iomem *addr = nic->reg_base + offset; 107 108 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT)); 109 } 110 111 /* VF -> PF mailbox communication */ 112 static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx) 113 { 114 u64 *msg = (u64 *)mbx; 115 116 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]); 117 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]); 118 } 119 120 int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx) 121 { 122 int timeout = NIC_MBOX_MSG_TIMEOUT; 123 int sleep = 10; 124 125 nic->pf_acked = false; 126 nic->pf_nacked = false; 127 128 nicvf_write_to_mbx(nic, mbx); 129 130 /* Wait for previous message to be acked, timeout 2sec */ 131 while (!nic->pf_acked) { 132 if (nic->pf_nacked) { 133 netdev_err(nic->netdev, 134 "PF NACK to mbox msg 0x%02x from VF%d\n", 135 (mbx->msg.msg & 0xFF), nic->vf_id); 136 return -EINVAL; 137 } 138 msleep(sleep); 139 if (nic->pf_acked) 140 break; 141 timeout -= sleep; 142 if (!timeout) { 143 netdev_err(nic->netdev, 144 "PF didn't ACK to mbox msg 0x%02x from VF%d\n", 145 (mbx->msg.msg & 0xFF), nic->vf_id); 146 return -EBUSY; 147 } 148 } 149 return 0; 150 } 151 152 /* Checks if VF is able to comminicate with PF 153 * and also gets the VNIC number this VF is associated to. 154 */ 155 static int nicvf_check_pf_ready(struct nicvf *nic) 156 { 157 union nic_mbx mbx = {}; 158 159 mbx.msg.msg = NIC_MBOX_MSG_READY; 160 if (nicvf_send_msg_to_pf(nic, &mbx)) { 161 netdev_err(nic->netdev, 162 "PF didn't respond to READY msg\n"); 163 return 0; 164 } 165 166 return 1; 167 } 168 169 static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx) 170 { 171 if (bgx->rx) 172 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats; 173 else 174 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats; 175 } 176 177 static void nicvf_handle_mbx_intr(struct nicvf *nic) 178 { 179 union nic_mbx mbx = {}; 180 u64 *mbx_data; 181 u64 mbx_addr; 182 int i; 183 184 mbx_addr = NIC_VF_PF_MAILBOX_0_1; 185 mbx_data = (u64 *)&mbx; 186 187 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 188 *mbx_data = nicvf_reg_read(nic, mbx_addr); 189 mbx_data++; 190 mbx_addr += sizeof(u64); 191 } 192 193 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg); 194 switch (mbx.msg.msg) { 195 case NIC_MBOX_MSG_READY: 196 nic->pf_acked = true; 197 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F; 198 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F; 199 nic->node = mbx.nic_cfg.node_id; 200 if (!nic->set_mac_pending) 201 ether_addr_copy(nic->netdev->dev_addr, 202 mbx.nic_cfg.mac_addr); 203 nic->sqs_mode = mbx.nic_cfg.sqs_mode; 204 nic->loopback_supported = mbx.nic_cfg.loopback_supported; 205 nic->link_up = false; 206 nic->duplex = 0; 207 nic->speed = 0; 208 break; 209 case NIC_MBOX_MSG_ACK: 210 nic->pf_acked = true; 211 break; 212 case NIC_MBOX_MSG_NACK: 213 nic->pf_nacked = true; 214 break; 215 case NIC_MBOX_MSG_RSS_SIZE: 216 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size; 217 nic->pf_acked = true; 218 break; 219 case NIC_MBOX_MSG_BGX_STATS: 220 nicvf_read_bgx_stats(nic, &mbx.bgx_stats); 221 nic->pf_acked = true; 222 break; 223 case NIC_MBOX_MSG_BGX_LINK_CHANGE: 224 nic->pf_acked = true; 225 nic->link_up = mbx.link_status.link_up; 226 nic->duplex = mbx.link_status.duplex; 227 nic->speed = mbx.link_status.speed; 228 nic->mac_type = mbx.link_status.mac_type; 229 if (nic->link_up) { 230 netdev_info(nic->netdev, "Link is Up %d Mbps %s duplex\n", 231 nic->speed, 232 nic->duplex == DUPLEX_FULL ? 233 "Full" : "Half"); 234 netif_carrier_on(nic->netdev); 235 netif_tx_start_all_queues(nic->netdev); 236 } else { 237 netdev_info(nic->netdev, "Link is Down\n"); 238 netif_carrier_off(nic->netdev); 239 netif_tx_stop_all_queues(nic->netdev); 240 } 241 break; 242 case NIC_MBOX_MSG_ALLOC_SQS: 243 nic->sqs_count = mbx.sqs_alloc.qs_count; 244 nic->pf_acked = true; 245 break; 246 case NIC_MBOX_MSG_SNICVF_PTR: 247 /* Primary VF: make note of secondary VF's pointer 248 * to be used while packet transmission. 249 */ 250 nic->snicvf[mbx.nicvf.sqs_id] = 251 (struct nicvf *)mbx.nicvf.nicvf; 252 nic->pf_acked = true; 253 break; 254 case NIC_MBOX_MSG_PNICVF_PTR: 255 /* Secondary VF/Qset: make note of primary VF's pointer 256 * to be used while packet reception, to handover packet 257 * to primary VF's netdev. 258 */ 259 nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf; 260 nic->pf_acked = true; 261 break; 262 case NIC_MBOX_MSG_PFC: 263 nic->pfc.autoneg = mbx.pfc.autoneg; 264 nic->pfc.fc_rx = mbx.pfc.fc_rx; 265 nic->pfc.fc_tx = mbx.pfc.fc_tx; 266 nic->pf_acked = true; 267 break; 268 default: 269 netdev_err(nic->netdev, 270 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg); 271 break; 272 } 273 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0); 274 } 275 276 static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev) 277 { 278 union nic_mbx mbx = {}; 279 280 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC; 281 mbx.mac.vf_id = nic->vf_id; 282 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr); 283 284 return nicvf_send_msg_to_pf(nic, &mbx); 285 } 286 287 static void nicvf_config_cpi(struct nicvf *nic) 288 { 289 union nic_mbx mbx = {}; 290 291 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG; 292 mbx.cpi_cfg.vf_id = nic->vf_id; 293 mbx.cpi_cfg.cpi_alg = nic->cpi_alg; 294 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt; 295 296 nicvf_send_msg_to_pf(nic, &mbx); 297 } 298 299 static void nicvf_get_rss_size(struct nicvf *nic) 300 { 301 union nic_mbx mbx = {}; 302 303 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 304 mbx.rss_size.vf_id = nic->vf_id; 305 nicvf_send_msg_to_pf(nic, &mbx); 306 } 307 308 void nicvf_config_rss(struct nicvf *nic) 309 { 310 union nic_mbx mbx = {}; 311 struct nicvf_rss_info *rss = &nic->rss_info; 312 int ind_tbl_len = rss->rss_size; 313 int i, nextq = 0; 314 315 mbx.rss_cfg.vf_id = nic->vf_id; 316 mbx.rss_cfg.hash_bits = rss->hash_bits; 317 while (ind_tbl_len) { 318 mbx.rss_cfg.tbl_offset = nextq; 319 mbx.rss_cfg.tbl_len = min(ind_tbl_len, 320 RSS_IND_TBL_LEN_PER_MBX_MSG); 321 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ? 322 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG; 323 324 for (i = 0; i < mbx.rss_cfg.tbl_len; i++) 325 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++]; 326 327 nicvf_send_msg_to_pf(nic, &mbx); 328 329 ind_tbl_len -= mbx.rss_cfg.tbl_len; 330 } 331 } 332 333 void nicvf_set_rss_key(struct nicvf *nic) 334 { 335 struct nicvf_rss_info *rss = &nic->rss_info; 336 u64 key_addr = NIC_VNIC_RSS_KEY_0_4; 337 int idx; 338 339 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) { 340 nicvf_reg_write(nic, key_addr, rss->key[idx]); 341 key_addr += sizeof(u64); 342 } 343 } 344 345 static int nicvf_rss_init(struct nicvf *nic) 346 { 347 struct nicvf_rss_info *rss = &nic->rss_info; 348 int idx; 349 350 nicvf_get_rss_size(nic); 351 352 if (cpi_alg != CPI_ALG_NONE) { 353 rss->enable = false; 354 rss->hash_bits = 0; 355 return 0; 356 } 357 358 rss->enable = true; 359 360 netdev_rss_key_fill(rss->key, RSS_HASH_KEY_SIZE * sizeof(u64)); 361 nicvf_set_rss_key(nic); 362 363 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA; 364 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg); 365 366 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size)); 367 368 for (idx = 0; idx < rss->rss_size; idx++) 369 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx, 370 nic->rx_queues); 371 nicvf_config_rss(nic); 372 return 1; 373 } 374 375 /* Request PF to allocate additional Qsets */ 376 static void nicvf_request_sqs(struct nicvf *nic) 377 { 378 union nic_mbx mbx = {}; 379 int sqs; 380 int sqs_count = nic->sqs_count; 381 int rx_queues = 0, tx_queues = 0; 382 383 /* Only primary VF should request */ 384 if (nic->sqs_mode || !nic->sqs_count) 385 return; 386 387 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 388 mbx.sqs_alloc.vf_id = nic->vf_id; 389 mbx.sqs_alloc.qs_count = nic->sqs_count; 390 if (nicvf_send_msg_to_pf(nic, &mbx)) { 391 /* No response from PF */ 392 nic->sqs_count = 0; 393 return; 394 } 395 396 /* Return if no Secondary Qsets available */ 397 if (!nic->sqs_count) 398 return; 399 400 if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS) 401 rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS; 402 403 tx_queues = nic->tx_queues + nic->xdp_tx_queues; 404 if (tx_queues > MAX_SND_QUEUES_PER_QS) 405 tx_queues = tx_queues - MAX_SND_QUEUES_PER_QS; 406 407 /* Set no of Rx/Tx queues in each of the SQsets */ 408 for (sqs = 0; sqs < nic->sqs_count; sqs++) { 409 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 410 mbx.nicvf.vf_id = nic->vf_id; 411 mbx.nicvf.sqs_id = sqs; 412 nicvf_send_msg_to_pf(nic, &mbx); 413 414 nic->snicvf[sqs]->sqs_id = sqs; 415 if (rx_queues > MAX_RCV_QUEUES_PER_QS) { 416 nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS; 417 rx_queues -= MAX_RCV_QUEUES_PER_QS; 418 } else { 419 nic->snicvf[sqs]->qs->rq_cnt = rx_queues; 420 rx_queues = 0; 421 } 422 423 if (tx_queues > MAX_SND_QUEUES_PER_QS) { 424 nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS; 425 tx_queues -= MAX_SND_QUEUES_PER_QS; 426 } else { 427 nic->snicvf[sqs]->qs->sq_cnt = tx_queues; 428 tx_queues = 0; 429 } 430 431 nic->snicvf[sqs]->qs->cq_cnt = 432 max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt); 433 434 /* Initialize secondary Qset's queues and its interrupts */ 435 nicvf_open(nic->snicvf[sqs]->netdev); 436 } 437 438 /* Update stack with actual Rx/Tx queue count allocated */ 439 if (sqs_count != nic->sqs_count) 440 nicvf_set_real_num_queues(nic->netdev, 441 nic->tx_queues, nic->rx_queues); 442 } 443 444 /* Send this Qset's nicvf pointer to PF. 445 * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs 446 * so that packets received by these Qsets can use primary VF's netdev 447 */ 448 static void nicvf_send_vf_struct(struct nicvf *nic) 449 { 450 union nic_mbx mbx = {}; 451 452 mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR; 453 mbx.nicvf.sqs_mode = nic->sqs_mode; 454 mbx.nicvf.nicvf = (u64)nic; 455 nicvf_send_msg_to_pf(nic, &mbx); 456 } 457 458 static void nicvf_get_primary_vf_struct(struct nicvf *nic) 459 { 460 union nic_mbx mbx = {}; 461 462 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 463 nicvf_send_msg_to_pf(nic, &mbx); 464 } 465 466 int nicvf_set_real_num_queues(struct net_device *netdev, 467 int tx_queues, int rx_queues) 468 { 469 int err = 0; 470 471 err = netif_set_real_num_tx_queues(netdev, tx_queues); 472 if (err) { 473 netdev_err(netdev, 474 "Failed to set no of Tx queues: %d\n", tx_queues); 475 return err; 476 } 477 478 err = netif_set_real_num_rx_queues(netdev, rx_queues); 479 if (err) 480 netdev_err(netdev, 481 "Failed to set no of Rx queues: %d\n", rx_queues); 482 return err; 483 } 484 485 static int nicvf_init_resources(struct nicvf *nic) 486 { 487 int err; 488 489 /* Enable Qset */ 490 nicvf_qset_config(nic, true); 491 492 /* Initialize queues and HW for data transfer */ 493 err = nicvf_config_data_transfer(nic, true); 494 if (err) { 495 netdev_err(nic->netdev, 496 "Failed to alloc/config VF's QSet resources\n"); 497 return err; 498 } 499 500 return 0; 501 } 502 503 static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog, 504 struct cqe_rx_t *cqe_rx, struct snd_queue *sq, 505 struct sk_buff **skb) 506 { 507 struct xdp_buff xdp; 508 struct page *page; 509 u32 action; 510 u16 len, offset = 0; 511 u64 dma_addr, cpu_addr; 512 void *orig_data; 513 514 /* Retrieve packet buffer's DMA address and length */ 515 len = *((u16 *)((void *)cqe_rx + (3 * sizeof(u64)))); 516 dma_addr = *((u64 *)((void *)cqe_rx + (7 * sizeof(u64)))); 517 518 cpu_addr = nicvf_iova_to_phys(nic, dma_addr); 519 if (!cpu_addr) 520 return false; 521 cpu_addr = (u64)phys_to_virt(cpu_addr); 522 page = virt_to_page((void *)cpu_addr); 523 524 xdp.data_hard_start = page_address(page); 525 xdp.data = (void *)cpu_addr; 526 xdp_set_data_meta_invalid(&xdp); 527 xdp.data_end = xdp.data + len; 528 orig_data = xdp.data; 529 530 rcu_read_lock(); 531 action = bpf_prog_run_xdp(prog, &xdp); 532 rcu_read_unlock(); 533 534 /* Check if XDP program has changed headers */ 535 if (orig_data != xdp.data) { 536 len = xdp.data_end - xdp.data; 537 offset = orig_data - xdp.data; 538 dma_addr -= offset; 539 } 540 541 switch (action) { 542 case XDP_PASS: 543 /* Check if it's a recycled page, if not 544 * unmap the DMA mapping. 545 * 546 * Recycled page holds an extra reference. 547 */ 548 if (page_ref_count(page) == 1) { 549 dma_addr &= PAGE_MASK; 550 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, 551 RCV_FRAG_LEN + XDP_PACKET_HEADROOM, 552 DMA_FROM_DEVICE, 553 DMA_ATTR_SKIP_CPU_SYNC); 554 } 555 556 /* Build SKB and pass on packet to network stack */ 557 *skb = build_skb(xdp.data, 558 RCV_FRAG_LEN - cqe_rx->align_pad + offset); 559 if (!*skb) 560 put_page(page); 561 else 562 skb_put(*skb, len); 563 return false; 564 case XDP_TX: 565 nicvf_xdp_sq_append_pkt(nic, sq, (u64)xdp.data, dma_addr, len); 566 return true; 567 default: 568 bpf_warn_invalid_xdp_action(action); 569 /* fall through */ 570 case XDP_ABORTED: 571 trace_xdp_exception(nic->netdev, prog, action); 572 /* fall through */ 573 case XDP_DROP: 574 /* Check if it's a recycled page, if not 575 * unmap the DMA mapping. 576 * 577 * Recycled page holds an extra reference. 578 */ 579 if (page_ref_count(page) == 1) { 580 dma_addr &= PAGE_MASK; 581 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, 582 RCV_FRAG_LEN + XDP_PACKET_HEADROOM, 583 DMA_FROM_DEVICE, 584 DMA_ATTR_SKIP_CPU_SYNC); 585 } 586 put_page(page); 587 return true; 588 } 589 return false; 590 } 591 592 static void nicvf_snd_pkt_handler(struct net_device *netdev, 593 struct cqe_send_t *cqe_tx, 594 int budget, int *subdesc_cnt, 595 unsigned int *tx_pkts, unsigned int *tx_bytes) 596 { 597 struct sk_buff *skb = NULL; 598 struct page *page; 599 struct nicvf *nic = netdev_priv(netdev); 600 struct snd_queue *sq; 601 struct sq_hdr_subdesc *hdr; 602 struct sq_hdr_subdesc *tso_sqe; 603 604 sq = &nic->qs->sq[cqe_tx->sq_idx]; 605 606 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr); 607 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) 608 return; 609 610 /* Check for errors */ 611 if (cqe_tx->send_status) 612 nicvf_check_cqe_tx_errs(nic->pnicvf, cqe_tx); 613 614 /* Is this a XDP designated Tx queue */ 615 if (sq->is_xdp) { 616 page = (struct page *)sq->xdp_page[cqe_tx->sqe_ptr]; 617 /* Check if it's recycled page or else unmap DMA mapping */ 618 if (page && (page_ref_count(page) == 1)) 619 nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr, 620 hdr->subdesc_cnt); 621 622 /* Release page reference for recycling */ 623 if (page) 624 put_page(page); 625 sq->xdp_page[cqe_tx->sqe_ptr] = (u64)NULL; 626 *subdesc_cnt += hdr->subdesc_cnt + 1; 627 return; 628 } 629 630 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr]; 631 if (skb) { 632 /* Check for dummy descriptor used for HW TSO offload on 88xx */ 633 if (hdr->dont_send) { 634 /* Get actual TSO descriptors and free them */ 635 tso_sqe = 636 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2); 637 nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2, 638 tso_sqe->subdesc_cnt); 639 *subdesc_cnt += tso_sqe->subdesc_cnt + 1; 640 } else { 641 nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr, 642 hdr->subdesc_cnt); 643 } 644 *subdesc_cnt += hdr->subdesc_cnt + 1; 645 prefetch(skb); 646 (*tx_pkts)++; 647 *tx_bytes += skb->len; 648 napi_consume_skb(skb, budget); 649 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL; 650 } else { 651 /* In case of SW TSO on 88xx, only last segment will have 652 * a SKB attached, so just free SQEs here. 653 */ 654 if (!nic->hw_tso) 655 *subdesc_cnt += hdr->subdesc_cnt + 1; 656 } 657 } 658 659 static inline void nicvf_set_rxhash(struct net_device *netdev, 660 struct cqe_rx_t *cqe_rx, 661 struct sk_buff *skb) 662 { 663 u8 hash_type; 664 u32 hash; 665 666 if (!(netdev->features & NETIF_F_RXHASH)) 667 return; 668 669 switch (cqe_rx->rss_alg) { 670 case RSS_ALG_TCP_IP: 671 case RSS_ALG_UDP_IP: 672 hash_type = PKT_HASH_TYPE_L4; 673 hash = cqe_rx->rss_tag; 674 break; 675 case RSS_ALG_IP: 676 hash_type = PKT_HASH_TYPE_L3; 677 hash = cqe_rx->rss_tag; 678 break; 679 default: 680 hash_type = PKT_HASH_TYPE_NONE; 681 hash = 0; 682 } 683 684 skb_set_hash(skb, hash, hash_type); 685 } 686 687 static void nicvf_rcv_pkt_handler(struct net_device *netdev, 688 struct napi_struct *napi, 689 struct cqe_rx_t *cqe_rx, struct snd_queue *sq) 690 { 691 struct sk_buff *skb = NULL; 692 struct nicvf *nic = netdev_priv(netdev); 693 struct nicvf *snic = nic; 694 int err = 0; 695 int rq_idx; 696 697 rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx); 698 699 if (nic->sqs_mode) { 700 /* Use primary VF's 'nicvf' struct */ 701 nic = nic->pnicvf; 702 netdev = nic->netdev; 703 } 704 705 /* Check for errors */ 706 if (cqe_rx->err_level || cqe_rx->err_opcode) { 707 err = nicvf_check_cqe_rx_errs(nic, cqe_rx); 708 if (err && !cqe_rx->rb_cnt) 709 return; 710 } 711 712 /* For XDP, ignore pkts spanning multiple pages */ 713 if (nic->xdp_prog && (cqe_rx->rb_cnt == 1)) { 714 /* Packet consumed by XDP */ 715 if (nicvf_xdp_rx(snic, nic->xdp_prog, cqe_rx, sq, &skb)) 716 return; 717 } else { 718 skb = nicvf_get_rcv_skb(snic, cqe_rx, 719 nic->xdp_prog ? true : false); 720 } 721 722 if (!skb) 723 return; 724 725 if (netif_msg_pktdata(nic)) { 726 netdev_info(nic->netdev, "skb 0x%p, len=%d\n", skb, skb->len); 727 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 728 skb->data, skb->len, true); 729 } 730 731 /* If error packet, drop it here */ 732 if (err) { 733 dev_kfree_skb_any(skb); 734 return; 735 } 736 737 nicvf_set_rxhash(netdev, cqe_rx, skb); 738 739 skb_record_rx_queue(skb, rq_idx); 740 if (netdev->hw_features & NETIF_F_RXCSUM) { 741 /* HW by default verifies TCP/UDP/SCTP checksums */ 742 skb->ip_summed = CHECKSUM_UNNECESSARY; 743 } else { 744 skb_checksum_none_assert(skb); 745 } 746 747 skb->protocol = eth_type_trans(skb, netdev); 748 749 /* Check for stripped VLAN */ 750 if (cqe_rx->vlan_found && cqe_rx->vlan_stripped) 751 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 752 ntohs((__force __be16)cqe_rx->vlan_tci)); 753 754 if (napi && (netdev->features & NETIF_F_GRO)) 755 napi_gro_receive(napi, skb); 756 else 757 netif_receive_skb(skb); 758 } 759 760 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx, 761 struct napi_struct *napi, int budget) 762 { 763 int processed_cqe, work_done = 0, tx_done = 0; 764 int cqe_count, cqe_head; 765 int subdesc_cnt = 0; 766 struct nicvf *nic = netdev_priv(netdev); 767 struct queue_set *qs = nic->qs; 768 struct cmp_queue *cq = &qs->cq[cq_idx]; 769 struct cqe_rx_t *cq_desc; 770 struct netdev_queue *txq; 771 struct snd_queue *sq = &qs->sq[cq_idx]; 772 unsigned int tx_pkts = 0, tx_bytes = 0, txq_idx; 773 774 spin_lock_bh(&cq->lock); 775 loop: 776 processed_cqe = 0; 777 /* Get no of valid CQ entries to process */ 778 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx); 779 cqe_count &= CQ_CQE_COUNT; 780 if (!cqe_count) 781 goto done; 782 783 /* Get head of the valid CQ entries */ 784 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9; 785 cqe_head &= 0xFFFF; 786 787 while (processed_cqe < cqe_count) { 788 /* Get the CQ descriptor */ 789 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); 790 cqe_head++; 791 cqe_head &= (cq->dmem.q_len - 1); 792 /* Initiate prefetch for next descriptor */ 793 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head)); 794 795 if ((work_done >= budget) && napi && 796 (cq_desc->cqe_type != CQE_TYPE_SEND)) { 797 break; 798 } 799 800 switch (cq_desc->cqe_type) { 801 case CQE_TYPE_RX: 802 nicvf_rcv_pkt_handler(netdev, napi, cq_desc, sq); 803 work_done++; 804 break; 805 case CQE_TYPE_SEND: 806 nicvf_snd_pkt_handler(netdev, (void *)cq_desc, 807 budget, &subdesc_cnt, 808 &tx_pkts, &tx_bytes); 809 tx_done++; 810 break; 811 case CQE_TYPE_INVALID: 812 case CQE_TYPE_RX_SPLIT: 813 case CQE_TYPE_RX_TCP: 814 case CQE_TYPE_SEND_PTP: 815 /* Ignore for now */ 816 break; 817 } 818 processed_cqe++; 819 } 820 821 /* Ring doorbell to inform H/W to reuse processed CQEs */ 822 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, 823 cq_idx, processed_cqe); 824 825 if ((work_done < budget) && napi) 826 goto loop; 827 828 done: 829 /* Update SQ's descriptor free count */ 830 if (subdesc_cnt) 831 nicvf_put_sq_desc(sq, subdesc_cnt); 832 833 txq_idx = nicvf_netdev_qidx(nic, cq_idx); 834 /* Handle XDP TX queues */ 835 if (nic->pnicvf->xdp_prog) { 836 if (txq_idx < nic->pnicvf->xdp_tx_queues) { 837 nicvf_xdp_sq_doorbell(nic, sq, cq_idx); 838 goto out; 839 } 840 nic = nic->pnicvf; 841 txq_idx -= nic->pnicvf->xdp_tx_queues; 842 } 843 844 /* Wakeup TXQ if its stopped earlier due to SQ full */ 845 if (tx_done || 846 (atomic_read(&sq->free_cnt) >= MIN_SQ_DESC_PER_PKT_XMIT)) { 847 netdev = nic->pnicvf->netdev; 848 txq = netdev_get_tx_queue(netdev, txq_idx); 849 if (tx_pkts) 850 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 851 852 /* To read updated queue and carrier status */ 853 smp_mb(); 854 if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) { 855 netif_tx_wake_queue(txq); 856 nic = nic->pnicvf; 857 this_cpu_inc(nic->drv_stats->txq_wake); 858 netif_warn(nic, tx_err, netdev, 859 "Transmit queue wakeup SQ%d\n", txq_idx); 860 } 861 } 862 863 out: 864 spin_unlock_bh(&cq->lock); 865 return work_done; 866 } 867 868 static int nicvf_poll(struct napi_struct *napi, int budget) 869 { 870 u64 cq_head; 871 int work_done = 0; 872 struct net_device *netdev = napi->dev; 873 struct nicvf *nic = netdev_priv(netdev); 874 struct nicvf_cq_poll *cq; 875 876 cq = container_of(napi, struct nicvf_cq_poll, napi); 877 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget); 878 879 if (work_done < budget) { 880 /* Slow packet rate, exit polling */ 881 napi_complete_done(napi, work_done); 882 /* Re-enable interrupts */ 883 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, 884 cq->cq_idx); 885 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 886 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD, 887 cq->cq_idx, cq_head); 888 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 889 } 890 return work_done; 891 } 892 893 /* Qset error interrupt handler 894 * 895 * As of now only CQ errors are handled 896 */ 897 static void nicvf_handle_qs_err(unsigned long data) 898 { 899 struct nicvf *nic = (struct nicvf *)data; 900 struct queue_set *qs = nic->qs; 901 int qidx; 902 u64 status; 903 904 netif_tx_disable(nic->netdev); 905 906 /* Check if it is CQ err */ 907 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 908 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, 909 qidx); 910 if (!(status & CQ_ERR_MASK)) 911 continue; 912 /* Process already queued CQEs and reconfig CQ */ 913 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 914 nicvf_sq_disable(nic, qidx); 915 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0); 916 nicvf_cmp_queue_config(nic, qs, qidx, true); 917 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx); 918 nicvf_sq_enable(nic, &qs->sq[qidx], qidx); 919 920 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 921 } 922 923 netif_tx_start_all_queues(nic->netdev); 924 /* Re-enable Qset error interrupt */ 925 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 926 } 927 928 static void nicvf_dump_intr_status(struct nicvf *nic) 929 { 930 netif_info(nic, intr, nic->netdev, "interrupt status 0x%llx\n", 931 nicvf_reg_read(nic, NIC_VF_INT)); 932 } 933 934 static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq) 935 { 936 struct nicvf *nic = (struct nicvf *)nicvf_irq; 937 u64 intr; 938 939 nicvf_dump_intr_status(nic); 940 941 intr = nicvf_reg_read(nic, NIC_VF_INT); 942 /* Check for spurious interrupt */ 943 if (!(intr & NICVF_INTR_MBOX_MASK)) 944 return IRQ_HANDLED; 945 946 nicvf_handle_mbx_intr(nic); 947 948 return IRQ_HANDLED; 949 } 950 951 static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq) 952 { 953 struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq; 954 struct nicvf *nic = cq_poll->nicvf; 955 int qidx = cq_poll->cq_idx; 956 957 nicvf_dump_intr_status(nic); 958 959 /* Disable interrupts */ 960 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 961 962 /* Schedule NAPI */ 963 napi_schedule_irqoff(&cq_poll->napi); 964 965 /* Clear interrupt */ 966 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 967 968 return IRQ_HANDLED; 969 } 970 971 static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq) 972 { 973 struct nicvf *nic = (struct nicvf *)nicvf_irq; 974 u8 qidx; 975 976 977 nicvf_dump_intr_status(nic); 978 979 /* Disable RBDR interrupt and schedule softirq */ 980 for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) { 981 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx)) 982 continue; 983 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 984 tasklet_hi_schedule(&nic->rbdr_task); 985 /* Clear interrupt */ 986 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 987 } 988 989 return IRQ_HANDLED; 990 } 991 992 static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq) 993 { 994 struct nicvf *nic = (struct nicvf *)nicvf_irq; 995 996 nicvf_dump_intr_status(nic); 997 998 /* Disable Qset err interrupt and schedule softirq */ 999 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 1000 tasklet_hi_schedule(&nic->qs_err_task); 1001 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 1002 1003 return IRQ_HANDLED; 1004 } 1005 1006 static void nicvf_set_irq_affinity(struct nicvf *nic) 1007 { 1008 int vec, cpu; 1009 1010 for (vec = 0; vec < nic->num_vec; vec++) { 1011 if (!nic->irq_allocated[vec]) 1012 continue; 1013 1014 if (!zalloc_cpumask_var(&nic->affinity_mask[vec], GFP_KERNEL)) 1015 return; 1016 /* CQ interrupts */ 1017 if (vec < NICVF_INTR_ID_SQ) 1018 /* Leave CPU0 for RBDR and other interrupts */ 1019 cpu = nicvf_netdev_qidx(nic, vec) + 1; 1020 else 1021 cpu = 0; 1022 1023 cpumask_set_cpu(cpumask_local_spread(cpu, nic->node), 1024 nic->affinity_mask[vec]); 1025 irq_set_affinity_hint(pci_irq_vector(nic->pdev, vec), 1026 nic->affinity_mask[vec]); 1027 } 1028 } 1029 1030 static int nicvf_register_interrupts(struct nicvf *nic) 1031 { 1032 int irq, ret = 0; 1033 1034 for_each_cq_irq(irq) 1035 sprintf(nic->irq_name[irq], "%s-rxtx-%d", 1036 nic->pnicvf->netdev->name, 1037 nicvf_netdev_qidx(nic, irq)); 1038 1039 for_each_sq_irq(irq) 1040 sprintf(nic->irq_name[irq], "%s-sq-%d", 1041 nic->pnicvf->netdev->name, 1042 nicvf_netdev_qidx(nic, irq - NICVF_INTR_ID_SQ)); 1043 1044 for_each_rbdr_irq(irq) 1045 sprintf(nic->irq_name[irq], "%s-rbdr-%d", 1046 nic->pnicvf->netdev->name, 1047 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 1048 1049 /* Register CQ interrupts */ 1050 for (irq = 0; irq < nic->qs->cq_cnt; irq++) { 1051 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1052 nicvf_intr_handler, 1053 0, nic->irq_name[irq], nic->napi[irq]); 1054 if (ret) 1055 goto err; 1056 nic->irq_allocated[irq] = true; 1057 } 1058 1059 /* Register RBDR interrupt */ 1060 for (irq = NICVF_INTR_ID_RBDR; 1061 irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) { 1062 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1063 nicvf_rbdr_intr_handler, 1064 0, nic->irq_name[irq], nic); 1065 if (ret) 1066 goto err; 1067 nic->irq_allocated[irq] = true; 1068 } 1069 1070 /* Register QS error interrupt */ 1071 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR], "%s-qset-err-%d", 1072 nic->pnicvf->netdev->name, 1073 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 1074 irq = NICVF_INTR_ID_QS_ERR; 1075 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1076 nicvf_qs_err_intr_handler, 1077 0, nic->irq_name[irq], nic); 1078 if (ret) 1079 goto err; 1080 1081 nic->irq_allocated[irq] = true; 1082 1083 /* Set IRQ affinities */ 1084 nicvf_set_irq_affinity(nic); 1085 1086 err: 1087 if (ret) 1088 netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq); 1089 1090 return ret; 1091 } 1092 1093 static void nicvf_unregister_interrupts(struct nicvf *nic) 1094 { 1095 struct pci_dev *pdev = nic->pdev; 1096 int irq; 1097 1098 /* Free registered interrupts */ 1099 for (irq = 0; irq < nic->num_vec; irq++) { 1100 if (!nic->irq_allocated[irq]) 1101 continue; 1102 1103 irq_set_affinity_hint(pci_irq_vector(pdev, irq), NULL); 1104 free_cpumask_var(nic->affinity_mask[irq]); 1105 1106 if (irq < NICVF_INTR_ID_SQ) 1107 free_irq(pci_irq_vector(pdev, irq), nic->napi[irq]); 1108 else 1109 free_irq(pci_irq_vector(pdev, irq), nic); 1110 1111 nic->irq_allocated[irq] = false; 1112 } 1113 1114 /* Disable MSI-X */ 1115 pci_free_irq_vectors(pdev); 1116 nic->num_vec = 0; 1117 } 1118 1119 /* Initialize MSIX vectors and register MISC interrupt. 1120 * Send READY message to PF to check if its alive 1121 */ 1122 static int nicvf_register_misc_interrupt(struct nicvf *nic) 1123 { 1124 int ret = 0; 1125 int irq = NICVF_INTR_ID_MISC; 1126 1127 /* Return if mailbox interrupt is already registered */ 1128 if (nic->pdev->msix_enabled) 1129 return 0; 1130 1131 /* Enable MSI-X */ 1132 nic->num_vec = pci_msix_vec_count(nic->pdev); 1133 ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec, 1134 PCI_IRQ_MSIX); 1135 if (ret < 0) { 1136 netdev_err(nic->netdev, 1137 "Req for #%d msix vectors failed\n", nic->num_vec); 1138 return 1; 1139 } 1140 1141 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF"); 1142 /* Register Misc interrupt */ 1143 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1144 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic); 1145 1146 if (ret) 1147 return ret; 1148 nic->irq_allocated[irq] = true; 1149 1150 /* Enable mailbox interrupt */ 1151 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0); 1152 1153 /* Check if VF is able to communicate with PF */ 1154 if (!nicvf_check_pf_ready(nic)) { 1155 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1156 nicvf_unregister_interrupts(nic); 1157 return 1; 1158 } 1159 1160 return 0; 1161 } 1162 1163 static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev) 1164 { 1165 struct nicvf *nic = netdev_priv(netdev); 1166 int qid = skb_get_queue_mapping(skb); 1167 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid); 1168 struct nicvf *snic; 1169 struct snd_queue *sq; 1170 int tmp; 1171 1172 /* Check for minimum packet length */ 1173 if (skb->len <= ETH_HLEN) { 1174 dev_kfree_skb(skb); 1175 return NETDEV_TX_OK; 1176 } 1177 1178 /* In XDP case, initial HW tx queues are used for XDP, 1179 * but stack's queue mapping starts at '0', so skip the 1180 * Tx queues attached to Rx queues for XDP. 1181 */ 1182 if (nic->xdp_prog) 1183 qid += nic->xdp_tx_queues; 1184 1185 snic = nic; 1186 /* Get secondary Qset's SQ structure */ 1187 if (qid >= MAX_SND_QUEUES_PER_QS) { 1188 tmp = qid / MAX_SND_QUEUES_PER_QS; 1189 snic = (struct nicvf *)nic->snicvf[tmp - 1]; 1190 if (!snic) { 1191 netdev_warn(nic->netdev, 1192 "Secondary Qset#%d's ptr not initialized\n", 1193 tmp - 1); 1194 dev_kfree_skb(skb); 1195 return NETDEV_TX_OK; 1196 } 1197 qid = qid % MAX_SND_QUEUES_PER_QS; 1198 } 1199 1200 sq = &snic->qs->sq[qid]; 1201 if (!netif_tx_queue_stopped(txq) && 1202 !nicvf_sq_append_skb(snic, sq, skb, qid)) { 1203 netif_tx_stop_queue(txq); 1204 1205 /* Barrier, so that stop_queue visible to other cpus */ 1206 smp_mb(); 1207 1208 /* Check again, incase another cpu freed descriptors */ 1209 if (atomic_read(&sq->free_cnt) > MIN_SQ_DESC_PER_PKT_XMIT) { 1210 netif_tx_wake_queue(txq); 1211 } else { 1212 this_cpu_inc(nic->drv_stats->txq_stop); 1213 netif_warn(nic, tx_err, netdev, 1214 "Transmit ring full, stopping SQ%d\n", qid); 1215 } 1216 return NETDEV_TX_BUSY; 1217 } 1218 1219 return NETDEV_TX_OK; 1220 } 1221 1222 static inline void nicvf_free_cq_poll(struct nicvf *nic) 1223 { 1224 struct nicvf_cq_poll *cq_poll; 1225 int qidx; 1226 1227 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1228 cq_poll = nic->napi[qidx]; 1229 if (!cq_poll) 1230 continue; 1231 nic->napi[qidx] = NULL; 1232 kfree(cq_poll); 1233 } 1234 } 1235 1236 int nicvf_stop(struct net_device *netdev) 1237 { 1238 int irq, qidx; 1239 struct nicvf *nic = netdev_priv(netdev); 1240 struct queue_set *qs = nic->qs; 1241 struct nicvf_cq_poll *cq_poll = NULL; 1242 union nic_mbx mbx = {}; 1243 1244 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN; 1245 nicvf_send_msg_to_pf(nic, &mbx); 1246 1247 netif_carrier_off(netdev); 1248 netif_tx_stop_all_queues(nic->netdev); 1249 nic->link_up = false; 1250 1251 /* Teardown secondary qsets first */ 1252 if (!nic->sqs_mode) { 1253 for (qidx = 0; qidx < nic->sqs_count; qidx++) { 1254 if (!nic->snicvf[qidx]) 1255 continue; 1256 nicvf_stop(nic->snicvf[qidx]->netdev); 1257 nic->snicvf[qidx] = NULL; 1258 } 1259 } 1260 1261 /* Disable RBDR & QS error interrupts */ 1262 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1263 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 1264 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 1265 } 1266 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 1267 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 1268 1269 /* Wait for pending IRQ handlers to finish */ 1270 for (irq = 0; irq < nic->num_vec; irq++) 1271 synchronize_irq(pci_irq_vector(nic->pdev, irq)); 1272 1273 tasklet_kill(&nic->rbdr_task); 1274 tasklet_kill(&nic->qs_err_task); 1275 if (nic->rb_work_scheduled) 1276 cancel_delayed_work_sync(&nic->rbdr_work); 1277 1278 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1279 cq_poll = nic->napi[qidx]; 1280 if (!cq_poll) 1281 continue; 1282 napi_synchronize(&cq_poll->napi); 1283 /* CQ intr is enabled while napi_complete, 1284 * so disable it now 1285 */ 1286 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 1287 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 1288 napi_disable(&cq_poll->napi); 1289 netif_napi_del(&cq_poll->napi); 1290 } 1291 1292 netif_tx_disable(netdev); 1293 1294 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1295 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1296 1297 /* Free resources */ 1298 nicvf_config_data_transfer(nic, false); 1299 1300 /* Disable HW Qset */ 1301 nicvf_qset_config(nic, false); 1302 1303 /* disable mailbox interrupt */ 1304 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1305 1306 nicvf_unregister_interrupts(nic); 1307 1308 nicvf_free_cq_poll(nic); 1309 1310 /* Clear multiqset info */ 1311 nic->pnicvf = nic; 1312 1313 return 0; 1314 } 1315 1316 static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) 1317 { 1318 union nic_mbx mbx = {}; 1319 1320 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; 1321 mbx.frs.max_frs = mtu; 1322 mbx.frs.vf_id = nic->vf_id; 1323 1324 return nicvf_send_msg_to_pf(nic, &mbx); 1325 } 1326 1327 int nicvf_open(struct net_device *netdev) 1328 { 1329 int cpu, err, qidx; 1330 struct nicvf *nic = netdev_priv(netdev); 1331 struct queue_set *qs = nic->qs; 1332 struct nicvf_cq_poll *cq_poll = NULL; 1333 union nic_mbx mbx = {}; 1334 1335 netif_carrier_off(netdev); 1336 1337 err = nicvf_register_misc_interrupt(nic); 1338 if (err) 1339 return err; 1340 1341 /* Register NAPI handler for processing CQEs */ 1342 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1343 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL); 1344 if (!cq_poll) { 1345 err = -ENOMEM; 1346 goto napi_del; 1347 } 1348 cq_poll->cq_idx = qidx; 1349 cq_poll->nicvf = nic; 1350 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll, 1351 NAPI_POLL_WEIGHT); 1352 napi_enable(&cq_poll->napi); 1353 nic->napi[qidx] = cq_poll; 1354 } 1355 1356 /* Check if we got MAC address from PF or else generate a radom MAC */ 1357 if (!nic->sqs_mode && is_zero_ether_addr(netdev->dev_addr)) { 1358 eth_hw_addr_random(netdev); 1359 nicvf_hw_set_mac_addr(nic, netdev); 1360 } 1361 1362 if (nic->set_mac_pending) { 1363 nic->set_mac_pending = false; 1364 nicvf_hw_set_mac_addr(nic, netdev); 1365 } 1366 1367 /* Init tasklet for handling Qset err interrupt */ 1368 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err, 1369 (unsigned long)nic); 1370 1371 /* Init RBDR tasklet which will refill RBDR */ 1372 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task, 1373 (unsigned long)nic); 1374 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work); 1375 1376 /* Configure CPI alorithm */ 1377 nic->cpi_alg = cpi_alg; 1378 if (!nic->sqs_mode) 1379 nicvf_config_cpi(nic); 1380 1381 nicvf_request_sqs(nic); 1382 if (nic->sqs_mode) 1383 nicvf_get_primary_vf_struct(nic); 1384 1385 /* Configure receive side scaling and MTU */ 1386 if (!nic->sqs_mode) { 1387 nicvf_rss_init(nic); 1388 err = nicvf_update_hw_max_frs(nic, netdev->mtu); 1389 if (err) 1390 goto cleanup; 1391 1392 /* Clear percpu stats */ 1393 for_each_possible_cpu(cpu) 1394 memset(per_cpu_ptr(nic->drv_stats, cpu), 0, 1395 sizeof(struct nicvf_drv_stats)); 1396 } 1397 1398 err = nicvf_register_interrupts(nic); 1399 if (err) 1400 goto cleanup; 1401 1402 /* Initialize the queues */ 1403 err = nicvf_init_resources(nic); 1404 if (err) 1405 goto cleanup; 1406 1407 /* Make sure queue initialization is written */ 1408 wmb(); 1409 1410 nicvf_reg_write(nic, NIC_VF_INT, -1); 1411 /* Enable Qset err interrupt */ 1412 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 1413 1414 /* Enable completion queue interrupt */ 1415 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1416 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 1417 1418 /* Enable RBDR threshold interrupt */ 1419 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1420 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); 1421 1422 /* Send VF config done msg to PF */ 1423 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; 1424 nicvf_write_to_mbx(nic, &mbx); 1425 1426 return 0; 1427 cleanup: 1428 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1429 nicvf_unregister_interrupts(nic); 1430 tasklet_kill(&nic->qs_err_task); 1431 tasklet_kill(&nic->rbdr_task); 1432 napi_del: 1433 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1434 cq_poll = nic->napi[qidx]; 1435 if (!cq_poll) 1436 continue; 1437 napi_disable(&cq_poll->napi); 1438 netif_napi_del(&cq_poll->napi); 1439 } 1440 nicvf_free_cq_poll(nic); 1441 return err; 1442 } 1443 1444 static int nicvf_change_mtu(struct net_device *netdev, int new_mtu) 1445 { 1446 struct nicvf *nic = netdev_priv(netdev); 1447 int orig_mtu = netdev->mtu; 1448 1449 netdev->mtu = new_mtu; 1450 1451 if (!netif_running(netdev)) 1452 return 0; 1453 1454 if (nicvf_update_hw_max_frs(nic, new_mtu)) { 1455 netdev->mtu = orig_mtu; 1456 return -EINVAL; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int nicvf_set_mac_address(struct net_device *netdev, void *p) 1463 { 1464 struct sockaddr *addr = p; 1465 struct nicvf *nic = netdev_priv(netdev); 1466 1467 if (!is_valid_ether_addr(addr->sa_data)) 1468 return -EADDRNOTAVAIL; 1469 1470 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1471 1472 if (nic->pdev->msix_enabled) { 1473 if (nicvf_hw_set_mac_addr(nic, netdev)) 1474 return -EBUSY; 1475 } else { 1476 nic->set_mac_pending = true; 1477 } 1478 1479 return 0; 1480 } 1481 1482 void nicvf_update_lmac_stats(struct nicvf *nic) 1483 { 1484 int stat = 0; 1485 union nic_mbx mbx = {}; 1486 1487 if (!netif_running(nic->netdev)) 1488 return; 1489 1490 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 1491 mbx.bgx_stats.vf_id = nic->vf_id; 1492 /* Rx stats */ 1493 mbx.bgx_stats.rx = 1; 1494 while (stat < BGX_RX_STATS_COUNT) { 1495 mbx.bgx_stats.idx = stat; 1496 if (nicvf_send_msg_to_pf(nic, &mbx)) 1497 return; 1498 stat++; 1499 } 1500 1501 stat = 0; 1502 1503 /* Tx stats */ 1504 mbx.bgx_stats.rx = 0; 1505 while (stat < BGX_TX_STATS_COUNT) { 1506 mbx.bgx_stats.idx = stat; 1507 if (nicvf_send_msg_to_pf(nic, &mbx)) 1508 return; 1509 stat++; 1510 } 1511 } 1512 1513 void nicvf_update_stats(struct nicvf *nic) 1514 { 1515 int qidx, cpu; 1516 u64 tmp_stats = 0; 1517 struct nicvf_hw_stats *stats = &nic->hw_stats; 1518 struct nicvf_drv_stats *drv_stats; 1519 struct queue_set *qs = nic->qs; 1520 1521 #define GET_RX_STATS(reg) \ 1522 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3)) 1523 #define GET_TX_STATS(reg) \ 1524 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3)) 1525 1526 stats->rx_bytes = GET_RX_STATS(RX_OCTS); 1527 stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST); 1528 stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST); 1529 stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST); 1530 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS); 1531 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR); 1532 stats->rx_drop_red = GET_RX_STATS(RX_RED); 1533 stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS); 1534 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN); 1535 stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS); 1536 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST); 1537 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST); 1538 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); 1539 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); 1540 1541 stats->tx_bytes = GET_TX_STATS(TX_OCTS); 1542 stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST); 1543 stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST); 1544 stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST); 1545 stats->tx_drops = GET_TX_STATS(TX_DROP); 1546 1547 /* On T88 pass 2.0, the dummy SQE added for TSO notification 1548 * via CQE has 'dont_send' set. Hence HW drops the pkt pointed 1549 * pointed by dummy SQE and results in tx_drops counter being 1550 * incremented. Subtracting it from tx_tso counter will give 1551 * exact tx_drops counter. 1552 */ 1553 if (nic->t88 && nic->hw_tso) { 1554 for_each_possible_cpu(cpu) { 1555 drv_stats = per_cpu_ptr(nic->drv_stats, cpu); 1556 tmp_stats += drv_stats->tx_tso; 1557 } 1558 stats->tx_drops = tmp_stats - stats->tx_drops; 1559 } 1560 stats->tx_frames = stats->tx_ucast_frames + 1561 stats->tx_bcast_frames + 1562 stats->tx_mcast_frames; 1563 stats->rx_frames = stats->rx_ucast_frames + 1564 stats->rx_bcast_frames + 1565 stats->rx_mcast_frames; 1566 stats->rx_drops = stats->rx_drop_red + 1567 stats->rx_drop_overrun; 1568 1569 /* Update RQ and SQ stats */ 1570 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1571 nicvf_update_rq_stats(nic, qidx); 1572 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1573 nicvf_update_sq_stats(nic, qidx); 1574 } 1575 1576 static void nicvf_get_stats64(struct net_device *netdev, 1577 struct rtnl_link_stats64 *stats) 1578 { 1579 struct nicvf *nic = netdev_priv(netdev); 1580 struct nicvf_hw_stats *hw_stats = &nic->hw_stats; 1581 1582 nicvf_update_stats(nic); 1583 1584 stats->rx_bytes = hw_stats->rx_bytes; 1585 stats->rx_packets = hw_stats->rx_frames; 1586 stats->rx_dropped = hw_stats->rx_drops; 1587 stats->multicast = hw_stats->rx_mcast_frames; 1588 1589 stats->tx_bytes = hw_stats->tx_bytes; 1590 stats->tx_packets = hw_stats->tx_frames; 1591 stats->tx_dropped = hw_stats->tx_drops; 1592 1593 } 1594 1595 static void nicvf_tx_timeout(struct net_device *dev) 1596 { 1597 struct nicvf *nic = netdev_priv(dev); 1598 1599 netif_warn(nic, tx_err, dev, "Transmit timed out, resetting\n"); 1600 1601 this_cpu_inc(nic->drv_stats->tx_timeout); 1602 schedule_work(&nic->reset_task); 1603 } 1604 1605 static void nicvf_reset_task(struct work_struct *work) 1606 { 1607 struct nicvf *nic; 1608 1609 nic = container_of(work, struct nicvf, reset_task); 1610 1611 if (!netif_running(nic->netdev)) 1612 return; 1613 1614 nicvf_stop(nic->netdev); 1615 nicvf_open(nic->netdev); 1616 netif_trans_update(nic->netdev); 1617 } 1618 1619 static int nicvf_config_loopback(struct nicvf *nic, 1620 netdev_features_t features) 1621 { 1622 union nic_mbx mbx = {}; 1623 1624 mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK; 1625 mbx.lbk.vf_id = nic->vf_id; 1626 mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0; 1627 1628 return nicvf_send_msg_to_pf(nic, &mbx); 1629 } 1630 1631 static netdev_features_t nicvf_fix_features(struct net_device *netdev, 1632 netdev_features_t features) 1633 { 1634 struct nicvf *nic = netdev_priv(netdev); 1635 1636 if ((features & NETIF_F_LOOPBACK) && 1637 netif_running(netdev) && !nic->loopback_supported) 1638 features &= ~NETIF_F_LOOPBACK; 1639 1640 return features; 1641 } 1642 1643 static int nicvf_set_features(struct net_device *netdev, 1644 netdev_features_t features) 1645 { 1646 struct nicvf *nic = netdev_priv(netdev); 1647 netdev_features_t changed = features ^ netdev->features; 1648 1649 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 1650 nicvf_config_vlan_stripping(nic, features); 1651 1652 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1653 return nicvf_config_loopback(nic, features); 1654 1655 return 0; 1656 } 1657 1658 static void nicvf_set_xdp_queues(struct nicvf *nic, bool bpf_attached) 1659 { 1660 u8 cq_count, txq_count; 1661 1662 /* Set XDP Tx queue count same as Rx queue count */ 1663 if (!bpf_attached) 1664 nic->xdp_tx_queues = 0; 1665 else 1666 nic->xdp_tx_queues = nic->rx_queues; 1667 1668 /* If queue count > MAX_CMP_QUEUES_PER_QS, then additional qsets 1669 * needs to be allocated, check how many. 1670 */ 1671 txq_count = nic->xdp_tx_queues + nic->tx_queues; 1672 cq_count = max(nic->rx_queues, txq_count); 1673 if (cq_count > MAX_CMP_QUEUES_PER_QS) { 1674 nic->sqs_count = roundup(cq_count, MAX_CMP_QUEUES_PER_QS); 1675 nic->sqs_count = (nic->sqs_count / MAX_CMP_QUEUES_PER_QS) - 1; 1676 } else { 1677 nic->sqs_count = 0; 1678 } 1679 1680 /* Set primary Qset's resources */ 1681 nic->qs->rq_cnt = min_t(u8, nic->rx_queues, MAX_RCV_QUEUES_PER_QS); 1682 nic->qs->sq_cnt = min_t(u8, txq_count, MAX_SND_QUEUES_PER_QS); 1683 nic->qs->cq_cnt = max_t(u8, nic->qs->rq_cnt, nic->qs->sq_cnt); 1684 1685 /* Update stack */ 1686 nicvf_set_real_num_queues(nic->netdev, nic->tx_queues, nic->rx_queues); 1687 } 1688 1689 static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog) 1690 { 1691 struct net_device *dev = nic->netdev; 1692 bool if_up = netif_running(nic->netdev); 1693 struct bpf_prog *old_prog; 1694 bool bpf_attached = false; 1695 1696 /* For now just support only the usual MTU sized frames */ 1697 if (prog && (dev->mtu > 1500)) { 1698 netdev_warn(dev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 1699 dev->mtu); 1700 return -EOPNOTSUPP; 1701 } 1702 1703 /* ALL SQs attached to CQs i.e same as RQs, are treated as 1704 * XDP Tx queues and more Tx queues are allocated for 1705 * network stack to send pkts out. 1706 * 1707 * No of Tx queues are either same as Rx queues or whatever 1708 * is left in max no of queues possible. 1709 */ 1710 if ((nic->rx_queues + nic->tx_queues) > nic->max_queues) { 1711 netdev_warn(dev, 1712 "Failed to attach BPF prog, RXQs + TXQs > Max %d\n", 1713 nic->max_queues); 1714 return -ENOMEM; 1715 } 1716 1717 if (if_up) 1718 nicvf_stop(nic->netdev); 1719 1720 old_prog = xchg(&nic->xdp_prog, prog); 1721 /* Detach old prog, if any */ 1722 if (old_prog) 1723 bpf_prog_put(old_prog); 1724 1725 if (nic->xdp_prog) { 1726 /* Attach BPF program */ 1727 nic->xdp_prog = bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1); 1728 if (!IS_ERR(nic->xdp_prog)) 1729 bpf_attached = true; 1730 } 1731 1732 /* Calculate Tx queues needed for XDP and network stack */ 1733 nicvf_set_xdp_queues(nic, bpf_attached); 1734 1735 if (if_up) { 1736 /* Reinitialize interface, clean slate */ 1737 nicvf_open(nic->netdev); 1738 netif_trans_update(nic->netdev); 1739 } 1740 1741 return 0; 1742 } 1743 1744 static int nicvf_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 1745 { 1746 struct nicvf *nic = netdev_priv(netdev); 1747 1748 /* To avoid checks while retrieving buffer address from CQE_RX, 1749 * do not support XDP for T88 pass1.x silicons which are anyway 1750 * not in use widely. 1751 */ 1752 if (pass1_silicon(nic->pdev)) 1753 return -EOPNOTSUPP; 1754 1755 switch (xdp->command) { 1756 case XDP_SETUP_PROG: 1757 return nicvf_xdp_setup(nic, xdp->prog); 1758 case XDP_QUERY_PROG: 1759 xdp->prog_attached = !!nic->xdp_prog; 1760 xdp->prog_id = nic->xdp_prog ? nic->xdp_prog->aux->id : 0; 1761 return 0; 1762 default: 1763 return -EINVAL; 1764 } 1765 } 1766 1767 static const struct net_device_ops nicvf_netdev_ops = { 1768 .ndo_open = nicvf_open, 1769 .ndo_stop = nicvf_stop, 1770 .ndo_start_xmit = nicvf_xmit, 1771 .ndo_change_mtu = nicvf_change_mtu, 1772 .ndo_set_mac_address = nicvf_set_mac_address, 1773 .ndo_get_stats64 = nicvf_get_stats64, 1774 .ndo_tx_timeout = nicvf_tx_timeout, 1775 .ndo_fix_features = nicvf_fix_features, 1776 .ndo_set_features = nicvf_set_features, 1777 .ndo_bpf = nicvf_xdp, 1778 }; 1779 1780 static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1781 { 1782 struct device *dev = &pdev->dev; 1783 struct net_device *netdev; 1784 struct nicvf *nic; 1785 int err, qcount; 1786 u16 sdevid; 1787 1788 err = pci_enable_device(pdev); 1789 if (err) { 1790 dev_err(dev, "Failed to enable PCI device\n"); 1791 return err; 1792 } 1793 1794 err = pci_request_regions(pdev, DRV_NAME); 1795 if (err) { 1796 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1797 goto err_disable_device; 1798 } 1799 1800 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 1801 if (err) { 1802 dev_err(dev, "Unable to get usable DMA configuration\n"); 1803 goto err_release_regions; 1804 } 1805 1806 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 1807 if (err) { 1808 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n"); 1809 goto err_release_regions; 1810 } 1811 1812 qcount = netif_get_num_default_rss_queues(); 1813 1814 /* Restrict multiqset support only for host bound VFs */ 1815 if (pdev->is_virtfn) { 1816 /* Set max number of queues per VF */ 1817 qcount = min_t(int, num_online_cpus(), 1818 (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS); 1819 } 1820 1821 netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount); 1822 if (!netdev) { 1823 err = -ENOMEM; 1824 goto err_release_regions; 1825 } 1826 1827 pci_set_drvdata(pdev, netdev); 1828 1829 SET_NETDEV_DEV(netdev, &pdev->dev); 1830 1831 nic = netdev_priv(netdev); 1832 nic->netdev = netdev; 1833 nic->pdev = pdev; 1834 nic->pnicvf = nic; 1835 nic->max_queues = qcount; 1836 1837 /* MAP VF's configuration registers */ 1838 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1839 if (!nic->reg_base) { 1840 dev_err(dev, "Cannot map config register space, aborting\n"); 1841 err = -ENOMEM; 1842 goto err_free_netdev; 1843 } 1844 1845 nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats); 1846 if (!nic->drv_stats) { 1847 err = -ENOMEM; 1848 goto err_free_netdev; 1849 } 1850 1851 err = nicvf_set_qset_resources(nic); 1852 if (err) 1853 goto err_free_netdev; 1854 1855 /* Check if PF is alive and get MAC address for this VF */ 1856 err = nicvf_register_misc_interrupt(nic); 1857 if (err) 1858 goto err_free_netdev; 1859 1860 nicvf_send_vf_struct(nic); 1861 1862 if (!pass1_silicon(nic->pdev)) 1863 nic->hw_tso = true; 1864 1865 /* Get iommu domain for iova to physical addr conversion */ 1866 nic->iommu_domain = iommu_get_domain_for_dev(dev); 1867 1868 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 1869 if (sdevid == 0xA134) 1870 nic->t88 = true; 1871 1872 /* Check if this VF is in QS only mode */ 1873 if (nic->sqs_mode) 1874 return 0; 1875 1876 err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues); 1877 if (err) 1878 goto err_unregister_interrupts; 1879 1880 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_SG | 1881 NETIF_F_TSO | NETIF_F_GRO | NETIF_F_TSO6 | 1882 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1883 NETIF_F_HW_VLAN_CTAG_RX); 1884 1885 netdev->hw_features |= NETIF_F_RXHASH; 1886 1887 netdev->features |= netdev->hw_features; 1888 netdev->hw_features |= NETIF_F_LOOPBACK; 1889 1890 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | 1891 NETIF_F_IPV6_CSUM | NETIF_F_TSO | NETIF_F_TSO6; 1892 1893 netdev->netdev_ops = &nicvf_netdev_ops; 1894 netdev->watchdog_timeo = NICVF_TX_TIMEOUT; 1895 1896 /* MTU range: 64 - 9200 */ 1897 netdev->min_mtu = NIC_HW_MIN_FRS; 1898 netdev->max_mtu = NIC_HW_MAX_FRS; 1899 1900 INIT_WORK(&nic->reset_task, nicvf_reset_task); 1901 1902 err = register_netdev(netdev); 1903 if (err) { 1904 dev_err(dev, "Failed to register netdevice\n"); 1905 goto err_unregister_interrupts; 1906 } 1907 1908 nic->msg_enable = debug; 1909 1910 nicvf_set_ethtool_ops(netdev); 1911 1912 return 0; 1913 1914 err_unregister_interrupts: 1915 nicvf_unregister_interrupts(nic); 1916 err_free_netdev: 1917 pci_set_drvdata(pdev, NULL); 1918 if (nic->drv_stats) 1919 free_percpu(nic->drv_stats); 1920 free_netdev(netdev); 1921 err_release_regions: 1922 pci_release_regions(pdev); 1923 err_disable_device: 1924 pci_disable_device(pdev); 1925 return err; 1926 } 1927 1928 static void nicvf_remove(struct pci_dev *pdev) 1929 { 1930 struct net_device *netdev = pci_get_drvdata(pdev); 1931 struct nicvf *nic; 1932 struct net_device *pnetdev; 1933 1934 if (!netdev) 1935 return; 1936 1937 nic = netdev_priv(netdev); 1938 pnetdev = nic->pnicvf->netdev; 1939 1940 /* Check if this Qset is assigned to different VF. 1941 * If yes, clean primary and all secondary Qsets. 1942 */ 1943 if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED)) 1944 unregister_netdev(pnetdev); 1945 nicvf_unregister_interrupts(nic); 1946 pci_set_drvdata(pdev, NULL); 1947 if (nic->drv_stats) 1948 free_percpu(nic->drv_stats); 1949 free_netdev(netdev); 1950 pci_release_regions(pdev); 1951 pci_disable_device(pdev); 1952 } 1953 1954 static void nicvf_shutdown(struct pci_dev *pdev) 1955 { 1956 nicvf_remove(pdev); 1957 } 1958 1959 static struct pci_driver nicvf_driver = { 1960 .name = DRV_NAME, 1961 .id_table = nicvf_id_table, 1962 .probe = nicvf_probe, 1963 .remove = nicvf_remove, 1964 .shutdown = nicvf_shutdown, 1965 }; 1966 1967 static int __init nicvf_init_module(void) 1968 { 1969 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1970 1971 return pci_register_driver(&nicvf_driver); 1972 } 1973 1974 static void __exit nicvf_cleanup_module(void) 1975 { 1976 pci_unregister_driver(&nicvf_driver); 1977 } 1978 1979 module_init(nicvf_init_module); 1980 module_exit(nicvf_cleanup_module); 1981