1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/if_vlan.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/log2.h> 17 #include <linux/prefetch.h> 18 #include <linux/irq.h> 19 #include <linux/iommu.h> 20 #include <linux/bpf.h> 21 #include <linux/bpf_trace.h> 22 #include <linux/filter.h> 23 24 #include "nic_reg.h" 25 #include "nic.h" 26 #include "nicvf_queues.h" 27 #include "thunder_bgx.h" 28 29 #define DRV_NAME "thunder-nicvf" 30 #define DRV_VERSION "1.0" 31 32 /* Supported devices */ 33 static const struct pci_device_id nicvf_id_table[] = { 34 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 35 PCI_DEVICE_ID_THUNDER_NIC_VF, 36 PCI_VENDOR_ID_CAVIUM, 37 PCI_SUBSYS_DEVID_88XX_NIC_VF) }, 38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 39 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF, 40 PCI_VENDOR_ID_CAVIUM, 41 PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF) }, 42 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 43 PCI_DEVICE_ID_THUNDER_NIC_VF, 44 PCI_VENDOR_ID_CAVIUM, 45 PCI_SUBSYS_DEVID_81XX_NIC_VF) }, 46 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, 47 PCI_DEVICE_ID_THUNDER_NIC_VF, 48 PCI_VENDOR_ID_CAVIUM, 49 PCI_SUBSYS_DEVID_83XX_NIC_VF) }, 50 { 0, } /* end of table */ 51 }; 52 53 MODULE_AUTHOR("Sunil Goutham"); 54 MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver"); 55 MODULE_LICENSE("GPL v2"); 56 MODULE_VERSION(DRV_VERSION); 57 MODULE_DEVICE_TABLE(pci, nicvf_id_table); 58 59 static int debug = 0x00; 60 module_param(debug, int, 0644); 61 MODULE_PARM_DESC(debug, "Debug message level bitmap"); 62 63 static int cpi_alg = CPI_ALG_NONE; 64 module_param(cpi_alg, int, S_IRUGO); 65 MODULE_PARM_DESC(cpi_alg, 66 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)"); 67 68 static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx) 69 { 70 if (nic->sqs_mode) 71 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS); 72 else 73 return qidx; 74 } 75 76 /* The Cavium ThunderX network controller can *only* be found in SoCs 77 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 78 * registers on this platform are implicitly strongly ordered with respect 79 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 80 * with no memory barriers in this driver. The readq()/writeq() functions add 81 * explicit ordering operation which in this case are redundant, and only 82 * add overhead. 83 */ 84 85 /* Register read/write APIs */ 86 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val) 87 { 88 writeq_relaxed(val, nic->reg_base + offset); 89 } 90 91 u64 nicvf_reg_read(struct nicvf *nic, u64 offset) 92 { 93 return readq_relaxed(nic->reg_base + offset); 94 } 95 96 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset, 97 u64 qidx, u64 val) 98 { 99 void __iomem *addr = nic->reg_base + offset; 100 101 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT)); 102 } 103 104 u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx) 105 { 106 void __iomem *addr = nic->reg_base + offset; 107 108 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT)); 109 } 110 111 /* VF -> PF mailbox communication */ 112 static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx) 113 { 114 u64 *msg = (u64 *)mbx; 115 116 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]); 117 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]); 118 } 119 120 int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx) 121 { 122 int timeout = NIC_MBOX_MSG_TIMEOUT; 123 int sleep = 10; 124 125 nic->pf_acked = false; 126 nic->pf_nacked = false; 127 128 nicvf_write_to_mbx(nic, mbx); 129 130 /* Wait for previous message to be acked, timeout 2sec */ 131 while (!nic->pf_acked) { 132 if (nic->pf_nacked) { 133 netdev_err(nic->netdev, 134 "PF NACK to mbox msg 0x%02x from VF%d\n", 135 (mbx->msg.msg & 0xFF), nic->vf_id); 136 return -EINVAL; 137 } 138 msleep(sleep); 139 if (nic->pf_acked) 140 break; 141 timeout -= sleep; 142 if (!timeout) { 143 netdev_err(nic->netdev, 144 "PF didn't ACK to mbox msg 0x%02x from VF%d\n", 145 (mbx->msg.msg & 0xFF), nic->vf_id); 146 return -EBUSY; 147 } 148 } 149 return 0; 150 } 151 152 /* Checks if VF is able to comminicate with PF 153 * and also gets the VNIC number this VF is associated to. 154 */ 155 static int nicvf_check_pf_ready(struct nicvf *nic) 156 { 157 union nic_mbx mbx = {}; 158 159 mbx.msg.msg = NIC_MBOX_MSG_READY; 160 if (nicvf_send_msg_to_pf(nic, &mbx)) { 161 netdev_err(nic->netdev, 162 "PF didn't respond to READY msg\n"); 163 return 0; 164 } 165 166 return 1; 167 } 168 169 static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx) 170 { 171 if (bgx->rx) 172 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats; 173 else 174 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats; 175 } 176 177 static void nicvf_handle_mbx_intr(struct nicvf *nic) 178 { 179 union nic_mbx mbx = {}; 180 u64 *mbx_data; 181 u64 mbx_addr; 182 int i; 183 184 mbx_addr = NIC_VF_PF_MAILBOX_0_1; 185 mbx_data = (u64 *)&mbx; 186 187 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 188 *mbx_data = nicvf_reg_read(nic, mbx_addr); 189 mbx_data++; 190 mbx_addr += sizeof(u64); 191 } 192 193 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg); 194 switch (mbx.msg.msg) { 195 case NIC_MBOX_MSG_READY: 196 nic->pf_acked = true; 197 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F; 198 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F; 199 nic->node = mbx.nic_cfg.node_id; 200 if (!nic->set_mac_pending) 201 ether_addr_copy(nic->netdev->dev_addr, 202 mbx.nic_cfg.mac_addr); 203 nic->sqs_mode = mbx.nic_cfg.sqs_mode; 204 nic->loopback_supported = mbx.nic_cfg.loopback_supported; 205 nic->link_up = false; 206 nic->duplex = 0; 207 nic->speed = 0; 208 break; 209 case NIC_MBOX_MSG_ACK: 210 nic->pf_acked = true; 211 break; 212 case NIC_MBOX_MSG_NACK: 213 nic->pf_nacked = true; 214 break; 215 case NIC_MBOX_MSG_RSS_SIZE: 216 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size; 217 nic->pf_acked = true; 218 break; 219 case NIC_MBOX_MSG_BGX_STATS: 220 nicvf_read_bgx_stats(nic, &mbx.bgx_stats); 221 nic->pf_acked = true; 222 break; 223 case NIC_MBOX_MSG_BGX_LINK_CHANGE: 224 nic->pf_acked = true; 225 nic->link_up = mbx.link_status.link_up; 226 nic->duplex = mbx.link_status.duplex; 227 nic->speed = mbx.link_status.speed; 228 nic->mac_type = mbx.link_status.mac_type; 229 if (nic->link_up) { 230 netdev_info(nic->netdev, "Link is Up %d Mbps %s duplex\n", 231 nic->speed, 232 nic->duplex == DUPLEX_FULL ? 233 "Full" : "Half"); 234 netif_carrier_on(nic->netdev); 235 netif_tx_start_all_queues(nic->netdev); 236 } else { 237 netdev_info(nic->netdev, "Link is Down\n"); 238 netif_carrier_off(nic->netdev); 239 netif_tx_stop_all_queues(nic->netdev); 240 } 241 break; 242 case NIC_MBOX_MSG_ALLOC_SQS: 243 nic->sqs_count = mbx.sqs_alloc.qs_count; 244 nic->pf_acked = true; 245 break; 246 case NIC_MBOX_MSG_SNICVF_PTR: 247 /* Primary VF: make note of secondary VF's pointer 248 * to be used while packet transmission. 249 */ 250 nic->snicvf[mbx.nicvf.sqs_id] = 251 (struct nicvf *)mbx.nicvf.nicvf; 252 nic->pf_acked = true; 253 break; 254 case NIC_MBOX_MSG_PNICVF_PTR: 255 /* Secondary VF/Qset: make note of primary VF's pointer 256 * to be used while packet reception, to handover packet 257 * to primary VF's netdev. 258 */ 259 nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf; 260 nic->pf_acked = true; 261 break; 262 case NIC_MBOX_MSG_PFC: 263 nic->pfc.autoneg = mbx.pfc.autoneg; 264 nic->pfc.fc_rx = mbx.pfc.fc_rx; 265 nic->pfc.fc_tx = mbx.pfc.fc_tx; 266 nic->pf_acked = true; 267 break; 268 default: 269 netdev_err(nic->netdev, 270 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg); 271 break; 272 } 273 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0); 274 } 275 276 static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev) 277 { 278 union nic_mbx mbx = {}; 279 280 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC; 281 mbx.mac.vf_id = nic->vf_id; 282 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr); 283 284 return nicvf_send_msg_to_pf(nic, &mbx); 285 } 286 287 static void nicvf_config_cpi(struct nicvf *nic) 288 { 289 union nic_mbx mbx = {}; 290 291 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG; 292 mbx.cpi_cfg.vf_id = nic->vf_id; 293 mbx.cpi_cfg.cpi_alg = nic->cpi_alg; 294 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt; 295 296 nicvf_send_msg_to_pf(nic, &mbx); 297 } 298 299 static void nicvf_get_rss_size(struct nicvf *nic) 300 { 301 union nic_mbx mbx = {}; 302 303 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 304 mbx.rss_size.vf_id = nic->vf_id; 305 nicvf_send_msg_to_pf(nic, &mbx); 306 } 307 308 void nicvf_config_rss(struct nicvf *nic) 309 { 310 union nic_mbx mbx = {}; 311 struct nicvf_rss_info *rss = &nic->rss_info; 312 int ind_tbl_len = rss->rss_size; 313 int i, nextq = 0; 314 315 mbx.rss_cfg.vf_id = nic->vf_id; 316 mbx.rss_cfg.hash_bits = rss->hash_bits; 317 while (ind_tbl_len) { 318 mbx.rss_cfg.tbl_offset = nextq; 319 mbx.rss_cfg.tbl_len = min(ind_tbl_len, 320 RSS_IND_TBL_LEN_PER_MBX_MSG); 321 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ? 322 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG; 323 324 for (i = 0; i < mbx.rss_cfg.tbl_len; i++) 325 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++]; 326 327 nicvf_send_msg_to_pf(nic, &mbx); 328 329 ind_tbl_len -= mbx.rss_cfg.tbl_len; 330 } 331 } 332 333 void nicvf_set_rss_key(struct nicvf *nic) 334 { 335 struct nicvf_rss_info *rss = &nic->rss_info; 336 u64 key_addr = NIC_VNIC_RSS_KEY_0_4; 337 int idx; 338 339 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) { 340 nicvf_reg_write(nic, key_addr, rss->key[idx]); 341 key_addr += sizeof(u64); 342 } 343 } 344 345 static int nicvf_rss_init(struct nicvf *nic) 346 { 347 struct nicvf_rss_info *rss = &nic->rss_info; 348 int idx; 349 350 nicvf_get_rss_size(nic); 351 352 if (cpi_alg != CPI_ALG_NONE) { 353 rss->enable = false; 354 rss->hash_bits = 0; 355 return 0; 356 } 357 358 rss->enable = true; 359 360 netdev_rss_key_fill(rss->key, RSS_HASH_KEY_SIZE * sizeof(u64)); 361 nicvf_set_rss_key(nic); 362 363 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA; 364 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg); 365 366 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size)); 367 368 for (idx = 0; idx < rss->rss_size; idx++) 369 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx, 370 nic->rx_queues); 371 nicvf_config_rss(nic); 372 return 1; 373 } 374 375 /* Request PF to allocate additional Qsets */ 376 static void nicvf_request_sqs(struct nicvf *nic) 377 { 378 union nic_mbx mbx = {}; 379 int sqs; 380 int sqs_count = nic->sqs_count; 381 int rx_queues = 0, tx_queues = 0; 382 383 /* Only primary VF should request */ 384 if (nic->sqs_mode || !nic->sqs_count) 385 return; 386 387 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 388 mbx.sqs_alloc.vf_id = nic->vf_id; 389 mbx.sqs_alloc.qs_count = nic->sqs_count; 390 if (nicvf_send_msg_to_pf(nic, &mbx)) { 391 /* No response from PF */ 392 nic->sqs_count = 0; 393 return; 394 } 395 396 /* Return if no Secondary Qsets available */ 397 if (!nic->sqs_count) 398 return; 399 400 if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS) 401 rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS; 402 403 tx_queues = nic->tx_queues + nic->xdp_tx_queues; 404 if (tx_queues > MAX_SND_QUEUES_PER_QS) 405 tx_queues = tx_queues - MAX_SND_QUEUES_PER_QS; 406 407 /* Set no of Rx/Tx queues in each of the SQsets */ 408 for (sqs = 0; sqs < nic->sqs_count; sqs++) { 409 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 410 mbx.nicvf.vf_id = nic->vf_id; 411 mbx.nicvf.sqs_id = sqs; 412 nicvf_send_msg_to_pf(nic, &mbx); 413 414 nic->snicvf[sqs]->sqs_id = sqs; 415 if (rx_queues > MAX_RCV_QUEUES_PER_QS) { 416 nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS; 417 rx_queues -= MAX_RCV_QUEUES_PER_QS; 418 } else { 419 nic->snicvf[sqs]->qs->rq_cnt = rx_queues; 420 rx_queues = 0; 421 } 422 423 if (tx_queues > MAX_SND_QUEUES_PER_QS) { 424 nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS; 425 tx_queues -= MAX_SND_QUEUES_PER_QS; 426 } else { 427 nic->snicvf[sqs]->qs->sq_cnt = tx_queues; 428 tx_queues = 0; 429 } 430 431 nic->snicvf[sqs]->qs->cq_cnt = 432 max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt); 433 434 /* Initialize secondary Qset's queues and its interrupts */ 435 nicvf_open(nic->snicvf[sqs]->netdev); 436 } 437 438 /* Update stack with actual Rx/Tx queue count allocated */ 439 if (sqs_count != nic->sqs_count) 440 nicvf_set_real_num_queues(nic->netdev, 441 nic->tx_queues, nic->rx_queues); 442 } 443 444 /* Send this Qset's nicvf pointer to PF. 445 * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs 446 * so that packets received by these Qsets can use primary VF's netdev 447 */ 448 static void nicvf_send_vf_struct(struct nicvf *nic) 449 { 450 union nic_mbx mbx = {}; 451 452 mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR; 453 mbx.nicvf.sqs_mode = nic->sqs_mode; 454 mbx.nicvf.nicvf = (u64)nic; 455 nicvf_send_msg_to_pf(nic, &mbx); 456 } 457 458 static void nicvf_get_primary_vf_struct(struct nicvf *nic) 459 { 460 union nic_mbx mbx = {}; 461 462 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 463 nicvf_send_msg_to_pf(nic, &mbx); 464 } 465 466 int nicvf_set_real_num_queues(struct net_device *netdev, 467 int tx_queues, int rx_queues) 468 { 469 int err = 0; 470 471 err = netif_set_real_num_tx_queues(netdev, tx_queues); 472 if (err) { 473 netdev_err(netdev, 474 "Failed to set no of Tx queues: %d\n", tx_queues); 475 return err; 476 } 477 478 err = netif_set_real_num_rx_queues(netdev, rx_queues); 479 if (err) 480 netdev_err(netdev, 481 "Failed to set no of Rx queues: %d\n", rx_queues); 482 return err; 483 } 484 485 static int nicvf_init_resources(struct nicvf *nic) 486 { 487 int err; 488 489 /* Enable Qset */ 490 nicvf_qset_config(nic, true); 491 492 /* Initialize queues and HW for data transfer */ 493 err = nicvf_config_data_transfer(nic, true); 494 if (err) { 495 netdev_err(nic->netdev, 496 "Failed to alloc/config VF's QSet resources\n"); 497 return err; 498 } 499 500 return 0; 501 } 502 503 static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog, 504 struct cqe_rx_t *cqe_rx, struct snd_queue *sq, 505 struct sk_buff **skb) 506 { 507 struct xdp_buff xdp; 508 struct page *page; 509 u32 action; 510 u16 len, offset = 0; 511 u64 dma_addr, cpu_addr; 512 void *orig_data; 513 514 /* Retrieve packet buffer's DMA address and length */ 515 len = *((u16 *)((void *)cqe_rx + (3 * sizeof(u64)))); 516 dma_addr = *((u64 *)((void *)cqe_rx + (7 * sizeof(u64)))); 517 518 cpu_addr = nicvf_iova_to_phys(nic, dma_addr); 519 if (!cpu_addr) 520 return false; 521 cpu_addr = (u64)phys_to_virt(cpu_addr); 522 page = virt_to_page((void *)cpu_addr); 523 524 xdp.data_hard_start = page_address(page); 525 xdp.data = (void *)cpu_addr; 526 xdp_set_data_meta_invalid(&xdp); 527 xdp.data_end = xdp.data + len; 528 orig_data = xdp.data; 529 530 rcu_read_lock(); 531 action = bpf_prog_run_xdp(prog, &xdp); 532 rcu_read_unlock(); 533 534 /* Check if XDP program has changed headers */ 535 if (orig_data != xdp.data) { 536 len = xdp.data_end - xdp.data; 537 offset = orig_data - xdp.data; 538 dma_addr -= offset; 539 } 540 541 switch (action) { 542 case XDP_PASS: 543 /* Check if it's a recycled page, if not 544 * unmap the DMA mapping. 545 * 546 * Recycled page holds an extra reference. 547 */ 548 if (page_ref_count(page) == 1) { 549 dma_addr &= PAGE_MASK; 550 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, 551 RCV_FRAG_LEN + XDP_PACKET_HEADROOM, 552 DMA_FROM_DEVICE, 553 DMA_ATTR_SKIP_CPU_SYNC); 554 } 555 556 /* Build SKB and pass on packet to network stack */ 557 *skb = build_skb(xdp.data, 558 RCV_FRAG_LEN - cqe_rx->align_pad + offset); 559 if (!*skb) 560 put_page(page); 561 else 562 skb_put(*skb, len); 563 return false; 564 case XDP_TX: 565 nicvf_xdp_sq_append_pkt(nic, sq, (u64)xdp.data, dma_addr, len); 566 return true; 567 default: 568 bpf_warn_invalid_xdp_action(action); 569 case XDP_ABORTED: 570 trace_xdp_exception(nic->netdev, prog, action); 571 case XDP_DROP: 572 /* Check if it's a recycled page, if not 573 * unmap the DMA mapping. 574 * 575 * Recycled page holds an extra reference. 576 */ 577 if (page_ref_count(page) == 1) { 578 dma_addr &= PAGE_MASK; 579 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, 580 RCV_FRAG_LEN + XDP_PACKET_HEADROOM, 581 DMA_FROM_DEVICE, 582 DMA_ATTR_SKIP_CPU_SYNC); 583 } 584 put_page(page); 585 return true; 586 } 587 return false; 588 } 589 590 static void nicvf_snd_pkt_handler(struct net_device *netdev, 591 struct cqe_send_t *cqe_tx, 592 int budget, int *subdesc_cnt, 593 unsigned int *tx_pkts, unsigned int *tx_bytes) 594 { 595 struct sk_buff *skb = NULL; 596 struct page *page; 597 struct nicvf *nic = netdev_priv(netdev); 598 struct snd_queue *sq; 599 struct sq_hdr_subdesc *hdr; 600 struct sq_hdr_subdesc *tso_sqe; 601 602 sq = &nic->qs->sq[cqe_tx->sq_idx]; 603 604 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr); 605 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) 606 return; 607 608 /* Check for errors */ 609 if (cqe_tx->send_status) 610 nicvf_check_cqe_tx_errs(nic->pnicvf, cqe_tx); 611 612 /* Is this a XDP designated Tx queue */ 613 if (sq->is_xdp) { 614 page = (struct page *)sq->xdp_page[cqe_tx->sqe_ptr]; 615 /* Check if it's recycled page or else unmap DMA mapping */ 616 if (page && (page_ref_count(page) == 1)) 617 nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr, 618 hdr->subdesc_cnt); 619 620 /* Release page reference for recycling */ 621 if (page) 622 put_page(page); 623 sq->xdp_page[cqe_tx->sqe_ptr] = (u64)NULL; 624 *subdesc_cnt += hdr->subdesc_cnt + 1; 625 return; 626 } 627 628 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr]; 629 if (skb) { 630 /* Check for dummy descriptor used for HW TSO offload on 88xx */ 631 if (hdr->dont_send) { 632 /* Get actual TSO descriptors and free them */ 633 tso_sqe = 634 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2); 635 nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2, 636 tso_sqe->subdesc_cnt); 637 *subdesc_cnt += tso_sqe->subdesc_cnt + 1; 638 } else { 639 nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr, 640 hdr->subdesc_cnt); 641 } 642 *subdesc_cnt += hdr->subdesc_cnt + 1; 643 prefetch(skb); 644 (*tx_pkts)++; 645 *tx_bytes += skb->len; 646 napi_consume_skb(skb, budget); 647 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL; 648 } else { 649 /* In case of SW TSO on 88xx, only last segment will have 650 * a SKB attached, so just free SQEs here. 651 */ 652 if (!nic->hw_tso) 653 *subdesc_cnt += hdr->subdesc_cnt + 1; 654 } 655 } 656 657 static inline void nicvf_set_rxhash(struct net_device *netdev, 658 struct cqe_rx_t *cqe_rx, 659 struct sk_buff *skb) 660 { 661 u8 hash_type; 662 u32 hash; 663 664 if (!(netdev->features & NETIF_F_RXHASH)) 665 return; 666 667 switch (cqe_rx->rss_alg) { 668 case RSS_ALG_TCP_IP: 669 case RSS_ALG_UDP_IP: 670 hash_type = PKT_HASH_TYPE_L4; 671 hash = cqe_rx->rss_tag; 672 break; 673 case RSS_ALG_IP: 674 hash_type = PKT_HASH_TYPE_L3; 675 hash = cqe_rx->rss_tag; 676 break; 677 default: 678 hash_type = PKT_HASH_TYPE_NONE; 679 hash = 0; 680 } 681 682 skb_set_hash(skb, hash, hash_type); 683 } 684 685 static void nicvf_rcv_pkt_handler(struct net_device *netdev, 686 struct napi_struct *napi, 687 struct cqe_rx_t *cqe_rx, struct snd_queue *sq) 688 { 689 struct sk_buff *skb = NULL; 690 struct nicvf *nic = netdev_priv(netdev); 691 struct nicvf *snic = nic; 692 int err = 0; 693 int rq_idx; 694 695 rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx); 696 697 if (nic->sqs_mode) { 698 /* Use primary VF's 'nicvf' struct */ 699 nic = nic->pnicvf; 700 netdev = nic->netdev; 701 } 702 703 /* Check for errors */ 704 if (cqe_rx->err_level || cqe_rx->err_opcode) { 705 err = nicvf_check_cqe_rx_errs(nic, cqe_rx); 706 if (err && !cqe_rx->rb_cnt) 707 return; 708 } 709 710 /* For XDP, ignore pkts spanning multiple pages */ 711 if (nic->xdp_prog && (cqe_rx->rb_cnt == 1)) { 712 /* Packet consumed by XDP */ 713 if (nicvf_xdp_rx(snic, nic->xdp_prog, cqe_rx, sq, &skb)) 714 return; 715 } else { 716 skb = nicvf_get_rcv_skb(snic, cqe_rx, 717 nic->xdp_prog ? true : false); 718 } 719 720 if (!skb) 721 return; 722 723 if (netif_msg_pktdata(nic)) { 724 netdev_info(nic->netdev, "skb 0x%p, len=%d\n", skb, skb->len); 725 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 726 skb->data, skb->len, true); 727 } 728 729 /* If error packet, drop it here */ 730 if (err) { 731 dev_kfree_skb_any(skb); 732 return; 733 } 734 735 nicvf_set_rxhash(netdev, cqe_rx, skb); 736 737 skb_record_rx_queue(skb, rq_idx); 738 if (netdev->hw_features & NETIF_F_RXCSUM) { 739 /* HW by default verifies TCP/UDP/SCTP checksums */ 740 skb->ip_summed = CHECKSUM_UNNECESSARY; 741 } else { 742 skb_checksum_none_assert(skb); 743 } 744 745 skb->protocol = eth_type_trans(skb, netdev); 746 747 /* Check for stripped VLAN */ 748 if (cqe_rx->vlan_found && cqe_rx->vlan_stripped) 749 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 750 ntohs((__force __be16)cqe_rx->vlan_tci)); 751 752 if (napi && (netdev->features & NETIF_F_GRO)) 753 napi_gro_receive(napi, skb); 754 else 755 netif_receive_skb(skb); 756 } 757 758 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx, 759 struct napi_struct *napi, int budget) 760 { 761 int processed_cqe, work_done = 0, tx_done = 0; 762 int cqe_count, cqe_head; 763 int subdesc_cnt = 0; 764 struct nicvf *nic = netdev_priv(netdev); 765 struct queue_set *qs = nic->qs; 766 struct cmp_queue *cq = &qs->cq[cq_idx]; 767 struct cqe_rx_t *cq_desc; 768 struct netdev_queue *txq; 769 struct snd_queue *sq = &qs->sq[cq_idx]; 770 unsigned int tx_pkts = 0, tx_bytes = 0, txq_idx; 771 772 spin_lock_bh(&cq->lock); 773 loop: 774 processed_cqe = 0; 775 /* Get no of valid CQ entries to process */ 776 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx); 777 cqe_count &= CQ_CQE_COUNT; 778 if (!cqe_count) 779 goto done; 780 781 /* Get head of the valid CQ entries */ 782 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9; 783 cqe_head &= 0xFFFF; 784 785 while (processed_cqe < cqe_count) { 786 /* Get the CQ descriptor */ 787 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); 788 cqe_head++; 789 cqe_head &= (cq->dmem.q_len - 1); 790 /* Initiate prefetch for next descriptor */ 791 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head)); 792 793 if ((work_done >= budget) && napi && 794 (cq_desc->cqe_type != CQE_TYPE_SEND)) { 795 break; 796 } 797 798 switch (cq_desc->cqe_type) { 799 case CQE_TYPE_RX: 800 nicvf_rcv_pkt_handler(netdev, napi, cq_desc, sq); 801 work_done++; 802 break; 803 case CQE_TYPE_SEND: 804 nicvf_snd_pkt_handler(netdev, (void *)cq_desc, 805 budget, &subdesc_cnt, 806 &tx_pkts, &tx_bytes); 807 tx_done++; 808 break; 809 case CQE_TYPE_INVALID: 810 case CQE_TYPE_RX_SPLIT: 811 case CQE_TYPE_RX_TCP: 812 case CQE_TYPE_SEND_PTP: 813 /* Ignore for now */ 814 break; 815 } 816 processed_cqe++; 817 } 818 819 /* Ring doorbell to inform H/W to reuse processed CQEs */ 820 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, 821 cq_idx, processed_cqe); 822 823 if ((work_done < budget) && napi) 824 goto loop; 825 826 done: 827 /* Update SQ's descriptor free count */ 828 if (subdesc_cnt) 829 nicvf_put_sq_desc(sq, subdesc_cnt); 830 831 txq_idx = nicvf_netdev_qidx(nic, cq_idx); 832 /* Handle XDP TX queues */ 833 if (nic->pnicvf->xdp_prog) { 834 if (txq_idx < nic->pnicvf->xdp_tx_queues) { 835 nicvf_xdp_sq_doorbell(nic, sq, cq_idx); 836 goto out; 837 } 838 nic = nic->pnicvf; 839 txq_idx -= nic->pnicvf->xdp_tx_queues; 840 } 841 842 /* Wakeup TXQ if its stopped earlier due to SQ full */ 843 if (tx_done || 844 (atomic_read(&sq->free_cnt) >= MIN_SQ_DESC_PER_PKT_XMIT)) { 845 netdev = nic->pnicvf->netdev; 846 txq = netdev_get_tx_queue(netdev, txq_idx); 847 if (tx_pkts) 848 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 849 850 /* To read updated queue and carrier status */ 851 smp_mb(); 852 if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) { 853 netif_tx_wake_queue(txq); 854 nic = nic->pnicvf; 855 this_cpu_inc(nic->drv_stats->txq_wake); 856 netif_warn(nic, tx_err, netdev, 857 "Transmit queue wakeup SQ%d\n", txq_idx); 858 } 859 } 860 861 out: 862 spin_unlock_bh(&cq->lock); 863 return work_done; 864 } 865 866 static int nicvf_poll(struct napi_struct *napi, int budget) 867 { 868 u64 cq_head; 869 int work_done = 0; 870 struct net_device *netdev = napi->dev; 871 struct nicvf *nic = netdev_priv(netdev); 872 struct nicvf_cq_poll *cq; 873 874 cq = container_of(napi, struct nicvf_cq_poll, napi); 875 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget); 876 877 if (work_done < budget) { 878 /* Slow packet rate, exit polling */ 879 napi_complete_done(napi, work_done); 880 /* Re-enable interrupts */ 881 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, 882 cq->cq_idx); 883 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 884 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD, 885 cq->cq_idx, cq_head); 886 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx); 887 } 888 return work_done; 889 } 890 891 /* Qset error interrupt handler 892 * 893 * As of now only CQ errors are handled 894 */ 895 static void nicvf_handle_qs_err(unsigned long data) 896 { 897 struct nicvf *nic = (struct nicvf *)data; 898 struct queue_set *qs = nic->qs; 899 int qidx; 900 u64 status; 901 902 netif_tx_disable(nic->netdev); 903 904 /* Check if it is CQ err */ 905 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 906 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, 907 qidx); 908 if (!(status & CQ_ERR_MASK)) 909 continue; 910 /* Process already queued CQEs and reconfig CQ */ 911 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 912 nicvf_sq_disable(nic, qidx); 913 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0); 914 nicvf_cmp_queue_config(nic, qs, qidx, true); 915 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx); 916 nicvf_sq_enable(nic, &qs->sq[qidx], qidx); 917 918 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 919 } 920 921 netif_tx_start_all_queues(nic->netdev); 922 /* Re-enable Qset error interrupt */ 923 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 924 } 925 926 static void nicvf_dump_intr_status(struct nicvf *nic) 927 { 928 netif_info(nic, intr, nic->netdev, "interrupt status 0x%llx\n", 929 nicvf_reg_read(nic, NIC_VF_INT)); 930 } 931 932 static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq) 933 { 934 struct nicvf *nic = (struct nicvf *)nicvf_irq; 935 u64 intr; 936 937 nicvf_dump_intr_status(nic); 938 939 intr = nicvf_reg_read(nic, NIC_VF_INT); 940 /* Check for spurious interrupt */ 941 if (!(intr & NICVF_INTR_MBOX_MASK)) 942 return IRQ_HANDLED; 943 944 nicvf_handle_mbx_intr(nic); 945 946 return IRQ_HANDLED; 947 } 948 949 static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq) 950 { 951 struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq; 952 struct nicvf *nic = cq_poll->nicvf; 953 int qidx = cq_poll->cq_idx; 954 955 nicvf_dump_intr_status(nic); 956 957 /* Disable interrupts */ 958 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 959 960 /* Schedule NAPI */ 961 napi_schedule_irqoff(&cq_poll->napi); 962 963 /* Clear interrupt */ 964 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 965 966 return IRQ_HANDLED; 967 } 968 969 static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq) 970 { 971 struct nicvf *nic = (struct nicvf *)nicvf_irq; 972 u8 qidx; 973 974 975 nicvf_dump_intr_status(nic); 976 977 /* Disable RBDR interrupt and schedule softirq */ 978 for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) { 979 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx)) 980 continue; 981 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 982 tasklet_hi_schedule(&nic->rbdr_task); 983 /* Clear interrupt */ 984 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 985 } 986 987 return IRQ_HANDLED; 988 } 989 990 static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq) 991 { 992 struct nicvf *nic = (struct nicvf *)nicvf_irq; 993 994 nicvf_dump_intr_status(nic); 995 996 /* Disable Qset err interrupt and schedule softirq */ 997 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 998 tasklet_hi_schedule(&nic->qs_err_task); 999 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 1000 1001 return IRQ_HANDLED; 1002 } 1003 1004 static void nicvf_set_irq_affinity(struct nicvf *nic) 1005 { 1006 int vec, cpu; 1007 1008 for (vec = 0; vec < nic->num_vec; vec++) { 1009 if (!nic->irq_allocated[vec]) 1010 continue; 1011 1012 if (!zalloc_cpumask_var(&nic->affinity_mask[vec], GFP_KERNEL)) 1013 return; 1014 /* CQ interrupts */ 1015 if (vec < NICVF_INTR_ID_SQ) 1016 /* Leave CPU0 for RBDR and other interrupts */ 1017 cpu = nicvf_netdev_qidx(nic, vec) + 1; 1018 else 1019 cpu = 0; 1020 1021 cpumask_set_cpu(cpumask_local_spread(cpu, nic->node), 1022 nic->affinity_mask[vec]); 1023 irq_set_affinity_hint(pci_irq_vector(nic->pdev, vec), 1024 nic->affinity_mask[vec]); 1025 } 1026 } 1027 1028 static int nicvf_register_interrupts(struct nicvf *nic) 1029 { 1030 int irq, ret = 0; 1031 1032 for_each_cq_irq(irq) 1033 sprintf(nic->irq_name[irq], "%s-rxtx-%d", 1034 nic->pnicvf->netdev->name, 1035 nicvf_netdev_qidx(nic, irq)); 1036 1037 for_each_sq_irq(irq) 1038 sprintf(nic->irq_name[irq], "%s-sq-%d", 1039 nic->pnicvf->netdev->name, 1040 nicvf_netdev_qidx(nic, irq - NICVF_INTR_ID_SQ)); 1041 1042 for_each_rbdr_irq(irq) 1043 sprintf(nic->irq_name[irq], "%s-rbdr-%d", 1044 nic->pnicvf->netdev->name, 1045 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 1046 1047 /* Register CQ interrupts */ 1048 for (irq = 0; irq < nic->qs->cq_cnt; irq++) { 1049 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1050 nicvf_intr_handler, 1051 0, nic->irq_name[irq], nic->napi[irq]); 1052 if (ret) 1053 goto err; 1054 nic->irq_allocated[irq] = true; 1055 } 1056 1057 /* Register RBDR interrupt */ 1058 for (irq = NICVF_INTR_ID_RBDR; 1059 irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) { 1060 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1061 nicvf_rbdr_intr_handler, 1062 0, nic->irq_name[irq], nic); 1063 if (ret) 1064 goto err; 1065 nic->irq_allocated[irq] = true; 1066 } 1067 1068 /* Register QS error interrupt */ 1069 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR], "%s-qset-err-%d", 1070 nic->pnicvf->netdev->name, 1071 nic->sqs_mode ? (nic->sqs_id + 1) : 0); 1072 irq = NICVF_INTR_ID_QS_ERR; 1073 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1074 nicvf_qs_err_intr_handler, 1075 0, nic->irq_name[irq], nic); 1076 if (ret) 1077 goto err; 1078 1079 nic->irq_allocated[irq] = true; 1080 1081 /* Set IRQ affinities */ 1082 nicvf_set_irq_affinity(nic); 1083 1084 err: 1085 if (ret) 1086 netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq); 1087 1088 return ret; 1089 } 1090 1091 static void nicvf_unregister_interrupts(struct nicvf *nic) 1092 { 1093 struct pci_dev *pdev = nic->pdev; 1094 int irq; 1095 1096 /* Free registered interrupts */ 1097 for (irq = 0; irq < nic->num_vec; irq++) { 1098 if (!nic->irq_allocated[irq]) 1099 continue; 1100 1101 irq_set_affinity_hint(pci_irq_vector(pdev, irq), NULL); 1102 free_cpumask_var(nic->affinity_mask[irq]); 1103 1104 if (irq < NICVF_INTR_ID_SQ) 1105 free_irq(pci_irq_vector(pdev, irq), nic->napi[irq]); 1106 else 1107 free_irq(pci_irq_vector(pdev, irq), nic); 1108 1109 nic->irq_allocated[irq] = false; 1110 } 1111 1112 /* Disable MSI-X */ 1113 pci_free_irq_vectors(pdev); 1114 nic->num_vec = 0; 1115 } 1116 1117 /* Initialize MSIX vectors and register MISC interrupt. 1118 * Send READY message to PF to check if its alive 1119 */ 1120 static int nicvf_register_misc_interrupt(struct nicvf *nic) 1121 { 1122 int ret = 0; 1123 int irq = NICVF_INTR_ID_MISC; 1124 1125 /* Return if mailbox interrupt is already registered */ 1126 if (nic->pdev->msix_enabled) 1127 return 0; 1128 1129 /* Enable MSI-X */ 1130 nic->num_vec = pci_msix_vec_count(nic->pdev); 1131 ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec, 1132 PCI_IRQ_MSIX); 1133 if (ret < 0) { 1134 netdev_err(nic->netdev, 1135 "Req for #%d msix vectors failed\n", nic->num_vec); 1136 return 1; 1137 } 1138 1139 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF"); 1140 /* Register Misc interrupt */ 1141 ret = request_irq(pci_irq_vector(nic->pdev, irq), 1142 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic); 1143 1144 if (ret) 1145 return ret; 1146 nic->irq_allocated[irq] = true; 1147 1148 /* Enable mailbox interrupt */ 1149 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0); 1150 1151 /* Check if VF is able to communicate with PF */ 1152 if (!nicvf_check_pf_ready(nic)) { 1153 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1154 nicvf_unregister_interrupts(nic); 1155 return 1; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev) 1162 { 1163 struct nicvf *nic = netdev_priv(netdev); 1164 int qid = skb_get_queue_mapping(skb); 1165 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid); 1166 struct nicvf *snic; 1167 struct snd_queue *sq; 1168 int tmp; 1169 1170 /* Check for minimum packet length */ 1171 if (skb->len <= ETH_HLEN) { 1172 dev_kfree_skb(skb); 1173 return NETDEV_TX_OK; 1174 } 1175 1176 /* In XDP case, initial HW tx queues are used for XDP, 1177 * but stack's queue mapping starts at '0', so skip the 1178 * Tx queues attached to Rx queues for XDP. 1179 */ 1180 if (nic->xdp_prog) 1181 qid += nic->xdp_tx_queues; 1182 1183 snic = nic; 1184 /* Get secondary Qset's SQ structure */ 1185 if (qid >= MAX_SND_QUEUES_PER_QS) { 1186 tmp = qid / MAX_SND_QUEUES_PER_QS; 1187 snic = (struct nicvf *)nic->snicvf[tmp - 1]; 1188 if (!snic) { 1189 netdev_warn(nic->netdev, 1190 "Secondary Qset#%d's ptr not initialized\n", 1191 tmp - 1); 1192 dev_kfree_skb(skb); 1193 return NETDEV_TX_OK; 1194 } 1195 qid = qid % MAX_SND_QUEUES_PER_QS; 1196 } 1197 1198 sq = &snic->qs->sq[qid]; 1199 if (!netif_tx_queue_stopped(txq) && 1200 !nicvf_sq_append_skb(snic, sq, skb, qid)) { 1201 netif_tx_stop_queue(txq); 1202 1203 /* Barrier, so that stop_queue visible to other cpus */ 1204 smp_mb(); 1205 1206 /* Check again, incase another cpu freed descriptors */ 1207 if (atomic_read(&sq->free_cnt) > MIN_SQ_DESC_PER_PKT_XMIT) { 1208 netif_tx_wake_queue(txq); 1209 } else { 1210 this_cpu_inc(nic->drv_stats->txq_stop); 1211 netif_warn(nic, tx_err, netdev, 1212 "Transmit ring full, stopping SQ%d\n", qid); 1213 } 1214 return NETDEV_TX_BUSY; 1215 } 1216 1217 return NETDEV_TX_OK; 1218 } 1219 1220 static inline void nicvf_free_cq_poll(struct nicvf *nic) 1221 { 1222 struct nicvf_cq_poll *cq_poll; 1223 int qidx; 1224 1225 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1226 cq_poll = nic->napi[qidx]; 1227 if (!cq_poll) 1228 continue; 1229 nic->napi[qidx] = NULL; 1230 kfree(cq_poll); 1231 } 1232 } 1233 1234 int nicvf_stop(struct net_device *netdev) 1235 { 1236 int irq, qidx; 1237 struct nicvf *nic = netdev_priv(netdev); 1238 struct queue_set *qs = nic->qs; 1239 struct nicvf_cq_poll *cq_poll = NULL; 1240 union nic_mbx mbx = {}; 1241 1242 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN; 1243 nicvf_send_msg_to_pf(nic, &mbx); 1244 1245 netif_carrier_off(netdev); 1246 netif_tx_stop_all_queues(nic->netdev); 1247 nic->link_up = false; 1248 1249 /* Teardown secondary qsets first */ 1250 if (!nic->sqs_mode) { 1251 for (qidx = 0; qidx < nic->sqs_count; qidx++) { 1252 if (!nic->snicvf[qidx]) 1253 continue; 1254 nicvf_stop(nic->snicvf[qidx]->netdev); 1255 nic->snicvf[qidx] = NULL; 1256 } 1257 } 1258 1259 /* Disable RBDR & QS error interrupts */ 1260 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) { 1261 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx); 1262 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx); 1263 } 1264 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0); 1265 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0); 1266 1267 /* Wait for pending IRQ handlers to finish */ 1268 for (irq = 0; irq < nic->num_vec; irq++) 1269 synchronize_irq(pci_irq_vector(nic->pdev, irq)); 1270 1271 tasklet_kill(&nic->rbdr_task); 1272 tasklet_kill(&nic->qs_err_task); 1273 if (nic->rb_work_scheduled) 1274 cancel_delayed_work_sync(&nic->rbdr_work); 1275 1276 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) { 1277 cq_poll = nic->napi[qidx]; 1278 if (!cq_poll) 1279 continue; 1280 napi_synchronize(&cq_poll->napi); 1281 /* CQ intr is enabled while napi_complete, 1282 * so disable it now 1283 */ 1284 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx); 1285 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx); 1286 napi_disable(&cq_poll->napi); 1287 netif_napi_del(&cq_poll->napi); 1288 } 1289 1290 netif_tx_disable(netdev); 1291 1292 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1293 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1294 1295 /* Free resources */ 1296 nicvf_config_data_transfer(nic, false); 1297 1298 /* Disable HW Qset */ 1299 nicvf_qset_config(nic, false); 1300 1301 /* disable mailbox interrupt */ 1302 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1303 1304 nicvf_unregister_interrupts(nic); 1305 1306 nicvf_free_cq_poll(nic); 1307 1308 /* Clear multiqset info */ 1309 nic->pnicvf = nic; 1310 1311 return 0; 1312 } 1313 1314 static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) 1315 { 1316 union nic_mbx mbx = {}; 1317 1318 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; 1319 mbx.frs.max_frs = mtu; 1320 mbx.frs.vf_id = nic->vf_id; 1321 1322 return nicvf_send_msg_to_pf(nic, &mbx); 1323 } 1324 1325 int nicvf_open(struct net_device *netdev) 1326 { 1327 int cpu, err, qidx; 1328 struct nicvf *nic = netdev_priv(netdev); 1329 struct queue_set *qs = nic->qs; 1330 struct nicvf_cq_poll *cq_poll = NULL; 1331 union nic_mbx mbx = {}; 1332 1333 netif_carrier_off(netdev); 1334 1335 err = nicvf_register_misc_interrupt(nic); 1336 if (err) 1337 return err; 1338 1339 /* Register NAPI handler for processing CQEs */ 1340 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1341 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL); 1342 if (!cq_poll) { 1343 err = -ENOMEM; 1344 goto napi_del; 1345 } 1346 cq_poll->cq_idx = qidx; 1347 cq_poll->nicvf = nic; 1348 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll, 1349 NAPI_POLL_WEIGHT); 1350 napi_enable(&cq_poll->napi); 1351 nic->napi[qidx] = cq_poll; 1352 } 1353 1354 /* Check if we got MAC address from PF or else generate a radom MAC */ 1355 if (!nic->sqs_mode && is_zero_ether_addr(netdev->dev_addr)) { 1356 eth_hw_addr_random(netdev); 1357 nicvf_hw_set_mac_addr(nic, netdev); 1358 } 1359 1360 if (nic->set_mac_pending) { 1361 nic->set_mac_pending = false; 1362 nicvf_hw_set_mac_addr(nic, netdev); 1363 } 1364 1365 /* Init tasklet for handling Qset err interrupt */ 1366 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err, 1367 (unsigned long)nic); 1368 1369 /* Init RBDR tasklet which will refill RBDR */ 1370 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task, 1371 (unsigned long)nic); 1372 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work); 1373 1374 /* Configure CPI alorithm */ 1375 nic->cpi_alg = cpi_alg; 1376 if (!nic->sqs_mode) 1377 nicvf_config_cpi(nic); 1378 1379 nicvf_request_sqs(nic); 1380 if (nic->sqs_mode) 1381 nicvf_get_primary_vf_struct(nic); 1382 1383 /* Configure receive side scaling and MTU */ 1384 if (!nic->sqs_mode) { 1385 nicvf_rss_init(nic); 1386 err = nicvf_update_hw_max_frs(nic, netdev->mtu); 1387 if (err) 1388 goto cleanup; 1389 1390 /* Clear percpu stats */ 1391 for_each_possible_cpu(cpu) 1392 memset(per_cpu_ptr(nic->drv_stats, cpu), 0, 1393 sizeof(struct nicvf_drv_stats)); 1394 } 1395 1396 err = nicvf_register_interrupts(nic); 1397 if (err) 1398 goto cleanup; 1399 1400 /* Initialize the queues */ 1401 err = nicvf_init_resources(nic); 1402 if (err) 1403 goto cleanup; 1404 1405 /* Make sure queue initialization is written */ 1406 wmb(); 1407 1408 nicvf_reg_write(nic, NIC_VF_INT, -1); 1409 /* Enable Qset err interrupt */ 1410 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0); 1411 1412 /* Enable completion queue interrupt */ 1413 for (qidx = 0; qidx < qs->cq_cnt; qidx++) 1414 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx); 1415 1416 /* Enable RBDR threshold interrupt */ 1417 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) 1418 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); 1419 1420 /* Send VF config done msg to PF */ 1421 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; 1422 nicvf_write_to_mbx(nic, &mbx); 1423 1424 return 0; 1425 cleanup: 1426 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0); 1427 nicvf_unregister_interrupts(nic); 1428 tasklet_kill(&nic->qs_err_task); 1429 tasklet_kill(&nic->rbdr_task); 1430 napi_del: 1431 for (qidx = 0; qidx < qs->cq_cnt; qidx++) { 1432 cq_poll = nic->napi[qidx]; 1433 if (!cq_poll) 1434 continue; 1435 napi_disable(&cq_poll->napi); 1436 netif_napi_del(&cq_poll->napi); 1437 } 1438 nicvf_free_cq_poll(nic); 1439 return err; 1440 } 1441 1442 static int nicvf_change_mtu(struct net_device *netdev, int new_mtu) 1443 { 1444 struct nicvf *nic = netdev_priv(netdev); 1445 int orig_mtu = netdev->mtu; 1446 1447 netdev->mtu = new_mtu; 1448 1449 if (!netif_running(netdev)) 1450 return 0; 1451 1452 if (nicvf_update_hw_max_frs(nic, new_mtu)) { 1453 netdev->mtu = orig_mtu; 1454 return -EINVAL; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static int nicvf_set_mac_address(struct net_device *netdev, void *p) 1461 { 1462 struct sockaddr *addr = p; 1463 struct nicvf *nic = netdev_priv(netdev); 1464 1465 if (!is_valid_ether_addr(addr->sa_data)) 1466 return -EADDRNOTAVAIL; 1467 1468 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1469 1470 if (nic->pdev->msix_enabled) { 1471 if (nicvf_hw_set_mac_addr(nic, netdev)) 1472 return -EBUSY; 1473 } else { 1474 nic->set_mac_pending = true; 1475 } 1476 1477 return 0; 1478 } 1479 1480 void nicvf_update_lmac_stats(struct nicvf *nic) 1481 { 1482 int stat = 0; 1483 union nic_mbx mbx = {}; 1484 1485 if (!netif_running(nic->netdev)) 1486 return; 1487 1488 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 1489 mbx.bgx_stats.vf_id = nic->vf_id; 1490 /* Rx stats */ 1491 mbx.bgx_stats.rx = 1; 1492 while (stat < BGX_RX_STATS_COUNT) { 1493 mbx.bgx_stats.idx = stat; 1494 if (nicvf_send_msg_to_pf(nic, &mbx)) 1495 return; 1496 stat++; 1497 } 1498 1499 stat = 0; 1500 1501 /* Tx stats */ 1502 mbx.bgx_stats.rx = 0; 1503 while (stat < BGX_TX_STATS_COUNT) { 1504 mbx.bgx_stats.idx = stat; 1505 if (nicvf_send_msg_to_pf(nic, &mbx)) 1506 return; 1507 stat++; 1508 } 1509 } 1510 1511 void nicvf_update_stats(struct nicvf *nic) 1512 { 1513 int qidx, cpu; 1514 u64 tmp_stats = 0; 1515 struct nicvf_hw_stats *stats = &nic->hw_stats; 1516 struct nicvf_drv_stats *drv_stats; 1517 struct queue_set *qs = nic->qs; 1518 1519 #define GET_RX_STATS(reg) \ 1520 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3)) 1521 #define GET_TX_STATS(reg) \ 1522 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3)) 1523 1524 stats->rx_bytes = GET_RX_STATS(RX_OCTS); 1525 stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST); 1526 stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST); 1527 stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST); 1528 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS); 1529 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR); 1530 stats->rx_drop_red = GET_RX_STATS(RX_RED); 1531 stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS); 1532 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN); 1533 stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS); 1534 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST); 1535 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST); 1536 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); 1537 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); 1538 1539 stats->tx_bytes = GET_TX_STATS(TX_OCTS); 1540 stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST); 1541 stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST); 1542 stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST); 1543 stats->tx_drops = GET_TX_STATS(TX_DROP); 1544 1545 /* On T88 pass 2.0, the dummy SQE added for TSO notification 1546 * via CQE has 'dont_send' set. Hence HW drops the pkt pointed 1547 * pointed by dummy SQE and results in tx_drops counter being 1548 * incremented. Subtracting it from tx_tso counter will give 1549 * exact tx_drops counter. 1550 */ 1551 if (nic->t88 && nic->hw_tso) { 1552 for_each_possible_cpu(cpu) { 1553 drv_stats = per_cpu_ptr(nic->drv_stats, cpu); 1554 tmp_stats += drv_stats->tx_tso; 1555 } 1556 stats->tx_drops = tmp_stats - stats->tx_drops; 1557 } 1558 stats->tx_frames = stats->tx_ucast_frames + 1559 stats->tx_bcast_frames + 1560 stats->tx_mcast_frames; 1561 stats->rx_frames = stats->rx_ucast_frames + 1562 stats->rx_bcast_frames + 1563 stats->rx_mcast_frames; 1564 stats->rx_drops = stats->rx_drop_red + 1565 stats->rx_drop_overrun; 1566 1567 /* Update RQ and SQ stats */ 1568 for (qidx = 0; qidx < qs->rq_cnt; qidx++) 1569 nicvf_update_rq_stats(nic, qidx); 1570 for (qidx = 0; qidx < qs->sq_cnt; qidx++) 1571 nicvf_update_sq_stats(nic, qidx); 1572 } 1573 1574 static void nicvf_get_stats64(struct net_device *netdev, 1575 struct rtnl_link_stats64 *stats) 1576 { 1577 struct nicvf *nic = netdev_priv(netdev); 1578 struct nicvf_hw_stats *hw_stats = &nic->hw_stats; 1579 1580 nicvf_update_stats(nic); 1581 1582 stats->rx_bytes = hw_stats->rx_bytes; 1583 stats->rx_packets = hw_stats->rx_frames; 1584 stats->rx_dropped = hw_stats->rx_drops; 1585 stats->multicast = hw_stats->rx_mcast_frames; 1586 1587 stats->tx_bytes = hw_stats->tx_bytes; 1588 stats->tx_packets = hw_stats->tx_frames; 1589 stats->tx_dropped = hw_stats->tx_drops; 1590 1591 } 1592 1593 static void nicvf_tx_timeout(struct net_device *dev) 1594 { 1595 struct nicvf *nic = netdev_priv(dev); 1596 1597 netif_warn(nic, tx_err, dev, "Transmit timed out, resetting\n"); 1598 1599 this_cpu_inc(nic->drv_stats->tx_timeout); 1600 schedule_work(&nic->reset_task); 1601 } 1602 1603 static void nicvf_reset_task(struct work_struct *work) 1604 { 1605 struct nicvf *nic; 1606 1607 nic = container_of(work, struct nicvf, reset_task); 1608 1609 if (!netif_running(nic->netdev)) 1610 return; 1611 1612 nicvf_stop(nic->netdev); 1613 nicvf_open(nic->netdev); 1614 netif_trans_update(nic->netdev); 1615 } 1616 1617 static int nicvf_config_loopback(struct nicvf *nic, 1618 netdev_features_t features) 1619 { 1620 union nic_mbx mbx = {}; 1621 1622 mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK; 1623 mbx.lbk.vf_id = nic->vf_id; 1624 mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0; 1625 1626 return nicvf_send_msg_to_pf(nic, &mbx); 1627 } 1628 1629 static netdev_features_t nicvf_fix_features(struct net_device *netdev, 1630 netdev_features_t features) 1631 { 1632 struct nicvf *nic = netdev_priv(netdev); 1633 1634 if ((features & NETIF_F_LOOPBACK) && 1635 netif_running(netdev) && !nic->loopback_supported) 1636 features &= ~NETIF_F_LOOPBACK; 1637 1638 return features; 1639 } 1640 1641 static int nicvf_set_features(struct net_device *netdev, 1642 netdev_features_t features) 1643 { 1644 struct nicvf *nic = netdev_priv(netdev); 1645 netdev_features_t changed = features ^ netdev->features; 1646 1647 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 1648 nicvf_config_vlan_stripping(nic, features); 1649 1650 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1651 return nicvf_config_loopback(nic, features); 1652 1653 return 0; 1654 } 1655 1656 static void nicvf_set_xdp_queues(struct nicvf *nic, bool bpf_attached) 1657 { 1658 u8 cq_count, txq_count; 1659 1660 /* Set XDP Tx queue count same as Rx queue count */ 1661 if (!bpf_attached) 1662 nic->xdp_tx_queues = 0; 1663 else 1664 nic->xdp_tx_queues = nic->rx_queues; 1665 1666 /* If queue count > MAX_CMP_QUEUES_PER_QS, then additional qsets 1667 * needs to be allocated, check how many. 1668 */ 1669 txq_count = nic->xdp_tx_queues + nic->tx_queues; 1670 cq_count = max(nic->rx_queues, txq_count); 1671 if (cq_count > MAX_CMP_QUEUES_PER_QS) { 1672 nic->sqs_count = roundup(cq_count, MAX_CMP_QUEUES_PER_QS); 1673 nic->sqs_count = (nic->sqs_count / MAX_CMP_QUEUES_PER_QS) - 1; 1674 } else { 1675 nic->sqs_count = 0; 1676 } 1677 1678 /* Set primary Qset's resources */ 1679 nic->qs->rq_cnt = min_t(u8, nic->rx_queues, MAX_RCV_QUEUES_PER_QS); 1680 nic->qs->sq_cnt = min_t(u8, txq_count, MAX_SND_QUEUES_PER_QS); 1681 nic->qs->cq_cnt = max_t(u8, nic->qs->rq_cnt, nic->qs->sq_cnt); 1682 1683 /* Update stack */ 1684 nicvf_set_real_num_queues(nic->netdev, nic->tx_queues, nic->rx_queues); 1685 } 1686 1687 static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog) 1688 { 1689 struct net_device *dev = nic->netdev; 1690 bool if_up = netif_running(nic->netdev); 1691 struct bpf_prog *old_prog; 1692 bool bpf_attached = false; 1693 1694 /* For now just support only the usual MTU sized frames */ 1695 if (prog && (dev->mtu > 1500)) { 1696 netdev_warn(dev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 1697 dev->mtu); 1698 return -EOPNOTSUPP; 1699 } 1700 1701 /* ALL SQs attached to CQs i.e same as RQs, are treated as 1702 * XDP Tx queues and more Tx queues are allocated for 1703 * network stack to send pkts out. 1704 * 1705 * No of Tx queues are either same as Rx queues or whatever 1706 * is left in max no of queues possible. 1707 */ 1708 if ((nic->rx_queues + nic->tx_queues) > nic->max_queues) { 1709 netdev_warn(dev, 1710 "Failed to attach BPF prog, RXQs + TXQs > Max %d\n", 1711 nic->max_queues); 1712 return -ENOMEM; 1713 } 1714 1715 if (if_up) 1716 nicvf_stop(nic->netdev); 1717 1718 old_prog = xchg(&nic->xdp_prog, prog); 1719 /* Detach old prog, if any */ 1720 if (old_prog) 1721 bpf_prog_put(old_prog); 1722 1723 if (nic->xdp_prog) { 1724 /* Attach BPF program */ 1725 nic->xdp_prog = bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1); 1726 if (!IS_ERR(nic->xdp_prog)) 1727 bpf_attached = true; 1728 } 1729 1730 /* Calculate Tx queues needed for XDP and network stack */ 1731 nicvf_set_xdp_queues(nic, bpf_attached); 1732 1733 if (if_up) { 1734 /* Reinitialize interface, clean slate */ 1735 nicvf_open(nic->netdev); 1736 netif_trans_update(nic->netdev); 1737 } 1738 1739 return 0; 1740 } 1741 1742 static int nicvf_xdp(struct net_device *netdev, struct netdev_xdp *xdp) 1743 { 1744 struct nicvf *nic = netdev_priv(netdev); 1745 1746 /* To avoid checks while retrieving buffer address from CQE_RX, 1747 * do not support XDP for T88 pass1.x silicons which are anyway 1748 * not in use widely. 1749 */ 1750 if (pass1_silicon(nic->pdev)) 1751 return -EOPNOTSUPP; 1752 1753 switch (xdp->command) { 1754 case XDP_SETUP_PROG: 1755 return nicvf_xdp_setup(nic, xdp->prog); 1756 case XDP_QUERY_PROG: 1757 xdp->prog_attached = !!nic->xdp_prog; 1758 xdp->prog_id = nic->xdp_prog ? nic->xdp_prog->aux->id : 0; 1759 return 0; 1760 default: 1761 return -EINVAL; 1762 } 1763 } 1764 1765 static const struct net_device_ops nicvf_netdev_ops = { 1766 .ndo_open = nicvf_open, 1767 .ndo_stop = nicvf_stop, 1768 .ndo_start_xmit = nicvf_xmit, 1769 .ndo_change_mtu = nicvf_change_mtu, 1770 .ndo_set_mac_address = nicvf_set_mac_address, 1771 .ndo_get_stats64 = nicvf_get_stats64, 1772 .ndo_tx_timeout = nicvf_tx_timeout, 1773 .ndo_fix_features = nicvf_fix_features, 1774 .ndo_set_features = nicvf_set_features, 1775 .ndo_xdp = nicvf_xdp, 1776 }; 1777 1778 static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1779 { 1780 struct device *dev = &pdev->dev; 1781 struct net_device *netdev; 1782 struct nicvf *nic; 1783 int err, qcount; 1784 u16 sdevid; 1785 1786 err = pci_enable_device(pdev); 1787 if (err) { 1788 dev_err(dev, "Failed to enable PCI device\n"); 1789 return err; 1790 } 1791 1792 err = pci_request_regions(pdev, DRV_NAME); 1793 if (err) { 1794 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1795 goto err_disable_device; 1796 } 1797 1798 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 1799 if (err) { 1800 dev_err(dev, "Unable to get usable DMA configuration\n"); 1801 goto err_release_regions; 1802 } 1803 1804 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 1805 if (err) { 1806 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n"); 1807 goto err_release_regions; 1808 } 1809 1810 qcount = netif_get_num_default_rss_queues(); 1811 1812 /* Restrict multiqset support only for host bound VFs */ 1813 if (pdev->is_virtfn) { 1814 /* Set max number of queues per VF */ 1815 qcount = min_t(int, num_online_cpus(), 1816 (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS); 1817 } 1818 1819 netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount); 1820 if (!netdev) { 1821 err = -ENOMEM; 1822 goto err_release_regions; 1823 } 1824 1825 pci_set_drvdata(pdev, netdev); 1826 1827 SET_NETDEV_DEV(netdev, &pdev->dev); 1828 1829 nic = netdev_priv(netdev); 1830 nic->netdev = netdev; 1831 nic->pdev = pdev; 1832 nic->pnicvf = nic; 1833 nic->max_queues = qcount; 1834 1835 /* MAP VF's configuration registers */ 1836 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1837 if (!nic->reg_base) { 1838 dev_err(dev, "Cannot map config register space, aborting\n"); 1839 err = -ENOMEM; 1840 goto err_free_netdev; 1841 } 1842 1843 nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats); 1844 if (!nic->drv_stats) { 1845 err = -ENOMEM; 1846 goto err_free_netdev; 1847 } 1848 1849 err = nicvf_set_qset_resources(nic); 1850 if (err) 1851 goto err_free_netdev; 1852 1853 /* Check if PF is alive and get MAC address for this VF */ 1854 err = nicvf_register_misc_interrupt(nic); 1855 if (err) 1856 goto err_free_netdev; 1857 1858 nicvf_send_vf_struct(nic); 1859 1860 if (!pass1_silicon(nic->pdev)) 1861 nic->hw_tso = true; 1862 1863 /* Get iommu domain for iova to physical addr conversion */ 1864 nic->iommu_domain = iommu_get_domain_for_dev(dev); 1865 1866 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 1867 if (sdevid == 0xA134) 1868 nic->t88 = true; 1869 1870 /* Check if this VF is in QS only mode */ 1871 if (nic->sqs_mode) 1872 return 0; 1873 1874 err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues); 1875 if (err) 1876 goto err_unregister_interrupts; 1877 1878 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_SG | 1879 NETIF_F_TSO | NETIF_F_GRO | NETIF_F_TSO6 | 1880 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1881 NETIF_F_HW_VLAN_CTAG_RX); 1882 1883 netdev->hw_features |= NETIF_F_RXHASH; 1884 1885 netdev->features |= netdev->hw_features; 1886 netdev->hw_features |= NETIF_F_LOOPBACK; 1887 1888 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | 1889 NETIF_F_IPV6_CSUM | NETIF_F_TSO | NETIF_F_TSO6; 1890 1891 netdev->netdev_ops = &nicvf_netdev_ops; 1892 netdev->watchdog_timeo = NICVF_TX_TIMEOUT; 1893 1894 /* MTU range: 64 - 9200 */ 1895 netdev->min_mtu = NIC_HW_MIN_FRS; 1896 netdev->max_mtu = NIC_HW_MAX_FRS; 1897 1898 INIT_WORK(&nic->reset_task, nicvf_reset_task); 1899 1900 err = register_netdev(netdev); 1901 if (err) { 1902 dev_err(dev, "Failed to register netdevice\n"); 1903 goto err_unregister_interrupts; 1904 } 1905 1906 nic->msg_enable = debug; 1907 1908 nicvf_set_ethtool_ops(netdev); 1909 1910 return 0; 1911 1912 err_unregister_interrupts: 1913 nicvf_unregister_interrupts(nic); 1914 err_free_netdev: 1915 pci_set_drvdata(pdev, NULL); 1916 if (nic->drv_stats) 1917 free_percpu(nic->drv_stats); 1918 free_netdev(netdev); 1919 err_release_regions: 1920 pci_release_regions(pdev); 1921 err_disable_device: 1922 pci_disable_device(pdev); 1923 return err; 1924 } 1925 1926 static void nicvf_remove(struct pci_dev *pdev) 1927 { 1928 struct net_device *netdev = pci_get_drvdata(pdev); 1929 struct nicvf *nic; 1930 struct net_device *pnetdev; 1931 1932 if (!netdev) 1933 return; 1934 1935 nic = netdev_priv(netdev); 1936 pnetdev = nic->pnicvf->netdev; 1937 1938 /* Check if this Qset is assigned to different VF. 1939 * If yes, clean primary and all secondary Qsets. 1940 */ 1941 if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED)) 1942 unregister_netdev(pnetdev); 1943 nicvf_unregister_interrupts(nic); 1944 pci_set_drvdata(pdev, NULL); 1945 if (nic->drv_stats) 1946 free_percpu(nic->drv_stats); 1947 free_netdev(netdev); 1948 pci_release_regions(pdev); 1949 pci_disable_device(pdev); 1950 } 1951 1952 static void nicvf_shutdown(struct pci_dev *pdev) 1953 { 1954 nicvf_remove(pdev); 1955 } 1956 1957 static struct pci_driver nicvf_driver = { 1958 .name = DRV_NAME, 1959 .id_table = nicvf_id_table, 1960 .probe = nicvf_probe, 1961 .remove = nicvf_remove, 1962 .shutdown = nicvf_shutdown, 1963 }; 1964 1965 static int __init nicvf_init_module(void) 1966 { 1967 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1968 1969 return pci_register_driver(&nicvf_driver); 1970 } 1971 1972 static void __exit nicvf_cleanup_module(void) 1973 { 1974 pci_unregister_driver(&nicvf_driver); 1975 } 1976 1977 module_init(nicvf_init_module); 1978 module_exit(nicvf_cleanup_module); 1979