1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef NIC_REG_H 10 #define NIC_REG_H 11 12 #define NIC_PF_REG_COUNT 29573 13 #define NIC_VF_REG_COUNT 249 14 15 /* Physical function register offsets */ 16 #define NIC_PF_CFG (0x0000) 17 #define NIC_PF_STATUS (0x0010) 18 #define NIC_PF_INTR_TIMER_CFG (0x0030) 19 #define NIC_PF_BIST_STATUS (0x0040) 20 #define NIC_PF_SOFT_RESET (0x0050) 21 #define NIC_PF_TCP_TIMER (0x0060) 22 #define NIC_PF_BP_CFG (0x0080) 23 #define NIC_PF_RRM_CFG (0x0088) 24 #define NIC_PF_CQM_CFG (0x00A0) 25 #define NIC_PF_CNM_CF (0x00A8) 26 #define NIC_PF_CNM_STATUS (0x00B0) 27 #define NIC_PF_CQ_AVG_CFG (0x00C0) 28 #define NIC_PF_RRM_AVG_CFG (0x00C8) 29 #define NIC_PF_INTF_0_1_SEND_CFG (0x0200) 30 #define NIC_PF_INTF_0_1_BP_CFG (0x0208) 31 #define NIC_PF_INTF_0_1_BP_DIS_0_1 (0x0210) 32 #define NIC_PF_INTF_0_1_BP_SW_0_1 (0x0220) 33 #define NIC_PF_RBDR_BP_STATE_0_3 (0x0240) 34 #define NIC_PF_MAILBOX_INT (0x0410) 35 #define NIC_PF_MAILBOX_INT_W1S (0x0430) 36 #define NIC_PF_MAILBOX_ENA_W1C (0x0450) 37 #define NIC_PF_MAILBOX_ENA_W1S (0x0470) 38 #define NIC_PF_RX_ETYPE_0_7 (0x0500) 39 #define NIC_PF_PKIND_0_15_CFG (0x0600) 40 #define NIC_PF_ECC0_FLIP0 (0x1000) 41 #define NIC_PF_ECC1_FLIP0 (0x1008) 42 #define NIC_PF_ECC2_FLIP0 (0x1010) 43 #define NIC_PF_ECC3_FLIP0 (0x1018) 44 #define NIC_PF_ECC0_FLIP1 (0x1080) 45 #define NIC_PF_ECC1_FLIP1 (0x1088) 46 #define NIC_PF_ECC2_FLIP1 (0x1090) 47 #define NIC_PF_ECC3_FLIP1 (0x1098) 48 #define NIC_PF_ECC0_CDIS (0x1100) 49 #define NIC_PF_ECC1_CDIS (0x1108) 50 #define NIC_PF_ECC2_CDIS (0x1110) 51 #define NIC_PF_ECC3_CDIS (0x1118) 52 #define NIC_PF_BIST0_STATUS (0x1280) 53 #define NIC_PF_BIST1_STATUS (0x1288) 54 #define NIC_PF_BIST2_STATUS (0x1290) 55 #define NIC_PF_BIST3_STATUS (0x1298) 56 #define NIC_PF_ECC0_SBE_INT (0x2000) 57 #define NIC_PF_ECC0_SBE_INT_W1S (0x2008) 58 #define NIC_PF_ECC0_SBE_ENA_W1C (0x2010) 59 #define NIC_PF_ECC0_SBE_ENA_W1S (0x2018) 60 #define NIC_PF_ECC0_DBE_INT (0x2100) 61 #define NIC_PF_ECC0_DBE_INT_W1S (0x2108) 62 #define NIC_PF_ECC0_DBE_ENA_W1C (0x2110) 63 #define NIC_PF_ECC0_DBE_ENA_W1S (0x2118) 64 #define NIC_PF_ECC1_SBE_INT (0x2200) 65 #define NIC_PF_ECC1_SBE_INT_W1S (0x2208) 66 #define NIC_PF_ECC1_SBE_ENA_W1C (0x2210) 67 #define NIC_PF_ECC1_SBE_ENA_W1S (0x2218) 68 #define NIC_PF_ECC1_DBE_INT (0x2300) 69 #define NIC_PF_ECC1_DBE_INT_W1S (0x2308) 70 #define NIC_PF_ECC1_DBE_ENA_W1C (0x2310) 71 #define NIC_PF_ECC1_DBE_ENA_W1S (0x2318) 72 #define NIC_PF_ECC2_SBE_INT (0x2400) 73 #define NIC_PF_ECC2_SBE_INT_W1S (0x2408) 74 #define NIC_PF_ECC2_SBE_ENA_W1C (0x2410) 75 #define NIC_PF_ECC2_SBE_ENA_W1S (0x2418) 76 #define NIC_PF_ECC2_DBE_INT (0x2500) 77 #define NIC_PF_ECC2_DBE_INT_W1S (0x2508) 78 #define NIC_PF_ECC2_DBE_ENA_W1C (0x2510) 79 #define NIC_PF_ECC2_DBE_ENA_W1S (0x2518) 80 #define NIC_PF_ECC3_SBE_INT (0x2600) 81 #define NIC_PF_ECC3_SBE_INT_W1S (0x2608) 82 #define NIC_PF_ECC3_SBE_ENA_W1C (0x2610) 83 #define NIC_PF_ECC3_SBE_ENA_W1S (0x2618) 84 #define NIC_PF_ECC3_DBE_INT (0x2700) 85 #define NIC_PF_ECC3_DBE_INT_W1S (0x2708) 86 #define NIC_PF_ECC3_DBE_ENA_W1C (0x2710) 87 #define NIC_PF_ECC3_DBE_ENA_W1S (0x2718) 88 #define NIC_PF_MCAM_0_191_ENA (0x100000) 89 #define NIC_PF_MCAM_0_191_M_0_5_DATA (0x110000) 90 #define NIC_PF_MCAM_CTRL (0x120000) 91 #define NIC_PF_CPI_0_2047_CFG (0x200000) 92 #define NIC_PF_MPI_0_2047_CFG (0x210000) 93 #define NIC_PF_RSSI_0_4097_RQ (0x220000) 94 #define NIC_PF_LMAC_0_7_CFG (0x240000) 95 #define NIC_PF_LMAC_0_7_SW_XOFF (0x242000) 96 #define NIC_PF_LMAC_0_7_CREDIT (0x244000) 97 #define NIC_PF_CHAN_0_255_TX_CFG (0x400000) 98 #define NIC_PF_CHAN_0_255_RX_CFG (0x420000) 99 #define NIC_PF_CHAN_0_255_SW_XOFF (0x440000) 100 #define NIC_PF_CHAN_0_255_CREDIT (0x460000) 101 #define NIC_PF_CHAN_0_255_RX_BP_CFG (0x480000) 102 #define NIC_PF_SW_SYNC_RX (0x490000) 103 #define NIC_PF_SW_SYNC_RX_DONE (0x490008) 104 #define NIC_PF_TL2_0_63_CFG (0x500000) 105 #define NIC_PF_TL2_0_63_PRI (0x520000) 106 #define NIC_PF_TL2_0_63_SH_STATUS (0x580000) 107 #define NIC_PF_TL3A_0_63_CFG (0x5F0000) 108 #define NIC_PF_TL3_0_255_CFG (0x600000) 109 #define NIC_PF_TL3_0_255_CHAN (0x620000) 110 #define NIC_PF_TL3_0_255_PIR (0x640000) 111 #define NIC_PF_TL3_0_255_SW_XOFF (0x660000) 112 #define NIC_PF_TL3_0_255_CNM_RATE (0x680000) 113 #define NIC_PF_TL3_0_255_SH_STATUS (0x6A0000) 114 #define NIC_PF_TL4A_0_255_CFG (0x6F0000) 115 #define NIC_PF_TL4_0_1023_CFG (0x800000) 116 #define NIC_PF_TL4_0_1023_SW_XOFF (0x820000) 117 #define NIC_PF_TL4_0_1023_SH_STATUS (0x840000) 118 #define NIC_PF_TL4A_0_1023_CNM_RATE (0x880000) 119 #define NIC_PF_TL4A_0_1023_CNM_STATUS (0x8A0000) 120 #define NIC_PF_VF_0_127_MAILBOX_0_1 (0x20002030) 121 #define NIC_PF_VNIC_0_127_TX_STAT_0_4 (0x20004000) 122 #define NIC_PF_VNIC_0_127_RX_STAT_0_13 (0x20004100) 123 #define NIC_PF_QSET_0_127_LOCK_0_15 (0x20006000) 124 #define NIC_PF_QSET_0_127_CFG (0x20010000) 125 #define NIC_PF_QSET_0_127_RQ_0_7_CFG (0x20010400) 126 #define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420) 127 #define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG (0x20010500) 128 #define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600) 129 #define NIC_PF_QSET_0_127_SQ_0_7_CFG (0x20010C00) 130 #define NIC_PF_QSET_0_127_SQ_0_7_CFG2 (0x20010C08) 131 #define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00) 132 133 #define NIC_PF_MSIX_VEC_0_18_ADDR (0x000000) 134 #define NIC_PF_MSIX_VEC_0_CTL (0x000008) 135 #define NIC_PF_MSIX_PBA_0 (0x0F0000) 136 137 /* Virtual function register offsets */ 138 #define NIC_VNIC_CFG (0x000020) 139 #define NIC_VF_PF_MAILBOX_0_1 (0x000130) 140 #define NIC_VF_INT (0x000200) 141 #define NIC_VF_INT_W1S (0x000220) 142 #define NIC_VF_ENA_W1C (0x000240) 143 #define NIC_VF_ENA_W1S (0x000260) 144 145 #define NIC_VNIC_RSS_CFG (0x0020E0) 146 #define NIC_VNIC_RSS_KEY_0_4 (0x002200) 147 #define NIC_VNIC_TX_STAT_0_4 (0x004000) 148 #define NIC_VNIC_RX_STAT_0_13 (0x004100) 149 #define NIC_QSET_RQ_GEN_CFG (0x010010) 150 151 #define NIC_QSET_CQ_0_7_CFG (0x010400) 152 #define NIC_QSET_CQ_0_7_CFG2 (0x010408) 153 #define NIC_QSET_CQ_0_7_THRESH (0x010410) 154 #define NIC_QSET_CQ_0_7_BASE (0x010420) 155 #define NIC_QSET_CQ_0_7_HEAD (0x010428) 156 #define NIC_QSET_CQ_0_7_TAIL (0x010430) 157 #define NIC_QSET_CQ_0_7_DOOR (0x010438) 158 #define NIC_QSET_CQ_0_7_STATUS (0x010440) 159 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448) 160 #define NIC_QSET_CQ_0_7_DEBUG (0x010450) 161 162 #define NIC_QSET_RQ_0_7_CFG (0x010600) 163 #define NIC_QSET_RQ_0_7_STAT_0_1 (0x010700) 164 165 #define NIC_QSET_SQ_0_7_CFG (0x010800) 166 #define NIC_QSET_SQ_0_7_THRESH (0x010810) 167 #define NIC_QSET_SQ_0_7_BASE (0x010820) 168 #define NIC_QSET_SQ_0_7_HEAD (0x010828) 169 #define NIC_QSET_SQ_0_7_TAIL (0x010830) 170 #define NIC_QSET_SQ_0_7_DOOR (0x010838) 171 #define NIC_QSET_SQ_0_7_STATUS (0x010840) 172 #define NIC_QSET_SQ_0_7_DEBUG (0x010848) 173 #define NIC_QSET_SQ_0_7_CNM_CHG (0x010860) 174 #define NIC_QSET_SQ_0_7_STAT_0_1 (0x010900) 175 176 #define NIC_QSET_RBDR_0_1_CFG (0x010C00) 177 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10) 178 #define NIC_QSET_RBDR_0_1_BASE (0x010C20) 179 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28) 180 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30) 181 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38) 182 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40) 183 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48) 184 #define NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50) 185 186 #define NIC_VF_MSIX_VECTOR_0_19_ADDR (0x000000) 187 #define NIC_VF_MSIX_VECTOR_0_19_CTL (0x000008) 188 #define NIC_VF_MSIX_PBA (0x0F0000) 189 190 /* Offsets within registers */ 191 #define NIC_MSIX_VEC_SHIFT 4 192 #define NIC_Q_NUM_SHIFT 18 193 #define NIC_QS_ID_SHIFT 21 194 #define NIC_VF_NUM_SHIFT 21 195 196 /* Port kind configuration register */ 197 struct pkind_cfg { 198 #if defined(__BIG_ENDIAN_BITFIELD) 199 u64 reserved_42_63:22; 200 u64 hdr_sl:5; /* Header skip length */ 201 u64 rx_hdr:3; /* TNS Receive header present */ 202 u64 lenerr_en:1;/* L2 length error check enable */ 203 u64 reserved_32_32:1; 204 u64 maxlen:16; /* Max frame size */ 205 u64 minlen:16; /* Min frame size */ 206 #elif defined(__LITTLE_ENDIAN_BITFIELD) 207 u64 minlen:16; 208 u64 maxlen:16; 209 u64 reserved_32_32:1; 210 u64 lenerr_en:1; 211 u64 rx_hdr:3; 212 u64 hdr_sl:5; 213 u64 reserved_42_63:22; 214 #endif 215 }; 216 217 #endif /* NIC_REG_H */ 218