1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/etherdevice.h> 13 #include <linux/of.h> 14 15 #include "nic_reg.h" 16 #include "nic.h" 17 #include "q_struct.h" 18 #include "thunder_bgx.h" 19 20 #define DRV_NAME "thunder-nic" 21 #define DRV_VERSION "1.0" 22 23 struct nicpf { 24 struct pci_dev *pdev; 25 u8 rev_id; 26 u8 node; 27 unsigned int flags; 28 u8 num_vf_en; /* No of VF enabled */ 29 bool vf_enabled[MAX_NUM_VFS_SUPPORTED]; 30 void __iomem *reg_base; /* Register start address */ 31 u8 num_sqs_en; /* Secondary qsets enabled */ 32 u64 nicvf[MAX_NUM_VFS_SUPPORTED]; 33 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF]; 34 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED]; 35 bool sqs_used[MAX_NUM_VFS_SUPPORTED]; 36 struct pkind_cfg pkind; 37 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF)) 38 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF) 39 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF) 40 u8 vf_lmac_map[MAX_LMAC]; 41 struct delayed_work dwork; 42 struct workqueue_struct *check_link; 43 u8 link[MAX_LMAC]; 44 u8 duplex[MAX_LMAC]; 45 u32 speed[MAX_LMAC]; 46 u16 cpi_base[MAX_NUM_VFS_SUPPORTED]; 47 u16 rss_ind_tbl_size; 48 bool mbx_lock[MAX_NUM_VFS_SUPPORTED]; 49 50 /* MSI-X */ 51 bool msix_enabled; 52 u8 num_vec; 53 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; 54 bool irq_allocated[NIC_PF_MSIX_VECTORS]; 55 }; 56 57 /* Supported devices */ 58 static const struct pci_device_id nic_id_table[] = { 59 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) }, 60 { 0, } /* end of table */ 61 }; 62 63 MODULE_AUTHOR("Sunil Goutham"); 64 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver"); 65 MODULE_LICENSE("GPL v2"); 66 MODULE_VERSION(DRV_VERSION); 67 MODULE_DEVICE_TABLE(pci, nic_id_table); 68 69 /* The Cavium ThunderX network controller can *only* be found in SoCs 70 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 71 * registers on this platform are implicitly strongly ordered with respect 72 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 73 * with no memory barriers in this driver. The readq()/writeq() functions add 74 * explicit ordering operation which in this case are redundant, and only 75 * add overhead. 76 */ 77 78 /* Register read/write APIs */ 79 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val) 80 { 81 writeq_relaxed(val, nic->reg_base + offset); 82 } 83 84 static u64 nic_reg_read(struct nicpf *nic, u64 offset) 85 { 86 return readq_relaxed(nic->reg_base + offset); 87 } 88 89 /* PF -> VF mailbox communication APIs */ 90 static void nic_enable_mbx_intr(struct nicpf *nic) 91 { 92 /* Enable mailbox interrupt for all 128 VFs */ 93 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull); 94 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull); 95 } 96 97 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 98 { 99 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf)); 100 } 101 102 static u64 nic_get_mbx_addr(int vf) 103 { 104 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT); 105 } 106 107 /* Send a mailbox message to VF 108 * @vf: vf to which this message to be sent 109 * @mbx: Message to be sent 110 */ 111 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 112 { 113 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf); 114 u64 *msg = (u64 *)mbx; 115 116 /* In first revision HW, mbox interrupt is triggerred 117 * when PF writes to MBOX(1), in next revisions when 118 * PF writes to MBOX(0) 119 */ 120 if (nic->rev_id == 0) { 121 /* see the comment for nic_reg_write()/nic_reg_read() 122 * functions above 123 */ 124 writeq_relaxed(msg[0], mbx_addr); 125 writeq_relaxed(msg[1], mbx_addr + 8); 126 } else { 127 writeq_relaxed(msg[1], mbx_addr + 8); 128 writeq_relaxed(msg[0], mbx_addr); 129 } 130 } 131 132 /* Responds to VF's READY message with VF's 133 * ID, node, MAC address e.t.c 134 * @vf: VF which sent READY message 135 */ 136 static void nic_mbx_send_ready(struct nicpf *nic, int vf) 137 { 138 union nic_mbx mbx = {}; 139 int bgx_idx, lmac; 140 const char *mac; 141 142 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 143 mbx.nic_cfg.vf_id = vf; 144 145 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 146 147 if (vf < MAX_LMAC) { 148 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 149 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 150 151 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 152 if (mac) 153 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac); 154 } 155 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false; 156 mbx.nic_cfg.node_id = nic->node; 157 158 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; 159 160 nic_send_msg_to_vf(nic, vf, &mbx); 161 } 162 163 /* ACKs VF's mailbox message 164 * @vf: VF to which ACK to be sent 165 */ 166 static void nic_mbx_send_ack(struct nicpf *nic, int vf) 167 { 168 union nic_mbx mbx = {}; 169 170 mbx.msg.msg = NIC_MBOX_MSG_ACK; 171 nic_send_msg_to_vf(nic, vf, &mbx); 172 } 173 174 /* NACKs VF's mailbox message that PF is not able to 175 * complete the action 176 * @vf: VF to which ACK to be sent 177 */ 178 static void nic_mbx_send_nack(struct nicpf *nic, int vf) 179 { 180 union nic_mbx mbx = {}; 181 182 mbx.msg.msg = NIC_MBOX_MSG_NACK; 183 nic_send_msg_to_vf(nic, vf, &mbx); 184 } 185 186 /* Flush all in flight receive packets to memory and 187 * bring down an active RQ 188 */ 189 static int nic_rcv_queue_sw_sync(struct nicpf *nic) 190 { 191 u16 timeout = ~0x00; 192 193 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 194 /* Wait till sync cycle is finished */ 195 while (timeout) { 196 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 197 break; 198 timeout--; 199 } 200 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 201 if (!timeout) { 202 dev_err(&nic->pdev->dev, "Receive queue software sync failed"); 203 return 1; 204 } 205 return 0; 206 } 207 208 /* Get BGX Rx/Tx stats and respond to VF's request */ 209 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 210 { 211 int bgx_idx, lmac; 212 union nic_mbx mbx = {}; 213 214 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 215 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 216 217 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 218 mbx.bgx_stats.vf_id = bgx->vf_id; 219 mbx.bgx_stats.rx = bgx->rx; 220 mbx.bgx_stats.idx = bgx->idx; 221 if (bgx->rx) 222 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx, 223 lmac, bgx->idx); 224 else 225 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx, 226 lmac, bgx->idx); 227 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 228 } 229 230 /* Update hardware min/max frame size */ 231 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 232 { 233 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { 234 dev_err(&nic->pdev->dev, 235 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n", 236 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); 237 return 1; 238 } 239 new_frs += ETH_HLEN; 240 if (new_frs <= nic->pkind.maxlen) 241 return 0; 242 243 nic->pkind.maxlen = new_frs; 244 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind); 245 return 0; 246 } 247 248 /* Set minimum transmit packet size */ 249 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size) 250 { 251 int lmac; 252 u64 lmac_cfg; 253 254 /* Max value that can be set is 60 */ 255 if (size > 60) 256 size = 60; 257 258 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { 259 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 260 lmac_cfg &= ~(0xF << 2); 261 lmac_cfg |= ((size / 4) << 2); 262 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 263 } 264 } 265 266 /* Function to check number of LMACs present and set VF::LMAC mapping. 267 * Mapping will be used while initializing channels. 268 */ 269 static void nic_set_lmac_vf_mapping(struct nicpf *nic) 270 { 271 unsigned bgx_map = bgx_get_map(nic->node); 272 int bgx, next_bgx_lmac = 0; 273 int lmac, lmac_cnt = 0; 274 u64 lmac_credit; 275 276 nic->num_vf_en = 0; 277 278 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { 279 if (!(bgx_map & (1 << bgx))) 280 continue; 281 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 282 for (lmac = 0; lmac < lmac_cnt; lmac++) 283 nic->vf_lmac_map[next_bgx_lmac++] = 284 NIC_SET_VF_LMAC_MAP(bgx, lmac); 285 nic->num_vf_en += lmac_cnt; 286 287 /* Program LMAC credits */ 288 lmac_credit = (1ull << 1); /* channel credit enable */ 289 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 290 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 291 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 292 NIC_HW_MAX_FRS) / 16) << 12); 293 lmac = bgx * MAX_LMAC_PER_BGX; 294 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) 295 nic_reg_write(nic, 296 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 297 lmac_credit); 298 } 299 } 300 301 #define BGX0_BLOCK 8 302 #define BGX1_BLOCK 9 303 304 static void nic_init_hw(struct nicpf *nic) 305 { 306 int i; 307 308 /* Reset NIC, in case the driver is repeatedly inserted and removed */ 309 nic_reg_write(nic, NIC_PF_SOFT_RESET, 1); 310 311 /* Enable NIC HW block */ 312 nic_reg_write(nic, NIC_PF_CFG, 0x3); 313 314 /* Enable backpressure */ 315 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03); 316 317 /* Disable TNS mode on both interfaces */ 318 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 319 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); 320 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 321 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); 322 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 323 (1ULL << 63) | BGX0_BLOCK); 324 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 325 (1ULL << 63) | BGX1_BLOCK); 326 327 /* PKIND configuration */ 328 nic->pkind.minlen = 0; 329 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN; 330 nic->pkind.lenerr_en = 1; 331 nic->pkind.rx_hdr = 0; 332 nic->pkind.hdr_sl = 0; 333 334 for (i = 0; i < NIC_MAX_PKIND; i++) 335 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 336 *(u64 *)&nic->pkind); 337 338 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 339 340 /* Timer config */ 341 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 342 343 /* Enable VLAN ethertype matching and stripping */ 344 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 345 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q); 346 } 347 348 /* Channel parse index configuration */ 349 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 350 { 351 u32 vnic, bgx, lmac, chan; 352 u32 padd, cpi_count = 0; 353 u64 cpi_base, cpi, rssi_base, rssi; 354 u8 qset, rq_idx = 0; 355 356 vnic = cfg->vf_id; 357 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 358 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 359 360 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 361 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); 362 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); 363 364 /* Rx channel configuration */ 365 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 366 (1ull << 63) | (vnic << 0)); 367 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 368 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48)); 369 370 if (cfg->cpi_alg == CPI_ALG_NONE) 371 cpi_count = 1; 372 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 373 cpi_count = 8; 374 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 375 cpi_count = 16; 376 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 377 cpi_count = NIC_MAX_CPI_PER_LMAC; 378 379 /* RSS Qset, Qidx mapping */ 380 qset = cfg->vf_id; 381 rssi = rssi_base; 382 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 383 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 384 (qset << 3) | rq_idx); 385 rq_idx++; 386 } 387 388 rssi = 0; 389 cpi = cpi_base; 390 for (; cpi < (cpi_base + cpi_count); cpi++) { 391 /* Determine port to channel adder */ 392 if (cfg->cpi_alg != CPI_ALG_DIFF) 393 padd = cpi % cpi_count; 394 else 395 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 396 397 /* Leave RSS_SIZE as '0' to disable RSS */ 398 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 399 (vnic << 24) | (padd << 16) | (rssi_base + rssi)); 400 401 if ((rssi + 1) >= cfg->rq_cnt) 402 continue; 403 404 if (cfg->cpi_alg == CPI_ALG_VLAN) 405 rssi++; 406 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 407 rssi = ((cpi - cpi_base) & 0xe) >> 1; 408 else if (cfg->cpi_alg == CPI_ALG_DIFF) 409 rssi = ((cpi - cpi_base) & 0x38) >> 3; 410 } 411 nic->cpi_base[cfg->vf_id] = cpi_base; 412 } 413 414 /* Responsds to VF with its RSS indirection table size */ 415 static void nic_send_rss_size(struct nicpf *nic, int vf) 416 { 417 union nic_mbx mbx = {}; 418 u64 *msg; 419 420 msg = (u64 *)&mbx; 421 422 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 423 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size; 424 nic_send_msg_to_vf(nic, vf, &mbx); 425 } 426 427 /* Receive side scaling configuration 428 * configure: 429 * - RSS index 430 * - indir table i.e hash::RQ mapping 431 * - no of hash bits to consider 432 */ 433 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) 434 { 435 u8 qset, idx = 0; 436 u64 cpi_cfg, cpi_base, rssi_base, rssi; 437 438 cpi_base = nic->cpi_base[cfg->vf_id]; 439 cpi_cfg = nic_reg_read(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3)); 440 rssi_base = (cpi_cfg & 0x0FFF) + cfg->tbl_offset; 441 442 rssi = rssi_base; 443 qset = cfg->vf_id; 444 445 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) { 446 u8 svf = cfg->ind_tbl[idx] >> 3; 447 448 if (svf) 449 qset = nic->vf_sqs[cfg->vf_id][svf - 1]; 450 else 451 qset = cfg->vf_id; 452 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 453 (qset << 3) | (cfg->ind_tbl[idx] & 0x7)); 454 idx++; 455 } 456 457 cpi_cfg &= ~(0xFULL << 20); 458 cpi_cfg |= (cfg->hash_bits << 20); 459 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3), cpi_cfg); 460 } 461 462 /* 4 level transmit side scheduler configutation 463 * for TNS bypass mode 464 * 465 * Sample configuration for SQ0 466 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 467 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 468 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 469 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 470 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 471 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 472 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 473 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 474 */ 475 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic, 476 struct sq_cfg_msg *sq) 477 { 478 u32 bgx, lmac, chan; 479 u32 tl2, tl3, tl4; 480 u32 rr_quantum; 481 u8 sq_idx = sq->sq_num; 482 u8 pqs_vnic; 483 484 if (sq->sqs_mode) 485 pqs_vnic = nic->pqs_vf[vnic]; 486 else 487 pqs_vnic = vnic; 488 489 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 490 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 491 492 /* 24 bytes for FCS, IPG and preamble */ 493 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 494 495 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); 496 tl4 += sq_idx; 497 if (sq->sqs_mode) 498 tl4 += vnic * 8; 499 500 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); 501 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 502 ((u64)vnic << NIC_QS_ID_SHIFT) | 503 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4); 504 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 505 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum); 506 507 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 508 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 509 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 510 /* Enable backpressure on the channel */ 511 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 512 513 tl2 = tl3 >> 2; 514 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 515 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 516 /* No priorities as of now */ 517 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 518 } 519 520 /* Send primary nicvf pointer to secondary QS's VF */ 521 static void nic_send_pnicvf(struct nicpf *nic, int sqs) 522 { 523 union nic_mbx mbx = {}; 524 525 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 526 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]]; 527 nic_send_msg_to_vf(nic, sqs, &mbx); 528 } 529 530 /* Send SQS's nicvf pointer to primary QS's VF */ 531 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf) 532 { 533 union nic_mbx mbx = {}; 534 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id]; 535 536 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 537 mbx.nicvf.sqs_id = nicvf->sqs_id; 538 mbx.nicvf.nicvf = nic->nicvf[sqs_id]; 539 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx); 540 } 541 542 /* Find next available Qset that can be assigned as a 543 * secondary Qset to a VF. 544 */ 545 static int nic_nxt_avail_sqs(struct nicpf *nic) 546 { 547 int sqs; 548 549 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) { 550 if (!nic->sqs_used[sqs]) 551 nic->sqs_used[sqs] = true; 552 else 553 continue; 554 return sqs + nic->num_vf_en; 555 } 556 return -1; 557 } 558 559 /* Allocate additional Qsets for requested VF */ 560 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs) 561 { 562 union nic_mbx mbx = {}; 563 int idx, alloc_qs = 0; 564 int sqs_id; 565 566 if (!nic->num_sqs_en) 567 goto send_mbox; 568 569 for (idx = 0; idx < sqs->qs_count; idx++) { 570 sqs_id = nic_nxt_avail_sqs(nic); 571 if (sqs_id < 0) 572 break; 573 nic->vf_sqs[sqs->vf_id][idx] = sqs_id; 574 nic->pqs_vf[sqs_id] = sqs->vf_id; 575 alloc_qs++; 576 } 577 578 send_mbox: 579 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 580 mbx.sqs_alloc.vf_id = sqs->vf_id; 581 mbx.sqs_alloc.qs_count = alloc_qs; 582 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx); 583 } 584 585 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 586 { 587 int bgx_idx, lmac_idx; 588 589 if (lbk->vf_id > MAX_LMAC) 590 return -1; 591 592 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 593 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 594 595 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 596 597 return 0; 598 } 599 600 /* Interrupt handler to handle mailbox messages from VFs */ 601 static void nic_handle_mbx_intr(struct nicpf *nic, int vf) 602 { 603 union nic_mbx mbx = {}; 604 u64 *mbx_data; 605 u64 mbx_addr; 606 u64 reg_addr; 607 u64 cfg; 608 int bgx, lmac; 609 int i; 610 int ret = 0; 611 612 nic->mbx_lock[vf] = true; 613 614 mbx_addr = nic_get_mbx_addr(vf); 615 mbx_data = (u64 *)&mbx; 616 617 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 618 *mbx_data = nic_reg_read(nic, mbx_addr); 619 mbx_data++; 620 mbx_addr += sizeof(u64); 621 } 622 623 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n", 624 __func__, mbx.msg.msg, vf); 625 switch (mbx.msg.msg) { 626 case NIC_MBOX_MSG_READY: 627 nic_mbx_send_ready(nic, vf); 628 if (vf < MAX_LMAC) { 629 nic->link[vf] = 0; 630 nic->duplex[vf] = 0; 631 nic->speed[vf] = 0; 632 } 633 ret = 1; 634 break; 635 case NIC_MBOX_MSG_QS_CFG: 636 reg_addr = NIC_PF_QSET_0_127_CFG | 637 (mbx.qs.num << NIC_QS_ID_SHIFT); 638 cfg = mbx.qs.cfg; 639 /* Check if its a secondary Qset */ 640 if (vf >= nic->num_vf_en) { 641 cfg = cfg & (~0x7FULL); 642 /* Assign this Qset to primary Qset's VF */ 643 cfg |= nic->pqs_vf[vf]; 644 } 645 nic_reg_write(nic, reg_addr, cfg); 646 break; 647 case NIC_MBOX_MSG_RQ_CFG: 648 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 649 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 650 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 651 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 652 break; 653 case NIC_MBOX_MSG_RQ_BP_CFG: 654 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 655 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 656 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 657 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 658 break; 659 case NIC_MBOX_MSG_RQ_SW_SYNC: 660 ret = nic_rcv_queue_sw_sync(nic); 661 break; 662 case NIC_MBOX_MSG_RQ_DROP_CFG: 663 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 664 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 665 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 666 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 667 break; 668 case NIC_MBOX_MSG_SQ_CFG: 669 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 670 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 671 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 672 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 673 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 674 break; 675 case NIC_MBOX_MSG_SET_MAC: 676 if (vf >= nic->num_vf_en) 677 break; 678 lmac = mbx.mac.vf_id; 679 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 680 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 681 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 682 break; 683 case NIC_MBOX_MSG_SET_MAX_FRS: 684 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, 685 mbx.frs.vf_id); 686 break; 687 case NIC_MBOX_MSG_CPI_CFG: 688 nic_config_cpi(nic, &mbx.cpi_cfg); 689 break; 690 case NIC_MBOX_MSG_RSS_SIZE: 691 nic_send_rss_size(nic, vf); 692 goto unlock; 693 case NIC_MBOX_MSG_RSS_CFG: 694 case NIC_MBOX_MSG_RSS_CFG_CONT: 695 nic_config_rss(nic, &mbx.rss_cfg); 696 break; 697 case NIC_MBOX_MSG_CFG_DONE: 698 /* Last message of VF config msg sequence */ 699 nic->vf_enabled[vf] = true; 700 goto unlock; 701 case NIC_MBOX_MSG_SHUTDOWN: 702 /* First msg in VF teardown sequence */ 703 nic->vf_enabled[vf] = false; 704 if (vf >= nic->num_vf_en) 705 nic->sqs_used[vf - nic->num_vf_en] = false; 706 nic->pqs_vf[vf] = 0; 707 break; 708 case NIC_MBOX_MSG_ALLOC_SQS: 709 nic_alloc_sqs(nic, &mbx.sqs_alloc); 710 goto unlock; 711 case NIC_MBOX_MSG_NICVF_PTR: 712 nic->nicvf[vf] = mbx.nicvf.nicvf; 713 break; 714 case NIC_MBOX_MSG_PNICVF_PTR: 715 nic_send_pnicvf(nic, vf); 716 goto unlock; 717 case NIC_MBOX_MSG_SNICVF_PTR: 718 nic_send_snicvf(nic, &mbx.nicvf); 719 goto unlock; 720 case NIC_MBOX_MSG_BGX_STATS: 721 nic_get_bgx_stats(nic, &mbx.bgx_stats); 722 goto unlock; 723 case NIC_MBOX_MSG_LOOPBACK: 724 ret = nic_config_loopback(nic, &mbx.lbk); 725 break; 726 default: 727 dev_err(&nic->pdev->dev, 728 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 729 break; 730 } 731 732 if (!ret) 733 nic_mbx_send_ack(nic, vf); 734 else if (mbx.msg.msg != NIC_MBOX_MSG_READY) 735 nic_mbx_send_nack(nic, vf); 736 unlock: 737 nic->mbx_lock[vf] = false; 738 } 739 740 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx) 741 { 742 u64 intr; 743 u8 vf, vf_per_mbx_reg = 64; 744 745 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 746 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr); 747 for (vf = 0; vf < vf_per_mbx_reg; vf++) { 748 if (intr & (1ULL << vf)) { 749 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n", 750 vf + (mbx * vf_per_mbx_reg)); 751 752 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); 753 nic_clear_mbx_intr(nic, vf, mbx); 754 } 755 } 756 } 757 758 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq) 759 { 760 struct nicpf *nic = (struct nicpf *)nic_irq; 761 762 nic_mbx_intr_handler(nic, 0); 763 764 return IRQ_HANDLED; 765 } 766 767 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq) 768 { 769 struct nicpf *nic = (struct nicpf *)nic_irq; 770 771 nic_mbx_intr_handler(nic, 1); 772 773 return IRQ_HANDLED; 774 } 775 776 static int nic_enable_msix(struct nicpf *nic) 777 { 778 int i, ret; 779 780 nic->num_vec = NIC_PF_MSIX_VECTORS; 781 782 for (i = 0; i < nic->num_vec; i++) 783 nic->msix_entries[i].entry = i; 784 785 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec); 786 if (ret) { 787 dev_err(&nic->pdev->dev, 788 "Request for #%d msix vectors failed\n", 789 nic->num_vec); 790 return ret; 791 } 792 793 nic->msix_enabled = 1; 794 return 0; 795 } 796 797 static void nic_disable_msix(struct nicpf *nic) 798 { 799 if (nic->msix_enabled) { 800 pci_disable_msix(nic->pdev); 801 nic->msix_enabled = 0; 802 nic->num_vec = 0; 803 } 804 } 805 806 static void nic_free_all_interrupts(struct nicpf *nic) 807 { 808 int irq; 809 810 for (irq = 0; irq < nic->num_vec; irq++) { 811 if (nic->irq_allocated[irq]) 812 free_irq(nic->msix_entries[irq].vector, nic); 813 nic->irq_allocated[irq] = false; 814 } 815 } 816 817 static int nic_register_interrupts(struct nicpf *nic) 818 { 819 int ret; 820 821 /* Enable MSI-X */ 822 ret = nic_enable_msix(nic); 823 if (ret) 824 return ret; 825 826 /* Register mailbox interrupt handlers */ 827 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector, 828 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic); 829 if (ret) 830 goto fail; 831 832 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true; 833 834 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector, 835 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic); 836 if (ret) 837 goto fail; 838 839 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true; 840 841 /* Enable mailbox interrupt */ 842 nic_enable_mbx_intr(nic); 843 return 0; 844 845 fail: 846 dev_err(&nic->pdev->dev, "Request irq failed\n"); 847 nic_free_all_interrupts(nic); 848 return ret; 849 } 850 851 static void nic_unregister_interrupts(struct nicpf *nic) 852 { 853 nic_free_all_interrupts(nic); 854 nic_disable_msix(nic); 855 } 856 857 static int nic_num_sqs_en(struct nicpf *nic, int vf_en) 858 { 859 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE; 860 u16 total_vf; 861 862 /* Check if its a multi-node environment */ 863 if (nr_node_ids > 1) 864 sqs_per_vf = MAX_SQS_PER_VF; 865 866 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV); 867 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf); 868 return min(total_vf - vf_en, vf_en * sqs_per_vf); 869 } 870 871 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic) 872 { 873 int pos = 0; 874 int vf_en; 875 int err; 876 u16 total_vf_cnt; 877 878 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 879 if (!pos) { 880 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n"); 881 return -ENODEV; 882 } 883 884 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt); 885 if (total_vf_cnt < nic->num_vf_en) 886 nic->num_vf_en = total_vf_cnt; 887 888 if (!total_vf_cnt) 889 return 0; 890 891 vf_en = nic->num_vf_en; 892 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en); 893 vf_en += nic->num_sqs_en; 894 895 err = pci_enable_sriov(pdev, vf_en); 896 if (err) { 897 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n", 898 vf_en); 899 nic->num_vf_en = 0; 900 return err; 901 } 902 903 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n", 904 vf_en); 905 906 nic->flags |= NIC_SRIOV_ENABLED; 907 return 0; 908 } 909 910 /* Poll for BGX LMAC link status and update corresponding VF 911 * if there is a change, valid only if internal L2 switch 912 * is not present otherwise VF link is always treated as up 913 */ 914 static void nic_poll_for_link(struct work_struct *work) 915 { 916 union nic_mbx mbx = {}; 917 struct nicpf *nic; 918 struct bgx_link_status link; 919 u8 vf, bgx, lmac; 920 921 nic = container_of(work, struct nicpf, dwork.work); 922 923 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 924 925 for (vf = 0; vf < nic->num_vf_en; vf++) { 926 /* Poll only if VF is UP */ 927 if (!nic->vf_enabled[vf]) 928 continue; 929 930 /* Get BGX, LMAC indices for the VF */ 931 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 932 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 933 /* Get interface link status */ 934 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 935 936 /* Inform VF only if link status changed */ 937 if (nic->link[vf] == link.link_up) 938 continue; 939 940 if (!nic->mbx_lock[vf]) { 941 nic->link[vf] = link.link_up; 942 nic->duplex[vf] = link.duplex; 943 nic->speed[vf] = link.speed; 944 945 /* Send a mbox message to VF with current link status */ 946 mbx.link_status.link_up = link.link_up; 947 mbx.link_status.duplex = link.duplex; 948 mbx.link_status.speed = link.speed; 949 nic_send_msg_to_vf(nic, vf, &mbx); 950 } 951 } 952 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2); 953 } 954 955 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 956 { 957 struct device *dev = &pdev->dev; 958 struct nicpf *nic; 959 int err; 960 961 BUILD_BUG_ON(sizeof(union nic_mbx) > 16); 962 963 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL); 964 if (!nic) 965 return -ENOMEM; 966 967 pci_set_drvdata(pdev, nic); 968 969 nic->pdev = pdev; 970 971 err = pci_enable_device(pdev); 972 if (err) { 973 dev_err(dev, "Failed to enable PCI device\n"); 974 pci_set_drvdata(pdev, NULL); 975 return err; 976 } 977 978 err = pci_request_regions(pdev, DRV_NAME); 979 if (err) { 980 dev_err(dev, "PCI request regions failed 0x%x\n", err); 981 goto err_disable_device; 982 } 983 984 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 985 if (err) { 986 dev_err(dev, "Unable to get usable DMA configuration\n"); 987 goto err_release_regions; 988 } 989 990 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 991 if (err) { 992 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n"); 993 goto err_release_regions; 994 } 995 996 /* MAP PF's configuration registers */ 997 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 998 if (!nic->reg_base) { 999 dev_err(dev, "Cannot map config register space, aborting\n"); 1000 err = -ENOMEM; 1001 goto err_release_regions; 1002 } 1003 1004 pci_read_config_byte(pdev, PCI_REVISION_ID, &nic->rev_id); 1005 1006 nic->node = nic_get_node_id(pdev); 1007 1008 nic_set_lmac_vf_mapping(nic); 1009 1010 /* Initialize hardware */ 1011 nic_init_hw(nic); 1012 1013 /* Set RSS TBL size for each VF */ 1014 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 1015 1016 /* Register interrupts */ 1017 err = nic_register_interrupts(nic); 1018 if (err) 1019 goto err_release_regions; 1020 1021 /* Configure SRIOV */ 1022 err = nic_sriov_init(pdev, nic); 1023 if (err) 1024 goto err_unregister_interrupts; 1025 1026 /* Register a physical link status poll fn() */ 1027 nic->check_link = alloc_workqueue("check_link_status", 1028 WQ_UNBOUND | WQ_MEM_RECLAIM, 1); 1029 if (!nic->check_link) { 1030 err = -ENOMEM; 1031 goto err_disable_sriov; 1032 } 1033 1034 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link); 1035 queue_delayed_work(nic->check_link, &nic->dwork, 0); 1036 1037 return 0; 1038 1039 err_disable_sriov: 1040 if (nic->flags & NIC_SRIOV_ENABLED) 1041 pci_disable_sriov(pdev); 1042 err_unregister_interrupts: 1043 nic_unregister_interrupts(nic); 1044 err_release_regions: 1045 pci_release_regions(pdev); 1046 err_disable_device: 1047 pci_disable_device(pdev); 1048 pci_set_drvdata(pdev, NULL); 1049 return err; 1050 } 1051 1052 static void nic_remove(struct pci_dev *pdev) 1053 { 1054 struct nicpf *nic = pci_get_drvdata(pdev); 1055 1056 if (nic->flags & NIC_SRIOV_ENABLED) 1057 pci_disable_sriov(pdev); 1058 1059 if (nic->check_link) { 1060 /* Destroy work Queue */ 1061 cancel_delayed_work(&nic->dwork); 1062 flush_workqueue(nic->check_link); 1063 destroy_workqueue(nic->check_link); 1064 } 1065 1066 nic_unregister_interrupts(nic); 1067 pci_release_regions(pdev); 1068 pci_disable_device(pdev); 1069 pci_set_drvdata(pdev, NULL); 1070 } 1071 1072 static struct pci_driver nic_driver = { 1073 .name = DRV_NAME, 1074 .id_table = nic_id_table, 1075 .probe = nic_probe, 1076 .remove = nic_remove, 1077 }; 1078 1079 static int __init nic_init_module(void) 1080 { 1081 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1082 1083 return pci_register_driver(&nic_driver); 1084 } 1085 1086 static void __exit nic_cleanup_module(void) 1087 { 1088 pci_unregister_driver(&nic_driver); 1089 } 1090 1091 module_init(nic_init_module); 1092 module_exit(nic_cleanup_module); 1093