1 /*
2  * Copyright (C) 2015 Cavium, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of version 2 of the GNU General Public License
6  * as published by the Free Software Foundation.
7  */
8 
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of.h>
14 
15 #include "nic_reg.h"
16 #include "nic.h"
17 #include "q_struct.h"
18 #include "thunder_bgx.h"
19 
20 #define DRV_NAME	"thunder-nic"
21 #define DRV_VERSION	"1.0"
22 
23 struct nicpf {
24 	struct pci_dev		*pdev;
25 	u8			rev_id;
26 	u8			node;
27 	unsigned int		flags;
28 	u8			num_vf_en;      /* No of VF enabled */
29 	bool			vf_enabled[MAX_NUM_VFS_SUPPORTED];
30 	void __iomem		*reg_base;       /* Register start address */
31 	struct pkind_cfg	pkind;
32 #define	NIC_SET_VF_LMAC_MAP(bgx, lmac)	(((bgx & 0xF) << 4) | (lmac & 0xF))
33 #define	NIC_GET_BGX_FROM_VF_LMAC_MAP(map)	((map >> 4) & 0xF)
34 #define	NIC_GET_LMAC_FROM_VF_LMAC_MAP(map)	(map & 0xF)
35 	u8			vf_lmac_map[MAX_LMAC];
36 	struct delayed_work     dwork;
37 	struct workqueue_struct *check_link;
38 	u8			link[MAX_LMAC];
39 	u8			duplex[MAX_LMAC];
40 	u32			speed[MAX_LMAC];
41 	u16			cpi_base[MAX_NUM_VFS_SUPPORTED];
42 	u16			rss_ind_tbl_size;
43 	bool			mbx_lock[MAX_NUM_VFS_SUPPORTED];
44 
45 	/* MSI-X */
46 	bool			msix_enabled;
47 	u8			num_vec;
48 	struct msix_entry	msix_entries[NIC_PF_MSIX_VECTORS];
49 	bool			irq_allocated[NIC_PF_MSIX_VECTORS];
50 };
51 
52 /* Supported devices */
53 static const struct pci_device_id nic_id_table[] = {
54 	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
55 	{ 0, }  /* end of table */
56 };
57 
58 MODULE_AUTHOR("Sunil Goutham");
59 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
60 MODULE_LICENSE("GPL v2");
61 MODULE_VERSION(DRV_VERSION);
62 MODULE_DEVICE_TABLE(pci, nic_id_table);
63 
64 /* The Cavium ThunderX network controller can *only* be found in SoCs
65  * containing the ThunderX ARM64 CPU implementation.  All accesses to the device
66  * registers on this platform are implicitly strongly ordered with respect
67  * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
68  * with no memory barriers in this driver.  The readq()/writeq() functions add
69  * explicit ordering operation which in this case are redundant, and only
70  * add overhead.
71  */
72 
73 /* Register read/write APIs */
74 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
75 {
76 	writeq_relaxed(val, nic->reg_base + offset);
77 }
78 
79 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
80 {
81 	return readq_relaxed(nic->reg_base + offset);
82 }
83 
84 /* PF -> VF mailbox communication APIs */
85 static void nic_enable_mbx_intr(struct nicpf *nic)
86 {
87 	/* Enable mailbox interrupt for all 128 VFs */
88 	nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
89 	nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
90 }
91 
92 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
93 {
94 	nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
95 }
96 
97 static u64 nic_get_mbx_addr(int vf)
98 {
99 	return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
100 }
101 
102 /* Send a mailbox message to VF
103  * @vf: vf to which this message to be sent
104  * @mbx: Message to be sent
105  */
106 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
107 {
108 	void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
109 	u64 *msg = (u64 *)mbx;
110 
111 	/* In first revision HW, mbox interrupt is triggerred
112 	 * when PF writes to MBOX(1), in next revisions when
113 	 * PF writes to MBOX(0)
114 	 */
115 	if (nic->rev_id == 0) {
116 		/* see the comment for nic_reg_write()/nic_reg_read()
117 		 * functions above
118 		 */
119 		writeq_relaxed(msg[0], mbx_addr);
120 		writeq_relaxed(msg[1], mbx_addr + 8);
121 	} else {
122 		writeq_relaxed(msg[1], mbx_addr + 8);
123 		writeq_relaxed(msg[0], mbx_addr);
124 	}
125 }
126 
127 /* Responds to VF's READY message with VF's
128  * ID, node, MAC address e.t.c
129  * @vf: VF which sent READY message
130  */
131 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
132 {
133 	union nic_mbx mbx = {};
134 	int bgx_idx, lmac;
135 	const char *mac;
136 
137 	mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
138 	mbx.nic_cfg.vf_id = vf;
139 
140 	mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
141 
142 	bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
143 	lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
144 
145 	mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
146 	if (mac)
147 		ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
148 
149 	mbx.nic_cfg.node_id = nic->node;
150 	nic_send_msg_to_vf(nic, vf, &mbx);
151 }
152 
153 /* ACKs VF's mailbox message
154  * @vf: VF to which ACK to be sent
155  */
156 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
157 {
158 	union nic_mbx mbx = {};
159 
160 	mbx.msg.msg = NIC_MBOX_MSG_ACK;
161 	nic_send_msg_to_vf(nic, vf, &mbx);
162 }
163 
164 /* NACKs VF's mailbox message that PF is not able to
165  * complete the action
166  * @vf: VF to which ACK to be sent
167  */
168 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
169 {
170 	union nic_mbx mbx = {};
171 
172 	mbx.msg.msg = NIC_MBOX_MSG_NACK;
173 	nic_send_msg_to_vf(nic, vf, &mbx);
174 }
175 
176 /* Flush all in flight receive packets to memory and
177  * bring down an active RQ
178  */
179 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
180 {
181 	u16 timeout = ~0x00;
182 
183 	nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
184 	/* Wait till sync cycle is finished */
185 	while (timeout) {
186 		if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
187 			break;
188 		timeout--;
189 	}
190 	nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
191 	if (!timeout) {
192 		dev_err(&nic->pdev->dev, "Receive queue software sync failed");
193 		return 1;
194 	}
195 	return 0;
196 }
197 
198 /* Get BGX Rx/Tx stats and respond to VF's request */
199 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
200 {
201 	int bgx_idx, lmac;
202 	union nic_mbx mbx = {};
203 
204 	bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
205 	lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
206 
207 	mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
208 	mbx.bgx_stats.vf_id = bgx->vf_id;
209 	mbx.bgx_stats.rx = bgx->rx;
210 	mbx.bgx_stats.idx = bgx->idx;
211 	if (bgx->rx)
212 		mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
213 							    lmac, bgx->idx);
214 	else
215 		mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
216 							    lmac, bgx->idx);
217 	nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
218 }
219 
220 /* Update hardware min/max frame size */
221 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
222 {
223 	if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
224 		dev_err(&nic->pdev->dev,
225 			"Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
226 			   vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
227 		return 1;
228 	}
229 	new_frs += ETH_HLEN;
230 	if (new_frs <= nic->pkind.maxlen)
231 		return 0;
232 
233 	nic->pkind.maxlen = new_frs;
234 	nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
235 	return 0;
236 }
237 
238 /* Set minimum transmit packet size */
239 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
240 {
241 	int lmac;
242 	u64 lmac_cfg;
243 
244 	/* Max value that can be set is 60 */
245 	if (size > 60)
246 		size = 60;
247 
248 	for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
249 		lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
250 		lmac_cfg &= ~(0xF << 2);
251 		lmac_cfg |= ((size / 4) << 2);
252 		nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
253 	}
254 }
255 
256 /* Function to check number of LMACs present and set VF::LMAC mapping.
257  * Mapping will be used while initializing channels.
258  */
259 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
260 {
261 	unsigned bgx_map = bgx_get_map(nic->node);
262 	int bgx, next_bgx_lmac = 0;
263 	int lmac, lmac_cnt = 0;
264 	u64 lmac_credit;
265 
266 	nic->num_vf_en = 0;
267 
268 	for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
269 		if (!(bgx_map & (1 << bgx)))
270 			continue;
271 		lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
272 		for (lmac = 0; lmac < lmac_cnt; lmac++)
273 			nic->vf_lmac_map[next_bgx_lmac++] =
274 						NIC_SET_VF_LMAC_MAP(bgx, lmac);
275 		nic->num_vf_en += lmac_cnt;
276 
277 		/* Program LMAC credits */
278 		lmac_credit = (1ull << 1); /* channel credit enable */
279 		lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
280 		/* 48KB BGX Tx buffer size, each unit is of size 16bytes */
281 		lmac_credit |= (((((48 * 1024) / lmac_cnt) -
282 				NIC_HW_MAX_FRS) / 16) << 12);
283 		lmac = bgx * MAX_LMAC_PER_BGX;
284 		for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
285 			nic_reg_write(nic,
286 				      NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
287 				      lmac_credit);
288 	}
289 }
290 
291 #define BGX0_BLOCK 8
292 #define BGX1_BLOCK 9
293 
294 static void nic_init_hw(struct nicpf *nic)
295 {
296 	int i;
297 
298 	/* Reset NIC, in case the driver is repeatedly inserted and removed */
299 	nic_reg_write(nic, NIC_PF_SOFT_RESET, 1);
300 
301 	/* Enable NIC HW block */
302 	nic_reg_write(nic, NIC_PF_CFG, 0x3);
303 
304 	/* Enable backpressure */
305 	nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
306 
307 	/* Disable TNS mode on both interfaces */
308 	nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
309 		      (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
310 	nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
311 		      (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
312 	nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
313 		      (1ULL << 63) | BGX0_BLOCK);
314 	nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
315 		      (1ULL << 63) | BGX1_BLOCK);
316 
317 	/* PKIND configuration */
318 	nic->pkind.minlen = 0;
319 	nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
320 	nic->pkind.lenerr_en = 1;
321 	nic->pkind.rx_hdr = 0;
322 	nic->pkind.hdr_sl = 0;
323 
324 	for (i = 0; i < NIC_MAX_PKIND; i++)
325 		nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
326 			      *(u64 *)&nic->pkind);
327 
328 	nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
329 
330 	/* Timer config */
331 	nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
332 }
333 
334 /* Channel parse index configuration */
335 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
336 {
337 	u32 vnic, bgx, lmac, chan;
338 	u32 padd, cpi_count = 0;
339 	u64 cpi_base, cpi, rssi_base, rssi;
340 	u8  qset, rq_idx = 0;
341 
342 	vnic = cfg->vf_id;
343 	bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
344 	lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
345 
346 	chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
347 	cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
348 	rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
349 
350 	/* Rx channel configuration */
351 	nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
352 		      (1ull << 63) | (vnic << 0));
353 	nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
354 		      ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
355 
356 	if (cfg->cpi_alg == CPI_ALG_NONE)
357 		cpi_count = 1;
358 	else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
359 		cpi_count = 8;
360 	else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
361 		cpi_count = 16;
362 	else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
363 		cpi_count = NIC_MAX_CPI_PER_LMAC;
364 
365 	/* RSS Qset, Qidx mapping */
366 	qset = cfg->vf_id;
367 	rssi = rssi_base;
368 	for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
369 		nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
370 			      (qset << 3) | rq_idx);
371 		rq_idx++;
372 	}
373 
374 	rssi = 0;
375 	cpi = cpi_base;
376 	for (; cpi < (cpi_base + cpi_count); cpi++) {
377 		/* Determine port to channel adder */
378 		if (cfg->cpi_alg != CPI_ALG_DIFF)
379 			padd = cpi % cpi_count;
380 		else
381 			padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
382 
383 		/* Leave RSS_SIZE as '0' to disable RSS */
384 		nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
385 			      (vnic << 24) | (padd << 16) | (rssi_base + rssi));
386 
387 		if ((rssi + 1) >= cfg->rq_cnt)
388 			continue;
389 
390 		if (cfg->cpi_alg == CPI_ALG_VLAN)
391 			rssi++;
392 		else if (cfg->cpi_alg == CPI_ALG_VLAN16)
393 			rssi = ((cpi - cpi_base) & 0xe) >> 1;
394 		else if (cfg->cpi_alg == CPI_ALG_DIFF)
395 			rssi = ((cpi - cpi_base) & 0x38) >> 3;
396 	}
397 	nic->cpi_base[cfg->vf_id] = cpi_base;
398 }
399 
400 /* Responsds to VF with its RSS indirection table size */
401 static void nic_send_rss_size(struct nicpf *nic, int vf)
402 {
403 	union nic_mbx mbx = {};
404 	u64  *msg;
405 
406 	msg = (u64 *)&mbx;
407 
408 	mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
409 	mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
410 	nic_send_msg_to_vf(nic, vf, &mbx);
411 }
412 
413 /* Receive side scaling configuration
414  * configure:
415  * - RSS index
416  * - indir table i.e hash::RQ mapping
417  * - no of hash bits to consider
418  */
419 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
420 {
421 	u8  qset, idx = 0;
422 	u64 cpi_cfg, cpi_base, rssi_base, rssi;
423 
424 	cpi_base = nic->cpi_base[cfg->vf_id];
425 	cpi_cfg = nic_reg_read(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3));
426 	rssi_base = (cpi_cfg & 0x0FFF) + cfg->tbl_offset;
427 
428 	rssi = rssi_base;
429 	qset = cfg->vf_id;
430 
431 	for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
432 		nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
433 			      (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
434 		idx++;
435 	}
436 
437 	cpi_cfg &= ~(0xFULL << 20);
438 	cpi_cfg |= (cfg->hash_bits << 20);
439 	nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3), cpi_cfg);
440 }
441 
442 /* 4 level transmit side scheduler configutation
443  * for TNS bypass mode
444  *
445  * Sample configuration for SQ0
446  * VNIC0-SQ0 -> TL4(0)   -> TL3[0]   -> TL2[0]  -> TL1[0] -> BGX0
447  * VNIC1-SQ0 -> TL4(8)   -> TL3[2]   -> TL2[0]  -> TL1[0] -> BGX0
448  * VNIC2-SQ0 -> TL4(16)  -> TL3[4]   -> TL2[1]  -> TL1[0] -> BGX0
449  * VNIC3-SQ0 -> TL4(24)  -> TL3[6]   -> TL2[1]  -> TL1[0] -> BGX0
450  * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
451  * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
452  * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
453  * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
454  */
455 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic, u8 sq_idx)
456 {
457 	u32 bgx, lmac, chan;
458 	u32 tl2, tl3, tl4;
459 	u32 rr_quantum;
460 
461 	bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
462 	lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
463 	/* 24 bytes for FCS, IPG and preamble */
464 	rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
465 
466 	tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
467 	tl4 += sq_idx;
468 	tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
469 	nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
470 		      ((u64)vnic << NIC_QS_ID_SHIFT) |
471 		      ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
472 	nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
473 		      ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
474 
475 	nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
476 	chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
477 	nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
478 	/* Enable backpressure on the channel */
479 	nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
480 
481 	tl2 = tl3 >> 2;
482 	nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
483 	nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
484 	/* No priorities as of now */
485 	nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
486 }
487 
488 /* Interrupt handler to handle mailbox messages from VFs */
489 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
490 {
491 	union nic_mbx mbx = {};
492 	u64 *mbx_data;
493 	u64 mbx_addr;
494 	u64 reg_addr;
495 	int bgx, lmac;
496 	int i;
497 	int ret = 0;
498 
499 	nic->mbx_lock[vf] = true;
500 
501 	mbx_addr = nic_get_mbx_addr(vf);
502 	mbx_data = (u64 *)&mbx;
503 
504 	for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
505 		*mbx_data = nic_reg_read(nic, mbx_addr);
506 		mbx_data++;
507 		mbx_addr += sizeof(u64);
508 	}
509 
510 	dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
511 		__func__, mbx.msg.msg, vf);
512 	switch (mbx.msg.msg) {
513 	case NIC_MBOX_MSG_READY:
514 		nic_mbx_send_ready(nic, vf);
515 		nic->link[vf] = 0;
516 		nic->duplex[vf] = 0;
517 		nic->speed[vf] = 0;
518 		ret = 1;
519 		break;
520 	case NIC_MBOX_MSG_QS_CFG:
521 		reg_addr = NIC_PF_QSET_0_127_CFG |
522 			   (mbx.qs.num << NIC_QS_ID_SHIFT);
523 		nic_reg_write(nic, reg_addr, mbx.qs.cfg);
524 		break;
525 	case NIC_MBOX_MSG_RQ_CFG:
526 		reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
527 			   (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
528 			   (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
529 		nic_reg_write(nic, reg_addr, mbx.rq.cfg);
530 		break;
531 	case NIC_MBOX_MSG_RQ_BP_CFG:
532 		reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
533 			   (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
534 			   (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
535 		nic_reg_write(nic, reg_addr, mbx.rq.cfg);
536 		break;
537 	case NIC_MBOX_MSG_RQ_SW_SYNC:
538 		ret = nic_rcv_queue_sw_sync(nic);
539 		break;
540 	case NIC_MBOX_MSG_RQ_DROP_CFG:
541 		reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
542 			   (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
543 			   (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
544 		nic_reg_write(nic, reg_addr, mbx.rq.cfg);
545 		break;
546 	case NIC_MBOX_MSG_SQ_CFG:
547 		reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
548 			   (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
549 			   (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
550 		nic_reg_write(nic, reg_addr, mbx.sq.cfg);
551 		nic_tx_channel_cfg(nic, mbx.qs.num, mbx.sq.sq_num);
552 		break;
553 	case NIC_MBOX_MSG_SET_MAC:
554 		lmac = mbx.mac.vf_id;
555 		bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
556 		lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
557 		bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
558 		break;
559 	case NIC_MBOX_MSG_SET_MAX_FRS:
560 		ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
561 					mbx.frs.vf_id);
562 		break;
563 	case NIC_MBOX_MSG_CPI_CFG:
564 		nic_config_cpi(nic, &mbx.cpi_cfg);
565 		break;
566 	case NIC_MBOX_MSG_RSS_SIZE:
567 		nic_send_rss_size(nic, vf);
568 		goto unlock;
569 	case NIC_MBOX_MSG_RSS_CFG:
570 	case NIC_MBOX_MSG_RSS_CFG_CONT:
571 		nic_config_rss(nic, &mbx.rss_cfg);
572 		break;
573 	case NIC_MBOX_MSG_CFG_DONE:
574 		/* Last message of VF config msg sequence */
575 		nic->vf_enabled[vf] = true;
576 		goto unlock;
577 	case NIC_MBOX_MSG_SHUTDOWN:
578 		/* First msg in VF teardown sequence */
579 		nic->vf_enabled[vf] = false;
580 		break;
581 	case NIC_MBOX_MSG_BGX_STATS:
582 		nic_get_bgx_stats(nic, &mbx.bgx_stats);
583 		goto unlock;
584 	default:
585 		dev_err(&nic->pdev->dev,
586 			"Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
587 		break;
588 	}
589 
590 	if (!ret)
591 		nic_mbx_send_ack(nic, vf);
592 	else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
593 		nic_mbx_send_nack(nic, vf);
594 unlock:
595 	nic->mbx_lock[vf] = false;
596 }
597 
598 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
599 {
600 	u64 intr;
601 	u8  vf, vf_per_mbx_reg = 64;
602 
603 	intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
604 	dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
605 	for (vf = 0; vf < vf_per_mbx_reg; vf++) {
606 		if (intr & (1ULL << vf)) {
607 			dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
608 				vf + (mbx * vf_per_mbx_reg));
609 			if ((vf + (mbx * vf_per_mbx_reg)) > nic->num_vf_en)
610 				break;
611 			nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
612 			nic_clear_mbx_intr(nic, vf, mbx);
613 		}
614 	}
615 }
616 
617 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
618 {
619 	struct nicpf *nic = (struct nicpf *)nic_irq;
620 
621 	nic_mbx_intr_handler(nic, 0);
622 
623 	return IRQ_HANDLED;
624 }
625 
626 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
627 {
628 	struct nicpf *nic = (struct nicpf *)nic_irq;
629 
630 	nic_mbx_intr_handler(nic, 1);
631 
632 	return IRQ_HANDLED;
633 }
634 
635 static int nic_enable_msix(struct nicpf *nic)
636 {
637 	int i, ret;
638 
639 	nic->num_vec = NIC_PF_MSIX_VECTORS;
640 
641 	for (i = 0; i < nic->num_vec; i++)
642 		nic->msix_entries[i].entry = i;
643 
644 	ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
645 	if (ret) {
646 		dev_err(&nic->pdev->dev,
647 			"Request for #%d msix vectors failed\n",
648 			   nic->num_vec);
649 		return ret;
650 	}
651 
652 	nic->msix_enabled = 1;
653 	return 0;
654 }
655 
656 static void nic_disable_msix(struct nicpf *nic)
657 {
658 	if (nic->msix_enabled) {
659 		pci_disable_msix(nic->pdev);
660 		nic->msix_enabled = 0;
661 		nic->num_vec = 0;
662 	}
663 }
664 
665 static void nic_free_all_interrupts(struct nicpf *nic)
666 {
667 	int irq;
668 
669 	for (irq = 0; irq < nic->num_vec; irq++) {
670 		if (nic->irq_allocated[irq])
671 			free_irq(nic->msix_entries[irq].vector, nic);
672 		nic->irq_allocated[irq] = false;
673 	}
674 }
675 
676 static int nic_register_interrupts(struct nicpf *nic)
677 {
678 	int ret;
679 
680 	/* Enable MSI-X */
681 	ret = nic_enable_msix(nic);
682 	if (ret)
683 		return ret;
684 
685 	/* Register mailbox interrupt handlers */
686 	ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
687 			  nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
688 	if (ret)
689 		goto fail;
690 
691 	nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
692 
693 	ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
694 			  nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
695 	if (ret)
696 		goto fail;
697 
698 	nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
699 
700 	/* Enable mailbox interrupt */
701 	nic_enable_mbx_intr(nic);
702 	return 0;
703 
704 fail:
705 	dev_err(&nic->pdev->dev, "Request irq failed\n");
706 	nic_free_all_interrupts(nic);
707 	return ret;
708 }
709 
710 static void nic_unregister_interrupts(struct nicpf *nic)
711 {
712 	nic_free_all_interrupts(nic);
713 	nic_disable_msix(nic);
714 }
715 
716 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
717 {
718 	int pos = 0;
719 	int err;
720 	u16 total_vf_cnt;
721 
722 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
723 	if (!pos) {
724 		dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
725 		return -ENODEV;
726 	}
727 
728 	pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
729 	if (total_vf_cnt < nic->num_vf_en)
730 		nic->num_vf_en = total_vf_cnt;
731 
732 	if (!total_vf_cnt)
733 		return 0;
734 
735 	err = pci_enable_sriov(pdev, nic->num_vf_en);
736 	if (err) {
737 		dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
738 			nic->num_vf_en);
739 		nic->num_vf_en = 0;
740 		return err;
741 	}
742 
743 	dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
744 		 nic->num_vf_en);
745 
746 	nic->flags |= NIC_SRIOV_ENABLED;
747 	return 0;
748 }
749 
750 /* Poll for BGX LMAC link status and update corresponding VF
751  * if there is a change, valid only if internal L2 switch
752  * is not present otherwise VF link is always treated as up
753  */
754 static void nic_poll_for_link(struct work_struct *work)
755 {
756 	union nic_mbx mbx = {};
757 	struct nicpf *nic;
758 	struct bgx_link_status link;
759 	u8 vf, bgx, lmac;
760 
761 	nic = container_of(work, struct nicpf, dwork.work);
762 
763 	mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
764 
765 	for (vf = 0; vf < nic->num_vf_en; vf++) {
766 		/* Poll only if VF is UP */
767 		if (!nic->vf_enabled[vf])
768 			continue;
769 
770 		/* Get BGX, LMAC indices for the VF */
771 		bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
772 		lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
773 		/* Get interface link status */
774 		bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
775 
776 		/* Inform VF only if link status changed */
777 		if (nic->link[vf] == link.link_up)
778 			continue;
779 
780 		if (!nic->mbx_lock[vf]) {
781 			nic->link[vf] = link.link_up;
782 			nic->duplex[vf] = link.duplex;
783 			nic->speed[vf] = link.speed;
784 
785 			/* Send a mbox message to VF with current link status */
786 			mbx.link_status.link_up = link.link_up;
787 			mbx.link_status.duplex = link.duplex;
788 			mbx.link_status.speed = link.speed;
789 			nic_send_msg_to_vf(nic, vf, &mbx);
790 		}
791 	}
792 	queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
793 }
794 
795 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
796 {
797 	struct device *dev = &pdev->dev;
798 	struct nicpf *nic;
799 	int    err;
800 
801 	BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
802 
803 	nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
804 	if (!nic)
805 		return -ENOMEM;
806 
807 	pci_set_drvdata(pdev, nic);
808 
809 	nic->pdev = pdev;
810 
811 	err = pci_enable_device(pdev);
812 	if (err) {
813 		dev_err(dev, "Failed to enable PCI device\n");
814 		pci_set_drvdata(pdev, NULL);
815 		return err;
816 	}
817 
818 	err = pci_request_regions(pdev, DRV_NAME);
819 	if (err) {
820 		dev_err(dev, "PCI request regions failed 0x%x\n", err);
821 		goto err_disable_device;
822 	}
823 
824 	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
825 	if (err) {
826 		dev_err(dev, "Unable to get usable DMA configuration\n");
827 		goto err_release_regions;
828 	}
829 
830 	err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
831 	if (err) {
832 		dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
833 		goto err_release_regions;
834 	}
835 
836 	/* MAP PF's configuration registers */
837 	nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
838 	if (!nic->reg_base) {
839 		dev_err(dev, "Cannot map config register space, aborting\n");
840 		err = -ENOMEM;
841 		goto err_release_regions;
842 	}
843 
844 	pci_read_config_byte(pdev, PCI_REVISION_ID, &nic->rev_id);
845 
846 	nic->node = nic_get_node_id(pdev);
847 
848 	nic_set_lmac_vf_mapping(nic);
849 
850 	/* Initialize hardware */
851 	nic_init_hw(nic);
852 
853 	/* Set RSS TBL size for each VF */
854 	nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
855 
856 	/* Register interrupts */
857 	err = nic_register_interrupts(nic);
858 	if (err)
859 		goto err_release_regions;
860 
861 	/* Configure SRIOV */
862 	err = nic_sriov_init(pdev, nic);
863 	if (err)
864 		goto err_unregister_interrupts;
865 
866 	/* Register a physical link status poll fn() */
867 	nic->check_link = alloc_workqueue("check_link_status",
868 					  WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
869 	if (!nic->check_link) {
870 		err = -ENOMEM;
871 		goto err_disable_sriov;
872 	}
873 
874 	INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
875 	queue_delayed_work(nic->check_link, &nic->dwork, 0);
876 
877 	return 0;
878 
879 err_disable_sriov:
880 	if (nic->flags & NIC_SRIOV_ENABLED)
881 		pci_disable_sriov(pdev);
882 err_unregister_interrupts:
883 	nic_unregister_interrupts(nic);
884 err_release_regions:
885 	pci_release_regions(pdev);
886 err_disable_device:
887 	pci_disable_device(pdev);
888 	pci_set_drvdata(pdev, NULL);
889 	return err;
890 }
891 
892 static void nic_remove(struct pci_dev *pdev)
893 {
894 	struct nicpf *nic = pci_get_drvdata(pdev);
895 
896 	if (nic->flags & NIC_SRIOV_ENABLED)
897 		pci_disable_sriov(pdev);
898 
899 	if (nic->check_link) {
900 		/* Destroy work Queue */
901 		cancel_delayed_work(&nic->dwork);
902 		flush_workqueue(nic->check_link);
903 		destroy_workqueue(nic->check_link);
904 	}
905 
906 	nic_unregister_interrupts(nic);
907 	pci_release_regions(pdev);
908 	pci_disable_device(pdev);
909 	pci_set_drvdata(pdev, NULL);
910 }
911 
912 static struct pci_driver nic_driver = {
913 	.name = DRV_NAME,
914 	.id_table = nic_id_table,
915 	.probe = nic_probe,
916 	.remove = nic_remove,
917 };
918 
919 static int __init nic_init_module(void)
920 {
921 	pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
922 
923 	return pci_register_driver(&nic_driver);
924 }
925 
926 static void __exit nic_cleanup_module(void)
927 {
928 	pci_unregister_driver(&nic_driver);
929 }
930 
931 module_init(nic_init_module);
932 module_exit(nic_cleanup_module);
933