1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/etherdevice.h> 13 #include <linux/of.h> 14 #include <linux/if_vlan.h> 15 16 #include "nic_reg.h" 17 #include "nic.h" 18 #include "q_struct.h" 19 #include "thunder_bgx.h" 20 21 #define DRV_NAME "nicpf" 22 #define DRV_VERSION "1.0" 23 24 #define NIC_VF_PER_MBX_REG 64 25 26 struct hw_info { 27 u8 bgx_cnt; 28 u8 chans_per_lmac; 29 u8 chans_per_bgx; /* Rx/Tx chans */ 30 u8 chans_per_rgx; 31 u8 chans_per_lbk; 32 u16 cpi_cnt; 33 u16 rssi_cnt; 34 u16 rss_ind_tbl_size; 35 u16 tl4_cnt; 36 u16 tl3_cnt; 37 u8 tl2_cnt; 38 u8 tl1_cnt; 39 bool tl1_per_bgx; /* TL1 per BGX or per LMAC */ 40 }; 41 42 struct nicpf { 43 struct pci_dev *pdev; 44 struct hw_info *hw; 45 u8 node; 46 unsigned int flags; 47 u8 num_vf_en; /* No of VF enabled */ 48 bool vf_enabled[MAX_NUM_VFS_SUPPORTED]; 49 void __iomem *reg_base; /* Register start address */ 50 u8 num_sqs_en; /* Secondary qsets enabled */ 51 u64 nicvf[MAX_NUM_VFS_SUPPORTED]; 52 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF]; 53 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED]; 54 bool sqs_used[MAX_NUM_VFS_SUPPORTED]; 55 struct pkind_cfg pkind; 56 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF)) 57 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF) 58 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF) 59 u8 *vf_lmac_map; 60 struct delayed_work dwork; 61 struct workqueue_struct *check_link; 62 u8 *link; 63 u8 *duplex; 64 u32 *speed; 65 u16 cpi_base[MAX_NUM_VFS_SUPPORTED]; 66 u16 rssi_base[MAX_NUM_VFS_SUPPORTED]; 67 bool mbx_lock[MAX_NUM_VFS_SUPPORTED]; 68 69 /* MSI-X */ 70 u8 num_vec; 71 bool irq_allocated[NIC_PF_MSIX_VECTORS]; 72 char irq_name[NIC_PF_MSIX_VECTORS][20]; 73 }; 74 75 /* Supported devices */ 76 static const struct pci_device_id nic_id_table[] = { 77 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) }, 78 { 0, } /* end of table */ 79 }; 80 81 MODULE_AUTHOR("Sunil Goutham"); 82 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver"); 83 MODULE_LICENSE("GPL v2"); 84 MODULE_VERSION(DRV_VERSION); 85 MODULE_DEVICE_TABLE(pci, nic_id_table); 86 87 /* The Cavium ThunderX network controller can *only* be found in SoCs 88 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 89 * registers on this platform are implicitly strongly ordered with respect 90 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 91 * with no memory barriers in this driver. The readq()/writeq() functions add 92 * explicit ordering operation which in this case are redundant, and only 93 * add overhead. 94 */ 95 96 /* Register read/write APIs */ 97 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val) 98 { 99 writeq_relaxed(val, nic->reg_base + offset); 100 } 101 102 static u64 nic_reg_read(struct nicpf *nic, u64 offset) 103 { 104 return readq_relaxed(nic->reg_base + offset); 105 } 106 107 /* PF -> VF mailbox communication APIs */ 108 static void nic_enable_mbx_intr(struct nicpf *nic) 109 { 110 int vf_cnt = pci_sriov_get_totalvfs(nic->pdev); 111 112 #define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull)) 113 114 /* Clear it, to avoid spurious interrupts (if any) */ 115 nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt)); 116 117 /* Enable mailbox interrupt for all VFs */ 118 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt)); 119 /* One mailbox intr enable reg per 64 VFs */ 120 if (vf_cnt > 64) { 121 nic_reg_write(nic, NIC_PF_MAILBOX_INT + sizeof(u64), 122 INTR_MASK(vf_cnt - 64)); 123 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), 124 INTR_MASK(vf_cnt - 64)); 125 } 126 } 127 128 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 129 { 130 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf)); 131 } 132 133 static u64 nic_get_mbx_addr(int vf) 134 { 135 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT); 136 } 137 138 /* Send a mailbox message to VF 139 * @vf: vf to which this message to be sent 140 * @mbx: Message to be sent 141 */ 142 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 143 { 144 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf); 145 u64 *msg = (u64 *)mbx; 146 147 /* In first revision HW, mbox interrupt is triggerred 148 * when PF writes to MBOX(1), in next revisions when 149 * PF writes to MBOX(0) 150 */ 151 if (pass1_silicon(nic->pdev)) { 152 /* see the comment for nic_reg_write()/nic_reg_read() 153 * functions above 154 */ 155 writeq_relaxed(msg[0], mbx_addr); 156 writeq_relaxed(msg[1], mbx_addr + 8); 157 } else { 158 writeq_relaxed(msg[1], mbx_addr + 8); 159 writeq_relaxed(msg[0], mbx_addr); 160 } 161 } 162 163 /* Responds to VF's READY message with VF's 164 * ID, node, MAC address e.t.c 165 * @vf: VF which sent READY message 166 */ 167 static void nic_mbx_send_ready(struct nicpf *nic, int vf) 168 { 169 union nic_mbx mbx = {}; 170 int bgx_idx, lmac; 171 const char *mac; 172 173 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 174 mbx.nic_cfg.vf_id = vf; 175 176 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 177 178 if (vf < nic->num_vf_en) { 179 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 180 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 181 182 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 183 if (mac) 184 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac); 185 } 186 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false; 187 mbx.nic_cfg.node_id = nic->node; 188 189 mbx.nic_cfg.loopback_supported = vf < nic->num_vf_en; 190 191 nic_send_msg_to_vf(nic, vf, &mbx); 192 } 193 194 /* ACKs VF's mailbox message 195 * @vf: VF to which ACK to be sent 196 */ 197 static void nic_mbx_send_ack(struct nicpf *nic, int vf) 198 { 199 union nic_mbx mbx = {}; 200 201 mbx.msg.msg = NIC_MBOX_MSG_ACK; 202 nic_send_msg_to_vf(nic, vf, &mbx); 203 } 204 205 /* NACKs VF's mailbox message that PF is not able to 206 * complete the action 207 * @vf: VF to which ACK to be sent 208 */ 209 static void nic_mbx_send_nack(struct nicpf *nic, int vf) 210 { 211 union nic_mbx mbx = {}; 212 213 mbx.msg.msg = NIC_MBOX_MSG_NACK; 214 nic_send_msg_to_vf(nic, vf, &mbx); 215 } 216 217 /* Flush all in flight receive packets to memory and 218 * bring down an active RQ 219 */ 220 static int nic_rcv_queue_sw_sync(struct nicpf *nic) 221 { 222 u16 timeout = ~0x00; 223 224 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 225 /* Wait till sync cycle is finished */ 226 while (timeout) { 227 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 228 break; 229 timeout--; 230 } 231 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 232 if (!timeout) { 233 dev_err(&nic->pdev->dev, "Receive queue software sync failed"); 234 return 1; 235 } 236 return 0; 237 } 238 239 /* Get BGX Rx/Tx stats and respond to VF's request */ 240 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 241 { 242 int bgx_idx, lmac; 243 union nic_mbx mbx = {}; 244 245 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 246 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 247 248 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 249 mbx.bgx_stats.vf_id = bgx->vf_id; 250 mbx.bgx_stats.rx = bgx->rx; 251 mbx.bgx_stats.idx = bgx->idx; 252 if (bgx->rx) 253 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx, 254 lmac, bgx->idx); 255 else 256 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx, 257 lmac, bgx->idx); 258 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 259 } 260 261 /* Update hardware min/max frame size */ 262 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 263 { 264 int bgx, lmac, lmac_cnt; 265 u64 lmac_credits; 266 267 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) 268 return 1; 269 270 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 271 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 272 lmac += bgx * MAX_LMAC_PER_BGX; 273 274 new_frs += VLAN_ETH_HLEN + ETH_FCS_LEN + 4; 275 276 /* Update corresponding LMAC credits */ 277 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 278 lmac_credits = nic_reg_read(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8)); 279 lmac_credits &= ~(0xFFFFFULL << 12); 280 lmac_credits |= (((((48 * 1024) / lmac_cnt) - new_frs) / 16) << 12); 281 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credits); 282 283 /* Enforce MTU in HW 284 * This config is supported only from 88xx pass 2.0 onwards. 285 */ 286 if (!pass1_silicon(nic->pdev)) 287 nic_reg_write(nic, 288 NIC_PF_LMAC_0_7_CFG2 + (lmac * 8), new_frs); 289 return 0; 290 } 291 292 /* Set minimum transmit packet size */ 293 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size) 294 { 295 int lmac, max_lmac; 296 u16 sdevid; 297 u64 lmac_cfg; 298 299 /* There is a issue in HW where-in while sending GSO sized 300 * pkts as part of TSO, if pkt len falls below this size 301 * NIC will zero PAD packet and also updates IP total length. 302 * Hence set this value to lessthan min pkt size of MAC+IP+TCP 303 * headers, BGX will do the padding to transmit 64 byte pkt. 304 */ 305 if (size > 52) 306 size = 52; 307 308 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 309 /* 81xx's RGX has only one LMAC */ 310 if (sdevid == PCI_SUBSYS_DEVID_81XX_NIC_PF) 311 max_lmac = ((nic->hw->bgx_cnt - 1) * MAX_LMAC_PER_BGX) + 1; 312 else 313 max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX; 314 315 for (lmac = 0; lmac < max_lmac; lmac++) { 316 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 317 lmac_cfg &= ~(0xF << 2); 318 lmac_cfg |= ((size / 4) << 2); 319 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 320 } 321 } 322 323 /* Function to check number of LMACs present and set VF::LMAC mapping. 324 * Mapping will be used while initializing channels. 325 */ 326 static void nic_set_lmac_vf_mapping(struct nicpf *nic) 327 { 328 unsigned bgx_map = bgx_get_map(nic->node); 329 int bgx, next_bgx_lmac = 0; 330 int lmac, lmac_cnt = 0; 331 u64 lmac_credit; 332 333 nic->num_vf_en = 0; 334 335 for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) { 336 if (!(bgx_map & (1 << bgx))) 337 continue; 338 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 339 for (lmac = 0; lmac < lmac_cnt; lmac++) 340 nic->vf_lmac_map[next_bgx_lmac++] = 341 NIC_SET_VF_LMAC_MAP(bgx, lmac); 342 nic->num_vf_en += lmac_cnt; 343 344 /* Program LMAC credits */ 345 lmac_credit = (1ull << 1); /* channel credit enable */ 346 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 347 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 348 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 349 NIC_HW_MAX_FRS) / 16) << 12); 350 lmac = bgx * MAX_LMAC_PER_BGX; 351 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) 352 nic_reg_write(nic, 353 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 354 lmac_credit); 355 356 /* On CN81XX there are only 8 VFs but max possible no of 357 * interfaces are 9. 358 */ 359 if (nic->num_vf_en >= pci_sriov_get_totalvfs(nic->pdev)) { 360 nic->num_vf_en = pci_sriov_get_totalvfs(nic->pdev); 361 break; 362 } 363 } 364 } 365 366 static void nic_get_hw_info(struct nicpf *nic) 367 { 368 u16 sdevid; 369 struct hw_info *hw = nic->hw; 370 371 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 372 373 switch (sdevid) { 374 case PCI_SUBSYS_DEVID_88XX_NIC_PF: 375 hw->bgx_cnt = MAX_BGX_PER_CN88XX; 376 hw->chans_per_lmac = 16; 377 hw->chans_per_bgx = 128; 378 hw->cpi_cnt = 2048; 379 hw->rssi_cnt = 4096; 380 hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 381 hw->tl3_cnt = 256; 382 hw->tl2_cnt = 64; 383 hw->tl1_cnt = 2; 384 hw->tl1_per_bgx = true; 385 break; 386 case PCI_SUBSYS_DEVID_81XX_NIC_PF: 387 hw->bgx_cnt = MAX_BGX_PER_CN81XX; 388 hw->chans_per_lmac = 8; 389 hw->chans_per_bgx = 32; 390 hw->chans_per_rgx = 8; 391 hw->chans_per_lbk = 24; 392 hw->cpi_cnt = 512; 393 hw->rssi_cnt = 256; 394 hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */ 395 hw->tl3_cnt = 64; 396 hw->tl2_cnt = 16; 397 hw->tl1_cnt = 10; 398 hw->tl1_per_bgx = false; 399 break; 400 case PCI_SUBSYS_DEVID_83XX_NIC_PF: 401 hw->bgx_cnt = MAX_BGX_PER_CN83XX; 402 hw->chans_per_lmac = 8; 403 hw->chans_per_bgx = 32; 404 hw->chans_per_lbk = 64; 405 hw->cpi_cnt = 2048; 406 hw->rssi_cnt = 1024; 407 hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */ 408 hw->tl3_cnt = 256; 409 hw->tl2_cnt = 64; 410 hw->tl1_cnt = 18; 411 hw->tl1_per_bgx = false; 412 break; 413 } 414 hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev); 415 } 416 417 #define BGX0_BLOCK 8 418 #define BGX1_BLOCK 9 419 420 static void nic_init_hw(struct nicpf *nic) 421 { 422 int i; 423 u64 cqm_cfg; 424 425 /* Enable NIC HW block */ 426 nic_reg_write(nic, NIC_PF_CFG, 0x3); 427 428 /* Enable backpressure */ 429 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03); 430 431 /* TNS and TNS bypass modes are present only on 88xx 432 * Also offset of this CSR has changed in 81xx and 83xx. 433 */ 434 if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) { 435 /* Disable TNS mode on both interfaces */ 436 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 437 (NIC_TNS_BYPASS_MODE << 7) | 438 BGX0_BLOCK | (1ULL << 16)); 439 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 440 (NIC_TNS_BYPASS_MODE << 7) | 441 BGX1_BLOCK | (1ULL << 16)); 442 } else { 443 /* Configure timestamp generation timeout to 10us */ 444 for (i = 0; i < nic->hw->bgx_cnt; i++) 445 nic_reg_write(nic, NIC_PF_INTFX_SEND_CFG | (i << 3), 446 (1ULL << 16)); 447 } 448 449 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 450 (1ULL << 63) | BGX0_BLOCK); 451 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 452 (1ULL << 63) | BGX1_BLOCK); 453 454 /* PKIND configuration */ 455 nic->pkind.minlen = 0; 456 nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4; 457 nic->pkind.lenerr_en = 1; 458 nic->pkind.rx_hdr = 0; 459 nic->pkind.hdr_sl = 0; 460 461 for (i = 0; i < NIC_MAX_PKIND; i++) 462 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 463 *(u64 *)&nic->pkind); 464 465 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 466 467 /* Timer config */ 468 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 469 470 /* Enable VLAN ethertype matching and stripping */ 471 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 472 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q); 473 474 /* Check if HW expected value is higher (could be in future chips) */ 475 cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG); 476 if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL) 477 nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL); 478 } 479 480 /* Channel parse index configuration */ 481 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 482 { 483 struct hw_info *hw = nic->hw; 484 u32 vnic, bgx, lmac, chan; 485 u32 padd, cpi_count = 0; 486 u64 cpi_base, cpi, rssi_base, rssi; 487 u8 qset, rq_idx = 0; 488 489 vnic = cfg->vf_id; 490 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 491 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 492 493 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx); 494 cpi_base = vnic * NIC_MAX_CPI_PER_LMAC; 495 rssi_base = vnic * hw->rss_ind_tbl_size; 496 497 /* Rx channel configuration */ 498 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 499 (1ull << 63) | (vnic << 0)); 500 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 501 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48)); 502 503 if (cfg->cpi_alg == CPI_ALG_NONE) 504 cpi_count = 1; 505 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 506 cpi_count = 8; 507 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 508 cpi_count = 16; 509 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 510 cpi_count = NIC_MAX_CPI_PER_LMAC; 511 512 /* RSS Qset, Qidx mapping */ 513 qset = cfg->vf_id; 514 rssi = rssi_base; 515 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 516 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 517 (qset << 3) | rq_idx); 518 rq_idx++; 519 } 520 521 rssi = 0; 522 cpi = cpi_base; 523 for (; cpi < (cpi_base + cpi_count); cpi++) { 524 /* Determine port to channel adder */ 525 if (cfg->cpi_alg != CPI_ALG_DIFF) 526 padd = cpi % cpi_count; 527 else 528 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 529 530 /* Leave RSS_SIZE as '0' to disable RSS */ 531 if (pass1_silicon(nic->pdev)) { 532 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 533 (vnic << 24) | (padd << 16) | 534 (rssi_base + rssi)); 535 } else { 536 /* Set MPI_ALG to '0' to disable MCAM parsing */ 537 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 538 (padd << 16)); 539 /* MPI index is same as CPI if MPI_ALG is not enabled */ 540 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), 541 (vnic << 24) | (rssi_base + rssi)); 542 } 543 544 if ((rssi + 1) >= cfg->rq_cnt) 545 continue; 546 547 if (cfg->cpi_alg == CPI_ALG_VLAN) 548 rssi++; 549 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 550 rssi = ((cpi - cpi_base) & 0xe) >> 1; 551 else if (cfg->cpi_alg == CPI_ALG_DIFF) 552 rssi = ((cpi - cpi_base) & 0x38) >> 3; 553 } 554 nic->cpi_base[cfg->vf_id] = cpi_base; 555 nic->rssi_base[cfg->vf_id] = rssi_base; 556 } 557 558 /* Responsds to VF with its RSS indirection table size */ 559 static void nic_send_rss_size(struct nicpf *nic, int vf) 560 { 561 union nic_mbx mbx = {}; 562 563 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 564 mbx.rss_size.ind_tbl_size = nic->hw->rss_ind_tbl_size; 565 nic_send_msg_to_vf(nic, vf, &mbx); 566 } 567 568 /* Receive side scaling configuration 569 * configure: 570 * - RSS index 571 * - indir table i.e hash::RQ mapping 572 * - no of hash bits to consider 573 */ 574 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) 575 { 576 u8 qset, idx = 0; 577 u64 cpi_cfg, cpi_base, rssi_base, rssi; 578 u64 idx_addr; 579 580 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset; 581 582 rssi = rssi_base; 583 584 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) { 585 u8 svf = cfg->ind_tbl[idx] >> 3; 586 587 if (svf) 588 qset = nic->vf_sqs[cfg->vf_id][svf - 1]; 589 else 590 qset = cfg->vf_id; 591 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 592 (qset << 3) | (cfg->ind_tbl[idx] & 0x7)); 593 idx++; 594 } 595 596 cpi_base = nic->cpi_base[cfg->vf_id]; 597 if (pass1_silicon(nic->pdev)) 598 idx_addr = NIC_PF_CPI_0_2047_CFG; 599 else 600 idx_addr = NIC_PF_MPI_0_2047_CFG; 601 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3)); 602 cpi_cfg &= ~(0xFULL << 20); 603 cpi_cfg |= (cfg->hash_bits << 20); 604 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg); 605 } 606 607 /* 4 level transmit side scheduler configutation 608 * for TNS bypass mode 609 * 610 * Sample configuration for SQ0 on 88xx 611 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 612 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 613 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 614 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 615 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 616 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 617 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 618 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 619 */ 620 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic, 621 struct sq_cfg_msg *sq) 622 { 623 struct hw_info *hw = nic->hw; 624 u32 bgx, lmac, chan; 625 u32 tl2, tl3, tl4; 626 u32 rr_quantum; 627 u8 sq_idx = sq->sq_num; 628 u8 pqs_vnic; 629 int svf; 630 631 if (sq->sqs_mode) 632 pqs_vnic = nic->pqs_vf[vnic]; 633 else 634 pqs_vnic = vnic; 635 636 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 637 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 638 639 /* 24 bytes for FCS, IPG and preamble */ 640 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 641 642 /* For 88xx 0-511 TL4 transmits via BGX0 and 643 * 512-1023 TL4s transmit via BGX1. 644 */ 645 if (hw->tl1_per_bgx) { 646 tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt); 647 if (!sq->sqs_mode) { 648 tl4 += (lmac * MAX_QUEUES_PER_QSET); 649 } else { 650 for (svf = 0; svf < MAX_SQS_PER_VF; svf++) { 651 if (nic->vf_sqs[pqs_vnic][svf] == vnic) 652 break; 653 } 654 tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET); 655 tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF); 656 tl4 += (svf * MAX_QUEUES_PER_QSET); 657 } 658 } else { 659 tl4 = (vnic * MAX_QUEUES_PER_QSET); 660 } 661 tl4 += sq_idx; 662 663 tl3 = tl4 / (hw->tl4_cnt / hw->tl3_cnt); 664 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 665 ((u64)vnic << NIC_QS_ID_SHIFT) | 666 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4); 667 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 668 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum); 669 670 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 671 672 /* On 88xx 0-127 channels are for BGX0 and 673 * 127-255 channels for BGX1. 674 * 675 * On 81xx/83xx TL3_CHAN reg should be configured with channel 676 * within LMAC i.e 0-7 and not the actual channel number like on 88xx 677 */ 678 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx); 679 if (hw->tl1_per_bgx) 680 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 681 else 682 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), 0); 683 684 /* Enable backpressure on the channel */ 685 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 686 687 tl2 = tl3 >> 2; 688 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 689 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 690 /* No priorities as of now */ 691 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 692 693 /* Unlike 88xx where TL2s 0-31 transmits to TL1 '0' and rest to TL1 '1' 694 * on 81xx/83xx TL2 needs to be configured to transmit to one of the 695 * possible LMACs. 696 * 697 * This register doesn't exist on 88xx. 698 */ 699 if (!hw->tl1_per_bgx) 700 nic_reg_write(nic, NIC_PF_TL2_LMAC | (tl2 << 3), 701 lmac + (bgx * MAX_LMAC_PER_BGX)); 702 } 703 704 /* Send primary nicvf pointer to secondary QS's VF */ 705 static void nic_send_pnicvf(struct nicpf *nic, int sqs) 706 { 707 union nic_mbx mbx = {}; 708 709 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 710 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]]; 711 nic_send_msg_to_vf(nic, sqs, &mbx); 712 } 713 714 /* Send SQS's nicvf pointer to primary QS's VF */ 715 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf) 716 { 717 union nic_mbx mbx = {}; 718 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id]; 719 720 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 721 mbx.nicvf.sqs_id = nicvf->sqs_id; 722 mbx.nicvf.nicvf = nic->nicvf[sqs_id]; 723 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx); 724 } 725 726 /* Find next available Qset that can be assigned as a 727 * secondary Qset to a VF. 728 */ 729 static int nic_nxt_avail_sqs(struct nicpf *nic) 730 { 731 int sqs; 732 733 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) { 734 if (!nic->sqs_used[sqs]) 735 nic->sqs_used[sqs] = true; 736 else 737 continue; 738 return sqs + nic->num_vf_en; 739 } 740 return -1; 741 } 742 743 /* Allocate additional Qsets for requested VF */ 744 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs) 745 { 746 union nic_mbx mbx = {}; 747 int idx, alloc_qs = 0; 748 int sqs_id; 749 750 if (!nic->num_sqs_en) 751 goto send_mbox; 752 753 for (idx = 0; idx < sqs->qs_count; idx++) { 754 sqs_id = nic_nxt_avail_sqs(nic); 755 if (sqs_id < 0) 756 break; 757 nic->vf_sqs[sqs->vf_id][idx] = sqs_id; 758 nic->pqs_vf[sqs_id] = sqs->vf_id; 759 alloc_qs++; 760 } 761 762 send_mbox: 763 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 764 mbx.sqs_alloc.vf_id = sqs->vf_id; 765 mbx.sqs_alloc.qs_count = alloc_qs; 766 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx); 767 } 768 769 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 770 { 771 int bgx_idx, lmac_idx; 772 773 if (lbk->vf_id >= nic->num_vf_en) 774 return -1; 775 776 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 777 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 778 779 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 780 781 /* Enable moving average calculation. 782 * Keep the LVL/AVG delay to HW enforced minimum so that, not too many 783 * packets sneek in between average calculations. 784 */ 785 nic_reg_write(nic, NIC_PF_CQ_AVG_CFG, 786 (BIT_ULL(20) | 0x2ull << 14 | 0x1)); 787 nic_reg_write(nic, NIC_PF_RRM_AVG_CFG, 788 (BIT_ULL(20) | 0x3ull << 14 | 0x1)); 789 790 return 0; 791 } 792 793 /* Reset statistics counters */ 794 static int nic_reset_stat_counters(struct nicpf *nic, 795 int vf, struct reset_stat_cfg *cfg) 796 { 797 int i, stat, qnum; 798 u64 reg_addr; 799 800 for (i = 0; i < RX_STATS_ENUM_LAST; i++) { 801 if (cfg->rx_stat_mask & BIT(i)) { 802 reg_addr = NIC_PF_VNIC_0_127_RX_STAT_0_13 | 803 (vf << NIC_QS_ID_SHIFT) | 804 (i << 3); 805 nic_reg_write(nic, reg_addr, 0); 806 } 807 } 808 809 for (i = 0; i < TX_STATS_ENUM_LAST; i++) { 810 if (cfg->tx_stat_mask & BIT(i)) { 811 reg_addr = NIC_PF_VNIC_0_127_TX_STAT_0_4 | 812 (vf << NIC_QS_ID_SHIFT) | 813 (i << 3); 814 nic_reg_write(nic, reg_addr, 0); 815 } 816 } 817 818 for (i = 0; i <= 15; i++) { 819 qnum = i >> 1; 820 stat = i & 1 ? 1 : 0; 821 reg_addr = (vf << NIC_QS_ID_SHIFT) | 822 (qnum << NIC_Q_NUM_SHIFT) | (stat << 3); 823 if (cfg->rq_stat_mask & BIT(i)) { 824 reg_addr |= NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1; 825 nic_reg_write(nic, reg_addr, 0); 826 } 827 if (cfg->sq_stat_mask & BIT(i)) { 828 reg_addr |= NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1; 829 nic_reg_write(nic, reg_addr, 0); 830 } 831 } 832 833 return 0; 834 } 835 836 static void nic_enable_tunnel_parsing(struct nicpf *nic, int vf) 837 { 838 u64 prot_def = (IPV6_PROT << 32) | (IPV4_PROT << 16) | ET_PROT; 839 u64 vxlan_prot_def = (IPV6_PROT_DEF << 32) | 840 (IPV4_PROT_DEF) << 16 | ET_PROT_DEF; 841 842 /* Configure tunnel parsing parameters */ 843 nic_reg_write(nic, NIC_PF_RX_GENEVE_DEF, 844 (1ULL << 63 | UDP_GENEVE_PORT_NUM)); 845 nic_reg_write(nic, NIC_PF_RX_GENEVE_PROT_DEF, 846 ((7ULL << 61) | prot_def)); 847 nic_reg_write(nic, NIC_PF_RX_NVGRE_PROT_DEF, 848 ((7ULL << 61) | prot_def)); 849 nic_reg_write(nic, NIC_PF_RX_VXLAN_DEF_0_1, 850 ((1ULL << 63) | UDP_VXLAN_PORT_NUM)); 851 nic_reg_write(nic, NIC_PF_RX_VXLAN_PROT_DEF, 852 ((0xfULL << 60) | vxlan_prot_def)); 853 } 854 855 static void nic_enable_vf(struct nicpf *nic, int vf, bool enable) 856 { 857 int bgx, lmac; 858 859 nic->vf_enabled[vf] = enable; 860 861 if (vf >= nic->num_vf_en) 862 return; 863 864 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 865 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 866 867 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, enable); 868 } 869 870 static void nic_pause_frame(struct nicpf *nic, int vf, struct pfc *cfg) 871 { 872 int bgx, lmac; 873 struct pfc pfc; 874 union nic_mbx mbx = {}; 875 876 if (vf >= nic->num_vf_en) 877 return; 878 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 879 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 880 881 if (cfg->get) { 882 bgx_lmac_get_pfc(nic->node, bgx, lmac, &pfc); 883 mbx.pfc.msg = NIC_MBOX_MSG_PFC; 884 mbx.pfc.autoneg = pfc.autoneg; 885 mbx.pfc.fc_rx = pfc.fc_rx; 886 mbx.pfc.fc_tx = pfc.fc_tx; 887 nic_send_msg_to_vf(nic, vf, &mbx); 888 } else { 889 bgx_lmac_set_pfc(nic->node, bgx, lmac, cfg); 890 nic_mbx_send_ack(nic, vf); 891 } 892 } 893 894 /* Enable or disable HW timestamping by BGX for pkts received on a LMAC */ 895 static void nic_config_timestamp(struct nicpf *nic, int vf, struct set_ptp *ptp) 896 { 897 struct pkind_cfg *pkind; 898 u8 lmac, bgx_idx; 899 u64 pkind_val, pkind_idx; 900 901 if (vf >= nic->num_vf_en) 902 return; 903 904 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 905 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 906 907 pkind_idx = lmac + bgx_idx * MAX_LMAC_PER_BGX; 908 pkind_val = nic_reg_read(nic, NIC_PF_PKIND_0_15_CFG | (pkind_idx << 3)); 909 pkind = (struct pkind_cfg *)&pkind_val; 910 911 if (ptp->enable && !pkind->hdr_sl) { 912 /* Skiplen to exclude 8byte timestamp while parsing pkt 913 * If not configured, will result in L2 errors. 914 */ 915 pkind->hdr_sl = 4; 916 /* Adjust max packet length allowed */ 917 pkind->maxlen += (pkind->hdr_sl * 2); 918 bgx_config_timestamping(nic->node, bgx_idx, lmac, true); 919 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7 | (1 << 3), 920 (ETYPE_ALG_ENDPARSE << 16) | ETH_P_1588); 921 } else if (!ptp->enable && pkind->hdr_sl) { 922 pkind->maxlen -= (pkind->hdr_sl * 2); 923 pkind->hdr_sl = 0; 924 bgx_config_timestamping(nic->node, bgx_idx, lmac, false); 925 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7 | (1 << 3), 926 (ETYPE_ALG_SKIP << 16) | ETH_P_8021Q); 927 } 928 929 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (pkind_idx << 3), pkind_val); 930 } 931 932 /* Interrupt handler to handle mailbox messages from VFs */ 933 static void nic_handle_mbx_intr(struct nicpf *nic, int vf) 934 { 935 union nic_mbx mbx = {}; 936 u64 *mbx_data; 937 u64 mbx_addr; 938 u64 reg_addr; 939 u64 cfg; 940 int bgx, lmac; 941 int i; 942 int ret = 0; 943 944 nic->mbx_lock[vf] = true; 945 946 mbx_addr = nic_get_mbx_addr(vf); 947 mbx_data = (u64 *)&mbx; 948 949 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 950 *mbx_data = nic_reg_read(nic, mbx_addr); 951 mbx_data++; 952 mbx_addr += sizeof(u64); 953 } 954 955 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg 0x%02x from VF%d\n", 956 __func__, mbx.msg.msg, vf); 957 switch (mbx.msg.msg) { 958 case NIC_MBOX_MSG_READY: 959 nic_mbx_send_ready(nic, vf); 960 if (vf < nic->num_vf_en) { 961 nic->link[vf] = 0; 962 nic->duplex[vf] = 0; 963 nic->speed[vf] = 0; 964 } 965 goto unlock; 966 case NIC_MBOX_MSG_QS_CFG: 967 reg_addr = NIC_PF_QSET_0_127_CFG | 968 (mbx.qs.num << NIC_QS_ID_SHIFT); 969 cfg = mbx.qs.cfg; 970 /* Check if its a secondary Qset */ 971 if (vf >= nic->num_vf_en) { 972 cfg = cfg & (~0x7FULL); 973 /* Assign this Qset to primary Qset's VF */ 974 cfg |= nic->pqs_vf[vf]; 975 } 976 nic_reg_write(nic, reg_addr, cfg); 977 break; 978 case NIC_MBOX_MSG_RQ_CFG: 979 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 980 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 981 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 982 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 983 /* Enable CQE_RX2_S extension in CQE_RX descriptor. 984 * This gets appended by default on 81xx/83xx chips, 985 * for consistency enabling the same on 88xx pass2 986 * where this is introduced. 987 */ 988 if (pass2_silicon(nic->pdev)) 989 nic_reg_write(nic, NIC_PF_RX_CFG, 0x01); 990 if (!pass1_silicon(nic->pdev)) 991 nic_enable_tunnel_parsing(nic, vf); 992 break; 993 case NIC_MBOX_MSG_RQ_BP_CFG: 994 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 995 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 996 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 997 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 998 break; 999 case NIC_MBOX_MSG_RQ_SW_SYNC: 1000 ret = nic_rcv_queue_sw_sync(nic); 1001 break; 1002 case NIC_MBOX_MSG_RQ_DROP_CFG: 1003 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 1004 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 1005 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 1006 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 1007 break; 1008 case NIC_MBOX_MSG_SQ_CFG: 1009 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 1010 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 1011 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 1012 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 1013 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 1014 break; 1015 case NIC_MBOX_MSG_SET_MAC: 1016 if (vf >= nic->num_vf_en) { 1017 ret = -1; /* NACK */ 1018 break; 1019 } 1020 lmac = mbx.mac.vf_id; 1021 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 1022 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 1023 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 1024 break; 1025 case NIC_MBOX_MSG_SET_MAX_FRS: 1026 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, 1027 mbx.frs.vf_id); 1028 break; 1029 case NIC_MBOX_MSG_CPI_CFG: 1030 nic_config_cpi(nic, &mbx.cpi_cfg); 1031 break; 1032 case NIC_MBOX_MSG_RSS_SIZE: 1033 nic_send_rss_size(nic, vf); 1034 goto unlock; 1035 case NIC_MBOX_MSG_RSS_CFG: 1036 case NIC_MBOX_MSG_RSS_CFG_CONT: 1037 nic_config_rss(nic, &mbx.rss_cfg); 1038 break; 1039 case NIC_MBOX_MSG_CFG_DONE: 1040 /* Last message of VF config msg sequence */ 1041 nic_enable_vf(nic, vf, true); 1042 goto unlock; 1043 case NIC_MBOX_MSG_SHUTDOWN: 1044 /* First msg in VF teardown sequence */ 1045 if (vf >= nic->num_vf_en) 1046 nic->sqs_used[vf - nic->num_vf_en] = false; 1047 nic->pqs_vf[vf] = 0; 1048 nic_enable_vf(nic, vf, false); 1049 break; 1050 case NIC_MBOX_MSG_ALLOC_SQS: 1051 nic_alloc_sqs(nic, &mbx.sqs_alloc); 1052 goto unlock; 1053 case NIC_MBOX_MSG_NICVF_PTR: 1054 nic->nicvf[vf] = mbx.nicvf.nicvf; 1055 break; 1056 case NIC_MBOX_MSG_PNICVF_PTR: 1057 nic_send_pnicvf(nic, vf); 1058 goto unlock; 1059 case NIC_MBOX_MSG_SNICVF_PTR: 1060 nic_send_snicvf(nic, &mbx.nicvf); 1061 goto unlock; 1062 case NIC_MBOX_MSG_BGX_STATS: 1063 nic_get_bgx_stats(nic, &mbx.bgx_stats); 1064 goto unlock; 1065 case NIC_MBOX_MSG_LOOPBACK: 1066 ret = nic_config_loopback(nic, &mbx.lbk); 1067 break; 1068 case NIC_MBOX_MSG_RESET_STAT_COUNTER: 1069 ret = nic_reset_stat_counters(nic, vf, &mbx.reset_stat); 1070 break; 1071 case NIC_MBOX_MSG_PFC: 1072 nic_pause_frame(nic, vf, &mbx.pfc); 1073 goto unlock; 1074 case NIC_MBOX_MSG_PTP_CFG: 1075 nic_config_timestamp(nic, vf, &mbx.ptp); 1076 break; 1077 case NIC_MBOX_MSG_RESET_XCAST: 1078 if (vf >= nic->num_vf_en) { 1079 ret = -1; /* NACK */ 1080 break; 1081 } 1082 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1083 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1084 bgx_reset_xcast_mode(nic->node, bgx, lmac, 1085 vf < NIC_VF_PER_MBX_REG ? vf : 1086 vf - NIC_VF_PER_MBX_REG); 1087 break; 1088 1089 case NIC_MBOX_MSG_ADD_MCAST: 1090 if (vf >= nic->num_vf_en) { 1091 ret = -1; /* NACK */ 1092 break; 1093 } 1094 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1095 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1096 bgx_set_dmac_cam_filter(nic->node, bgx, lmac, 1097 mbx.xcast.data.mac, 1098 vf < NIC_VF_PER_MBX_REG ? vf : 1099 vf - NIC_VF_PER_MBX_REG); 1100 break; 1101 1102 case NIC_MBOX_MSG_SET_XCAST: 1103 if (vf >= nic->num_vf_en) { 1104 ret = -1; /* NACK */ 1105 break; 1106 } 1107 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1108 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1109 bgx_set_xcast_mode(nic->node, bgx, lmac, mbx.xcast.data.mode); 1110 break; 1111 default: 1112 dev_err(&nic->pdev->dev, 1113 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 1114 break; 1115 } 1116 1117 if (!ret) { 1118 nic_mbx_send_ack(nic, vf); 1119 } else if (mbx.msg.msg != NIC_MBOX_MSG_READY) { 1120 dev_err(&nic->pdev->dev, "NACK for MBOX 0x%02x from VF %d\n", 1121 mbx.msg.msg, vf); 1122 nic_mbx_send_nack(nic, vf); 1123 } 1124 unlock: 1125 nic->mbx_lock[vf] = false; 1126 } 1127 1128 static irqreturn_t nic_mbx_intr_handler(int irq, void *nic_irq) 1129 { 1130 struct nicpf *nic = (struct nicpf *)nic_irq; 1131 int mbx; 1132 u64 intr; 1133 u8 vf; 1134 1135 if (irq == pci_irq_vector(nic->pdev, NIC_PF_INTR_ID_MBOX0)) 1136 mbx = 0; 1137 else 1138 mbx = 1; 1139 1140 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 1141 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr); 1142 for (vf = 0; vf < NIC_VF_PER_MBX_REG; vf++) { 1143 if (intr & (1ULL << vf)) { 1144 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n", 1145 vf + (mbx * NIC_VF_PER_MBX_REG)); 1146 1147 nic_handle_mbx_intr(nic, vf + 1148 (mbx * NIC_VF_PER_MBX_REG)); 1149 nic_clear_mbx_intr(nic, vf, mbx); 1150 } 1151 } 1152 return IRQ_HANDLED; 1153 } 1154 1155 static void nic_free_all_interrupts(struct nicpf *nic) 1156 { 1157 int irq; 1158 1159 for (irq = 0; irq < nic->num_vec; irq++) { 1160 if (nic->irq_allocated[irq]) 1161 free_irq(pci_irq_vector(nic->pdev, irq), nic); 1162 nic->irq_allocated[irq] = false; 1163 } 1164 } 1165 1166 static int nic_register_interrupts(struct nicpf *nic) 1167 { 1168 int i, ret; 1169 nic->num_vec = pci_msix_vec_count(nic->pdev); 1170 1171 /* Enable MSI-X */ 1172 ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec, 1173 PCI_IRQ_MSIX); 1174 if (ret < 0) { 1175 dev_err(&nic->pdev->dev, 1176 "Request for #%d msix vectors failed, returned %d\n", 1177 nic->num_vec, ret); 1178 return 1; 1179 } 1180 1181 /* Register mailbox interrupt handler */ 1182 for (i = NIC_PF_INTR_ID_MBOX0; i < nic->num_vec; i++) { 1183 sprintf(nic->irq_name[i], 1184 "NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0)); 1185 1186 ret = request_irq(pci_irq_vector(nic->pdev, i), 1187 nic_mbx_intr_handler, 0, 1188 nic->irq_name[i], nic); 1189 if (ret) 1190 goto fail; 1191 1192 nic->irq_allocated[i] = true; 1193 } 1194 1195 /* Enable mailbox interrupt */ 1196 nic_enable_mbx_intr(nic); 1197 return 0; 1198 1199 fail: 1200 dev_err(&nic->pdev->dev, "Request irq failed\n"); 1201 nic_free_all_interrupts(nic); 1202 pci_free_irq_vectors(nic->pdev); 1203 nic->num_vec = 0; 1204 return ret; 1205 } 1206 1207 static void nic_unregister_interrupts(struct nicpf *nic) 1208 { 1209 nic_free_all_interrupts(nic); 1210 pci_free_irq_vectors(nic->pdev); 1211 nic->num_vec = 0; 1212 } 1213 1214 static int nic_num_sqs_en(struct nicpf *nic, int vf_en) 1215 { 1216 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE; 1217 u16 total_vf; 1218 1219 /* Secondary Qsets are needed only if CPU count is 1220 * morethan MAX_QUEUES_PER_QSET. 1221 */ 1222 if (num_online_cpus() <= MAX_QUEUES_PER_QSET) 1223 return 0; 1224 1225 /* Check if its a multi-node environment */ 1226 if (nr_node_ids > 1) 1227 sqs_per_vf = MAX_SQS_PER_VF; 1228 1229 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV); 1230 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf); 1231 return min(total_vf - vf_en, vf_en * sqs_per_vf); 1232 } 1233 1234 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic) 1235 { 1236 int pos = 0; 1237 int vf_en; 1238 int err; 1239 u16 total_vf_cnt; 1240 1241 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 1242 if (!pos) { 1243 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n"); 1244 return -ENODEV; 1245 } 1246 1247 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt); 1248 if (total_vf_cnt < nic->num_vf_en) 1249 nic->num_vf_en = total_vf_cnt; 1250 1251 if (!total_vf_cnt) 1252 return 0; 1253 1254 vf_en = nic->num_vf_en; 1255 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en); 1256 vf_en += nic->num_sqs_en; 1257 1258 err = pci_enable_sriov(pdev, vf_en); 1259 if (err) { 1260 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n", 1261 vf_en); 1262 nic->num_vf_en = 0; 1263 return err; 1264 } 1265 1266 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n", 1267 vf_en); 1268 1269 nic->flags |= NIC_SRIOV_ENABLED; 1270 return 0; 1271 } 1272 1273 /* Poll for BGX LMAC link status and update corresponding VF 1274 * if there is a change, valid only if internal L2 switch 1275 * is not present otherwise VF link is always treated as up 1276 */ 1277 static void nic_poll_for_link(struct work_struct *work) 1278 { 1279 union nic_mbx mbx = {}; 1280 struct nicpf *nic; 1281 struct bgx_link_status link; 1282 u8 vf, bgx, lmac; 1283 1284 nic = container_of(work, struct nicpf, dwork.work); 1285 1286 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 1287 1288 for (vf = 0; vf < nic->num_vf_en; vf++) { 1289 /* Poll only if VF is UP */ 1290 if (!nic->vf_enabled[vf]) 1291 continue; 1292 1293 /* Get BGX, LMAC indices for the VF */ 1294 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1295 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1296 /* Get interface link status */ 1297 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 1298 1299 /* Inform VF only if link status changed */ 1300 if (nic->link[vf] == link.link_up) 1301 continue; 1302 1303 if (!nic->mbx_lock[vf]) { 1304 nic->link[vf] = link.link_up; 1305 nic->duplex[vf] = link.duplex; 1306 nic->speed[vf] = link.speed; 1307 1308 /* Send a mbox message to VF with current link status */ 1309 mbx.link_status.link_up = link.link_up; 1310 mbx.link_status.duplex = link.duplex; 1311 mbx.link_status.speed = link.speed; 1312 mbx.link_status.mac_type = link.mac_type; 1313 nic_send_msg_to_vf(nic, vf, &mbx); 1314 } 1315 } 1316 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2); 1317 } 1318 1319 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1320 { 1321 struct device *dev = &pdev->dev; 1322 struct nicpf *nic; 1323 u8 max_lmac; 1324 int err; 1325 1326 BUILD_BUG_ON(sizeof(union nic_mbx) > 16); 1327 1328 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL); 1329 if (!nic) 1330 return -ENOMEM; 1331 1332 nic->hw = devm_kzalloc(dev, sizeof(struct hw_info), GFP_KERNEL); 1333 if (!nic->hw) 1334 return -ENOMEM; 1335 1336 pci_set_drvdata(pdev, nic); 1337 1338 nic->pdev = pdev; 1339 1340 err = pci_enable_device(pdev); 1341 if (err) { 1342 dev_err(dev, "Failed to enable PCI device\n"); 1343 pci_set_drvdata(pdev, NULL); 1344 return err; 1345 } 1346 1347 err = pci_request_regions(pdev, DRV_NAME); 1348 if (err) { 1349 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1350 goto err_disable_device; 1351 } 1352 1353 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 1354 if (err) { 1355 dev_err(dev, "Unable to get usable DMA configuration\n"); 1356 goto err_release_regions; 1357 } 1358 1359 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 1360 if (err) { 1361 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n"); 1362 goto err_release_regions; 1363 } 1364 1365 /* MAP PF's configuration registers */ 1366 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1367 if (!nic->reg_base) { 1368 dev_err(dev, "Cannot map config register space, aborting\n"); 1369 err = -ENOMEM; 1370 goto err_release_regions; 1371 } 1372 1373 nic->node = nic_get_node_id(pdev); 1374 1375 /* Get HW capability info */ 1376 nic_get_hw_info(nic); 1377 1378 /* Allocate memory for LMAC tracking elements */ 1379 err = -ENOMEM; 1380 max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX; 1381 1382 nic->vf_lmac_map = devm_kmalloc_array(dev, max_lmac, sizeof(u8), 1383 GFP_KERNEL); 1384 if (!nic->vf_lmac_map) 1385 goto err_release_regions; 1386 1387 nic->link = devm_kmalloc_array(dev, max_lmac, sizeof(u8), GFP_KERNEL); 1388 if (!nic->link) 1389 goto err_release_regions; 1390 1391 nic->duplex = devm_kmalloc_array(dev, max_lmac, sizeof(u8), GFP_KERNEL); 1392 if (!nic->duplex) 1393 goto err_release_regions; 1394 1395 nic->speed = devm_kmalloc_array(dev, max_lmac, sizeof(u32), GFP_KERNEL); 1396 if (!nic->speed) 1397 goto err_release_regions; 1398 1399 /* Initialize hardware */ 1400 nic_init_hw(nic); 1401 1402 nic_set_lmac_vf_mapping(nic); 1403 1404 /* Register interrupts */ 1405 err = nic_register_interrupts(nic); 1406 if (err) 1407 goto err_release_regions; 1408 1409 /* Configure SRIOV */ 1410 err = nic_sriov_init(pdev, nic); 1411 if (err) 1412 goto err_unregister_interrupts; 1413 1414 /* Register a physical link status poll fn() */ 1415 nic->check_link = alloc_workqueue("check_link_status", 1416 WQ_UNBOUND | WQ_MEM_RECLAIM, 1); 1417 if (!nic->check_link) { 1418 err = -ENOMEM; 1419 goto err_disable_sriov; 1420 } 1421 1422 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link); 1423 queue_delayed_work(nic->check_link, &nic->dwork, 0); 1424 1425 return 0; 1426 1427 err_disable_sriov: 1428 if (nic->flags & NIC_SRIOV_ENABLED) 1429 pci_disable_sriov(pdev); 1430 err_unregister_interrupts: 1431 nic_unregister_interrupts(nic); 1432 err_release_regions: 1433 pci_release_regions(pdev); 1434 err_disable_device: 1435 pci_disable_device(pdev); 1436 pci_set_drvdata(pdev, NULL); 1437 return err; 1438 } 1439 1440 static void nic_remove(struct pci_dev *pdev) 1441 { 1442 struct nicpf *nic = pci_get_drvdata(pdev); 1443 1444 if (nic->flags & NIC_SRIOV_ENABLED) 1445 pci_disable_sriov(pdev); 1446 1447 if (nic->check_link) { 1448 /* Destroy work Queue */ 1449 cancel_delayed_work_sync(&nic->dwork); 1450 destroy_workqueue(nic->check_link); 1451 } 1452 1453 nic_unregister_interrupts(nic); 1454 pci_release_regions(pdev); 1455 1456 pci_disable_device(pdev); 1457 pci_set_drvdata(pdev, NULL); 1458 } 1459 1460 static struct pci_driver nic_driver = { 1461 .name = DRV_NAME, 1462 .id_table = nic_id_table, 1463 .probe = nic_probe, 1464 .remove = nic_remove, 1465 }; 1466 1467 static int __init nic_init_module(void) 1468 { 1469 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1470 1471 return pci_register_driver(&nic_driver); 1472 } 1473 1474 static void __exit nic_cleanup_module(void) 1475 { 1476 pci_unregister_driver(&nic_driver); 1477 } 1478 1479 module_init(nic_init_module); 1480 module_exit(nic_cleanup_module); 1481