1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/etherdevice.h> 13 #include <linux/of.h> 14 #include <linux/if_vlan.h> 15 16 #include "nic_reg.h" 17 #include "nic.h" 18 #include "q_struct.h" 19 #include "thunder_bgx.h" 20 21 #define DRV_NAME "thunder-nic" 22 #define DRV_VERSION "1.0" 23 24 struct hw_info { 25 u8 bgx_cnt; 26 u8 chans_per_lmac; 27 u8 chans_per_bgx; /* Rx/Tx chans */ 28 u8 chans_per_rgx; 29 u8 chans_per_lbk; 30 u16 cpi_cnt; 31 u16 rssi_cnt; 32 u16 rss_ind_tbl_size; 33 u16 tl4_cnt; 34 u16 tl3_cnt; 35 u8 tl2_cnt; 36 u8 tl1_cnt; 37 bool tl1_per_bgx; /* TL1 per BGX or per LMAC */ 38 }; 39 40 struct nicpf { 41 struct pci_dev *pdev; 42 struct hw_info *hw; 43 u8 node; 44 unsigned int flags; 45 u8 num_vf_en; /* No of VF enabled */ 46 bool vf_enabled[MAX_NUM_VFS_SUPPORTED]; 47 void __iomem *reg_base; /* Register start address */ 48 u8 num_sqs_en; /* Secondary qsets enabled */ 49 u64 nicvf[MAX_NUM_VFS_SUPPORTED]; 50 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF]; 51 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED]; 52 bool sqs_used[MAX_NUM_VFS_SUPPORTED]; 53 struct pkind_cfg pkind; 54 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF)) 55 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF) 56 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF) 57 u8 *vf_lmac_map; 58 struct delayed_work dwork; 59 struct workqueue_struct *check_link; 60 u8 *link; 61 u8 *duplex; 62 u32 *speed; 63 u16 cpi_base[MAX_NUM_VFS_SUPPORTED]; 64 u16 rssi_base[MAX_NUM_VFS_SUPPORTED]; 65 bool mbx_lock[MAX_NUM_VFS_SUPPORTED]; 66 67 /* MSI-X */ 68 u8 num_vec; 69 bool irq_allocated[NIC_PF_MSIX_VECTORS]; 70 char irq_name[NIC_PF_MSIX_VECTORS][20]; 71 }; 72 73 /* Supported devices */ 74 static const struct pci_device_id nic_id_table[] = { 75 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) }, 76 { 0, } /* end of table */ 77 }; 78 79 MODULE_AUTHOR("Sunil Goutham"); 80 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver"); 81 MODULE_LICENSE("GPL v2"); 82 MODULE_VERSION(DRV_VERSION); 83 MODULE_DEVICE_TABLE(pci, nic_id_table); 84 85 /* The Cavium ThunderX network controller can *only* be found in SoCs 86 * containing the ThunderX ARM64 CPU implementation. All accesses to the device 87 * registers on this platform are implicitly strongly ordered with respect 88 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use 89 * with no memory barriers in this driver. The readq()/writeq() functions add 90 * explicit ordering operation which in this case are redundant, and only 91 * add overhead. 92 */ 93 94 /* Register read/write APIs */ 95 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val) 96 { 97 writeq_relaxed(val, nic->reg_base + offset); 98 } 99 100 static u64 nic_reg_read(struct nicpf *nic, u64 offset) 101 { 102 return readq_relaxed(nic->reg_base + offset); 103 } 104 105 /* PF -> VF mailbox communication APIs */ 106 static void nic_enable_mbx_intr(struct nicpf *nic) 107 { 108 int vf_cnt = pci_sriov_get_totalvfs(nic->pdev); 109 110 #define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull)) 111 112 /* Clear it, to avoid spurious interrupts (if any) */ 113 nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt)); 114 115 /* Enable mailbox interrupt for all VFs */ 116 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt)); 117 /* One mailbox intr enable reg per 64 VFs */ 118 if (vf_cnt > 64) { 119 nic_reg_write(nic, NIC_PF_MAILBOX_INT + sizeof(u64), 120 INTR_MASK(vf_cnt - 64)); 121 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), 122 INTR_MASK(vf_cnt - 64)); 123 } 124 } 125 126 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 127 { 128 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf)); 129 } 130 131 static u64 nic_get_mbx_addr(int vf) 132 { 133 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT); 134 } 135 136 /* Send a mailbox message to VF 137 * @vf: vf to which this message to be sent 138 * @mbx: Message to be sent 139 */ 140 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 141 { 142 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf); 143 u64 *msg = (u64 *)mbx; 144 145 /* In first revision HW, mbox interrupt is triggerred 146 * when PF writes to MBOX(1), in next revisions when 147 * PF writes to MBOX(0) 148 */ 149 if (pass1_silicon(nic->pdev)) { 150 /* see the comment for nic_reg_write()/nic_reg_read() 151 * functions above 152 */ 153 writeq_relaxed(msg[0], mbx_addr); 154 writeq_relaxed(msg[1], mbx_addr + 8); 155 } else { 156 writeq_relaxed(msg[1], mbx_addr + 8); 157 writeq_relaxed(msg[0], mbx_addr); 158 } 159 } 160 161 /* Responds to VF's READY message with VF's 162 * ID, node, MAC address e.t.c 163 * @vf: VF which sent READY message 164 */ 165 static void nic_mbx_send_ready(struct nicpf *nic, int vf) 166 { 167 union nic_mbx mbx = {}; 168 int bgx_idx, lmac; 169 const char *mac; 170 171 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 172 mbx.nic_cfg.vf_id = vf; 173 174 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 175 176 if (vf < nic->num_vf_en) { 177 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 178 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 179 180 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 181 if (mac) 182 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac); 183 } 184 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false; 185 mbx.nic_cfg.node_id = nic->node; 186 187 mbx.nic_cfg.loopback_supported = vf < nic->num_vf_en; 188 189 nic_send_msg_to_vf(nic, vf, &mbx); 190 } 191 192 /* ACKs VF's mailbox message 193 * @vf: VF to which ACK to be sent 194 */ 195 static void nic_mbx_send_ack(struct nicpf *nic, int vf) 196 { 197 union nic_mbx mbx = {}; 198 199 mbx.msg.msg = NIC_MBOX_MSG_ACK; 200 nic_send_msg_to_vf(nic, vf, &mbx); 201 } 202 203 /* NACKs VF's mailbox message that PF is not able to 204 * complete the action 205 * @vf: VF to which ACK to be sent 206 */ 207 static void nic_mbx_send_nack(struct nicpf *nic, int vf) 208 { 209 union nic_mbx mbx = {}; 210 211 mbx.msg.msg = NIC_MBOX_MSG_NACK; 212 nic_send_msg_to_vf(nic, vf, &mbx); 213 } 214 215 /* Flush all in flight receive packets to memory and 216 * bring down an active RQ 217 */ 218 static int nic_rcv_queue_sw_sync(struct nicpf *nic) 219 { 220 u16 timeout = ~0x00; 221 222 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 223 /* Wait till sync cycle is finished */ 224 while (timeout) { 225 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 226 break; 227 timeout--; 228 } 229 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 230 if (!timeout) { 231 dev_err(&nic->pdev->dev, "Receive queue software sync failed"); 232 return 1; 233 } 234 return 0; 235 } 236 237 /* Get BGX Rx/Tx stats and respond to VF's request */ 238 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 239 { 240 int bgx_idx, lmac; 241 union nic_mbx mbx = {}; 242 243 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 244 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 245 246 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 247 mbx.bgx_stats.vf_id = bgx->vf_id; 248 mbx.bgx_stats.rx = bgx->rx; 249 mbx.bgx_stats.idx = bgx->idx; 250 if (bgx->rx) 251 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx, 252 lmac, bgx->idx); 253 else 254 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx, 255 lmac, bgx->idx); 256 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 257 } 258 259 /* Update hardware min/max frame size */ 260 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 261 { 262 int bgx, lmac, lmac_cnt; 263 u64 lmac_credits; 264 265 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) 266 return 1; 267 268 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 269 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 270 lmac += bgx * MAX_LMAC_PER_BGX; 271 272 new_frs += VLAN_ETH_HLEN + ETH_FCS_LEN + 4; 273 274 /* Update corresponding LMAC credits */ 275 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 276 lmac_credits = nic_reg_read(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8)); 277 lmac_credits &= ~(0xFFFFFULL << 12); 278 lmac_credits |= (((((48 * 1024) / lmac_cnt) - new_frs) / 16) << 12); 279 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credits); 280 281 /* Enforce MTU in HW 282 * This config is supported only from 88xx pass 2.0 onwards. 283 */ 284 if (!pass1_silicon(nic->pdev)) 285 nic_reg_write(nic, 286 NIC_PF_LMAC_0_7_CFG2 + (lmac * 8), new_frs); 287 return 0; 288 } 289 290 /* Set minimum transmit packet size */ 291 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size) 292 { 293 int lmac, max_lmac; 294 u16 sdevid; 295 u64 lmac_cfg; 296 297 /* There is a issue in HW where-in while sending GSO sized 298 * pkts as part of TSO, if pkt len falls below this size 299 * NIC will zero PAD packet and also updates IP total length. 300 * Hence set this value to lessthan min pkt size of MAC+IP+TCP 301 * headers, BGX will do the padding to transmit 64 byte pkt. 302 */ 303 if (size > 52) 304 size = 52; 305 306 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 307 /* 81xx's RGX has only one LMAC */ 308 if (sdevid == PCI_SUBSYS_DEVID_81XX_NIC_PF) 309 max_lmac = ((nic->hw->bgx_cnt - 1) * MAX_LMAC_PER_BGX) + 1; 310 else 311 max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX; 312 313 for (lmac = 0; lmac < max_lmac; lmac++) { 314 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 315 lmac_cfg &= ~(0xF << 2); 316 lmac_cfg |= ((size / 4) << 2); 317 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 318 } 319 } 320 321 /* Function to check number of LMACs present and set VF::LMAC mapping. 322 * Mapping will be used while initializing channels. 323 */ 324 static void nic_set_lmac_vf_mapping(struct nicpf *nic) 325 { 326 unsigned bgx_map = bgx_get_map(nic->node); 327 int bgx, next_bgx_lmac = 0; 328 int lmac, lmac_cnt = 0; 329 u64 lmac_credit; 330 331 nic->num_vf_en = 0; 332 333 for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) { 334 if (!(bgx_map & (1 << bgx))) 335 continue; 336 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 337 for (lmac = 0; lmac < lmac_cnt; lmac++) 338 nic->vf_lmac_map[next_bgx_lmac++] = 339 NIC_SET_VF_LMAC_MAP(bgx, lmac); 340 nic->num_vf_en += lmac_cnt; 341 342 /* Program LMAC credits */ 343 lmac_credit = (1ull << 1); /* channel credit enable */ 344 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 345 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 346 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 347 NIC_HW_MAX_FRS) / 16) << 12); 348 lmac = bgx * MAX_LMAC_PER_BGX; 349 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) 350 nic_reg_write(nic, 351 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 352 lmac_credit); 353 354 /* On CN81XX there are only 8 VFs but max possible no of 355 * interfaces are 9. 356 */ 357 if (nic->num_vf_en >= pci_sriov_get_totalvfs(nic->pdev)) { 358 nic->num_vf_en = pci_sriov_get_totalvfs(nic->pdev); 359 break; 360 } 361 } 362 } 363 364 static void nic_get_hw_info(struct nicpf *nic) 365 { 366 u16 sdevid; 367 struct hw_info *hw = nic->hw; 368 369 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid); 370 371 switch (sdevid) { 372 case PCI_SUBSYS_DEVID_88XX_NIC_PF: 373 hw->bgx_cnt = MAX_BGX_PER_CN88XX; 374 hw->chans_per_lmac = 16; 375 hw->chans_per_bgx = 128; 376 hw->cpi_cnt = 2048; 377 hw->rssi_cnt = 4096; 378 hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 379 hw->tl3_cnt = 256; 380 hw->tl2_cnt = 64; 381 hw->tl1_cnt = 2; 382 hw->tl1_per_bgx = true; 383 break; 384 case PCI_SUBSYS_DEVID_81XX_NIC_PF: 385 hw->bgx_cnt = MAX_BGX_PER_CN81XX; 386 hw->chans_per_lmac = 8; 387 hw->chans_per_bgx = 32; 388 hw->chans_per_rgx = 8; 389 hw->chans_per_lbk = 24; 390 hw->cpi_cnt = 512; 391 hw->rssi_cnt = 256; 392 hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */ 393 hw->tl3_cnt = 64; 394 hw->tl2_cnt = 16; 395 hw->tl1_cnt = 10; 396 hw->tl1_per_bgx = false; 397 break; 398 case PCI_SUBSYS_DEVID_83XX_NIC_PF: 399 hw->bgx_cnt = MAX_BGX_PER_CN83XX; 400 hw->chans_per_lmac = 8; 401 hw->chans_per_bgx = 32; 402 hw->chans_per_lbk = 64; 403 hw->cpi_cnt = 2048; 404 hw->rssi_cnt = 1024; 405 hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */ 406 hw->tl3_cnt = 256; 407 hw->tl2_cnt = 64; 408 hw->tl1_cnt = 18; 409 hw->tl1_per_bgx = false; 410 break; 411 } 412 hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev); 413 } 414 415 #define BGX0_BLOCK 8 416 #define BGX1_BLOCK 9 417 418 static void nic_init_hw(struct nicpf *nic) 419 { 420 int i; 421 u64 cqm_cfg; 422 423 /* Enable NIC HW block */ 424 nic_reg_write(nic, NIC_PF_CFG, 0x3); 425 426 /* Enable backpressure */ 427 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03); 428 429 /* TNS and TNS bypass modes are present only on 88xx */ 430 if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) { 431 /* Disable TNS mode on both interfaces */ 432 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 433 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); 434 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 435 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); 436 } 437 438 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 439 (1ULL << 63) | BGX0_BLOCK); 440 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 441 (1ULL << 63) | BGX1_BLOCK); 442 443 /* PKIND configuration */ 444 nic->pkind.minlen = 0; 445 nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4; 446 nic->pkind.lenerr_en = 1; 447 nic->pkind.rx_hdr = 0; 448 nic->pkind.hdr_sl = 0; 449 450 for (i = 0; i < NIC_MAX_PKIND; i++) 451 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 452 *(u64 *)&nic->pkind); 453 454 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 455 456 /* Timer config */ 457 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 458 459 /* Enable VLAN ethertype matching and stripping */ 460 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 461 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q); 462 463 /* Check if HW expected value is higher (could be in future chips) */ 464 cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG); 465 if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL) 466 nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL); 467 } 468 469 /* Channel parse index configuration */ 470 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 471 { 472 struct hw_info *hw = nic->hw; 473 u32 vnic, bgx, lmac, chan; 474 u32 padd, cpi_count = 0; 475 u64 cpi_base, cpi, rssi_base, rssi; 476 u8 qset, rq_idx = 0; 477 478 vnic = cfg->vf_id; 479 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 480 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 481 482 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx); 483 cpi_base = vnic * NIC_MAX_CPI_PER_LMAC; 484 rssi_base = vnic * hw->rss_ind_tbl_size; 485 486 /* Rx channel configuration */ 487 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 488 (1ull << 63) | (vnic << 0)); 489 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 490 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48)); 491 492 if (cfg->cpi_alg == CPI_ALG_NONE) 493 cpi_count = 1; 494 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 495 cpi_count = 8; 496 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 497 cpi_count = 16; 498 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 499 cpi_count = NIC_MAX_CPI_PER_LMAC; 500 501 /* RSS Qset, Qidx mapping */ 502 qset = cfg->vf_id; 503 rssi = rssi_base; 504 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 505 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 506 (qset << 3) | rq_idx); 507 rq_idx++; 508 } 509 510 rssi = 0; 511 cpi = cpi_base; 512 for (; cpi < (cpi_base + cpi_count); cpi++) { 513 /* Determine port to channel adder */ 514 if (cfg->cpi_alg != CPI_ALG_DIFF) 515 padd = cpi % cpi_count; 516 else 517 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 518 519 /* Leave RSS_SIZE as '0' to disable RSS */ 520 if (pass1_silicon(nic->pdev)) { 521 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 522 (vnic << 24) | (padd << 16) | 523 (rssi_base + rssi)); 524 } else { 525 /* Set MPI_ALG to '0' to disable MCAM parsing */ 526 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 527 (padd << 16)); 528 /* MPI index is same as CPI if MPI_ALG is not enabled */ 529 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), 530 (vnic << 24) | (rssi_base + rssi)); 531 } 532 533 if ((rssi + 1) >= cfg->rq_cnt) 534 continue; 535 536 if (cfg->cpi_alg == CPI_ALG_VLAN) 537 rssi++; 538 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 539 rssi = ((cpi - cpi_base) & 0xe) >> 1; 540 else if (cfg->cpi_alg == CPI_ALG_DIFF) 541 rssi = ((cpi - cpi_base) & 0x38) >> 3; 542 } 543 nic->cpi_base[cfg->vf_id] = cpi_base; 544 nic->rssi_base[cfg->vf_id] = rssi_base; 545 } 546 547 /* Responsds to VF with its RSS indirection table size */ 548 static void nic_send_rss_size(struct nicpf *nic, int vf) 549 { 550 union nic_mbx mbx = {}; 551 552 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 553 mbx.rss_size.ind_tbl_size = nic->hw->rss_ind_tbl_size; 554 nic_send_msg_to_vf(nic, vf, &mbx); 555 } 556 557 /* Receive side scaling configuration 558 * configure: 559 * - RSS index 560 * - indir table i.e hash::RQ mapping 561 * - no of hash bits to consider 562 */ 563 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) 564 { 565 u8 qset, idx = 0; 566 u64 cpi_cfg, cpi_base, rssi_base, rssi; 567 u64 idx_addr; 568 569 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset; 570 571 rssi = rssi_base; 572 573 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) { 574 u8 svf = cfg->ind_tbl[idx] >> 3; 575 576 if (svf) 577 qset = nic->vf_sqs[cfg->vf_id][svf - 1]; 578 else 579 qset = cfg->vf_id; 580 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 581 (qset << 3) | (cfg->ind_tbl[idx] & 0x7)); 582 idx++; 583 } 584 585 cpi_base = nic->cpi_base[cfg->vf_id]; 586 if (pass1_silicon(nic->pdev)) 587 idx_addr = NIC_PF_CPI_0_2047_CFG; 588 else 589 idx_addr = NIC_PF_MPI_0_2047_CFG; 590 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3)); 591 cpi_cfg &= ~(0xFULL << 20); 592 cpi_cfg |= (cfg->hash_bits << 20); 593 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg); 594 } 595 596 /* 4 level transmit side scheduler configutation 597 * for TNS bypass mode 598 * 599 * Sample configuration for SQ0 on 88xx 600 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 601 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 602 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 603 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 604 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 605 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 606 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 607 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 608 */ 609 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic, 610 struct sq_cfg_msg *sq) 611 { 612 struct hw_info *hw = nic->hw; 613 u32 bgx, lmac, chan; 614 u32 tl2, tl3, tl4; 615 u32 rr_quantum; 616 u8 sq_idx = sq->sq_num; 617 u8 pqs_vnic; 618 int svf; 619 620 if (sq->sqs_mode) 621 pqs_vnic = nic->pqs_vf[vnic]; 622 else 623 pqs_vnic = vnic; 624 625 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 626 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 627 628 /* 24 bytes for FCS, IPG and preamble */ 629 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 630 631 /* For 88xx 0-511 TL4 transmits via BGX0 and 632 * 512-1023 TL4s transmit via BGX1. 633 */ 634 if (hw->tl1_per_bgx) { 635 tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt); 636 if (!sq->sqs_mode) { 637 tl4 += (lmac * MAX_QUEUES_PER_QSET); 638 } else { 639 for (svf = 0; svf < MAX_SQS_PER_VF; svf++) { 640 if (nic->vf_sqs[pqs_vnic][svf] == vnic) 641 break; 642 } 643 tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET); 644 tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF); 645 tl4 += (svf * MAX_QUEUES_PER_QSET); 646 } 647 } else { 648 tl4 = (vnic * MAX_QUEUES_PER_QSET); 649 } 650 tl4 += sq_idx; 651 652 tl3 = tl4 / (hw->tl4_cnt / hw->tl3_cnt); 653 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 654 ((u64)vnic << NIC_QS_ID_SHIFT) | 655 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4); 656 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 657 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum); 658 659 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 660 661 /* On 88xx 0-127 channels are for BGX0 and 662 * 127-255 channels for BGX1. 663 * 664 * On 81xx/83xx TL3_CHAN reg should be configured with channel 665 * within LMAC i.e 0-7 and not the actual channel number like on 88xx 666 */ 667 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx); 668 if (hw->tl1_per_bgx) 669 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 670 else 671 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), 0); 672 673 /* Enable backpressure on the channel */ 674 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 675 676 tl2 = tl3 >> 2; 677 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 678 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 679 /* No priorities as of now */ 680 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 681 682 /* Unlike 88xx where TL2s 0-31 transmits to TL1 '0' and rest to TL1 '1' 683 * on 81xx/83xx TL2 needs to be configured to transmit to one of the 684 * possible LMACs. 685 * 686 * This register doesn't exist on 88xx. 687 */ 688 if (!hw->tl1_per_bgx) 689 nic_reg_write(nic, NIC_PF_TL2_LMAC | (tl2 << 3), 690 lmac + (bgx * MAX_LMAC_PER_BGX)); 691 } 692 693 /* Send primary nicvf pointer to secondary QS's VF */ 694 static void nic_send_pnicvf(struct nicpf *nic, int sqs) 695 { 696 union nic_mbx mbx = {}; 697 698 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR; 699 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]]; 700 nic_send_msg_to_vf(nic, sqs, &mbx); 701 } 702 703 /* Send SQS's nicvf pointer to primary QS's VF */ 704 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf) 705 { 706 union nic_mbx mbx = {}; 707 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id]; 708 709 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR; 710 mbx.nicvf.sqs_id = nicvf->sqs_id; 711 mbx.nicvf.nicvf = nic->nicvf[sqs_id]; 712 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx); 713 } 714 715 /* Find next available Qset that can be assigned as a 716 * secondary Qset to a VF. 717 */ 718 static int nic_nxt_avail_sqs(struct nicpf *nic) 719 { 720 int sqs; 721 722 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) { 723 if (!nic->sqs_used[sqs]) 724 nic->sqs_used[sqs] = true; 725 else 726 continue; 727 return sqs + nic->num_vf_en; 728 } 729 return -1; 730 } 731 732 /* Allocate additional Qsets for requested VF */ 733 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs) 734 { 735 union nic_mbx mbx = {}; 736 int idx, alloc_qs = 0; 737 int sqs_id; 738 739 if (!nic->num_sqs_en) 740 goto send_mbox; 741 742 for (idx = 0; idx < sqs->qs_count; idx++) { 743 sqs_id = nic_nxt_avail_sqs(nic); 744 if (sqs_id < 0) 745 break; 746 nic->vf_sqs[sqs->vf_id][idx] = sqs_id; 747 nic->pqs_vf[sqs_id] = sqs->vf_id; 748 alloc_qs++; 749 } 750 751 send_mbox: 752 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS; 753 mbx.sqs_alloc.vf_id = sqs->vf_id; 754 mbx.sqs_alloc.qs_count = alloc_qs; 755 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx); 756 } 757 758 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 759 { 760 int bgx_idx, lmac_idx; 761 762 if (lbk->vf_id >= nic->num_vf_en) 763 return -1; 764 765 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 766 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 767 768 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 769 770 /* Enable moving average calculation. 771 * Keep the LVL/AVG delay to HW enforced minimum so that, not too many 772 * packets sneek in between average calculations. 773 */ 774 nic_reg_write(nic, NIC_PF_CQ_AVG_CFG, 775 (BIT_ULL(20) | 0x2ull << 14 | 0x1)); 776 nic_reg_write(nic, NIC_PF_RRM_AVG_CFG, 777 (BIT_ULL(20) | 0x3ull << 14 | 0x1)); 778 779 return 0; 780 } 781 782 /* Reset statistics counters */ 783 static int nic_reset_stat_counters(struct nicpf *nic, 784 int vf, struct reset_stat_cfg *cfg) 785 { 786 int i, stat, qnum; 787 u64 reg_addr; 788 789 for (i = 0; i < RX_STATS_ENUM_LAST; i++) { 790 if (cfg->rx_stat_mask & BIT(i)) { 791 reg_addr = NIC_PF_VNIC_0_127_RX_STAT_0_13 | 792 (vf << NIC_QS_ID_SHIFT) | 793 (i << 3); 794 nic_reg_write(nic, reg_addr, 0); 795 } 796 } 797 798 for (i = 0; i < TX_STATS_ENUM_LAST; i++) { 799 if (cfg->tx_stat_mask & BIT(i)) { 800 reg_addr = NIC_PF_VNIC_0_127_TX_STAT_0_4 | 801 (vf << NIC_QS_ID_SHIFT) | 802 (i << 3); 803 nic_reg_write(nic, reg_addr, 0); 804 } 805 } 806 807 for (i = 0; i <= 15; i++) { 808 qnum = i >> 1; 809 stat = i & 1 ? 1 : 0; 810 reg_addr = (vf << NIC_QS_ID_SHIFT) | 811 (qnum << NIC_Q_NUM_SHIFT) | (stat << 3); 812 if (cfg->rq_stat_mask & BIT(i)) { 813 reg_addr |= NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1; 814 nic_reg_write(nic, reg_addr, 0); 815 } 816 if (cfg->sq_stat_mask & BIT(i)) { 817 reg_addr |= NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1; 818 nic_reg_write(nic, reg_addr, 0); 819 } 820 } 821 822 return 0; 823 } 824 825 static void nic_enable_tunnel_parsing(struct nicpf *nic, int vf) 826 { 827 u64 prot_def = (IPV6_PROT << 32) | (IPV4_PROT << 16) | ET_PROT; 828 u64 vxlan_prot_def = (IPV6_PROT_DEF << 32) | 829 (IPV4_PROT_DEF) << 16 | ET_PROT_DEF; 830 831 /* Configure tunnel parsing parameters */ 832 nic_reg_write(nic, NIC_PF_RX_GENEVE_DEF, 833 (1ULL << 63 | UDP_GENEVE_PORT_NUM)); 834 nic_reg_write(nic, NIC_PF_RX_GENEVE_PROT_DEF, 835 ((7ULL << 61) | prot_def)); 836 nic_reg_write(nic, NIC_PF_RX_NVGRE_PROT_DEF, 837 ((7ULL << 61) | prot_def)); 838 nic_reg_write(nic, NIC_PF_RX_VXLAN_DEF_0_1, 839 ((1ULL << 63) | UDP_VXLAN_PORT_NUM)); 840 nic_reg_write(nic, NIC_PF_RX_VXLAN_PROT_DEF, 841 ((0xfULL << 60) | vxlan_prot_def)); 842 } 843 844 static void nic_enable_vf(struct nicpf *nic, int vf, bool enable) 845 { 846 int bgx, lmac; 847 848 nic->vf_enabled[vf] = enable; 849 850 if (vf >= nic->num_vf_en) 851 return; 852 853 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 854 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 855 856 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, enable); 857 } 858 859 static void nic_pause_frame(struct nicpf *nic, int vf, struct pfc *cfg) 860 { 861 int bgx, lmac; 862 struct pfc pfc; 863 union nic_mbx mbx = {}; 864 865 if (vf >= nic->num_vf_en) 866 return; 867 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 868 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 869 870 if (cfg->get) { 871 bgx_lmac_get_pfc(nic->node, bgx, lmac, &pfc); 872 mbx.pfc.msg = NIC_MBOX_MSG_PFC; 873 mbx.pfc.autoneg = pfc.autoneg; 874 mbx.pfc.fc_rx = pfc.fc_rx; 875 mbx.pfc.fc_tx = pfc.fc_tx; 876 nic_send_msg_to_vf(nic, vf, &mbx); 877 } else { 878 bgx_lmac_set_pfc(nic->node, bgx, lmac, cfg); 879 nic_mbx_send_ack(nic, vf); 880 } 881 } 882 883 /* Interrupt handler to handle mailbox messages from VFs */ 884 static void nic_handle_mbx_intr(struct nicpf *nic, int vf) 885 { 886 union nic_mbx mbx = {}; 887 u64 *mbx_data; 888 u64 mbx_addr; 889 u64 reg_addr; 890 u64 cfg; 891 int bgx, lmac; 892 int i; 893 int ret = 0; 894 895 nic->mbx_lock[vf] = true; 896 897 mbx_addr = nic_get_mbx_addr(vf); 898 mbx_data = (u64 *)&mbx; 899 900 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 901 *mbx_data = nic_reg_read(nic, mbx_addr); 902 mbx_data++; 903 mbx_addr += sizeof(u64); 904 } 905 906 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg 0x%02x from VF%d\n", 907 __func__, mbx.msg.msg, vf); 908 switch (mbx.msg.msg) { 909 case NIC_MBOX_MSG_READY: 910 nic_mbx_send_ready(nic, vf); 911 if (vf < nic->num_vf_en) { 912 nic->link[vf] = 0; 913 nic->duplex[vf] = 0; 914 nic->speed[vf] = 0; 915 } 916 goto unlock; 917 case NIC_MBOX_MSG_QS_CFG: 918 reg_addr = NIC_PF_QSET_0_127_CFG | 919 (mbx.qs.num << NIC_QS_ID_SHIFT); 920 cfg = mbx.qs.cfg; 921 /* Check if its a secondary Qset */ 922 if (vf >= nic->num_vf_en) { 923 cfg = cfg & (~0x7FULL); 924 /* Assign this Qset to primary Qset's VF */ 925 cfg |= nic->pqs_vf[vf]; 926 } 927 nic_reg_write(nic, reg_addr, cfg); 928 break; 929 case NIC_MBOX_MSG_RQ_CFG: 930 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 931 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 932 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 933 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 934 /* Enable CQE_RX2_S extension in CQE_RX descriptor. 935 * This gets appended by default on 81xx/83xx chips, 936 * for consistency enabling the same on 88xx pass2 937 * where this is introduced. 938 */ 939 if (pass2_silicon(nic->pdev)) 940 nic_reg_write(nic, NIC_PF_RX_CFG, 0x01); 941 if (!pass1_silicon(nic->pdev)) 942 nic_enable_tunnel_parsing(nic, vf); 943 break; 944 case NIC_MBOX_MSG_RQ_BP_CFG: 945 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 946 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 947 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 948 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 949 break; 950 case NIC_MBOX_MSG_RQ_SW_SYNC: 951 ret = nic_rcv_queue_sw_sync(nic); 952 break; 953 case NIC_MBOX_MSG_RQ_DROP_CFG: 954 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 955 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 956 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 957 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 958 break; 959 case NIC_MBOX_MSG_SQ_CFG: 960 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 961 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 962 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 963 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 964 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 965 break; 966 case NIC_MBOX_MSG_SET_MAC: 967 if (vf >= nic->num_vf_en) { 968 ret = -1; /* NACK */ 969 break; 970 } 971 lmac = mbx.mac.vf_id; 972 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 973 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 974 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 975 break; 976 case NIC_MBOX_MSG_SET_MAX_FRS: 977 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, 978 mbx.frs.vf_id); 979 break; 980 case NIC_MBOX_MSG_CPI_CFG: 981 nic_config_cpi(nic, &mbx.cpi_cfg); 982 break; 983 case NIC_MBOX_MSG_RSS_SIZE: 984 nic_send_rss_size(nic, vf); 985 goto unlock; 986 case NIC_MBOX_MSG_RSS_CFG: 987 case NIC_MBOX_MSG_RSS_CFG_CONT: 988 nic_config_rss(nic, &mbx.rss_cfg); 989 break; 990 case NIC_MBOX_MSG_CFG_DONE: 991 /* Last message of VF config msg sequence */ 992 nic_enable_vf(nic, vf, true); 993 goto unlock; 994 case NIC_MBOX_MSG_SHUTDOWN: 995 /* First msg in VF teardown sequence */ 996 if (vf >= nic->num_vf_en) 997 nic->sqs_used[vf - nic->num_vf_en] = false; 998 nic->pqs_vf[vf] = 0; 999 nic_enable_vf(nic, vf, false); 1000 break; 1001 case NIC_MBOX_MSG_ALLOC_SQS: 1002 nic_alloc_sqs(nic, &mbx.sqs_alloc); 1003 goto unlock; 1004 case NIC_MBOX_MSG_NICVF_PTR: 1005 nic->nicvf[vf] = mbx.nicvf.nicvf; 1006 break; 1007 case NIC_MBOX_MSG_PNICVF_PTR: 1008 nic_send_pnicvf(nic, vf); 1009 goto unlock; 1010 case NIC_MBOX_MSG_SNICVF_PTR: 1011 nic_send_snicvf(nic, &mbx.nicvf); 1012 goto unlock; 1013 case NIC_MBOX_MSG_BGX_STATS: 1014 nic_get_bgx_stats(nic, &mbx.bgx_stats); 1015 goto unlock; 1016 case NIC_MBOX_MSG_LOOPBACK: 1017 ret = nic_config_loopback(nic, &mbx.lbk); 1018 break; 1019 case NIC_MBOX_MSG_RESET_STAT_COUNTER: 1020 ret = nic_reset_stat_counters(nic, vf, &mbx.reset_stat); 1021 break; 1022 case NIC_MBOX_MSG_PFC: 1023 nic_pause_frame(nic, vf, &mbx.pfc); 1024 goto unlock; 1025 default: 1026 dev_err(&nic->pdev->dev, 1027 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 1028 break; 1029 } 1030 1031 if (!ret) { 1032 nic_mbx_send_ack(nic, vf); 1033 } else if (mbx.msg.msg != NIC_MBOX_MSG_READY) { 1034 dev_err(&nic->pdev->dev, "NACK for MBOX 0x%02x from VF %d\n", 1035 mbx.msg.msg, vf); 1036 nic_mbx_send_nack(nic, vf); 1037 } 1038 unlock: 1039 nic->mbx_lock[vf] = false; 1040 } 1041 1042 static irqreturn_t nic_mbx_intr_handler(int irq, void *nic_irq) 1043 { 1044 struct nicpf *nic = (struct nicpf *)nic_irq; 1045 int mbx; 1046 u64 intr; 1047 u8 vf, vf_per_mbx_reg = 64; 1048 1049 if (irq == pci_irq_vector(nic->pdev, NIC_PF_INTR_ID_MBOX0)) 1050 mbx = 0; 1051 else 1052 mbx = 1; 1053 1054 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 1055 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr); 1056 for (vf = 0; vf < vf_per_mbx_reg; vf++) { 1057 if (intr & (1ULL << vf)) { 1058 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n", 1059 vf + (mbx * vf_per_mbx_reg)); 1060 1061 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); 1062 nic_clear_mbx_intr(nic, vf, mbx); 1063 } 1064 } 1065 return IRQ_HANDLED; 1066 } 1067 1068 static void nic_free_all_interrupts(struct nicpf *nic) 1069 { 1070 int irq; 1071 1072 for (irq = 0; irq < nic->num_vec; irq++) { 1073 if (nic->irq_allocated[irq]) 1074 free_irq(pci_irq_vector(nic->pdev, irq), nic); 1075 nic->irq_allocated[irq] = false; 1076 } 1077 } 1078 1079 static int nic_register_interrupts(struct nicpf *nic) 1080 { 1081 int i, ret; 1082 nic->num_vec = pci_msix_vec_count(nic->pdev); 1083 1084 /* Enable MSI-X */ 1085 ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec, 1086 PCI_IRQ_MSIX); 1087 if (ret < 0) { 1088 dev_err(&nic->pdev->dev, 1089 "Request for #%d msix vectors failed, returned %d\n", 1090 nic->num_vec, ret); 1091 return 1; 1092 } 1093 1094 /* Register mailbox interrupt handler */ 1095 for (i = NIC_PF_INTR_ID_MBOX0; i < nic->num_vec; i++) { 1096 sprintf(nic->irq_name[i], 1097 "NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0)); 1098 1099 ret = request_irq(pci_irq_vector(nic->pdev, i), 1100 nic_mbx_intr_handler, 0, 1101 nic->irq_name[i], nic); 1102 if (ret) 1103 goto fail; 1104 1105 nic->irq_allocated[i] = true; 1106 } 1107 1108 /* Enable mailbox interrupt */ 1109 nic_enable_mbx_intr(nic); 1110 return 0; 1111 1112 fail: 1113 dev_err(&nic->pdev->dev, "Request irq failed\n"); 1114 nic_free_all_interrupts(nic); 1115 pci_free_irq_vectors(nic->pdev); 1116 nic->num_vec = 0; 1117 return ret; 1118 } 1119 1120 static void nic_unregister_interrupts(struct nicpf *nic) 1121 { 1122 nic_free_all_interrupts(nic); 1123 pci_free_irq_vectors(nic->pdev); 1124 nic->num_vec = 0; 1125 } 1126 1127 static int nic_num_sqs_en(struct nicpf *nic, int vf_en) 1128 { 1129 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE; 1130 u16 total_vf; 1131 1132 /* Secondary Qsets are needed only if CPU count is 1133 * morethan MAX_QUEUES_PER_QSET. 1134 */ 1135 if (num_online_cpus() <= MAX_QUEUES_PER_QSET) 1136 return 0; 1137 1138 /* Check if its a multi-node environment */ 1139 if (nr_node_ids > 1) 1140 sqs_per_vf = MAX_SQS_PER_VF; 1141 1142 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV); 1143 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf); 1144 return min(total_vf - vf_en, vf_en * sqs_per_vf); 1145 } 1146 1147 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic) 1148 { 1149 int pos = 0; 1150 int vf_en; 1151 int err; 1152 u16 total_vf_cnt; 1153 1154 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 1155 if (!pos) { 1156 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n"); 1157 return -ENODEV; 1158 } 1159 1160 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt); 1161 if (total_vf_cnt < nic->num_vf_en) 1162 nic->num_vf_en = total_vf_cnt; 1163 1164 if (!total_vf_cnt) 1165 return 0; 1166 1167 vf_en = nic->num_vf_en; 1168 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en); 1169 vf_en += nic->num_sqs_en; 1170 1171 err = pci_enable_sriov(pdev, vf_en); 1172 if (err) { 1173 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n", 1174 vf_en); 1175 nic->num_vf_en = 0; 1176 return err; 1177 } 1178 1179 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n", 1180 vf_en); 1181 1182 nic->flags |= NIC_SRIOV_ENABLED; 1183 return 0; 1184 } 1185 1186 /* Poll for BGX LMAC link status and update corresponding VF 1187 * if there is a change, valid only if internal L2 switch 1188 * is not present otherwise VF link is always treated as up 1189 */ 1190 static void nic_poll_for_link(struct work_struct *work) 1191 { 1192 union nic_mbx mbx = {}; 1193 struct nicpf *nic; 1194 struct bgx_link_status link; 1195 u8 vf, bgx, lmac; 1196 1197 nic = container_of(work, struct nicpf, dwork.work); 1198 1199 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 1200 1201 for (vf = 0; vf < nic->num_vf_en; vf++) { 1202 /* Poll only if VF is UP */ 1203 if (!nic->vf_enabled[vf]) 1204 continue; 1205 1206 /* Get BGX, LMAC indices for the VF */ 1207 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1208 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1209 /* Get interface link status */ 1210 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 1211 1212 /* Inform VF only if link status changed */ 1213 if (nic->link[vf] == link.link_up) 1214 continue; 1215 1216 if (!nic->mbx_lock[vf]) { 1217 nic->link[vf] = link.link_up; 1218 nic->duplex[vf] = link.duplex; 1219 nic->speed[vf] = link.speed; 1220 1221 /* Send a mbox message to VF with current link status */ 1222 mbx.link_status.link_up = link.link_up; 1223 mbx.link_status.duplex = link.duplex; 1224 mbx.link_status.speed = link.speed; 1225 mbx.link_status.mac_type = link.mac_type; 1226 nic_send_msg_to_vf(nic, vf, &mbx); 1227 } 1228 } 1229 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2); 1230 } 1231 1232 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1233 { 1234 struct device *dev = &pdev->dev; 1235 struct nicpf *nic; 1236 u8 max_lmac; 1237 int err; 1238 1239 BUILD_BUG_ON(sizeof(union nic_mbx) > 16); 1240 1241 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL); 1242 if (!nic) 1243 return -ENOMEM; 1244 1245 nic->hw = devm_kzalloc(dev, sizeof(struct hw_info), GFP_KERNEL); 1246 if (!nic->hw) 1247 return -ENOMEM; 1248 1249 pci_set_drvdata(pdev, nic); 1250 1251 nic->pdev = pdev; 1252 1253 err = pci_enable_device(pdev); 1254 if (err) { 1255 dev_err(dev, "Failed to enable PCI device\n"); 1256 pci_set_drvdata(pdev, NULL); 1257 return err; 1258 } 1259 1260 err = pci_request_regions(pdev, DRV_NAME); 1261 if (err) { 1262 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1263 goto err_disable_device; 1264 } 1265 1266 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 1267 if (err) { 1268 dev_err(dev, "Unable to get usable DMA configuration\n"); 1269 goto err_release_regions; 1270 } 1271 1272 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 1273 if (err) { 1274 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n"); 1275 goto err_release_regions; 1276 } 1277 1278 /* MAP PF's configuration registers */ 1279 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1280 if (!nic->reg_base) { 1281 dev_err(dev, "Cannot map config register space, aborting\n"); 1282 err = -ENOMEM; 1283 goto err_release_regions; 1284 } 1285 1286 nic->node = nic_get_node_id(pdev); 1287 1288 /* Get HW capability info */ 1289 nic_get_hw_info(nic); 1290 1291 /* Allocate memory for LMAC tracking elements */ 1292 err = -ENOMEM; 1293 max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX; 1294 1295 nic->vf_lmac_map = devm_kmalloc_array(dev, max_lmac, sizeof(u8), 1296 GFP_KERNEL); 1297 if (!nic->vf_lmac_map) 1298 goto err_release_regions; 1299 1300 nic->link = devm_kmalloc_array(dev, max_lmac, sizeof(u8), GFP_KERNEL); 1301 if (!nic->link) 1302 goto err_release_regions; 1303 1304 nic->duplex = devm_kmalloc_array(dev, max_lmac, sizeof(u8), GFP_KERNEL); 1305 if (!nic->duplex) 1306 goto err_release_regions; 1307 1308 nic->speed = devm_kmalloc_array(dev, max_lmac, sizeof(u32), GFP_KERNEL); 1309 if (!nic->speed) 1310 goto err_release_regions; 1311 1312 /* Initialize hardware */ 1313 nic_init_hw(nic); 1314 1315 nic_set_lmac_vf_mapping(nic); 1316 1317 /* Register interrupts */ 1318 err = nic_register_interrupts(nic); 1319 if (err) 1320 goto err_release_regions; 1321 1322 /* Configure SRIOV */ 1323 err = nic_sriov_init(pdev, nic); 1324 if (err) 1325 goto err_unregister_interrupts; 1326 1327 /* Register a physical link status poll fn() */ 1328 nic->check_link = alloc_workqueue("check_link_status", 1329 WQ_UNBOUND | WQ_MEM_RECLAIM, 1); 1330 if (!nic->check_link) { 1331 err = -ENOMEM; 1332 goto err_disable_sriov; 1333 } 1334 1335 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link); 1336 queue_delayed_work(nic->check_link, &nic->dwork, 0); 1337 1338 return 0; 1339 1340 err_disable_sriov: 1341 if (nic->flags & NIC_SRIOV_ENABLED) 1342 pci_disable_sriov(pdev); 1343 err_unregister_interrupts: 1344 nic_unregister_interrupts(nic); 1345 err_release_regions: 1346 pci_release_regions(pdev); 1347 err_disable_device: 1348 pci_disable_device(pdev); 1349 pci_set_drvdata(pdev, NULL); 1350 return err; 1351 } 1352 1353 static void nic_remove(struct pci_dev *pdev) 1354 { 1355 struct nicpf *nic = pci_get_drvdata(pdev); 1356 1357 if (nic->flags & NIC_SRIOV_ENABLED) 1358 pci_disable_sriov(pdev); 1359 1360 if (nic->check_link) { 1361 /* Destroy work Queue */ 1362 cancel_delayed_work_sync(&nic->dwork); 1363 destroy_workqueue(nic->check_link); 1364 } 1365 1366 nic_unregister_interrupts(nic); 1367 pci_release_regions(pdev); 1368 1369 pci_disable_device(pdev); 1370 pci_set_drvdata(pdev, NULL); 1371 } 1372 1373 static struct pci_driver nic_driver = { 1374 .name = DRV_NAME, 1375 .id_table = nic_id_table, 1376 .probe = nic_probe, 1377 .remove = nic_remove, 1378 }; 1379 1380 static int __init nic_init_module(void) 1381 { 1382 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION); 1383 1384 return pci_register_driver(&nic_driver); 1385 } 1386 1387 static void __exit nic_cleanup_module(void) 1388 { 1389 pci_unregister_driver(&nic_driver); 1390 } 1391 1392 module_init(nic_init_module); 1393 module_exit(nic_cleanup_module); 1394