1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef NIC_H 10 #define NIC_H 11 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include "thunder_bgx.h" 16 17 /* PCI device IDs */ 18 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 19 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 20 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 21 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 22 23 /* PCI BAR nos */ 24 #define PCI_CFG_REG_BAR_NUM 0 25 #define PCI_MSIX_REG_BAR_NUM 4 26 27 /* NIC SRIOV VF count */ 28 #define MAX_NUM_VFS_SUPPORTED 128 29 #define DEFAULT_NUM_VF_ENABLED 8 30 31 #define NIC_TNS_BYPASS_MODE 0 32 #define NIC_TNS_MODE 1 33 34 /* NIC priv flags */ 35 #define NIC_SRIOV_ENABLED BIT(0) 36 37 /* Min/Max packet size */ 38 #define NIC_HW_MIN_FRS 64 39 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 40 41 /* Max pkinds */ 42 #define NIC_MAX_PKIND 16 43 44 /* Rx Channels */ 45 /* Receive channel configuration in TNS bypass mode 46 * Below is configuration in TNS bypass mode 47 * BGX0-LMAC0-CHAN0 - VNIC CHAN0 48 * BGX0-LMAC1-CHAN0 - VNIC CHAN16 49 * ... 50 * BGX1-LMAC0-CHAN0 - VNIC CHAN128 51 * ... 52 * BGX1-LMAC3-CHAN0 - VNIC CHAN174 53 */ 54 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ 55 #define NIC_CHANS_PER_INF 128 56 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) 57 #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ 58 59 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ 60 #define NIC_MAX_BGX MAX_BGX_PER_CN88XX 61 #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) 62 #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ 63 #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) 64 65 /* Tx scheduling */ 66 #define NIC_MAX_TL4 1024 67 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ 68 #define NIC_MAX_TL3 256 69 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ 70 #define NIC_MAX_TL2 64 71 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ 72 #define NIC_MAX_TL1 2 73 74 /* TNS bypass mode */ 75 #define NIC_TL2_PER_BGX 32 76 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) 77 #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) 78 79 /* NIC VF Interrupts */ 80 #define NICVF_INTR_CQ 0 81 #define NICVF_INTR_SQ 1 82 #define NICVF_INTR_RBDR 2 83 #define NICVF_INTR_PKT_DROP 3 84 #define NICVF_INTR_TCP_TIMER 4 85 #define NICVF_INTR_MBOX 5 86 #define NICVF_INTR_QS_ERR 6 87 88 #define NICVF_INTR_CQ_SHIFT 0 89 #define NICVF_INTR_SQ_SHIFT 8 90 #define NICVF_INTR_RBDR_SHIFT 16 91 #define NICVF_INTR_PKT_DROP_SHIFT 20 92 #define NICVF_INTR_TCP_TIMER_SHIFT 21 93 #define NICVF_INTR_MBOX_SHIFT 22 94 #define NICVF_INTR_QS_ERR_SHIFT 23 95 96 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 97 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 98 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 99 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 100 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 101 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 102 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 103 104 /* MSI-X interrupts */ 105 #define NIC_PF_MSIX_VECTORS 10 106 #define NIC_VF_MSIX_VECTORS 20 107 108 #define NIC_PF_INTR_ID_ECC0_SBE 0 109 #define NIC_PF_INTR_ID_ECC0_DBE 1 110 #define NIC_PF_INTR_ID_ECC1_SBE 2 111 #define NIC_PF_INTR_ID_ECC1_DBE 3 112 #define NIC_PF_INTR_ID_ECC2_SBE 4 113 #define NIC_PF_INTR_ID_ECC2_DBE 5 114 #define NIC_PF_INTR_ID_ECC3_SBE 6 115 #define NIC_PF_INTR_ID_ECC3_DBE 7 116 #define NIC_PF_INTR_ID_MBOX0 8 117 #define NIC_PF_INTR_ID_MBOX1 9 118 119 /* Global timer for CQ timer thresh interrupts 120 * Calculated for SCLK of 700Mhz 121 * value written should be a 1/16th of what is expected 122 * 123 * 1 tick per 0.025usec 124 */ 125 #define NICPF_CLK_PER_INT_TICK 1 126 127 /* Time to wait before we decide that a SQ is stuck. 128 * 129 * Since both pkt rx and tx notifications are done with same CQ, 130 * when packets are being received at very high rate (eg: L2 forwarding) 131 * then freeing transmitted skbs will be delayed and watchdog 132 * will kick in, resetting interface. Hence keeping this value high. 133 */ 134 #define NICVF_TX_TIMEOUT (50 * HZ) 135 136 struct nicvf_cq_poll { 137 struct nicvf *nicvf; 138 u8 cq_idx; /* Completion queue index */ 139 struct napi_struct napi; 140 }; 141 142 #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ 143 #define NIC_MAX_RSS_HASH_BITS 8 144 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 145 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 146 147 struct nicvf_rss_info { 148 bool enable; 149 #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 150 #define RSS_IP_HASH_ENA BIT(1) 151 #define RSS_TCP_HASH_ENA BIT(2) 152 #define RSS_TCP_SYN_DIS BIT(3) 153 #define RSS_UDP_HASH_ENA BIT(4) 154 #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 155 #define RSS_ROCE_ENA BIT(6) 156 #define RSS_L3_BI_DIRECTION_ENA BIT(7) 157 #define RSS_L4_BI_DIRECTION_ENA BIT(8) 158 u64 cfg; 159 u8 hash_bits; 160 u16 rss_size; 161 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 162 u64 key[RSS_HASH_KEY_SIZE]; 163 } ____cacheline_aligned_in_smp; 164 165 enum rx_stats_reg_offset { 166 RX_OCTS = 0x0, 167 RX_UCAST = 0x1, 168 RX_BCAST = 0x2, 169 RX_MCAST = 0x3, 170 RX_RED = 0x4, 171 RX_RED_OCTS = 0x5, 172 RX_ORUN = 0x6, 173 RX_ORUN_OCTS = 0x7, 174 RX_FCS = 0x8, 175 RX_L2ERR = 0x9, 176 RX_DRP_BCAST = 0xa, 177 RX_DRP_MCAST = 0xb, 178 RX_DRP_L3BCAST = 0xc, 179 RX_DRP_L3MCAST = 0xd, 180 RX_STATS_ENUM_LAST, 181 }; 182 183 enum tx_stats_reg_offset { 184 TX_OCTS = 0x0, 185 TX_UCAST = 0x1, 186 TX_BCAST = 0x2, 187 TX_MCAST = 0x3, 188 TX_DROP = 0x4, 189 TX_STATS_ENUM_LAST, 190 }; 191 192 struct nicvf_hw_stats { 193 u64 rx_bytes; 194 u64 rx_ucast_frames; 195 u64 rx_bcast_frames; 196 u64 rx_mcast_frames; 197 u64 rx_fcs_errors; 198 u64 rx_l2_errors; 199 u64 rx_drop_red; 200 u64 rx_drop_red_bytes; 201 u64 rx_drop_overrun; 202 u64 rx_drop_overrun_bytes; 203 u64 rx_drop_bcast; 204 u64 rx_drop_mcast; 205 u64 rx_drop_l3_bcast; 206 u64 rx_drop_l3_mcast; 207 u64 rx_bgx_truncated_pkts; 208 u64 rx_jabber_errs; 209 u64 rx_fcs_errs; 210 u64 rx_bgx_errs; 211 u64 rx_prel2_errs; 212 u64 rx_l2_hdr_malformed; 213 u64 rx_oversize; 214 u64 rx_undersize; 215 u64 rx_l2_len_mismatch; 216 u64 rx_l2_pclp; 217 u64 rx_ip_ver_errs; 218 u64 rx_ip_csum_errs; 219 u64 rx_ip_hdr_malformed; 220 u64 rx_ip_payload_malformed; 221 u64 rx_ip_ttl_errs; 222 u64 rx_l3_pclp; 223 u64 rx_l4_malformed; 224 u64 rx_l4_csum_errs; 225 u64 rx_udp_len_errs; 226 u64 rx_l4_port_errs; 227 u64 rx_tcp_flag_errs; 228 u64 rx_tcp_offset_errs; 229 u64 rx_l4_pclp; 230 u64 rx_truncated_pkts; 231 232 u64 tx_bytes_ok; 233 u64 tx_ucast_frames_ok; 234 u64 tx_bcast_frames_ok; 235 u64 tx_mcast_frames_ok; 236 u64 tx_drops; 237 }; 238 239 struct nicvf_drv_stats { 240 /* Rx */ 241 u64 rx_frames_ok; 242 u64 rx_frames_64; 243 u64 rx_frames_127; 244 u64 rx_frames_255; 245 u64 rx_frames_511; 246 u64 rx_frames_1023; 247 u64 rx_frames_1518; 248 u64 rx_frames_jumbo; 249 u64 rx_drops; 250 251 /* Tx */ 252 u64 tx_frames_ok; 253 u64 tx_drops; 254 u64 tx_tso; 255 u64 txq_stop; 256 u64 txq_wake; 257 }; 258 259 struct nicvf { 260 struct nicvf *pnicvf; 261 struct net_device *netdev; 262 struct pci_dev *pdev; 263 u8 vf_id; 264 u8 node; 265 u8 tns_mode:1; 266 u8 sqs_mode:1; 267 u8 loopback_supported:1; 268 u16 mtu; 269 struct queue_set *qs; 270 #define MAX_SQS_PER_VF_SINGLE_NODE 5 271 #define MAX_SQS_PER_VF 11 272 u8 sqs_id; 273 u8 sqs_count; /* Secondary Qset count */ 274 struct nicvf *snicvf[MAX_SQS_PER_VF]; 275 u8 rx_queues; 276 u8 tx_queues; 277 u8 max_queues; 278 void __iomem *reg_base; 279 bool link_up; 280 u8 duplex; 281 u32 speed; 282 struct page *rb_page; 283 u32 rb_page_offset; 284 bool rb_alloc_fail; 285 bool rb_work_scheduled; 286 struct delayed_work rbdr_work; 287 struct tasklet_struct rbdr_task; 288 struct tasklet_struct qs_err_task; 289 struct tasklet_struct cq_task; 290 struct nicvf_cq_poll *napi[8]; 291 struct nicvf_rss_info rss_info; 292 u8 cpi_alg; 293 /* Interrupt coalescing settings */ 294 u32 cq_coalesce_usecs; 295 296 u32 msg_enable; 297 struct nicvf_hw_stats hw_stats; 298 struct nicvf_drv_stats drv_stats; 299 struct bgx_stats bgx_stats; 300 struct work_struct reset_task; 301 302 /* MSI-X */ 303 bool msix_enabled; 304 u8 num_vec; 305 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 306 char irq_name[NIC_VF_MSIX_VECTORS][20]; 307 bool irq_allocated[NIC_VF_MSIX_VECTORS]; 308 309 /* VF <-> PF mailbox communication */ 310 bool pf_acked; 311 bool pf_nacked; 312 bool set_mac_pending; 313 } ____cacheline_aligned_in_smp; 314 315 /* PF <--> VF Mailbox communication 316 * Eight 64bit registers are shared between PF and VF. 317 * Separate set for each VF. 318 * Writing '1' into last register mbx7 means end of message. 319 */ 320 321 /* PF <--> VF mailbox communication */ 322 #define NIC_PF_VF_MAILBOX_SIZE 2 323 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 324 325 /* Mailbox message types */ 326 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 327 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 328 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 329 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 330 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 331 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 332 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 333 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 334 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 335 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 336 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 337 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 338 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 339 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 340 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 341 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 342 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 343 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 344 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 345 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 346 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 347 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 348 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 349 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 350 351 struct nic_cfg_msg { 352 u8 msg; 353 u8 vf_id; 354 u8 node_id; 355 u8 tns_mode:1; 356 u8 sqs_mode:1; 357 u8 loopback_supported:1; 358 u8 mac_addr[ETH_ALEN]; 359 }; 360 361 /* Qset configuration */ 362 struct qs_cfg_msg { 363 u8 msg; 364 u8 num; 365 u8 sqs_count; 366 u64 cfg; 367 }; 368 369 /* Receive queue configuration */ 370 struct rq_cfg_msg { 371 u8 msg; 372 u8 qs_num; 373 u8 rq_num; 374 u64 cfg; 375 }; 376 377 /* Send queue configuration */ 378 struct sq_cfg_msg { 379 u8 msg; 380 u8 qs_num; 381 u8 sq_num; 382 bool sqs_mode; 383 u64 cfg; 384 }; 385 386 /* Set VF's MAC address */ 387 struct set_mac_msg { 388 u8 msg; 389 u8 vf_id; 390 u8 mac_addr[ETH_ALEN]; 391 }; 392 393 /* Set Maximum frame size */ 394 struct set_frs_msg { 395 u8 msg; 396 u8 vf_id; 397 u16 max_frs; 398 }; 399 400 /* Set CPI algorithm type */ 401 struct cpi_cfg_msg { 402 u8 msg; 403 u8 vf_id; 404 u8 rq_cnt; 405 u8 cpi_alg; 406 }; 407 408 /* Get RSS table size */ 409 struct rss_sz_msg { 410 u8 msg; 411 u8 vf_id; 412 u16 ind_tbl_size; 413 }; 414 415 /* Set RSS configuration */ 416 struct rss_cfg_msg { 417 u8 msg; 418 u8 vf_id; 419 u8 hash_bits; 420 u8 tbl_len; 421 u8 tbl_offset; 422 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 423 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 424 }; 425 426 struct bgx_stats_msg { 427 u8 msg; 428 u8 vf_id; 429 u8 rx; 430 u8 idx; 431 u64 stats; 432 }; 433 434 /* Physical interface link status */ 435 struct bgx_link_status { 436 u8 msg; 437 u8 link_up; 438 u8 duplex; 439 u32 speed; 440 }; 441 442 /* Get Extra Qset IDs */ 443 struct sqs_alloc { 444 u8 msg; 445 u8 vf_id; 446 u8 qs_count; 447 }; 448 449 struct nicvf_ptr { 450 u8 msg; 451 u8 vf_id; 452 bool sqs_mode; 453 u8 sqs_id; 454 u64 nicvf; 455 }; 456 457 /* Set interface in loopback mode */ 458 struct set_loopback { 459 u8 msg; 460 u8 vf_id; 461 bool enable; 462 }; 463 464 /* 128 bit shared memory between PF and each VF */ 465 union nic_mbx { 466 struct { u8 msg; } msg; 467 struct nic_cfg_msg nic_cfg; 468 struct qs_cfg_msg qs; 469 struct rq_cfg_msg rq; 470 struct sq_cfg_msg sq; 471 struct set_mac_msg mac; 472 struct set_frs_msg frs; 473 struct cpi_cfg_msg cpi_cfg; 474 struct rss_sz_msg rss_size; 475 struct rss_cfg_msg rss_cfg; 476 struct bgx_stats_msg bgx_stats; 477 struct bgx_link_status link_status; 478 struct sqs_alloc sqs_alloc; 479 struct nicvf_ptr nicvf; 480 struct set_loopback lbk; 481 }; 482 483 #define NIC_NODE_ID_MASK 0x03 484 #define NIC_NODE_ID_SHIFT 44 485 486 static inline int nic_get_node_id(struct pci_dev *pdev) 487 { 488 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 489 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 490 } 491 492 int nicvf_set_real_num_queues(struct net_device *netdev, 493 int tx_queues, int rx_queues); 494 int nicvf_open(struct net_device *netdev); 495 int nicvf_stop(struct net_device *netdev); 496 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 497 void nicvf_config_rss(struct nicvf *nic); 498 void nicvf_set_rss_key(struct nicvf *nic); 499 void nicvf_set_ethtool_ops(struct net_device *netdev); 500 void nicvf_update_stats(struct nicvf *nic); 501 void nicvf_update_lmac_stats(struct nicvf *nic); 502 503 #endif /* NIC_H */ 504