1 /* 2 * Copyright (C) 2015 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef NIC_H 10 #define NIC_H 11 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include "thunder_bgx.h" 16 17 /* PCI device IDs */ 18 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 19 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 20 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 21 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 22 23 /* PCI BAR nos */ 24 #define PCI_CFG_REG_BAR_NUM 0 25 #define PCI_MSIX_REG_BAR_NUM 4 26 27 /* NIC SRIOV VF count */ 28 #define MAX_NUM_VFS_SUPPORTED 128 29 #define DEFAULT_NUM_VF_ENABLED 8 30 31 #define NIC_TNS_BYPASS_MODE 0 32 #define NIC_TNS_MODE 1 33 34 /* NIC priv flags */ 35 #define NIC_SRIOV_ENABLED BIT(0) 36 37 /* Min/Max packet size */ 38 #define NIC_HW_MIN_FRS 64 39 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 40 41 /* Max pkinds */ 42 #define NIC_MAX_PKIND 16 43 44 /* Rx Channels */ 45 /* Receive channel configuration in TNS bypass mode 46 * Below is configuration in TNS bypass mode 47 * BGX0-LMAC0-CHAN0 - VNIC CHAN0 48 * BGX0-LMAC1-CHAN0 - VNIC CHAN16 49 * ... 50 * BGX1-LMAC0-CHAN0 - VNIC CHAN128 51 * ... 52 * BGX1-LMAC3-CHAN0 - VNIC CHAN174 53 */ 54 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ 55 #define NIC_CHANS_PER_INF 128 56 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) 57 #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ 58 59 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ 60 #define NIC_MAX_BGX MAX_BGX_PER_CN88XX 61 #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) 62 #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ 63 #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) 64 65 /* Tx scheduling */ 66 #define NIC_MAX_TL4 1024 67 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ 68 #define NIC_MAX_TL3 256 69 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ 70 #define NIC_MAX_TL2 64 71 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ 72 #define NIC_MAX_TL1 2 73 74 /* TNS bypass mode */ 75 #define NIC_TL2_PER_BGX 32 76 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) 77 #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) 78 79 /* NIC VF Interrupts */ 80 #define NICVF_INTR_CQ 0 81 #define NICVF_INTR_SQ 1 82 #define NICVF_INTR_RBDR 2 83 #define NICVF_INTR_PKT_DROP 3 84 #define NICVF_INTR_TCP_TIMER 4 85 #define NICVF_INTR_MBOX 5 86 #define NICVF_INTR_QS_ERR 6 87 88 #define NICVF_INTR_CQ_SHIFT 0 89 #define NICVF_INTR_SQ_SHIFT 8 90 #define NICVF_INTR_RBDR_SHIFT 16 91 #define NICVF_INTR_PKT_DROP_SHIFT 20 92 #define NICVF_INTR_TCP_TIMER_SHIFT 21 93 #define NICVF_INTR_MBOX_SHIFT 22 94 #define NICVF_INTR_QS_ERR_SHIFT 23 95 96 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 97 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 98 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 99 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 100 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 101 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 102 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 103 104 /* MSI-X interrupts */ 105 #define NIC_PF_MSIX_VECTORS 10 106 #define NIC_VF_MSIX_VECTORS 20 107 108 #define NIC_PF_INTR_ID_ECC0_SBE 0 109 #define NIC_PF_INTR_ID_ECC0_DBE 1 110 #define NIC_PF_INTR_ID_ECC1_SBE 2 111 #define NIC_PF_INTR_ID_ECC1_DBE 3 112 #define NIC_PF_INTR_ID_ECC2_SBE 4 113 #define NIC_PF_INTR_ID_ECC2_DBE 5 114 #define NIC_PF_INTR_ID_ECC3_SBE 6 115 #define NIC_PF_INTR_ID_ECC3_DBE 7 116 #define NIC_PF_INTR_ID_MBOX0 8 117 #define NIC_PF_INTR_ID_MBOX1 9 118 119 /* Global timer for CQ timer thresh interrupts 120 * Calculated for SCLK of 700Mhz 121 * value written should be a 1/16th of what is expected 122 * 123 * 1 tick per 0.05usec = value of 2.2 124 * This 10% would be covered in CQ timer thresh value 125 */ 126 #define NICPF_CLK_PER_INT_TICK 2 127 128 struct nicvf_cq_poll { 129 u8 cq_idx; /* Completion queue index */ 130 struct napi_struct napi; 131 }; 132 133 #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ 134 #define NIC_MAX_RSS_HASH_BITS 8 135 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 136 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 137 138 struct nicvf_rss_info { 139 bool enable; 140 #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 141 #define RSS_IP_HASH_ENA BIT(1) 142 #define RSS_TCP_HASH_ENA BIT(2) 143 #define RSS_TCP_SYN_DIS BIT(3) 144 #define RSS_UDP_HASH_ENA BIT(4) 145 #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 146 #define RSS_ROCE_ENA BIT(6) 147 #define RSS_L3_BI_DIRECTION_ENA BIT(7) 148 #define RSS_L4_BI_DIRECTION_ENA BIT(8) 149 u64 cfg; 150 u8 hash_bits; 151 u16 rss_size; 152 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 153 u64 key[RSS_HASH_KEY_SIZE]; 154 } ____cacheline_aligned_in_smp; 155 156 enum rx_stats_reg_offset { 157 RX_OCTS = 0x0, 158 RX_UCAST = 0x1, 159 RX_BCAST = 0x2, 160 RX_MCAST = 0x3, 161 RX_RED = 0x4, 162 RX_RED_OCTS = 0x5, 163 RX_ORUN = 0x6, 164 RX_ORUN_OCTS = 0x7, 165 RX_FCS = 0x8, 166 RX_L2ERR = 0x9, 167 RX_DRP_BCAST = 0xa, 168 RX_DRP_MCAST = 0xb, 169 RX_DRP_L3BCAST = 0xc, 170 RX_DRP_L3MCAST = 0xd, 171 RX_STATS_ENUM_LAST, 172 }; 173 174 enum tx_stats_reg_offset { 175 TX_OCTS = 0x0, 176 TX_UCAST = 0x1, 177 TX_BCAST = 0x2, 178 TX_MCAST = 0x3, 179 TX_DROP = 0x4, 180 TX_STATS_ENUM_LAST, 181 }; 182 183 struct nicvf_hw_stats { 184 u64 rx_bytes_ok; 185 u64 rx_ucast_frames_ok; 186 u64 rx_bcast_frames_ok; 187 u64 rx_mcast_frames_ok; 188 u64 rx_fcs_errors; 189 u64 rx_l2_errors; 190 u64 rx_drop_red; 191 u64 rx_drop_red_bytes; 192 u64 rx_drop_overrun; 193 u64 rx_drop_overrun_bytes; 194 u64 rx_drop_bcast; 195 u64 rx_drop_mcast; 196 u64 rx_drop_l3_bcast; 197 u64 rx_drop_l3_mcast; 198 u64 tx_bytes_ok; 199 u64 tx_ucast_frames_ok; 200 u64 tx_bcast_frames_ok; 201 u64 tx_mcast_frames_ok; 202 u64 tx_drops; 203 }; 204 205 struct nicvf_drv_stats { 206 /* Rx */ 207 u64 rx_frames_ok; 208 u64 rx_frames_64; 209 u64 rx_frames_127; 210 u64 rx_frames_255; 211 u64 rx_frames_511; 212 u64 rx_frames_1023; 213 u64 rx_frames_1518; 214 u64 rx_frames_jumbo; 215 u64 rx_drops; 216 /* Tx */ 217 u64 tx_frames_ok; 218 u64 tx_drops; 219 u64 tx_busy; 220 u64 tx_tso; 221 }; 222 223 struct nicvf { 224 struct net_device *netdev; 225 struct pci_dev *pdev; 226 u8 vf_id; 227 u8 node; 228 u8 tns_mode; 229 u16 mtu; 230 struct queue_set *qs; 231 void __iomem *reg_base; 232 bool link_up; 233 u8 duplex; 234 u32 speed; 235 struct page *rb_page; 236 u32 rb_page_offset; 237 bool rb_alloc_fail; 238 bool rb_work_scheduled; 239 struct delayed_work rbdr_work; 240 struct tasklet_struct rbdr_task; 241 struct tasklet_struct qs_err_task; 242 struct tasklet_struct cq_task; 243 struct nicvf_cq_poll *napi[8]; 244 struct nicvf_rss_info rss_info; 245 u8 cpi_alg; 246 /* Interrupt coalescing settings */ 247 u32 cq_coalesce_usecs; 248 249 u32 msg_enable; 250 struct nicvf_hw_stats stats; 251 struct nicvf_drv_stats drv_stats; 252 struct bgx_stats bgx_stats; 253 struct work_struct reset_task; 254 255 /* MSI-X */ 256 bool msix_enabled; 257 u8 num_vec; 258 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 259 char irq_name[NIC_VF_MSIX_VECTORS][20]; 260 bool irq_allocated[NIC_VF_MSIX_VECTORS]; 261 262 bool pf_ready_to_rcv_msg; 263 bool pf_acked; 264 bool pf_nacked; 265 bool bgx_stats_acked; 266 bool set_mac_pending; 267 } ____cacheline_aligned_in_smp; 268 269 /* PF <--> VF Mailbox communication 270 * Eight 64bit registers are shared between PF and VF. 271 * Separate set for each VF. 272 * Writing '1' into last register mbx7 means end of message. 273 */ 274 275 /* PF <--> VF mailbox communication */ 276 #define NIC_PF_VF_MAILBOX_SIZE 2 277 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 278 279 /* Mailbox message types */ 280 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 281 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 282 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 283 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 284 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 285 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 286 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 287 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 288 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 289 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 290 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 291 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 292 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 293 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 294 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 295 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 296 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 297 #define NIC_MBOX_MSG_CFG_DONE 0x12 /* VF configuration done */ 298 #define NIC_MBOX_MSG_SHUTDOWN 0x13 /* VF is being shutdown */ 299 300 struct nic_cfg_msg { 301 u8 msg; 302 u8 vf_id; 303 u8 tns_mode; 304 u8 node_id; 305 u8 mac_addr[ETH_ALEN]; 306 }; 307 308 /* Qset configuration */ 309 struct qs_cfg_msg { 310 u8 msg; 311 u8 num; 312 u64 cfg; 313 }; 314 315 /* Receive queue configuration */ 316 struct rq_cfg_msg { 317 u8 msg; 318 u8 qs_num; 319 u8 rq_num; 320 u64 cfg; 321 }; 322 323 /* Send queue configuration */ 324 struct sq_cfg_msg { 325 u8 msg; 326 u8 qs_num; 327 u8 sq_num; 328 u64 cfg; 329 }; 330 331 /* Set VF's MAC address */ 332 struct set_mac_msg { 333 u8 msg; 334 u8 vf_id; 335 u8 mac_addr[ETH_ALEN]; 336 }; 337 338 /* Set Maximum frame size */ 339 struct set_frs_msg { 340 u8 msg; 341 u8 vf_id; 342 u16 max_frs; 343 }; 344 345 /* Set CPI algorithm type */ 346 struct cpi_cfg_msg { 347 u8 msg; 348 u8 vf_id; 349 u8 rq_cnt; 350 u8 cpi_alg; 351 }; 352 353 /* Get RSS table size */ 354 struct rss_sz_msg { 355 u8 msg; 356 u8 vf_id; 357 u16 ind_tbl_size; 358 }; 359 360 /* Set RSS configuration */ 361 struct rss_cfg_msg { 362 u8 msg; 363 u8 vf_id; 364 u8 hash_bits; 365 u8 tbl_len; 366 u8 tbl_offset; 367 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 368 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 369 }; 370 371 struct bgx_stats_msg { 372 u8 msg; 373 u8 vf_id; 374 u8 rx; 375 u8 idx; 376 u64 stats; 377 }; 378 379 /* Physical interface link status */ 380 struct bgx_link_status { 381 u8 msg; 382 u8 link_up; 383 u8 duplex; 384 u32 speed; 385 }; 386 387 /* 128 bit shared memory between PF and each VF */ 388 union nic_mbx { 389 struct { u8 msg; } msg; 390 struct nic_cfg_msg nic_cfg; 391 struct qs_cfg_msg qs; 392 struct rq_cfg_msg rq; 393 struct sq_cfg_msg sq; 394 struct set_mac_msg mac; 395 struct set_frs_msg frs; 396 struct cpi_cfg_msg cpi_cfg; 397 struct rss_sz_msg rss_size; 398 struct rss_cfg_msg rss_cfg; 399 struct bgx_stats_msg bgx_stats; 400 struct bgx_link_status link_status; 401 }; 402 403 #define NIC_NODE_ID_MASK 0x03 404 #define NIC_NODE_ID_SHIFT 44 405 406 static inline int nic_get_node_id(struct pci_dev *pdev) 407 { 408 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 409 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 410 } 411 412 int nicvf_set_real_num_queues(struct net_device *netdev, 413 int tx_queues, int rx_queues); 414 int nicvf_open(struct net_device *netdev); 415 int nicvf_stop(struct net_device *netdev); 416 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 417 void nicvf_config_rss(struct nicvf *nic); 418 void nicvf_set_rss_key(struct nicvf *nic); 419 void nicvf_set_ethtool_ops(struct net_device *netdev); 420 void nicvf_update_stats(struct nicvf *nic); 421 void nicvf_update_lmac_stats(struct nicvf *nic); 422 423 #endif /* NIC_H */ 424