14863dea3SSunil Goutham /* 24863dea3SSunil Goutham * Copyright (C) 2015 Cavium, Inc. 34863dea3SSunil Goutham * 44863dea3SSunil Goutham * This program is free software; you can redistribute it and/or modify it 54863dea3SSunil Goutham * under the terms of version 2 of the GNU General Public License 64863dea3SSunil Goutham * as published by the Free Software Foundation. 74863dea3SSunil Goutham */ 84863dea3SSunil Goutham 94863dea3SSunil Goutham #ifndef NIC_H 104863dea3SSunil Goutham #define NIC_H 114863dea3SSunil Goutham 124863dea3SSunil Goutham #include <linux/netdevice.h> 134863dea3SSunil Goutham #include <linux/interrupt.h> 14d768b678SRobert Richter #include <linux/pci.h> 154863dea3SSunil Goutham #include "thunder_bgx.h" 164863dea3SSunil Goutham 174863dea3SSunil Goutham /* PCI device IDs */ 184863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 194863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 204863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 214863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 224863dea3SSunil Goutham 234863dea3SSunil Goutham /* PCI BAR nos */ 244863dea3SSunil Goutham #define PCI_CFG_REG_BAR_NUM 0 254863dea3SSunil Goutham #define PCI_MSIX_REG_BAR_NUM 4 264863dea3SSunil Goutham 274863dea3SSunil Goutham /* NIC SRIOV VF count */ 284863dea3SSunil Goutham #define MAX_NUM_VFS_SUPPORTED 128 294863dea3SSunil Goutham #define DEFAULT_NUM_VF_ENABLED 8 304863dea3SSunil Goutham 314863dea3SSunil Goutham #define NIC_TNS_BYPASS_MODE 0 324863dea3SSunil Goutham #define NIC_TNS_MODE 1 334863dea3SSunil Goutham 344863dea3SSunil Goutham /* NIC priv flags */ 354863dea3SSunil Goutham #define NIC_SRIOV_ENABLED BIT(0) 364863dea3SSunil Goutham 374863dea3SSunil Goutham /* Min/Max packet size */ 384863dea3SSunil Goutham #define NIC_HW_MIN_FRS 64 394863dea3SSunil Goutham #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 404863dea3SSunil Goutham 414863dea3SSunil Goutham /* Max pkinds */ 424863dea3SSunil Goutham #define NIC_MAX_PKIND 16 434863dea3SSunil Goutham 444863dea3SSunil Goutham /* Rx Channels */ 454863dea3SSunil Goutham /* Receive channel configuration in TNS bypass mode 464863dea3SSunil Goutham * Below is configuration in TNS bypass mode 474863dea3SSunil Goutham * BGX0-LMAC0-CHAN0 - VNIC CHAN0 484863dea3SSunil Goutham * BGX0-LMAC1-CHAN0 - VNIC CHAN16 494863dea3SSunil Goutham * ... 504863dea3SSunil Goutham * BGX1-LMAC0-CHAN0 - VNIC CHAN128 514863dea3SSunil Goutham * ... 524863dea3SSunil Goutham * BGX1-LMAC3-CHAN0 - VNIC CHAN174 534863dea3SSunil Goutham */ 544863dea3SSunil Goutham #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ 554863dea3SSunil Goutham #define NIC_CHANS_PER_INF 128 564863dea3SSunil Goutham #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) 574863dea3SSunil Goutham #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ 584863dea3SSunil Goutham 594863dea3SSunil Goutham /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ 604863dea3SSunil Goutham #define NIC_MAX_BGX MAX_BGX_PER_CN88XX 614863dea3SSunil Goutham #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) 624863dea3SSunil Goutham #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ 634863dea3SSunil Goutham #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) 644863dea3SSunil Goutham 654863dea3SSunil Goutham /* Tx scheduling */ 664863dea3SSunil Goutham #define NIC_MAX_TL4 1024 674863dea3SSunil Goutham #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ 684863dea3SSunil Goutham #define NIC_MAX_TL3 256 694863dea3SSunil Goutham #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ 704863dea3SSunil Goutham #define NIC_MAX_TL2 64 714863dea3SSunil Goutham #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ 724863dea3SSunil Goutham #define NIC_MAX_TL1 2 734863dea3SSunil Goutham 744863dea3SSunil Goutham /* TNS bypass mode */ 754863dea3SSunil Goutham #define NIC_TL2_PER_BGX 32 764863dea3SSunil Goutham #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) 774863dea3SSunil Goutham #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) 784863dea3SSunil Goutham 794863dea3SSunil Goutham /* NIC VF Interrupts */ 804863dea3SSunil Goutham #define NICVF_INTR_CQ 0 814863dea3SSunil Goutham #define NICVF_INTR_SQ 1 824863dea3SSunil Goutham #define NICVF_INTR_RBDR 2 834863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP 3 844863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER 4 854863dea3SSunil Goutham #define NICVF_INTR_MBOX 5 864863dea3SSunil Goutham #define NICVF_INTR_QS_ERR 6 874863dea3SSunil Goutham 884863dea3SSunil Goutham #define NICVF_INTR_CQ_SHIFT 0 894863dea3SSunil Goutham #define NICVF_INTR_SQ_SHIFT 8 904863dea3SSunil Goutham #define NICVF_INTR_RBDR_SHIFT 16 914863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP_SHIFT 20 924863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER_SHIFT 21 934863dea3SSunil Goutham #define NICVF_INTR_MBOX_SHIFT 22 944863dea3SSunil Goutham #define NICVF_INTR_QS_ERR_SHIFT 23 954863dea3SSunil Goutham 964863dea3SSunil Goutham #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 974863dea3SSunil Goutham #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 984863dea3SSunil Goutham #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 994863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 1004863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 1014863dea3SSunil Goutham #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 1024863dea3SSunil Goutham #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 1034863dea3SSunil Goutham 1044863dea3SSunil Goutham /* MSI-X interrupts */ 1054863dea3SSunil Goutham #define NIC_PF_MSIX_VECTORS 10 1064863dea3SSunil Goutham #define NIC_VF_MSIX_VECTORS 20 1074863dea3SSunil Goutham 1084863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC0_SBE 0 1094863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC0_DBE 1 1104863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC1_SBE 2 1114863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC1_DBE 3 1124863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC2_SBE 4 1134863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC2_DBE 5 1144863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC3_SBE 6 1154863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC3_DBE 7 1164863dea3SSunil Goutham #define NIC_PF_INTR_ID_MBOX0 8 1174863dea3SSunil Goutham #define NIC_PF_INTR_ID_MBOX1 9 1184863dea3SSunil Goutham 1194c0b6eafSSunil Goutham /* Minimum FIFO level before all packets for the CQ are dropped 1204c0b6eafSSunil Goutham * 1214c0b6eafSSunil Goutham * This value ensures that once a packet has been "accepted" 1224c0b6eafSSunil Goutham * for reception it will not get dropped due to non-availability 1234c0b6eafSSunil Goutham * of CQ descriptor. An errata in HW mandates this value to be 1244c0b6eafSSunil Goutham * atleast 0x100. 1254c0b6eafSSunil Goutham */ 1264c0b6eafSSunil Goutham #define NICPF_CQM_MIN_DROP_LEVEL 0x100 1274c0b6eafSSunil Goutham 1284863dea3SSunil Goutham /* Global timer for CQ timer thresh interrupts 1294863dea3SSunil Goutham * Calculated for SCLK of 700Mhz 1304863dea3SSunil Goutham * value written should be a 1/16th of what is expected 1314863dea3SSunil Goutham * 132006394a7SSunil Goutham * 1 tick per 0.025usec 1334863dea3SSunil Goutham */ 134006394a7SSunil Goutham #define NICPF_CLK_PER_INT_TICK 1 1354863dea3SSunil Goutham 1363d7a8aaaSSunil Goutham /* Time to wait before we decide that a SQ is stuck. 1373d7a8aaaSSunil Goutham * 1383d7a8aaaSSunil Goutham * Since both pkt rx and tx notifications are done with same CQ, 1393d7a8aaaSSunil Goutham * when packets are being received at very high rate (eg: L2 forwarding) 1403d7a8aaaSSunil Goutham * then freeing transmitted skbs will be delayed and watchdog 1413d7a8aaaSSunil Goutham * will kick in, resetting interface. Hence keeping this value high. 1423d7a8aaaSSunil Goutham */ 1433d7a8aaaSSunil Goutham #define NICVF_TX_TIMEOUT (50 * HZ) 1443d7a8aaaSSunil Goutham 1454863dea3SSunil Goutham struct nicvf_cq_poll { 14639ad6eeaSSunil Goutham struct nicvf *nicvf; 1474863dea3SSunil Goutham u8 cq_idx; /* Completion queue index */ 1484863dea3SSunil Goutham struct napi_struct napi; 1494863dea3SSunil Goutham }; 1504863dea3SSunil Goutham 1514863dea3SSunil Goutham #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ 1524863dea3SSunil Goutham #define NIC_MAX_RSS_HASH_BITS 8 1534863dea3SSunil Goutham #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 1544863dea3SSunil Goutham #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 1554863dea3SSunil Goutham 1564863dea3SSunil Goutham struct nicvf_rss_info { 1574863dea3SSunil Goutham bool enable; 1584863dea3SSunil Goutham #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 1594863dea3SSunil Goutham #define RSS_IP_HASH_ENA BIT(1) 1604863dea3SSunil Goutham #define RSS_TCP_HASH_ENA BIT(2) 1614863dea3SSunil Goutham #define RSS_TCP_SYN_DIS BIT(3) 1624863dea3SSunil Goutham #define RSS_UDP_HASH_ENA BIT(4) 1634863dea3SSunil Goutham #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 1644863dea3SSunil Goutham #define RSS_ROCE_ENA BIT(6) 1654863dea3SSunil Goutham #define RSS_L3_BI_DIRECTION_ENA BIT(7) 1664863dea3SSunil Goutham #define RSS_L4_BI_DIRECTION_ENA BIT(8) 1674863dea3SSunil Goutham u64 cfg; 1684863dea3SSunil Goutham u8 hash_bits; 1694863dea3SSunil Goutham u16 rss_size; 1704863dea3SSunil Goutham u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 1714863dea3SSunil Goutham u64 key[RSS_HASH_KEY_SIZE]; 1724863dea3SSunil Goutham } ____cacheline_aligned_in_smp; 1734863dea3SSunil Goutham 1744863dea3SSunil Goutham enum rx_stats_reg_offset { 1754863dea3SSunil Goutham RX_OCTS = 0x0, 1764863dea3SSunil Goutham RX_UCAST = 0x1, 1774863dea3SSunil Goutham RX_BCAST = 0x2, 1784863dea3SSunil Goutham RX_MCAST = 0x3, 1794863dea3SSunil Goutham RX_RED = 0x4, 1804863dea3SSunil Goutham RX_RED_OCTS = 0x5, 1814863dea3SSunil Goutham RX_ORUN = 0x6, 1824863dea3SSunil Goutham RX_ORUN_OCTS = 0x7, 1834863dea3SSunil Goutham RX_FCS = 0x8, 1844863dea3SSunil Goutham RX_L2ERR = 0x9, 1854863dea3SSunil Goutham RX_DRP_BCAST = 0xa, 1864863dea3SSunil Goutham RX_DRP_MCAST = 0xb, 1874863dea3SSunil Goutham RX_DRP_L3BCAST = 0xc, 1884863dea3SSunil Goutham RX_DRP_L3MCAST = 0xd, 1894863dea3SSunil Goutham RX_STATS_ENUM_LAST, 1904863dea3SSunil Goutham }; 1914863dea3SSunil Goutham 1924863dea3SSunil Goutham enum tx_stats_reg_offset { 1934863dea3SSunil Goutham TX_OCTS = 0x0, 1944863dea3SSunil Goutham TX_UCAST = 0x1, 1954863dea3SSunil Goutham TX_BCAST = 0x2, 1964863dea3SSunil Goutham TX_MCAST = 0x3, 1974863dea3SSunil Goutham TX_DROP = 0x4, 1984863dea3SSunil Goutham TX_STATS_ENUM_LAST, 1994863dea3SSunil Goutham }; 2004863dea3SSunil Goutham 2014863dea3SSunil Goutham struct nicvf_hw_stats { 202a2dc5dedSSunil Goutham u64 rx_bytes; 203a2dc5dedSSunil Goutham u64 rx_ucast_frames; 204a2dc5dedSSunil Goutham u64 rx_bcast_frames; 205a2dc5dedSSunil Goutham u64 rx_mcast_frames; 2064863dea3SSunil Goutham u64 rx_fcs_errors; 2074863dea3SSunil Goutham u64 rx_l2_errors; 2084863dea3SSunil Goutham u64 rx_drop_red; 2094863dea3SSunil Goutham u64 rx_drop_red_bytes; 2104863dea3SSunil Goutham u64 rx_drop_overrun; 2114863dea3SSunil Goutham u64 rx_drop_overrun_bytes; 2124863dea3SSunil Goutham u64 rx_drop_bcast; 2134863dea3SSunil Goutham u64 rx_drop_mcast; 2144863dea3SSunil Goutham u64 rx_drop_l3_bcast; 2154863dea3SSunil Goutham u64 rx_drop_l3_mcast; 216a2dc5dedSSunil Goutham u64 rx_bgx_truncated_pkts; 217a2dc5dedSSunil Goutham u64 rx_jabber_errs; 218a2dc5dedSSunil Goutham u64 rx_fcs_errs; 219a2dc5dedSSunil Goutham u64 rx_bgx_errs; 220a2dc5dedSSunil Goutham u64 rx_prel2_errs; 221a2dc5dedSSunil Goutham u64 rx_l2_hdr_malformed; 222a2dc5dedSSunil Goutham u64 rx_oversize; 223a2dc5dedSSunil Goutham u64 rx_undersize; 224a2dc5dedSSunil Goutham u64 rx_l2_len_mismatch; 225a2dc5dedSSunil Goutham u64 rx_l2_pclp; 226a2dc5dedSSunil Goutham u64 rx_ip_ver_errs; 227a2dc5dedSSunil Goutham u64 rx_ip_csum_errs; 228a2dc5dedSSunil Goutham u64 rx_ip_hdr_malformed; 229a2dc5dedSSunil Goutham u64 rx_ip_payload_malformed; 230a2dc5dedSSunil Goutham u64 rx_ip_ttl_errs; 231a2dc5dedSSunil Goutham u64 rx_l3_pclp; 232a2dc5dedSSunil Goutham u64 rx_l4_malformed; 233a2dc5dedSSunil Goutham u64 rx_l4_csum_errs; 234a2dc5dedSSunil Goutham u64 rx_udp_len_errs; 235a2dc5dedSSunil Goutham u64 rx_l4_port_errs; 236a2dc5dedSSunil Goutham u64 rx_tcp_flag_errs; 237a2dc5dedSSunil Goutham u64 rx_tcp_offset_errs; 238a2dc5dedSSunil Goutham u64 rx_l4_pclp; 239a2dc5dedSSunil Goutham u64 rx_truncated_pkts; 240a2dc5dedSSunil Goutham 2414863dea3SSunil Goutham u64 tx_bytes_ok; 2424863dea3SSunil Goutham u64 tx_ucast_frames_ok; 2434863dea3SSunil Goutham u64 tx_bcast_frames_ok; 2444863dea3SSunil Goutham u64 tx_mcast_frames_ok; 2454863dea3SSunil Goutham u64 tx_drops; 2464863dea3SSunil Goutham }; 2474863dea3SSunil Goutham 2484863dea3SSunil Goutham struct nicvf_drv_stats { 2494863dea3SSunil Goutham /* Rx */ 2504863dea3SSunil Goutham u64 rx_frames_ok; 2514863dea3SSunil Goutham u64 rx_frames_64; 2524863dea3SSunil Goutham u64 rx_frames_127; 2534863dea3SSunil Goutham u64 rx_frames_255; 2544863dea3SSunil Goutham u64 rx_frames_511; 2554863dea3SSunil Goutham u64 rx_frames_1023; 2564863dea3SSunil Goutham u64 rx_frames_1518; 2574863dea3SSunil Goutham u64 rx_frames_jumbo; 2584863dea3SSunil Goutham u64 rx_drops; 259a2dc5dedSSunil Goutham 260a05d4845SThanneeru Srinivasulu u64 rcv_buffer_alloc_failures; 261a05d4845SThanneeru Srinivasulu 2624863dea3SSunil Goutham /* Tx */ 2634863dea3SSunil Goutham u64 tx_frames_ok; 2644863dea3SSunil Goutham u64 tx_drops; 2654863dea3SSunil Goutham u64 tx_tso; 266a05d4845SThanneeru Srinivasulu u64 tx_timeout; 26774840b83SSunil Goutham u64 txq_stop; 26874840b83SSunil Goutham u64 txq_wake; 2694863dea3SSunil Goutham }; 2704863dea3SSunil Goutham 2714863dea3SSunil Goutham struct nicvf { 27292dc8769SSunil Goutham struct nicvf *pnicvf; 2734863dea3SSunil Goutham struct net_device *netdev; 2744863dea3SSunil Goutham struct pci_dev *pdev; 2754863dea3SSunil Goutham void __iomem *reg_base; 2761d368790SSunil Goutham struct queue_set *qs; 2771d368790SSunil Goutham struct nicvf_cq_poll *napi[8]; 2781d368790SSunil Goutham u8 vf_id; 2791d368790SSunil Goutham u8 sqs_id; 2801d368790SSunil Goutham bool sqs_mode; 2811d368790SSunil Goutham bool hw_tso; 2827ceb8a13SSunil Goutham bool t88; 2831d368790SSunil Goutham 2841d368790SSunil Goutham /* Receive buffer alloc */ 2854863dea3SSunil Goutham u32 rb_page_offset; 2865c2e26f6SSunil Goutham u16 rb_pageref; 2874863dea3SSunil Goutham bool rb_alloc_fail; 2884863dea3SSunil Goutham bool rb_work_scheduled; 2891d368790SSunil Goutham struct page *rb_page; 2904863dea3SSunil Goutham struct delayed_work rbdr_work; 2914863dea3SSunil Goutham struct tasklet_struct rbdr_task; 2921d368790SSunil Goutham 2931d368790SSunil Goutham /* Secondary Qset */ 2941d368790SSunil Goutham u8 sqs_count; 2951d368790SSunil Goutham #define MAX_SQS_PER_VF_SINGLE_NODE 5 2961d368790SSunil Goutham #define MAX_SQS_PER_VF 11 2971d368790SSunil Goutham struct nicvf *snicvf[MAX_SQS_PER_VF]; 2981d368790SSunil Goutham 2991d368790SSunil Goutham /* Queue count */ 3001d368790SSunil Goutham u8 rx_queues; 3011d368790SSunil Goutham u8 tx_queues; 3021d368790SSunil Goutham u8 max_queues; 3031d368790SSunil Goutham 3041d368790SSunil Goutham u8 node; 3054863dea3SSunil Goutham u8 cpi_alg; 3061d368790SSunil Goutham u16 mtu; 3071d368790SSunil Goutham bool link_up; 3081d368790SSunil Goutham u8 duplex; 3091d368790SSunil Goutham u32 speed; 3101d368790SSunil Goutham bool tns_mode; 3111d368790SSunil Goutham bool loopback_supported; 3121d368790SSunil Goutham struct nicvf_rss_info rss_info; 3131d368790SSunil Goutham struct tasklet_struct qs_err_task; 3141d368790SSunil Goutham struct work_struct reset_task; 3151d368790SSunil Goutham 3164863dea3SSunil Goutham /* Interrupt coalescing settings */ 3174863dea3SSunil Goutham u32 cq_coalesce_usecs; 3184863dea3SSunil Goutham u32 msg_enable; 3191d368790SSunil Goutham 3201d368790SSunil Goutham /* Stats */ 321a2dc5dedSSunil Goutham struct nicvf_hw_stats hw_stats; 3224863dea3SSunil Goutham struct nicvf_drv_stats drv_stats; 3234863dea3SSunil Goutham struct bgx_stats bgx_stats; 3244863dea3SSunil Goutham 3254863dea3SSunil Goutham /* MSI-X */ 3264863dea3SSunil Goutham bool msix_enabled; 3274863dea3SSunil Goutham u8 num_vec; 3284863dea3SSunil Goutham struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 3294863dea3SSunil Goutham char irq_name[NIC_VF_MSIX_VECTORS][20]; 3304863dea3SSunil Goutham bool irq_allocated[NIC_VF_MSIX_VECTORS]; 331fb4b7d98SSunil Goutham cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; 3324863dea3SSunil Goutham 3336051cba7SSunil Goutham /* VF <-> PF mailbox communication */ 3344863dea3SSunil Goutham bool pf_acked; 3354863dea3SSunil Goutham bool pf_nacked; 336bd049a90SPavel Fedin bool set_mac_pending; 3374863dea3SSunil Goutham } ____cacheline_aligned_in_smp; 3384863dea3SSunil Goutham 3394863dea3SSunil Goutham /* PF <--> VF Mailbox communication 3404863dea3SSunil Goutham * Eight 64bit registers are shared between PF and VF. 3414863dea3SSunil Goutham * Separate set for each VF. 3424863dea3SSunil Goutham * Writing '1' into last register mbx7 means end of message. 3434863dea3SSunil Goutham */ 3444863dea3SSunil Goutham 3454863dea3SSunil Goutham /* PF <--> VF mailbox communication */ 3464863dea3SSunil Goutham #define NIC_PF_VF_MAILBOX_SIZE 2 3474863dea3SSunil Goutham #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 3484863dea3SSunil Goutham 3494863dea3SSunil Goutham /* Mailbox message types */ 3504863dea3SSunil Goutham #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 3514863dea3SSunil Goutham #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 3524863dea3SSunil Goutham #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 3534863dea3SSunil Goutham #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 3544863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 3554863dea3SSunil Goutham #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 3564863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 3574863dea3SSunil Goutham #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 3584863dea3SSunil Goutham #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 3594863dea3SSunil Goutham #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 3604863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 3614863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 3624863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 3634863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 3644863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 3654863dea3SSunil Goutham #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 3664863dea3SSunil Goutham #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 36792dc8769SSunil Goutham #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 36892dc8769SSunil Goutham #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 36992dc8769SSunil Goutham #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 37092dc8769SSunil Goutham #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 371d77a2384SSunil Goutham #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 37292dc8769SSunil Goutham #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 37392dc8769SSunil Goutham #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 3744863dea3SSunil Goutham 3754863dea3SSunil Goutham struct nic_cfg_msg { 3764863dea3SSunil Goutham u8 msg; 3774863dea3SSunil Goutham u8 vf_id; 3784863dea3SSunil Goutham u8 node_id; 37992dc8769SSunil Goutham u8 tns_mode:1; 38092dc8769SSunil Goutham u8 sqs_mode:1; 381d77a2384SSunil Goutham u8 loopback_supported:1; 382e610cb32SAleksey Makarov u8 mac_addr[ETH_ALEN]; 3834863dea3SSunil Goutham }; 3844863dea3SSunil Goutham 3854863dea3SSunil Goutham /* Qset configuration */ 3864863dea3SSunil Goutham struct qs_cfg_msg { 3874863dea3SSunil Goutham u8 msg; 3884863dea3SSunil Goutham u8 num; 38992dc8769SSunil Goutham u8 sqs_count; 3904863dea3SSunil Goutham u64 cfg; 3914863dea3SSunil Goutham }; 3924863dea3SSunil Goutham 3934863dea3SSunil Goutham /* Receive queue configuration */ 3944863dea3SSunil Goutham struct rq_cfg_msg { 3954863dea3SSunil Goutham u8 msg; 3964863dea3SSunil Goutham u8 qs_num; 3974863dea3SSunil Goutham u8 rq_num; 3984863dea3SSunil Goutham u64 cfg; 3994863dea3SSunil Goutham }; 4004863dea3SSunil Goutham 4014863dea3SSunil Goutham /* Send queue configuration */ 4024863dea3SSunil Goutham struct sq_cfg_msg { 4034863dea3SSunil Goutham u8 msg; 4044863dea3SSunil Goutham u8 qs_num; 4054863dea3SSunil Goutham u8 sq_num; 40692dc8769SSunil Goutham bool sqs_mode; 4074863dea3SSunil Goutham u64 cfg; 4084863dea3SSunil Goutham }; 4094863dea3SSunil Goutham 4104863dea3SSunil Goutham /* Set VF's MAC address */ 4114863dea3SSunil Goutham struct set_mac_msg { 4124863dea3SSunil Goutham u8 msg; 4134863dea3SSunil Goutham u8 vf_id; 414e610cb32SAleksey Makarov u8 mac_addr[ETH_ALEN]; 4154863dea3SSunil Goutham }; 4164863dea3SSunil Goutham 4174863dea3SSunil Goutham /* Set Maximum frame size */ 4184863dea3SSunil Goutham struct set_frs_msg { 4194863dea3SSunil Goutham u8 msg; 4204863dea3SSunil Goutham u8 vf_id; 4214863dea3SSunil Goutham u16 max_frs; 4224863dea3SSunil Goutham }; 4234863dea3SSunil Goutham 4244863dea3SSunil Goutham /* Set CPI algorithm type */ 4254863dea3SSunil Goutham struct cpi_cfg_msg { 4264863dea3SSunil Goutham u8 msg; 4274863dea3SSunil Goutham u8 vf_id; 4284863dea3SSunil Goutham u8 rq_cnt; 4294863dea3SSunil Goutham u8 cpi_alg; 4304863dea3SSunil Goutham }; 4314863dea3SSunil Goutham 4324863dea3SSunil Goutham /* Get RSS table size */ 4334863dea3SSunil Goutham struct rss_sz_msg { 4344863dea3SSunil Goutham u8 msg; 4354863dea3SSunil Goutham u8 vf_id; 4364863dea3SSunil Goutham u16 ind_tbl_size; 4374863dea3SSunil Goutham }; 4384863dea3SSunil Goutham 4394863dea3SSunil Goutham /* Set RSS configuration */ 4404863dea3SSunil Goutham struct rss_cfg_msg { 4414863dea3SSunil Goutham u8 msg; 4424863dea3SSunil Goutham u8 vf_id; 4434863dea3SSunil Goutham u8 hash_bits; 4444863dea3SSunil Goutham u8 tbl_len; 4454863dea3SSunil Goutham u8 tbl_offset; 4464863dea3SSunil Goutham #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 4474863dea3SSunil Goutham u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 4484863dea3SSunil Goutham }; 4494863dea3SSunil Goutham 4504863dea3SSunil Goutham struct bgx_stats_msg { 4514863dea3SSunil Goutham u8 msg; 4524863dea3SSunil Goutham u8 vf_id; 4534863dea3SSunil Goutham u8 rx; 4544863dea3SSunil Goutham u8 idx; 4554863dea3SSunil Goutham u64 stats; 4564863dea3SSunil Goutham }; 4574863dea3SSunil Goutham 4584863dea3SSunil Goutham /* Physical interface link status */ 4594863dea3SSunil Goutham struct bgx_link_status { 4604863dea3SSunil Goutham u8 msg; 4614863dea3SSunil Goutham u8 link_up; 4624863dea3SSunil Goutham u8 duplex; 4634863dea3SSunil Goutham u32 speed; 4644863dea3SSunil Goutham }; 4654863dea3SSunil Goutham 46692dc8769SSunil Goutham /* Get Extra Qset IDs */ 46792dc8769SSunil Goutham struct sqs_alloc { 46892dc8769SSunil Goutham u8 msg; 46992dc8769SSunil Goutham u8 vf_id; 47092dc8769SSunil Goutham u8 qs_count; 47192dc8769SSunil Goutham }; 47292dc8769SSunil Goutham 47392dc8769SSunil Goutham struct nicvf_ptr { 47492dc8769SSunil Goutham u8 msg; 47592dc8769SSunil Goutham u8 vf_id; 47692dc8769SSunil Goutham bool sqs_mode; 47792dc8769SSunil Goutham u8 sqs_id; 47892dc8769SSunil Goutham u64 nicvf; 47992dc8769SSunil Goutham }; 48092dc8769SSunil Goutham 481d77a2384SSunil Goutham /* Set interface in loopback mode */ 482d77a2384SSunil Goutham struct set_loopback { 483d77a2384SSunil Goutham u8 msg; 484d77a2384SSunil Goutham u8 vf_id; 485d77a2384SSunil Goutham bool enable; 486d77a2384SSunil Goutham }; 487d77a2384SSunil Goutham 4884863dea3SSunil Goutham /* 128 bit shared memory between PF and each VF */ 4894863dea3SSunil Goutham union nic_mbx { 4904863dea3SSunil Goutham struct { u8 msg; } msg; 4914863dea3SSunil Goutham struct nic_cfg_msg nic_cfg; 4924863dea3SSunil Goutham struct qs_cfg_msg qs; 4934863dea3SSunil Goutham struct rq_cfg_msg rq; 4944863dea3SSunil Goutham struct sq_cfg_msg sq; 4954863dea3SSunil Goutham struct set_mac_msg mac; 4964863dea3SSunil Goutham struct set_frs_msg frs; 4974863dea3SSunil Goutham struct cpi_cfg_msg cpi_cfg; 4984863dea3SSunil Goutham struct rss_sz_msg rss_size; 4994863dea3SSunil Goutham struct rss_cfg_msg rss_cfg; 5004863dea3SSunil Goutham struct bgx_stats_msg bgx_stats; 5014863dea3SSunil Goutham struct bgx_link_status link_status; 50292dc8769SSunil Goutham struct sqs_alloc sqs_alloc; 50392dc8769SSunil Goutham struct nicvf_ptr nicvf; 504d77a2384SSunil Goutham struct set_loopback lbk; 5054863dea3SSunil Goutham }; 5064863dea3SSunil Goutham 507d768b678SRobert Richter #define NIC_NODE_ID_MASK 0x03 508d768b678SRobert Richter #define NIC_NODE_ID_SHIFT 44 509d768b678SRobert Richter 510d768b678SRobert Richter static inline int nic_get_node_id(struct pci_dev *pdev) 511d768b678SRobert Richter { 512d768b678SRobert Richter u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 513d768b678SRobert Richter return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 514d768b678SRobert Richter } 515d768b678SRobert Richter 51640fb5f8aSSunil Goutham static inline bool pass1_silicon(struct pci_dev *pdev) 51740fb5f8aSSunil Goutham { 51840fb5f8aSSunil Goutham return pdev->revision < 8; 51940fb5f8aSSunil Goutham } 52040fb5f8aSSunil Goutham 5214863dea3SSunil Goutham int nicvf_set_real_num_queues(struct net_device *netdev, 5224863dea3SSunil Goutham int tx_queues, int rx_queues); 5234863dea3SSunil Goutham int nicvf_open(struct net_device *netdev); 5244863dea3SSunil Goutham int nicvf_stop(struct net_device *netdev); 5254863dea3SSunil Goutham int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 5264863dea3SSunil Goutham void nicvf_config_rss(struct nicvf *nic); 5274863dea3SSunil Goutham void nicvf_set_rss_key(struct nicvf *nic); 5284863dea3SSunil Goutham void nicvf_set_ethtool_ops(struct net_device *netdev); 5294863dea3SSunil Goutham void nicvf_update_stats(struct nicvf *nic); 5304863dea3SSunil Goutham void nicvf_update_lmac_stats(struct nicvf *nic); 5314863dea3SSunil Goutham 5324863dea3SSunil Goutham #endif /* NIC_H */ 533