14863dea3SSunil Goutham /* 24863dea3SSunil Goutham * Copyright (C) 2015 Cavium, Inc. 34863dea3SSunil Goutham * 44863dea3SSunil Goutham * This program is free software; you can redistribute it and/or modify it 54863dea3SSunil Goutham * under the terms of version 2 of the GNU General Public License 64863dea3SSunil Goutham * as published by the Free Software Foundation. 74863dea3SSunil Goutham */ 84863dea3SSunil Goutham 94863dea3SSunil Goutham #ifndef NIC_H 104863dea3SSunil Goutham #define NIC_H 114863dea3SSunil Goutham 124863dea3SSunil Goutham #include <linux/netdevice.h> 134863dea3SSunil Goutham #include <linux/interrupt.h> 14d768b678SRobert Richter #include <linux/pci.h> 154863dea3SSunil Goutham #include "thunder_bgx.h" 164863dea3SSunil Goutham 174863dea3SSunil Goutham /* PCI device IDs */ 184863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 194863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 204863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 214863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 224863dea3SSunil Goutham 23a5c3d498SSunil Goutham /* Subsystem device IDs */ 24a5c3d498SSunil Goutham #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E 25f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E 26f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E 27f7ff0ae8SSunil Goutham 28f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E 29f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134 30f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234 31f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334 32f7ff0ae8SSunil Goutham 33a5c3d498SSunil Goutham 344863dea3SSunil Goutham /* PCI BAR nos */ 354863dea3SSunil Goutham #define PCI_CFG_REG_BAR_NUM 0 364863dea3SSunil Goutham #define PCI_MSIX_REG_BAR_NUM 4 374863dea3SSunil Goutham 384863dea3SSunil Goutham /* NIC SRIOV VF count */ 394863dea3SSunil Goutham #define MAX_NUM_VFS_SUPPORTED 128 404863dea3SSunil Goutham #define DEFAULT_NUM_VF_ENABLED 8 414863dea3SSunil Goutham 424863dea3SSunil Goutham #define NIC_TNS_BYPASS_MODE 0 434863dea3SSunil Goutham #define NIC_TNS_MODE 1 444863dea3SSunil Goutham 454863dea3SSunil Goutham /* NIC priv flags */ 464863dea3SSunil Goutham #define NIC_SRIOV_ENABLED BIT(0) 474863dea3SSunil Goutham 484863dea3SSunil Goutham /* Min/Max packet size */ 494863dea3SSunil Goutham #define NIC_HW_MIN_FRS 64 50712c3185SSunil Goutham #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */ 514863dea3SSunil Goutham 524863dea3SSunil Goutham /* Max pkinds */ 534863dea3SSunil Goutham #define NIC_MAX_PKIND 16 544863dea3SSunil Goutham 55a5c3d498SSunil Goutham /* Max when CPI_ALG is IP diffserv */ 56a5c3d498SSunil Goutham #define NIC_MAX_CPI_PER_LMAC 64 574863dea3SSunil Goutham 584863dea3SSunil Goutham /* NIC VF Interrupts */ 594863dea3SSunil Goutham #define NICVF_INTR_CQ 0 604863dea3SSunil Goutham #define NICVF_INTR_SQ 1 614863dea3SSunil Goutham #define NICVF_INTR_RBDR 2 624863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP 3 634863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER 4 644863dea3SSunil Goutham #define NICVF_INTR_MBOX 5 654863dea3SSunil Goutham #define NICVF_INTR_QS_ERR 6 664863dea3SSunil Goutham 674863dea3SSunil Goutham #define NICVF_INTR_CQ_SHIFT 0 684863dea3SSunil Goutham #define NICVF_INTR_SQ_SHIFT 8 694863dea3SSunil Goutham #define NICVF_INTR_RBDR_SHIFT 16 704863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP_SHIFT 20 714863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER_SHIFT 21 724863dea3SSunil Goutham #define NICVF_INTR_MBOX_SHIFT 22 734863dea3SSunil Goutham #define NICVF_INTR_QS_ERR_SHIFT 23 744863dea3SSunil Goutham 754863dea3SSunil Goutham #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 764863dea3SSunil Goutham #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 774863dea3SSunil Goutham #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 784863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 794863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 804863dea3SSunil Goutham #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 814863dea3SSunil Goutham #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 824863dea3SSunil Goutham 834863dea3SSunil Goutham /* MSI-X interrupts */ 844863dea3SSunil Goutham #define NIC_PF_MSIX_VECTORS 10 854863dea3SSunil Goutham #define NIC_VF_MSIX_VECTORS 20 864863dea3SSunil Goutham 874863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC0_SBE 0 884863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC0_DBE 1 894863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC1_SBE 2 904863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC1_DBE 3 914863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC2_SBE 4 924863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC2_DBE 5 934863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC3_SBE 6 944863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC3_DBE 7 954863dea3SSunil Goutham #define NIC_PF_INTR_ID_MBOX0 8 964863dea3SSunil Goutham #define NIC_PF_INTR_ID_MBOX1 9 974863dea3SSunil Goutham 984c0b6eafSSunil Goutham /* Minimum FIFO level before all packets for the CQ are dropped 994c0b6eafSSunil Goutham * 1004c0b6eafSSunil Goutham * This value ensures that once a packet has been "accepted" 1014c0b6eafSSunil Goutham * for reception it will not get dropped due to non-availability 1024c0b6eafSSunil Goutham * of CQ descriptor. An errata in HW mandates this value to be 1034c0b6eafSSunil Goutham * atleast 0x100. 1044c0b6eafSSunil Goutham */ 1054c0b6eafSSunil Goutham #define NICPF_CQM_MIN_DROP_LEVEL 0x100 1064c0b6eafSSunil Goutham 1074863dea3SSunil Goutham /* Global timer for CQ timer thresh interrupts 1084863dea3SSunil Goutham * Calculated for SCLK of 700Mhz 1094863dea3SSunil Goutham * value written should be a 1/16th of what is expected 1104863dea3SSunil Goutham * 111006394a7SSunil Goutham * 1 tick per 0.025usec 1124863dea3SSunil Goutham */ 113006394a7SSunil Goutham #define NICPF_CLK_PER_INT_TICK 1 1144863dea3SSunil Goutham 1153d7a8aaaSSunil Goutham /* Time to wait before we decide that a SQ is stuck. 1163d7a8aaaSSunil Goutham * 1173d7a8aaaSSunil Goutham * Since both pkt rx and tx notifications are done with same CQ, 1183d7a8aaaSSunil Goutham * when packets are being received at very high rate (eg: L2 forwarding) 1193d7a8aaaSSunil Goutham * then freeing transmitted skbs will be delayed and watchdog 1203d7a8aaaSSunil Goutham * will kick in, resetting interface. Hence keeping this value high. 1213d7a8aaaSSunil Goutham */ 1223d7a8aaaSSunil Goutham #define NICVF_TX_TIMEOUT (50 * HZ) 1233d7a8aaaSSunil Goutham 1244863dea3SSunil Goutham struct nicvf_cq_poll { 12539ad6eeaSSunil Goutham struct nicvf *nicvf; 1264863dea3SSunil Goutham u8 cq_idx; /* Completion queue index */ 1274863dea3SSunil Goutham struct napi_struct napi; 1284863dea3SSunil Goutham }; 1294863dea3SSunil Goutham 1304863dea3SSunil Goutham #define NIC_MAX_RSS_HASH_BITS 8 1314863dea3SSunil Goutham #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 1324863dea3SSunil Goutham #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 1334863dea3SSunil Goutham 1344863dea3SSunil Goutham struct nicvf_rss_info { 1354863dea3SSunil Goutham bool enable; 1364863dea3SSunil Goutham #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 1374863dea3SSunil Goutham #define RSS_IP_HASH_ENA BIT(1) 1384863dea3SSunil Goutham #define RSS_TCP_HASH_ENA BIT(2) 1394863dea3SSunil Goutham #define RSS_TCP_SYN_DIS BIT(3) 1404863dea3SSunil Goutham #define RSS_UDP_HASH_ENA BIT(4) 1414863dea3SSunil Goutham #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 1424863dea3SSunil Goutham #define RSS_ROCE_ENA BIT(6) 1434863dea3SSunil Goutham #define RSS_L3_BI_DIRECTION_ENA BIT(7) 1444863dea3SSunil Goutham #define RSS_L4_BI_DIRECTION_ENA BIT(8) 1454863dea3SSunil Goutham u64 cfg; 1464863dea3SSunil Goutham u8 hash_bits; 1474863dea3SSunil Goutham u16 rss_size; 1484863dea3SSunil Goutham u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 1494863dea3SSunil Goutham u64 key[RSS_HASH_KEY_SIZE]; 1504863dea3SSunil Goutham } ____cacheline_aligned_in_smp; 1514863dea3SSunil Goutham 152430da208SSunil Goutham struct nicvf_pfc { 153430da208SSunil Goutham u8 autoneg; 154430da208SSunil Goutham u8 fc_rx; 155430da208SSunil Goutham u8 fc_tx; 156430da208SSunil Goutham }; 157430da208SSunil Goutham 1584863dea3SSunil Goutham enum rx_stats_reg_offset { 1594863dea3SSunil Goutham RX_OCTS = 0x0, 1604863dea3SSunil Goutham RX_UCAST = 0x1, 1614863dea3SSunil Goutham RX_BCAST = 0x2, 1624863dea3SSunil Goutham RX_MCAST = 0x3, 1634863dea3SSunil Goutham RX_RED = 0x4, 1644863dea3SSunil Goutham RX_RED_OCTS = 0x5, 1654863dea3SSunil Goutham RX_ORUN = 0x6, 1664863dea3SSunil Goutham RX_ORUN_OCTS = 0x7, 1674863dea3SSunil Goutham RX_FCS = 0x8, 1684863dea3SSunil Goutham RX_L2ERR = 0x9, 1694863dea3SSunil Goutham RX_DRP_BCAST = 0xa, 1704863dea3SSunil Goutham RX_DRP_MCAST = 0xb, 1714863dea3SSunil Goutham RX_DRP_L3BCAST = 0xc, 1724863dea3SSunil Goutham RX_DRP_L3MCAST = 0xd, 1734863dea3SSunil Goutham RX_STATS_ENUM_LAST, 1744863dea3SSunil Goutham }; 1754863dea3SSunil Goutham 1764863dea3SSunil Goutham enum tx_stats_reg_offset { 1774863dea3SSunil Goutham TX_OCTS = 0x0, 1784863dea3SSunil Goutham TX_UCAST = 0x1, 1794863dea3SSunil Goutham TX_BCAST = 0x2, 1804863dea3SSunil Goutham TX_MCAST = 0x3, 1814863dea3SSunil Goutham TX_DROP = 0x4, 1824863dea3SSunil Goutham TX_STATS_ENUM_LAST, 1834863dea3SSunil Goutham }; 1844863dea3SSunil Goutham 1854863dea3SSunil Goutham struct nicvf_hw_stats { 186a2dc5dedSSunil Goutham u64 rx_bytes; 187964cb69bSSunil Goutham u64 rx_frames; 188a2dc5dedSSunil Goutham u64 rx_ucast_frames; 189a2dc5dedSSunil Goutham u64 rx_bcast_frames; 190a2dc5dedSSunil Goutham u64 rx_mcast_frames; 191964cb69bSSunil Goutham u64 rx_drops; 1924863dea3SSunil Goutham u64 rx_drop_red; 1934863dea3SSunil Goutham u64 rx_drop_red_bytes; 1944863dea3SSunil Goutham u64 rx_drop_overrun; 1954863dea3SSunil Goutham u64 rx_drop_overrun_bytes; 1964863dea3SSunil Goutham u64 rx_drop_bcast; 1974863dea3SSunil Goutham u64 rx_drop_mcast; 1984863dea3SSunil Goutham u64 rx_drop_l3_bcast; 1994863dea3SSunil Goutham u64 rx_drop_l3_mcast; 200964cb69bSSunil Goutham u64 rx_fcs_errors; 201964cb69bSSunil Goutham u64 rx_l2_errors; 202964cb69bSSunil Goutham 203964cb69bSSunil Goutham u64 tx_bytes; 204964cb69bSSunil Goutham u64 tx_frames; 205964cb69bSSunil Goutham u64 tx_ucast_frames; 206964cb69bSSunil Goutham u64 tx_bcast_frames; 207964cb69bSSunil Goutham u64 tx_mcast_frames; 208964cb69bSSunil Goutham u64 tx_drops; 209964cb69bSSunil Goutham }; 210964cb69bSSunil Goutham 211964cb69bSSunil Goutham struct nicvf_drv_stats { 212964cb69bSSunil Goutham /* CQE Rx errs */ 213a2dc5dedSSunil Goutham u64 rx_bgx_truncated_pkts; 214a2dc5dedSSunil Goutham u64 rx_jabber_errs; 215a2dc5dedSSunil Goutham u64 rx_fcs_errs; 216a2dc5dedSSunil Goutham u64 rx_bgx_errs; 217a2dc5dedSSunil Goutham u64 rx_prel2_errs; 218a2dc5dedSSunil Goutham u64 rx_l2_hdr_malformed; 219a2dc5dedSSunil Goutham u64 rx_oversize; 220a2dc5dedSSunil Goutham u64 rx_undersize; 221a2dc5dedSSunil Goutham u64 rx_l2_len_mismatch; 222a2dc5dedSSunil Goutham u64 rx_l2_pclp; 223a2dc5dedSSunil Goutham u64 rx_ip_ver_errs; 224a2dc5dedSSunil Goutham u64 rx_ip_csum_errs; 225a2dc5dedSSunil Goutham u64 rx_ip_hdr_malformed; 226a2dc5dedSSunil Goutham u64 rx_ip_payload_malformed; 227a2dc5dedSSunil Goutham u64 rx_ip_ttl_errs; 228a2dc5dedSSunil Goutham u64 rx_l3_pclp; 229a2dc5dedSSunil Goutham u64 rx_l4_malformed; 230a2dc5dedSSunil Goutham u64 rx_l4_csum_errs; 231a2dc5dedSSunil Goutham u64 rx_udp_len_errs; 232a2dc5dedSSunil Goutham u64 rx_l4_port_errs; 233a2dc5dedSSunil Goutham u64 rx_tcp_flag_errs; 234a2dc5dedSSunil Goutham u64 rx_tcp_offset_errs; 235a2dc5dedSSunil Goutham u64 rx_l4_pclp; 236a2dc5dedSSunil Goutham u64 rx_truncated_pkts; 237a2dc5dedSSunil Goutham 238964cb69bSSunil Goutham /* CQE Tx errs */ 239964cb69bSSunil Goutham u64 tx_desc_fault; 240964cb69bSSunil Goutham u64 tx_hdr_cons_err; 241964cb69bSSunil Goutham u64 tx_subdesc_err; 242964cb69bSSunil Goutham u64 tx_max_size_exceeded; 243964cb69bSSunil Goutham u64 tx_imm_size_oflow; 244964cb69bSSunil Goutham u64 tx_data_seq_err; 245964cb69bSSunil Goutham u64 tx_mem_seq_err; 246964cb69bSSunil Goutham u64 tx_lock_viol; 247964cb69bSSunil Goutham u64 tx_data_fault; 248964cb69bSSunil Goutham u64 tx_tstmp_conflict; 249964cb69bSSunil Goutham u64 tx_tstmp_timeout; 250964cb69bSSunil Goutham u64 tx_mem_fault; 251964cb69bSSunil Goutham u64 tx_csum_overlap; 252964cb69bSSunil Goutham u64 tx_csum_overflow; 2534863dea3SSunil Goutham 254964cb69bSSunil Goutham /* driver debug stats */ 2554863dea3SSunil Goutham u64 tx_tso; 256a05d4845SThanneeru Srinivasulu u64 tx_timeout; 25774840b83SSunil Goutham u64 txq_stop; 25874840b83SSunil Goutham u64 txq_wake; 259964cb69bSSunil Goutham 2605836b442SSunil Goutham u64 rcv_buffer_alloc_failures; 2615836b442SSunil Goutham u64 page_alloc; 2625836b442SSunil Goutham 263964cb69bSSunil Goutham struct u64_stats_sync syncp; 2644863dea3SSunil Goutham }; 2654863dea3SSunil Goutham 2664a875509SSunil Goutham struct cavium_ptp; 2674a875509SSunil Goutham 2681b6d55f2SVadim Lomovtsev struct xcast_addr_list { 2691b6d55f2SVadim Lomovtsev int count; 2709b5c4dfbSVadim Lomovtsev u64 mc[]; 2711b6d55f2SVadim Lomovtsev }; 2721b6d55f2SVadim Lomovtsev 2731b6d55f2SVadim Lomovtsev struct nicvf_work { 2742ecbe4f4SVadim Lomovtsev struct work_struct work; 2751b6d55f2SVadim Lomovtsev u8 mode; 2761b6d55f2SVadim Lomovtsev struct xcast_addr_list *mc; 2771b6d55f2SVadim Lomovtsev }; 2781b6d55f2SVadim Lomovtsev 2794863dea3SSunil Goutham struct nicvf { 28092dc8769SSunil Goutham struct nicvf *pnicvf; 2814863dea3SSunil Goutham struct net_device *netdev; 2824863dea3SSunil Goutham struct pci_dev *pdev; 2834863dea3SSunil Goutham void __iomem *reg_base; 28405c773f5SSunil Goutham struct bpf_prog *xdp_prog; 285a5c3d498SSunil Goutham #define MAX_QUEUES_PER_QSET 8 2861d368790SSunil Goutham struct queue_set *qs; 28783abb7d7SSunil Goutham void *iommu_domain; 2881d368790SSunil Goutham u8 vf_id; 2891d368790SSunil Goutham u8 sqs_id; 2901d368790SSunil Goutham bool sqs_mode; 2911d368790SSunil Goutham bool hw_tso; 2927ceb8a13SSunil Goutham bool t88; 2931d368790SSunil Goutham 2941d368790SSunil Goutham /* Receive buffer alloc */ 2954863dea3SSunil Goutham u32 rb_page_offset; 2965c2e26f6SSunil Goutham u16 rb_pageref; 2974863dea3SSunil Goutham bool rb_alloc_fail; 2984863dea3SSunil Goutham bool rb_work_scheduled; 2991d368790SSunil Goutham struct page *rb_page; 3004863dea3SSunil Goutham struct delayed_work rbdr_work; 3014863dea3SSunil Goutham struct tasklet_struct rbdr_task; 3021d368790SSunil Goutham 3031d368790SSunil Goutham /* Secondary Qset */ 3041d368790SSunil Goutham u8 sqs_count; 3051d368790SSunil Goutham #define MAX_SQS_PER_VF_SINGLE_NODE 5 3061d368790SSunil Goutham #define MAX_SQS_PER_VF 11 3071d368790SSunil Goutham struct nicvf *snicvf[MAX_SQS_PER_VF]; 3081d368790SSunil Goutham 3091d368790SSunil Goutham /* Queue count */ 3101d368790SSunil Goutham u8 rx_queues; 3111d368790SSunil Goutham u8 tx_queues; 31205c773f5SSunil Goutham u8 xdp_tx_queues; 3131d368790SSunil Goutham u8 max_queues; 3141d368790SSunil Goutham 3151d368790SSunil Goutham u8 node; 3164863dea3SSunil Goutham u8 cpi_alg; 3171d368790SSunil Goutham bool link_up; 3181cc70259SThanneeru Srinivasulu u8 mac_type; 3191d368790SSunil Goutham u8 duplex; 3201d368790SSunil Goutham u32 speed; 3211d368790SSunil Goutham bool tns_mode; 3221d368790SSunil Goutham bool loopback_supported; 3231d368790SSunil Goutham struct nicvf_rss_info rss_info; 324430da208SSunil Goutham struct nicvf_pfc pfc; 3251d368790SSunil Goutham struct tasklet_struct qs_err_task; 3261d368790SSunil Goutham struct work_struct reset_task; 3271b6d55f2SVadim Lomovtsev struct nicvf_work rx_mode_work; 328469998c8SVadim Lomovtsev /* spinlock to protect workqueue arguments from concurrent access */ 329469998c8SVadim Lomovtsev spinlock_t rx_mode_wq_lock; 3302ecbe4f4SVadim Lomovtsev /* workqueue for handling kernel ndo_set_rx_mode() calls */ 3312ecbe4f4SVadim Lomovtsev struct workqueue_struct *nicvf_rx_mode_wq; 332609ea65cSVadim Lomovtsev /* mutex to protect VF's mailbox contents from concurrent access */ 333609ea65cSVadim Lomovtsev struct mutex rx_mode_mtx; 3341d368790SSunil Goutham 3354a875509SSunil Goutham /* PTP timestamp */ 3364a875509SSunil Goutham struct cavium_ptp *ptp_clock; 3374a875509SSunil Goutham /* Inbound timestamping is on */ 3384a875509SSunil Goutham bool hw_rx_tstamp; 3394a875509SSunil Goutham /* When the packet that requires timestamping is sent, hardware inserts 3404a875509SSunil Goutham * two entries to the completion queue. First is the regular 3414a875509SSunil Goutham * CQE_TYPE_SEND entry that signals that the packet was sent. 3424a875509SSunil Goutham * The second is CQE_TYPE_SEND_PTP that contains the actual timestamp 3434a875509SSunil Goutham * for that packet. 3444a875509SSunil Goutham * `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND 3454a875509SSunil Goutham * entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP 3464a875509SSunil Goutham * entry. 3474a875509SSunil Goutham * So `ptp_skb` is used to hold the pointer to the packet between 3484a875509SSunil Goutham * the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers. 3494a875509SSunil Goutham */ 3504a875509SSunil Goutham struct sk_buff *ptp_skb; 3514a875509SSunil Goutham /* `tx_ptp_skbs` is set when the hardware is sending a packet that 3524a875509SSunil Goutham * requires timestamping. Cavium hardware can not process more than one 3534a875509SSunil Goutham * such packet at once so this is set each time the driver submits 3544a875509SSunil Goutham * a packet that requires timestamping to the send queue and clears 3554a875509SSunil Goutham * each time it receives the entry on the completion queue saying 3564a875509SSunil Goutham * that such packet was sent. 3574a875509SSunil Goutham * So `tx_ptp_skbs` prevents driver from submitting more than one 3584a875509SSunil Goutham * packet that requires timestamping to the hardware for transmitting. 3594a875509SSunil Goutham */ 3604a875509SSunil Goutham atomic_t tx_ptp_skbs; 3614a875509SSunil Goutham 3624863dea3SSunil Goutham /* Interrupt coalescing settings */ 3634863dea3SSunil Goutham u32 cq_coalesce_usecs; 3644863dea3SSunil Goutham u32 msg_enable; 3651d368790SSunil Goutham 3661d368790SSunil Goutham /* Stats */ 367a2dc5dedSSunil Goutham struct nicvf_hw_stats hw_stats; 368964cb69bSSunil Goutham struct nicvf_drv_stats __percpu *drv_stats; 3694863dea3SSunil Goutham struct bgx_stats bgx_stats; 3704863dea3SSunil Goutham 37105c773f5SSunil Goutham /* Napi */ 37205c773f5SSunil Goutham struct nicvf_cq_poll *napi[8]; 37305c773f5SSunil Goutham 3744863dea3SSunil Goutham /* MSI-X */ 3754863dea3SSunil Goutham u8 num_vec; 376b4e28c1fSSunil Goutham char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15]; 3774863dea3SSunil Goutham bool irq_allocated[NIC_VF_MSIX_VECTORS]; 378fb4b7d98SSunil Goutham cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; 3794863dea3SSunil Goutham 3806051cba7SSunil Goutham /* VF <-> PF mailbox communication */ 3814863dea3SSunil Goutham bool pf_acked; 3824863dea3SSunil Goutham bool pf_nacked; 383bd049a90SPavel Fedin bool set_mac_pending; 3844863dea3SSunil Goutham } ____cacheline_aligned_in_smp; 3854863dea3SSunil Goutham 3864863dea3SSunil Goutham /* PF <--> VF Mailbox communication 3874863dea3SSunil Goutham * Eight 64bit registers are shared between PF and VF. 3884863dea3SSunil Goutham * Separate set for each VF. 3894863dea3SSunil Goutham * Writing '1' into last register mbx7 means end of message. 3904863dea3SSunil Goutham */ 3914863dea3SSunil Goutham 3924863dea3SSunil Goutham /* PF <--> VF mailbox communication */ 3934863dea3SSunil Goutham #define NIC_PF_VF_MAILBOX_SIZE 2 3944863dea3SSunil Goutham #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 3954863dea3SSunil Goutham 3964863dea3SSunil Goutham /* Mailbox message types */ 3974863dea3SSunil Goutham #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 3984863dea3SSunil Goutham #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 3994863dea3SSunil Goutham #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 4004863dea3SSunil Goutham #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 4014863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 4024863dea3SSunil Goutham #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 4034863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 4044863dea3SSunil Goutham #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 4054863dea3SSunil Goutham #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 4064863dea3SSunil Goutham #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 4074863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 4084863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 4094863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 4104863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 4114863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 4124863dea3SSunil Goutham #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 4134863dea3SSunil Goutham #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 41492dc8769SSunil Goutham #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 41592dc8769SSunil Goutham #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 41692dc8769SSunil Goutham #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 41792dc8769SSunil Goutham #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 418d77a2384SSunil Goutham #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 4193458c40dSJerin Jacob #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ 420430da208SSunil Goutham #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */ 4214a875509SSunil Goutham #define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */ 42292dc8769SSunil Goutham #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 42392dc8769SSunil Goutham #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 4240b849f58SVadim Lomovtsev #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ 4250b849f58SVadim Lomovtsev #define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */ 4260b849f58SVadim Lomovtsev #define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */ 4274863dea3SSunil Goutham 4284863dea3SSunil Goutham struct nic_cfg_msg { 4294863dea3SSunil Goutham u8 msg; 4304863dea3SSunil Goutham u8 vf_id; 4314863dea3SSunil Goutham u8 node_id; 43292dc8769SSunil Goutham u8 tns_mode:1; 43392dc8769SSunil Goutham u8 sqs_mode:1; 434d77a2384SSunil Goutham u8 loopback_supported:1; 435e610cb32SAleksey Makarov u8 mac_addr[ETH_ALEN]; 4364863dea3SSunil Goutham }; 4374863dea3SSunil Goutham 4384863dea3SSunil Goutham /* Qset configuration */ 4394863dea3SSunil Goutham struct qs_cfg_msg { 4404863dea3SSunil Goutham u8 msg; 4414863dea3SSunil Goutham u8 num; 44292dc8769SSunil Goutham u8 sqs_count; 4434863dea3SSunil Goutham u64 cfg; 4444863dea3SSunil Goutham }; 4454863dea3SSunil Goutham 4464863dea3SSunil Goutham /* Receive queue configuration */ 4474863dea3SSunil Goutham struct rq_cfg_msg { 4484863dea3SSunil Goutham u8 msg; 4494863dea3SSunil Goutham u8 qs_num; 4504863dea3SSunil Goutham u8 rq_num; 4514863dea3SSunil Goutham u64 cfg; 4524863dea3SSunil Goutham }; 4534863dea3SSunil Goutham 4544863dea3SSunil Goutham /* Send queue configuration */ 4554863dea3SSunil Goutham struct sq_cfg_msg { 4564863dea3SSunil Goutham u8 msg; 4574863dea3SSunil Goutham u8 qs_num; 4584863dea3SSunil Goutham u8 sq_num; 45992dc8769SSunil Goutham bool sqs_mode; 4604863dea3SSunil Goutham u64 cfg; 4614863dea3SSunil Goutham }; 4624863dea3SSunil Goutham 4634863dea3SSunil Goutham /* Set VF's MAC address */ 4644863dea3SSunil Goutham struct set_mac_msg { 4654863dea3SSunil Goutham u8 msg; 4664863dea3SSunil Goutham u8 vf_id; 467e610cb32SAleksey Makarov u8 mac_addr[ETH_ALEN]; 4684863dea3SSunil Goutham }; 4694863dea3SSunil Goutham 4704863dea3SSunil Goutham /* Set Maximum frame size */ 4714863dea3SSunil Goutham struct set_frs_msg { 4724863dea3SSunil Goutham u8 msg; 4734863dea3SSunil Goutham u8 vf_id; 4744863dea3SSunil Goutham u16 max_frs; 4754863dea3SSunil Goutham }; 4764863dea3SSunil Goutham 4774863dea3SSunil Goutham /* Set CPI algorithm type */ 4784863dea3SSunil Goutham struct cpi_cfg_msg { 4794863dea3SSunil Goutham u8 msg; 4804863dea3SSunil Goutham u8 vf_id; 4814863dea3SSunil Goutham u8 rq_cnt; 4824863dea3SSunil Goutham u8 cpi_alg; 4834863dea3SSunil Goutham }; 4844863dea3SSunil Goutham 4854863dea3SSunil Goutham /* Get RSS table size */ 4864863dea3SSunil Goutham struct rss_sz_msg { 4874863dea3SSunil Goutham u8 msg; 4884863dea3SSunil Goutham u8 vf_id; 4894863dea3SSunil Goutham u16 ind_tbl_size; 4904863dea3SSunil Goutham }; 4914863dea3SSunil Goutham 4924863dea3SSunil Goutham /* Set RSS configuration */ 4934863dea3SSunil Goutham struct rss_cfg_msg { 4944863dea3SSunil Goutham u8 msg; 4954863dea3SSunil Goutham u8 vf_id; 4964863dea3SSunil Goutham u8 hash_bits; 4974863dea3SSunil Goutham u8 tbl_len; 4984863dea3SSunil Goutham u8 tbl_offset; 4994863dea3SSunil Goutham #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 5004863dea3SSunil Goutham u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 5014863dea3SSunil Goutham }; 5024863dea3SSunil Goutham 5034863dea3SSunil Goutham struct bgx_stats_msg { 5044863dea3SSunil Goutham u8 msg; 5054863dea3SSunil Goutham u8 vf_id; 5064863dea3SSunil Goutham u8 rx; 5074863dea3SSunil Goutham u8 idx; 5084863dea3SSunil Goutham u64 stats; 5094863dea3SSunil Goutham }; 5104863dea3SSunil Goutham 5114863dea3SSunil Goutham /* Physical interface link status */ 5124863dea3SSunil Goutham struct bgx_link_status { 5134863dea3SSunil Goutham u8 msg; 5141cc70259SThanneeru Srinivasulu u8 mac_type; 5154863dea3SSunil Goutham u8 link_up; 5164863dea3SSunil Goutham u8 duplex; 5174863dea3SSunil Goutham u32 speed; 5184863dea3SSunil Goutham }; 5194863dea3SSunil Goutham 52092dc8769SSunil Goutham /* Get Extra Qset IDs */ 52192dc8769SSunil Goutham struct sqs_alloc { 52292dc8769SSunil Goutham u8 msg; 52392dc8769SSunil Goutham u8 vf_id; 52492dc8769SSunil Goutham u8 qs_count; 52592dc8769SSunil Goutham }; 52692dc8769SSunil Goutham 52792dc8769SSunil Goutham struct nicvf_ptr { 52892dc8769SSunil Goutham u8 msg; 52992dc8769SSunil Goutham u8 vf_id; 53092dc8769SSunil Goutham bool sqs_mode; 53192dc8769SSunil Goutham u8 sqs_id; 53292dc8769SSunil Goutham u64 nicvf; 53392dc8769SSunil Goutham }; 53492dc8769SSunil Goutham 535d77a2384SSunil Goutham /* Set interface in loopback mode */ 536d77a2384SSunil Goutham struct set_loopback { 537d77a2384SSunil Goutham u8 msg; 538d77a2384SSunil Goutham u8 vf_id; 539d77a2384SSunil Goutham bool enable; 540d77a2384SSunil Goutham }; 541d77a2384SSunil Goutham 5423458c40dSJerin Jacob /* Reset statistics counters */ 5433458c40dSJerin Jacob struct reset_stat_cfg { 5443458c40dSJerin Jacob u8 msg; 5453458c40dSJerin Jacob /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */ 5463458c40dSJerin Jacob u16 rx_stat_mask; 5473458c40dSJerin Jacob /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */ 5483458c40dSJerin Jacob u8 tx_stat_mask; 5493458c40dSJerin Jacob /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1) 5503458c40dSJerin Jacob * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1) 5513458c40dSJerin Jacob * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1) 5523458c40dSJerin Jacob * .. 5533458c40dSJerin Jacob * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1) 5543458c40dSJerin Jacob * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1) 5553458c40dSJerin Jacob */ 5563458c40dSJerin Jacob u16 rq_stat_mask; 5573458c40dSJerin Jacob /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1) 5583458c40dSJerin Jacob * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1) 5593458c40dSJerin Jacob * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1) 5603458c40dSJerin Jacob * .. 5613458c40dSJerin Jacob * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1) 5623458c40dSJerin Jacob * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1) 5633458c40dSJerin Jacob */ 5643458c40dSJerin Jacob u16 sq_stat_mask; 5653458c40dSJerin Jacob }; 5663458c40dSJerin Jacob 567430da208SSunil Goutham struct pfc { 568430da208SSunil Goutham u8 msg; 569430da208SSunil Goutham u8 get; /* Get or set PFC settings */ 570430da208SSunil Goutham u8 autoneg; 571430da208SSunil Goutham u8 fc_rx; 572430da208SSunil Goutham u8 fc_tx; 573430da208SSunil Goutham }; 574430da208SSunil Goutham 5754a875509SSunil Goutham struct set_ptp { 5764a875509SSunil Goutham u8 msg; 5774a875509SSunil Goutham bool enable; 5784a875509SSunil Goutham }; 5794a875509SSunil Goutham 5800b849f58SVadim Lomovtsev struct xcast { 5810b849f58SVadim Lomovtsev u8 msg; 5820b849f58SVadim Lomovtsev u8 mode; 58353544396SVadim Lomovtsev u64 mac:48; 5840b849f58SVadim Lomovtsev }; 5850b849f58SVadim Lomovtsev 5864863dea3SSunil Goutham /* 128 bit shared memory between PF and each VF */ 5874863dea3SSunil Goutham union nic_mbx { 5884863dea3SSunil Goutham struct { u8 msg; } msg; 5894863dea3SSunil Goutham struct nic_cfg_msg nic_cfg; 5904863dea3SSunil Goutham struct qs_cfg_msg qs; 5914863dea3SSunil Goutham struct rq_cfg_msg rq; 5924863dea3SSunil Goutham struct sq_cfg_msg sq; 5934863dea3SSunil Goutham struct set_mac_msg mac; 5944863dea3SSunil Goutham struct set_frs_msg frs; 5954863dea3SSunil Goutham struct cpi_cfg_msg cpi_cfg; 5964863dea3SSunil Goutham struct rss_sz_msg rss_size; 5974863dea3SSunil Goutham struct rss_cfg_msg rss_cfg; 5984863dea3SSunil Goutham struct bgx_stats_msg bgx_stats; 5994863dea3SSunil Goutham struct bgx_link_status link_status; 60092dc8769SSunil Goutham struct sqs_alloc sqs_alloc; 60192dc8769SSunil Goutham struct nicvf_ptr nicvf; 602d77a2384SSunil Goutham struct set_loopback lbk; 6033458c40dSJerin Jacob struct reset_stat_cfg reset_stat; 604430da208SSunil Goutham struct pfc pfc; 6054a875509SSunil Goutham struct set_ptp ptp; 6060b849f58SVadim Lomovtsev struct xcast xcast; 6074863dea3SSunil Goutham }; 6084863dea3SSunil Goutham 609d768b678SRobert Richter #define NIC_NODE_ID_MASK 0x03 610d768b678SRobert Richter #define NIC_NODE_ID_SHIFT 44 611d768b678SRobert Richter 612d768b678SRobert Richter static inline int nic_get_node_id(struct pci_dev *pdev) 613d768b678SRobert Richter { 614d768b678SRobert Richter u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 615d768b678SRobert Richter return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 616d768b678SRobert Richter } 617d768b678SRobert Richter 61840fb5f8aSSunil Goutham static inline bool pass1_silicon(struct pci_dev *pdev) 61940fb5f8aSSunil Goutham { 62002a72bd8SSunil Goutham return (pdev->revision < 8) && 62102a72bd8SSunil Goutham (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); 62202a72bd8SSunil Goutham } 62302a72bd8SSunil Goutham 62402a72bd8SSunil Goutham static inline bool pass2_silicon(struct pci_dev *pdev) 62502a72bd8SSunil Goutham { 62602a72bd8SSunil Goutham return (pdev->revision >= 8) && 62702a72bd8SSunil Goutham (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); 62840fb5f8aSSunil Goutham } 62940fb5f8aSSunil Goutham 6304863dea3SSunil Goutham int nicvf_set_real_num_queues(struct net_device *netdev, 6314863dea3SSunil Goutham int tx_queues, int rx_queues); 6324863dea3SSunil Goutham int nicvf_open(struct net_device *netdev); 6334863dea3SSunil Goutham int nicvf_stop(struct net_device *netdev); 6344863dea3SSunil Goutham int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 6354863dea3SSunil Goutham void nicvf_config_rss(struct nicvf *nic); 6364863dea3SSunil Goutham void nicvf_set_rss_key(struct nicvf *nic); 6374863dea3SSunil Goutham void nicvf_set_ethtool_ops(struct net_device *netdev); 6384863dea3SSunil Goutham void nicvf_update_stats(struct nicvf *nic); 6394863dea3SSunil Goutham void nicvf_update_lmac_stats(struct nicvf *nic); 6404863dea3SSunil Goutham 6414863dea3SSunil Goutham #endif /* NIC_H */ 642