14863dea3SSunil Goutham /* 24863dea3SSunil Goutham * Copyright (C) 2015 Cavium, Inc. 34863dea3SSunil Goutham * 44863dea3SSunil Goutham * This program is free software; you can redistribute it and/or modify it 54863dea3SSunil Goutham * under the terms of version 2 of the GNU General Public License 64863dea3SSunil Goutham * as published by the Free Software Foundation. 74863dea3SSunil Goutham */ 84863dea3SSunil Goutham 94863dea3SSunil Goutham #ifndef NIC_H 104863dea3SSunil Goutham #define NIC_H 114863dea3SSunil Goutham 124863dea3SSunil Goutham #include <linux/netdevice.h> 134863dea3SSunil Goutham #include <linux/interrupt.h> 14d768b678SRobert Richter #include <linux/pci.h> 154863dea3SSunil Goutham #include "thunder_bgx.h" 164863dea3SSunil Goutham 174863dea3SSunil Goutham /* PCI device IDs */ 184863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 194863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 204863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 214863dea3SSunil Goutham #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 224863dea3SSunil Goutham 23a5c3d498SSunil Goutham /* Subsystem device IDs */ 24a5c3d498SSunil Goutham #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E 25f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E 26f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E 27f7ff0ae8SSunil Goutham 28f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E 29f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134 30f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234 31f7ff0ae8SSunil Goutham #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334 32f7ff0ae8SSunil Goutham 33a5c3d498SSunil Goutham 344863dea3SSunil Goutham /* PCI BAR nos */ 354863dea3SSunil Goutham #define PCI_CFG_REG_BAR_NUM 0 364863dea3SSunil Goutham #define PCI_MSIX_REG_BAR_NUM 4 374863dea3SSunil Goutham 384863dea3SSunil Goutham /* NIC SRIOV VF count */ 394863dea3SSunil Goutham #define MAX_NUM_VFS_SUPPORTED 128 404863dea3SSunil Goutham #define DEFAULT_NUM_VF_ENABLED 8 414863dea3SSunil Goutham 424863dea3SSunil Goutham #define NIC_TNS_BYPASS_MODE 0 434863dea3SSunil Goutham #define NIC_TNS_MODE 1 444863dea3SSunil Goutham 454863dea3SSunil Goutham /* NIC priv flags */ 464863dea3SSunil Goutham #define NIC_SRIOV_ENABLED BIT(0) 474863dea3SSunil Goutham 484863dea3SSunil Goutham /* Min/Max packet size */ 494863dea3SSunil Goutham #define NIC_HW_MIN_FRS 64 504863dea3SSunil Goutham #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 514863dea3SSunil Goutham 524863dea3SSunil Goutham /* Max pkinds */ 534863dea3SSunil Goutham #define NIC_MAX_PKIND 16 544863dea3SSunil Goutham 55a5c3d498SSunil Goutham /* Max when CPI_ALG is IP diffserv */ 56a5c3d498SSunil Goutham #define NIC_MAX_CPI_PER_LMAC 64 574863dea3SSunil Goutham 584863dea3SSunil Goutham /* NIC VF Interrupts */ 594863dea3SSunil Goutham #define NICVF_INTR_CQ 0 604863dea3SSunil Goutham #define NICVF_INTR_SQ 1 614863dea3SSunil Goutham #define NICVF_INTR_RBDR 2 624863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP 3 634863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER 4 644863dea3SSunil Goutham #define NICVF_INTR_MBOX 5 654863dea3SSunil Goutham #define NICVF_INTR_QS_ERR 6 664863dea3SSunil Goutham 674863dea3SSunil Goutham #define NICVF_INTR_CQ_SHIFT 0 684863dea3SSunil Goutham #define NICVF_INTR_SQ_SHIFT 8 694863dea3SSunil Goutham #define NICVF_INTR_RBDR_SHIFT 16 704863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP_SHIFT 20 714863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER_SHIFT 21 724863dea3SSunil Goutham #define NICVF_INTR_MBOX_SHIFT 22 734863dea3SSunil Goutham #define NICVF_INTR_QS_ERR_SHIFT 23 744863dea3SSunil Goutham 754863dea3SSunil Goutham #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 764863dea3SSunil Goutham #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 774863dea3SSunil Goutham #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 784863dea3SSunil Goutham #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) 794863dea3SSunil Goutham #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) 804863dea3SSunil Goutham #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) 814863dea3SSunil Goutham #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) 824863dea3SSunil Goutham 834863dea3SSunil Goutham /* MSI-X interrupts */ 844863dea3SSunil Goutham #define NIC_PF_MSIX_VECTORS 10 854863dea3SSunil Goutham #define NIC_VF_MSIX_VECTORS 20 864863dea3SSunil Goutham 874863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC0_SBE 0 884863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC0_DBE 1 894863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC1_SBE 2 904863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC1_DBE 3 914863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC2_SBE 4 924863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC2_DBE 5 934863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC3_SBE 6 944863dea3SSunil Goutham #define NIC_PF_INTR_ID_ECC3_DBE 7 954863dea3SSunil Goutham #define NIC_PF_INTR_ID_MBOX0 8 964863dea3SSunil Goutham #define NIC_PF_INTR_ID_MBOX1 9 974863dea3SSunil Goutham 984c0b6eafSSunil Goutham /* Minimum FIFO level before all packets for the CQ are dropped 994c0b6eafSSunil Goutham * 1004c0b6eafSSunil Goutham * This value ensures that once a packet has been "accepted" 1014c0b6eafSSunil Goutham * for reception it will not get dropped due to non-availability 1024c0b6eafSSunil Goutham * of CQ descriptor. An errata in HW mandates this value to be 1034c0b6eafSSunil Goutham * atleast 0x100. 1044c0b6eafSSunil Goutham */ 1054c0b6eafSSunil Goutham #define NICPF_CQM_MIN_DROP_LEVEL 0x100 1064c0b6eafSSunil Goutham 1074863dea3SSunil Goutham /* Global timer for CQ timer thresh interrupts 1084863dea3SSunil Goutham * Calculated for SCLK of 700Mhz 1094863dea3SSunil Goutham * value written should be a 1/16th of what is expected 1104863dea3SSunil Goutham * 111006394a7SSunil Goutham * 1 tick per 0.025usec 1124863dea3SSunil Goutham */ 113006394a7SSunil Goutham #define NICPF_CLK_PER_INT_TICK 1 1144863dea3SSunil Goutham 1153d7a8aaaSSunil Goutham /* Time to wait before we decide that a SQ is stuck. 1163d7a8aaaSSunil Goutham * 1173d7a8aaaSSunil Goutham * Since both pkt rx and tx notifications are done with same CQ, 1183d7a8aaaSSunil Goutham * when packets are being received at very high rate (eg: L2 forwarding) 1193d7a8aaaSSunil Goutham * then freeing transmitted skbs will be delayed and watchdog 1203d7a8aaaSSunil Goutham * will kick in, resetting interface. Hence keeping this value high. 1213d7a8aaaSSunil Goutham */ 1223d7a8aaaSSunil Goutham #define NICVF_TX_TIMEOUT (50 * HZ) 1233d7a8aaaSSunil Goutham 1244863dea3SSunil Goutham struct nicvf_cq_poll { 12539ad6eeaSSunil Goutham struct nicvf *nicvf; 1264863dea3SSunil Goutham u8 cq_idx; /* Completion queue index */ 1274863dea3SSunil Goutham struct napi_struct napi; 1284863dea3SSunil Goutham }; 1294863dea3SSunil Goutham 1304863dea3SSunil Goutham #define NIC_MAX_RSS_HASH_BITS 8 1314863dea3SSunil Goutham #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 1324863dea3SSunil Goutham #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 1334863dea3SSunil Goutham 1344863dea3SSunil Goutham struct nicvf_rss_info { 1354863dea3SSunil Goutham bool enable; 1364863dea3SSunil Goutham #define RSS_L2_EXTENDED_HASH_ENA BIT(0) 1374863dea3SSunil Goutham #define RSS_IP_HASH_ENA BIT(1) 1384863dea3SSunil Goutham #define RSS_TCP_HASH_ENA BIT(2) 1394863dea3SSunil Goutham #define RSS_TCP_SYN_DIS BIT(3) 1404863dea3SSunil Goutham #define RSS_UDP_HASH_ENA BIT(4) 1414863dea3SSunil Goutham #define RSS_L4_EXTENDED_HASH_ENA BIT(5) 1424863dea3SSunil Goutham #define RSS_ROCE_ENA BIT(6) 1434863dea3SSunil Goutham #define RSS_L3_BI_DIRECTION_ENA BIT(7) 1444863dea3SSunil Goutham #define RSS_L4_BI_DIRECTION_ENA BIT(8) 1454863dea3SSunil Goutham u64 cfg; 1464863dea3SSunil Goutham u8 hash_bits; 1474863dea3SSunil Goutham u16 rss_size; 1484863dea3SSunil Goutham u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 1494863dea3SSunil Goutham u64 key[RSS_HASH_KEY_SIZE]; 1504863dea3SSunil Goutham } ____cacheline_aligned_in_smp; 1514863dea3SSunil Goutham 1524863dea3SSunil Goutham enum rx_stats_reg_offset { 1534863dea3SSunil Goutham RX_OCTS = 0x0, 1544863dea3SSunil Goutham RX_UCAST = 0x1, 1554863dea3SSunil Goutham RX_BCAST = 0x2, 1564863dea3SSunil Goutham RX_MCAST = 0x3, 1574863dea3SSunil Goutham RX_RED = 0x4, 1584863dea3SSunil Goutham RX_RED_OCTS = 0x5, 1594863dea3SSunil Goutham RX_ORUN = 0x6, 1604863dea3SSunil Goutham RX_ORUN_OCTS = 0x7, 1614863dea3SSunil Goutham RX_FCS = 0x8, 1624863dea3SSunil Goutham RX_L2ERR = 0x9, 1634863dea3SSunil Goutham RX_DRP_BCAST = 0xa, 1644863dea3SSunil Goutham RX_DRP_MCAST = 0xb, 1654863dea3SSunil Goutham RX_DRP_L3BCAST = 0xc, 1664863dea3SSunil Goutham RX_DRP_L3MCAST = 0xd, 1674863dea3SSunil Goutham RX_STATS_ENUM_LAST, 1684863dea3SSunil Goutham }; 1694863dea3SSunil Goutham 1704863dea3SSunil Goutham enum tx_stats_reg_offset { 1714863dea3SSunil Goutham TX_OCTS = 0x0, 1724863dea3SSunil Goutham TX_UCAST = 0x1, 1734863dea3SSunil Goutham TX_BCAST = 0x2, 1744863dea3SSunil Goutham TX_MCAST = 0x3, 1754863dea3SSunil Goutham TX_DROP = 0x4, 1764863dea3SSunil Goutham TX_STATS_ENUM_LAST, 1774863dea3SSunil Goutham }; 1784863dea3SSunil Goutham 1794863dea3SSunil Goutham struct nicvf_hw_stats { 180a2dc5dedSSunil Goutham u64 rx_bytes; 181a2dc5dedSSunil Goutham u64 rx_ucast_frames; 182a2dc5dedSSunil Goutham u64 rx_bcast_frames; 183a2dc5dedSSunil Goutham u64 rx_mcast_frames; 1844863dea3SSunil Goutham u64 rx_fcs_errors; 1854863dea3SSunil Goutham u64 rx_l2_errors; 1864863dea3SSunil Goutham u64 rx_drop_red; 1874863dea3SSunil Goutham u64 rx_drop_red_bytes; 1884863dea3SSunil Goutham u64 rx_drop_overrun; 1894863dea3SSunil Goutham u64 rx_drop_overrun_bytes; 1904863dea3SSunil Goutham u64 rx_drop_bcast; 1914863dea3SSunil Goutham u64 rx_drop_mcast; 1924863dea3SSunil Goutham u64 rx_drop_l3_bcast; 1934863dea3SSunil Goutham u64 rx_drop_l3_mcast; 194a2dc5dedSSunil Goutham u64 rx_bgx_truncated_pkts; 195a2dc5dedSSunil Goutham u64 rx_jabber_errs; 196a2dc5dedSSunil Goutham u64 rx_fcs_errs; 197a2dc5dedSSunil Goutham u64 rx_bgx_errs; 198a2dc5dedSSunil Goutham u64 rx_prel2_errs; 199a2dc5dedSSunil Goutham u64 rx_l2_hdr_malformed; 200a2dc5dedSSunil Goutham u64 rx_oversize; 201a2dc5dedSSunil Goutham u64 rx_undersize; 202a2dc5dedSSunil Goutham u64 rx_l2_len_mismatch; 203a2dc5dedSSunil Goutham u64 rx_l2_pclp; 204a2dc5dedSSunil Goutham u64 rx_ip_ver_errs; 205a2dc5dedSSunil Goutham u64 rx_ip_csum_errs; 206a2dc5dedSSunil Goutham u64 rx_ip_hdr_malformed; 207a2dc5dedSSunil Goutham u64 rx_ip_payload_malformed; 208a2dc5dedSSunil Goutham u64 rx_ip_ttl_errs; 209a2dc5dedSSunil Goutham u64 rx_l3_pclp; 210a2dc5dedSSunil Goutham u64 rx_l4_malformed; 211a2dc5dedSSunil Goutham u64 rx_l4_csum_errs; 212a2dc5dedSSunil Goutham u64 rx_udp_len_errs; 213a2dc5dedSSunil Goutham u64 rx_l4_port_errs; 214a2dc5dedSSunil Goutham u64 rx_tcp_flag_errs; 215a2dc5dedSSunil Goutham u64 rx_tcp_offset_errs; 216a2dc5dedSSunil Goutham u64 rx_l4_pclp; 217a2dc5dedSSunil Goutham u64 rx_truncated_pkts; 218a2dc5dedSSunil Goutham 2194863dea3SSunil Goutham u64 tx_bytes_ok; 2204863dea3SSunil Goutham u64 tx_ucast_frames_ok; 2214863dea3SSunil Goutham u64 tx_bcast_frames_ok; 2224863dea3SSunil Goutham u64 tx_mcast_frames_ok; 2234863dea3SSunil Goutham u64 tx_drops; 2244863dea3SSunil Goutham }; 2254863dea3SSunil Goutham 2264863dea3SSunil Goutham struct nicvf_drv_stats { 2274863dea3SSunil Goutham /* Rx */ 2284863dea3SSunil Goutham u64 rx_frames_ok; 2294863dea3SSunil Goutham u64 rx_frames_64; 2304863dea3SSunil Goutham u64 rx_frames_127; 2314863dea3SSunil Goutham u64 rx_frames_255; 2324863dea3SSunil Goutham u64 rx_frames_511; 2334863dea3SSunil Goutham u64 rx_frames_1023; 2344863dea3SSunil Goutham u64 rx_frames_1518; 2354863dea3SSunil Goutham u64 rx_frames_jumbo; 2364863dea3SSunil Goutham u64 rx_drops; 237a2dc5dedSSunil Goutham 238a05d4845SThanneeru Srinivasulu u64 rcv_buffer_alloc_failures; 239a05d4845SThanneeru Srinivasulu 2404863dea3SSunil Goutham /* Tx */ 2414863dea3SSunil Goutham u64 tx_frames_ok; 2424863dea3SSunil Goutham u64 tx_drops; 2434863dea3SSunil Goutham u64 tx_tso; 244a05d4845SThanneeru Srinivasulu u64 tx_timeout; 24574840b83SSunil Goutham u64 txq_stop; 24674840b83SSunil Goutham u64 txq_wake; 2474863dea3SSunil Goutham }; 2484863dea3SSunil Goutham 2494863dea3SSunil Goutham struct nicvf { 25092dc8769SSunil Goutham struct nicvf *pnicvf; 2514863dea3SSunil Goutham struct net_device *netdev; 2524863dea3SSunil Goutham struct pci_dev *pdev; 2534863dea3SSunil Goutham void __iomem *reg_base; 254a5c3d498SSunil Goutham #define MAX_QUEUES_PER_QSET 8 2551d368790SSunil Goutham struct queue_set *qs; 2561d368790SSunil Goutham struct nicvf_cq_poll *napi[8]; 2571d368790SSunil Goutham u8 vf_id; 2581d368790SSunil Goutham u8 sqs_id; 2591d368790SSunil Goutham bool sqs_mode; 2601d368790SSunil Goutham bool hw_tso; 2611d368790SSunil Goutham 2621d368790SSunil Goutham /* Receive buffer alloc */ 2634863dea3SSunil Goutham u32 rb_page_offset; 2645c2e26f6SSunil Goutham u16 rb_pageref; 2654863dea3SSunil Goutham bool rb_alloc_fail; 2664863dea3SSunil Goutham bool rb_work_scheduled; 2671d368790SSunil Goutham struct page *rb_page; 2684863dea3SSunil Goutham struct delayed_work rbdr_work; 2694863dea3SSunil Goutham struct tasklet_struct rbdr_task; 2701d368790SSunil Goutham 2711d368790SSunil Goutham /* Secondary Qset */ 2721d368790SSunil Goutham u8 sqs_count; 2731d368790SSunil Goutham #define MAX_SQS_PER_VF_SINGLE_NODE 5 2741d368790SSunil Goutham #define MAX_SQS_PER_VF 11 2751d368790SSunil Goutham struct nicvf *snicvf[MAX_SQS_PER_VF]; 2761d368790SSunil Goutham 2771d368790SSunil Goutham /* Queue count */ 2781d368790SSunil Goutham u8 rx_queues; 2791d368790SSunil Goutham u8 tx_queues; 2801d368790SSunil Goutham u8 max_queues; 2811d368790SSunil Goutham 2821d368790SSunil Goutham u8 node; 2834863dea3SSunil Goutham u8 cpi_alg; 2841d368790SSunil Goutham u16 mtu; 2851d368790SSunil Goutham bool link_up; 2861d368790SSunil Goutham u8 duplex; 2871d368790SSunil Goutham u32 speed; 2881d368790SSunil Goutham bool tns_mode; 2891d368790SSunil Goutham bool loopback_supported; 2901d368790SSunil Goutham struct nicvf_rss_info rss_info; 2911d368790SSunil Goutham struct tasklet_struct qs_err_task; 2921d368790SSunil Goutham struct work_struct reset_task; 2931d368790SSunil Goutham 2944863dea3SSunil Goutham /* Interrupt coalescing settings */ 2954863dea3SSunil Goutham u32 cq_coalesce_usecs; 2964863dea3SSunil Goutham u32 msg_enable; 2971d368790SSunil Goutham 2981d368790SSunil Goutham /* Stats */ 299a2dc5dedSSunil Goutham struct nicvf_hw_stats hw_stats; 3004863dea3SSunil Goutham struct nicvf_drv_stats drv_stats; 3014863dea3SSunil Goutham struct bgx_stats bgx_stats; 3024863dea3SSunil Goutham 3034863dea3SSunil Goutham /* MSI-X */ 3044863dea3SSunil Goutham bool msix_enabled; 3054863dea3SSunil Goutham u8 num_vec; 3064863dea3SSunil Goutham struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 3074863dea3SSunil Goutham char irq_name[NIC_VF_MSIX_VECTORS][20]; 3084863dea3SSunil Goutham bool irq_allocated[NIC_VF_MSIX_VECTORS]; 309fb4b7d98SSunil Goutham cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; 3104863dea3SSunil Goutham 3116051cba7SSunil Goutham /* VF <-> PF mailbox communication */ 3124863dea3SSunil Goutham bool pf_acked; 3134863dea3SSunil Goutham bool pf_nacked; 314bd049a90SPavel Fedin bool set_mac_pending; 3154863dea3SSunil Goutham } ____cacheline_aligned_in_smp; 3164863dea3SSunil Goutham 3174863dea3SSunil Goutham /* PF <--> VF Mailbox communication 3184863dea3SSunil Goutham * Eight 64bit registers are shared between PF and VF. 3194863dea3SSunil Goutham * Separate set for each VF. 3204863dea3SSunil Goutham * Writing '1' into last register mbx7 means end of message. 3214863dea3SSunil Goutham */ 3224863dea3SSunil Goutham 3234863dea3SSunil Goutham /* PF <--> VF mailbox communication */ 3244863dea3SSunil Goutham #define NIC_PF_VF_MAILBOX_SIZE 2 3254863dea3SSunil Goutham #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 3264863dea3SSunil Goutham 3274863dea3SSunil Goutham /* Mailbox message types */ 3284863dea3SSunil Goutham #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 3294863dea3SSunil Goutham #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 3304863dea3SSunil Goutham #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 3314863dea3SSunil Goutham #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 3324863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 3334863dea3SSunil Goutham #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 3344863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 3354863dea3SSunil Goutham #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 3364863dea3SSunil Goutham #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 3374863dea3SSunil Goutham #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 3384863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 3394863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 3404863dea3SSunil Goutham #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 3414863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 3424863dea3SSunil Goutham #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 3434863dea3SSunil Goutham #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 3444863dea3SSunil Goutham #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 34592dc8769SSunil Goutham #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 34692dc8769SSunil Goutham #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 34792dc8769SSunil Goutham #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 34892dc8769SSunil Goutham #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 349d77a2384SSunil Goutham #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 3503458c40dSJerin Jacob #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ 35192dc8769SSunil Goutham #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 35292dc8769SSunil Goutham #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 3534863dea3SSunil Goutham 3544863dea3SSunil Goutham struct nic_cfg_msg { 3554863dea3SSunil Goutham u8 msg; 3564863dea3SSunil Goutham u8 vf_id; 3574863dea3SSunil Goutham u8 node_id; 35892dc8769SSunil Goutham u8 tns_mode:1; 35992dc8769SSunil Goutham u8 sqs_mode:1; 360d77a2384SSunil Goutham u8 loopback_supported:1; 361e610cb32SAleksey Makarov u8 mac_addr[ETH_ALEN]; 3624863dea3SSunil Goutham }; 3634863dea3SSunil Goutham 3644863dea3SSunil Goutham /* Qset configuration */ 3654863dea3SSunil Goutham struct qs_cfg_msg { 3664863dea3SSunil Goutham u8 msg; 3674863dea3SSunil Goutham u8 num; 36892dc8769SSunil Goutham u8 sqs_count; 3694863dea3SSunil Goutham u64 cfg; 3704863dea3SSunil Goutham }; 3714863dea3SSunil Goutham 3724863dea3SSunil Goutham /* Receive queue configuration */ 3734863dea3SSunil Goutham struct rq_cfg_msg { 3744863dea3SSunil Goutham u8 msg; 3754863dea3SSunil Goutham u8 qs_num; 3764863dea3SSunil Goutham u8 rq_num; 3774863dea3SSunil Goutham u64 cfg; 3784863dea3SSunil Goutham }; 3794863dea3SSunil Goutham 3804863dea3SSunil Goutham /* Send queue configuration */ 3814863dea3SSunil Goutham struct sq_cfg_msg { 3824863dea3SSunil Goutham u8 msg; 3834863dea3SSunil Goutham u8 qs_num; 3844863dea3SSunil Goutham u8 sq_num; 38592dc8769SSunil Goutham bool sqs_mode; 3864863dea3SSunil Goutham u64 cfg; 3874863dea3SSunil Goutham }; 3884863dea3SSunil Goutham 3894863dea3SSunil Goutham /* Set VF's MAC address */ 3904863dea3SSunil Goutham struct set_mac_msg { 3914863dea3SSunil Goutham u8 msg; 3924863dea3SSunil Goutham u8 vf_id; 393e610cb32SAleksey Makarov u8 mac_addr[ETH_ALEN]; 3944863dea3SSunil Goutham }; 3954863dea3SSunil Goutham 3964863dea3SSunil Goutham /* Set Maximum frame size */ 3974863dea3SSunil Goutham struct set_frs_msg { 3984863dea3SSunil Goutham u8 msg; 3994863dea3SSunil Goutham u8 vf_id; 4004863dea3SSunil Goutham u16 max_frs; 4014863dea3SSunil Goutham }; 4024863dea3SSunil Goutham 4034863dea3SSunil Goutham /* Set CPI algorithm type */ 4044863dea3SSunil Goutham struct cpi_cfg_msg { 4054863dea3SSunil Goutham u8 msg; 4064863dea3SSunil Goutham u8 vf_id; 4074863dea3SSunil Goutham u8 rq_cnt; 4084863dea3SSunil Goutham u8 cpi_alg; 4094863dea3SSunil Goutham }; 4104863dea3SSunil Goutham 4114863dea3SSunil Goutham /* Get RSS table size */ 4124863dea3SSunil Goutham struct rss_sz_msg { 4134863dea3SSunil Goutham u8 msg; 4144863dea3SSunil Goutham u8 vf_id; 4154863dea3SSunil Goutham u16 ind_tbl_size; 4164863dea3SSunil Goutham }; 4174863dea3SSunil Goutham 4184863dea3SSunil Goutham /* Set RSS configuration */ 4194863dea3SSunil Goutham struct rss_cfg_msg { 4204863dea3SSunil Goutham u8 msg; 4214863dea3SSunil Goutham u8 vf_id; 4224863dea3SSunil Goutham u8 hash_bits; 4234863dea3SSunil Goutham u8 tbl_len; 4244863dea3SSunil Goutham u8 tbl_offset; 4254863dea3SSunil Goutham #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 4264863dea3SSunil Goutham u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 4274863dea3SSunil Goutham }; 4284863dea3SSunil Goutham 4294863dea3SSunil Goutham struct bgx_stats_msg { 4304863dea3SSunil Goutham u8 msg; 4314863dea3SSunil Goutham u8 vf_id; 4324863dea3SSunil Goutham u8 rx; 4334863dea3SSunil Goutham u8 idx; 4344863dea3SSunil Goutham u64 stats; 4354863dea3SSunil Goutham }; 4364863dea3SSunil Goutham 4374863dea3SSunil Goutham /* Physical interface link status */ 4384863dea3SSunil Goutham struct bgx_link_status { 4394863dea3SSunil Goutham u8 msg; 4404863dea3SSunil Goutham u8 link_up; 4414863dea3SSunil Goutham u8 duplex; 4424863dea3SSunil Goutham u32 speed; 4434863dea3SSunil Goutham }; 4444863dea3SSunil Goutham 44592dc8769SSunil Goutham /* Get Extra Qset IDs */ 44692dc8769SSunil Goutham struct sqs_alloc { 44792dc8769SSunil Goutham u8 msg; 44892dc8769SSunil Goutham u8 vf_id; 44992dc8769SSunil Goutham u8 qs_count; 45092dc8769SSunil Goutham }; 45192dc8769SSunil Goutham 45292dc8769SSunil Goutham struct nicvf_ptr { 45392dc8769SSunil Goutham u8 msg; 45492dc8769SSunil Goutham u8 vf_id; 45592dc8769SSunil Goutham bool sqs_mode; 45692dc8769SSunil Goutham u8 sqs_id; 45792dc8769SSunil Goutham u64 nicvf; 45892dc8769SSunil Goutham }; 45992dc8769SSunil Goutham 460d77a2384SSunil Goutham /* Set interface in loopback mode */ 461d77a2384SSunil Goutham struct set_loopback { 462d77a2384SSunil Goutham u8 msg; 463d77a2384SSunil Goutham u8 vf_id; 464d77a2384SSunil Goutham bool enable; 465d77a2384SSunil Goutham }; 466d77a2384SSunil Goutham 4673458c40dSJerin Jacob /* Reset statistics counters */ 4683458c40dSJerin Jacob struct reset_stat_cfg { 4693458c40dSJerin Jacob u8 msg; 4703458c40dSJerin Jacob /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */ 4713458c40dSJerin Jacob u16 rx_stat_mask; 4723458c40dSJerin Jacob /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */ 4733458c40dSJerin Jacob u8 tx_stat_mask; 4743458c40dSJerin Jacob /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1) 4753458c40dSJerin Jacob * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1) 4763458c40dSJerin Jacob * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1) 4773458c40dSJerin Jacob * .. 4783458c40dSJerin Jacob * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1) 4793458c40dSJerin Jacob * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1) 4803458c40dSJerin Jacob */ 4813458c40dSJerin Jacob u16 rq_stat_mask; 4823458c40dSJerin Jacob /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1) 4833458c40dSJerin Jacob * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1) 4843458c40dSJerin Jacob * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1) 4853458c40dSJerin Jacob * .. 4863458c40dSJerin Jacob * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1) 4873458c40dSJerin Jacob * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1) 4883458c40dSJerin Jacob */ 4893458c40dSJerin Jacob u16 sq_stat_mask; 4903458c40dSJerin Jacob }; 4913458c40dSJerin Jacob 4924863dea3SSunil Goutham /* 128 bit shared memory between PF and each VF */ 4934863dea3SSunil Goutham union nic_mbx { 4944863dea3SSunil Goutham struct { u8 msg; } msg; 4954863dea3SSunil Goutham struct nic_cfg_msg nic_cfg; 4964863dea3SSunil Goutham struct qs_cfg_msg qs; 4974863dea3SSunil Goutham struct rq_cfg_msg rq; 4984863dea3SSunil Goutham struct sq_cfg_msg sq; 4994863dea3SSunil Goutham struct set_mac_msg mac; 5004863dea3SSunil Goutham struct set_frs_msg frs; 5014863dea3SSunil Goutham struct cpi_cfg_msg cpi_cfg; 5024863dea3SSunil Goutham struct rss_sz_msg rss_size; 5034863dea3SSunil Goutham struct rss_cfg_msg rss_cfg; 5044863dea3SSunil Goutham struct bgx_stats_msg bgx_stats; 5054863dea3SSunil Goutham struct bgx_link_status link_status; 50692dc8769SSunil Goutham struct sqs_alloc sqs_alloc; 50792dc8769SSunil Goutham struct nicvf_ptr nicvf; 508d77a2384SSunil Goutham struct set_loopback lbk; 5093458c40dSJerin Jacob struct reset_stat_cfg reset_stat; 5104863dea3SSunil Goutham }; 5114863dea3SSunil Goutham 512d768b678SRobert Richter #define NIC_NODE_ID_MASK 0x03 513d768b678SRobert Richter #define NIC_NODE_ID_SHIFT 44 514d768b678SRobert Richter 515d768b678SRobert Richter static inline int nic_get_node_id(struct pci_dev *pdev) 516d768b678SRobert Richter { 517d768b678SRobert Richter u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); 518d768b678SRobert Richter return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 519d768b678SRobert Richter } 520d768b678SRobert Richter 52140fb5f8aSSunil Goutham static inline bool pass1_silicon(struct pci_dev *pdev) 52240fb5f8aSSunil Goutham { 52302a72bd8SSunil Goutham return (pdev->revision < 8) && 52402a72bd8SSunil Goutham (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); 52502a72bd8SSunil Goutham } 52602a72bd8SSunil Goutham 52702a72bd8SSunil Goutham static inline bool pass2_silicon(struct pci_dev *pdev) 52802a72bd8SSunil Goutham { 52902a72bd8SSunil Goutham return (pdev->revision >= 8) && 53002a72bd8SSunil Goutham (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); 53140fb5f8aSSunil Goutham } 53240fb5f8aSSunil Goutham 5334863dea3SSunil Goutham int nicvf_set_real_num_queues(struct net_device *netdev, 5344863dea3SSunil Goutham int tx_queues, int rx_queues); 5354863dea3SSunil Goutham int nicvf_open(struct net_device *netdev); 5364863dea3SSunil Goutham int nicvf_stop(struct net_device *netdev); 5374863dea3SSunil Goutham int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 5384863dea3SSunil Goutham void nicvf_config_rss(struct nicvf *nic); 5394863dea3SSunil Goutham void nicvf_set_rss_key(struct nicvf *nic); 5404863dea3SSunil Goutham void nicvf_set_ethtool_ops(struct net_device *netdev); 5414863dea3SSunil Goutham void nicvf_update_stats(struct nicvf *nic); 5424863dea3SSunil Goutham void nicvf_update_lmac_stats(struct nicvf *nic); 5434863dea3SSunil Goutham 5444863dea3SSunil Goutham #endif /* NIC_H */ 545