1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2009-2012 Cavium, Inc 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/etherdevice.h> 12 #include <linux/capability.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/interrupt.h> 15 #include <linux/netdevice.h> 16 #include <linux/spinlock.h> 17 #include <linux/if_vlan.h> 18 #include <linux/of_mdio.h> 19 #include <linux/module.h> 20 #include <linux/of_net.h> 21 #include <linux/init.h> 22 #include <linux/slab.h> 23 #include <linux/phy.h> 24 #include <linux/io.h> 25 26 #include <asm/octeon/octeon.h> 27 #include <asm/octeon/cvmx-mixx-defs.h> 28 #include <asm/octeon/cvmx-agl-defs.h> 29 30 #define DRV_NAME "octeon_mgmt" 31 #define DRV_VERSION "2.0" 32 #define DRV_DESCRIPTION \ 33 "Cavium Networks Octeon MII (management) port Network Driver" 34 35 #define OCTEON_MGMT_NAPI_WEIGHT 16 36 37 /* Ring sizes that are powers of two allow for more efficient modulo 38 * opertions. 39 */ 40 #define OCTEON_MGMT_RX_RING_SIZE 512 41 #define OCTEON_MGMT_TX_RING_SIZE 128 42 43 /* Allow 8 bytes for vlan and FCS. */ 44 #define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 45 46 union mgmt_port_ring_entry { 47 u64 d64; 48 struct { 49 #define RING_ENTRY_CODE_DONE 0xf 50 #define RING_ENTRY_CODE_MORE 0x10 51 #ifdef __BIG_ENDIAN_BITFIELD 52 u64 reserved_62_63:2; 53 /* Length of the buffer/packet in bytes */ 54 u64 len:14; 55 /* For TX, signals that the packet should be timestamped */ 56 u64 tstamp:1; 57 /* The RX error code */ 58 u64 code:7; 59 /* Physical address of the buffer */ 60 u64 addr:40; 61 #else 62 u64 addr:40; 63 u64 code:7; 64 u64 tstamp:1; 65 u64 len:14; 66 u64 reserved_62_63:2; 67 #endif 68 } s; 69 }; 70 71 #define MIX_ORING1 0x0 72 #define MIX_ORING2 0x8 73 #define MIX_IRING1 0x10 74 #define MIX_IRING2 0x18 75 #define MIX_CTL 0x20 76 #define MIX_IRHWM 0x28 77 #define MIX_IRCNT 0x30 78 #define MIX_ORHWM 0x38 79 #define MIX_ORCNT 0x40 80 #define MIX_ISR 0x48 81 #define MIX_INTENA 0x50 82 #define MIX_REMCNT 0x58 83 #define MIX_BIST 0x78 84 85 #define AGL_GMX_PRT_CFG 0x10 86 #define AGL_GMX_RX_FRM_CTL 0x18 87 #define AGL_GMX_RX_FRM_MAX 0x30 88 #define AGL_GMX_RX_JABBER 0x38 89 #define AGL_GMX_RX_STATS_CTL 0x50 90 91 #define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 92 #define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 93 #define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 94 95 #define AGL_GMX_RX_ADR_CTL 0x100 96 #define AGL_GMX_RX_ADR_CAM_EN 0x108 97 #define AGL_GMX_RX_ADR_CAM0 0x180 98 #define AGL_GMX_RX_ADR_CAM1 0x188 99 #define AGL_GMX_RX_ADR_CAM2 0x190 100 #define AGL_GMX_RX_ADR_CAM3 0x198 101 #define AGL_GMX_RX_ADR_CAM4 0x1a0 102 #define AGL_GMX_RX_ADR_CAM5 0x1a8 103 104 #define AGL_GMX_TX_CLK 0x208 105 #define AGL_GMX_TX_STATS_CTL 0x268 106 #define AGL_GMX_TX_CTL 0x270 107 #define AGL_GMX_TX_STAT0 0x280 108 #define AGL_GMX_TX_STAT1 0x288 109 #define AGL_GMX_TX_STAT2 0x290 110 #define AGL_GMX_TX_STAT3 0x298 111 #define AGL_GMX_TX_STAT4 0x2a0 112 #define AGL_GMX_TX_STAT5 0x2a8 113 #define AGL_GMX_TX_STAT6 0x2b0 114 #define AGL_GMX_TX_STAT7 0x2b8 115 #define AGL_GMX_TX_STAT8 0x2c0 116 #define AGL_GMX_TX_STAT9 0x2c8 117 118 struct octeon_mgmt { 119 struct net_device *netdev; 120 u64 mix; 121 u64 agl; 122 u64 agl_prt_ctl; 123 int port; 124 int irq; 125 bool has_rx_tstamp; 126 u64 *tx_ring; 127 dma_addr_t tx_ring_handle; 128 unsigned int tx_next; 129 unsigned int tx_next_clean; 130 unsigned int tx_current_fill; 131 /* The tx_list lock also protects the ring related variables */ 132 struct sk_buff_head tx_list; 133 134 /* RX variables only touched in napi_poll. No locking necessary. */ 135 u64 *rx_ring; 136 dma_addr_t rx_ring_handle; 137 unsigned int rx_next; 138 unsigned int rx_next_fill; 139 unsigned int rx_current_fill; 140 struct sk_buff_head rx_list; 141 142 spinlock_t lock; 143 unsigned int last_duplex; 144 unsigned int last_link; 145 unsigned int last_speed; 146 struct device *dev; 147 struct napi_struct napi; 148 struct tasklet_struct tx_clean_tasklet; 149 struct device_node *phy_np; 150 resource_size_t mix_phys; 151 resource_size_t mix_size; 152 resource_size_t agl_phys; 153 resource_size_t agl_size; 154 resource_size_t agl_prt_ctl_phys; 155 resource_size_t agl_prt_ctl_size; 156 }; 157 158 static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) 159 { 160 union cvmx_mixx_intena mix_intena; 161 unsigned long flags; 162 163 spin_lock_irqsave(&p->lock, flags); 164 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); 165 mix_intena.s.ithena = enable ? 1 : 0; 166 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); 167 spin_unlock_irqrestore(&p->lock, flags); 168 } 169 170 static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) 171 { 172 union cvmx_mixx_intena mix_intena; 173 unsigned long flags; 174 175 spin_lock_irqsave(&p->lock, flags); 176 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); 177 mix_intena.s.othena = enable ? 1 : 0; 178 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); 179 spin_unlock_irqrestore(&p->lock, flags); 180 } 181 182 static void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p) 183 { 184 octeon_mgmt_set_rx_irq(p, 1); 185 } 186 187 static void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p) 188 { 189 octeon_mgmt_set_rx_irq(p, 0); 190 } 191 192 static void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p) 193 { 194 octeon_mgmt_set_tx_irq(p, 1); 195 } 196 197 static void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p) 198 { 199 octeon_mgmt_set_tx_irq(p, 0); 200 } 201 202 static unsigned int ring_max_fill(unsigned int ring_size) 203 { 204 return ring_size - 8; 205 } 206 207 static unsigned int ring_size_to_bytes(unsigned int ring_size) 208 { 209 return ring_size * sizeof(union mgmt_port_ring_entry); 210 } 211 212 static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) 213 { 214 struct octeon_mgmt *p = netdev_priv(netdev); 215 216 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { 217 unsigned int size; 218 union mgmt_port_ring_entry re; 219 struct sk_buff *skb; 220 221 /* CN56XX pass 1 needs 8 bytes of padding. */ 222 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN; 223 224 skb = netdev_alloc_skb(netdev, size); 225 if (!skb) 226 break; 227 skb_reserve(skb, NET_IP_ALIGN); 228 __skb_queue_tail(&p->rx_list, skb); 229 230 re.d64 = 0; 231 re.s.len = size; 232 re.s.addr = dma_map_single(p->dev, skb->data, 233 size, 234 DMA_FROM_DEVICE); 235 236 /* Put it in the ring. */ 237 p->rx_ring[p->rx_next_fill] = re.d64; 238 dma_sync_single_for_device(p->dev, p->rx_ring_handle, 239 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 240 DMA_BIDIRECTIONAL); 241 p->rx_next_fill = 242 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; 243 p->rx_current_fill++; 244 /* Ring the bell. */ 245 cvmx_write_csr(p->mix + MIX_IRING2, 1); 246 } 247 } 248 249 static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) 250 { 251 union cvmx_mixx_orcnt mix_orcnt; 252 union mgmt_port_ring_entry re; 253 struct sk_buff *skb; 254 int cleaned = 0; 255 unsigned long flags; 256 257 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); 258 while (mix_orcnt.s.orcnt) { 259 spin_lock_irqsave(&p->tx_list.lock, flags); 260 261 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); 262 263 if (mix_orcnt.s.orcnt == 0) { 264 spin_unlock_irqrestore(&p->tx_list.lock, flags); 265 break; 266 } 267 268 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle, 269 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 270 DMA_BIDIRECTIONAL); 271 272 re.d64 = p->tx_ring[p->tx_next_clean]; 273 p->tx_next_clean = 274 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE; 275 skb = __skb_dequeue(&p->tx_list); 276 277 mix_orcnt.u64 = 0; 278 mix_orcnt.s.orcnt = 1; 279 280 /* Acknowledge to hardware that we have the buffer. */ 281 cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); 282 p->tx_current_fill--; 283 284 spin_unlock_irqrestore(&p->tx_list.lock, flags); 285 286 dma_unmap_single(p->dev, re.s.addr, re.s.len, 287 DMA_TO_DEVICE); 288 289 /* Read the hardware TX timestamp if one was recorded */ 290 if (unlikely(re.s.tstamp)) { 291 struct skb_shared_hwtstamps ts; 292 u64 ns; 293 294 memset(&ts, 0, sizeof(ts)); 295 /* Read the timestamp */ 296 ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port)); 297 /* Remove the timestamp from the FIFO */ 298 cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0); 299 /* Tell the kernel about the timestamp */ 300 ts.hwtstamp = ns_to_ktime(ns); 301 skb_tstamp_tx(skb, &ts); 302 } 303 304 dev_kfree_skb_any(skb); 305 cleaned++; 306 307 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); 308 } 309 310 if (cleaned && netif_queue_stopped(p->netdev)) 311 netif_wake_queue(p->netdev); 312 } 313 314 static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) 315 { 316 struct octeon_mgmt *p = (struct octeon_mgmt *)arg; 317 octeon_mgmt_clean_tx_buffers(p); 318 octeon_mgmt_enable_tx_irq(p); 319 } 320 321 static void octeon_mgmt_update_rx_stats(struct net_device *netdev) 322 { 323 struct octeon_mgmt *p = netdev_priv(netdev); 324 unsigned long flags; 325 u64 drop, bad; 326 327 /* These reads also clear the count registers. */ 328 drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); 329 bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); 330 331 if (drop || bad) { 332 /* Do an atomic update. */ 333 spin_lock_irqsave(&p->lock, flags); 334 netdev->stats.rx_errors += bad; 335 netdev->stats.rx_dropped += drop; 336 spin_unlock_irqrestore(&p->lock, flags); 337 } 338 } 339 340 static void octeon_mgmt_update_tx_stats(struct net_device *netdev) 341 { 342 struct octeon_mgmt *p = netdev_priv(netdev); 343 unsigned long flags; 344 345 union cvmx_agl_gmx_txx_stat0 s0; 346 union cvmx_agl_gmx_txx_stat1 s1; 347 348 /* These reads also clear the count registers. */ 349 s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); 350 s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); 351 352 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { 353 /* Do an atomic update. */ 354 spin_lock_irqsave(&p->lock, flags); 355 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol; 356 netdev->stats.collisions += s1.s.scol + s1.s.mcol; 357 spin_unlock_irqrestore(&p->lock, flags); 358 } 359 } 360 361 /* 362 * Dequeue a receive skb and its corresponding ring entry. The ring 363 * entry is returned, *pskb is updated to point to the skb. 364 */ 365 static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, 366 struct sk_buff **pskb) 367 { 368 union mgmt_port_ring_entry re; 369 370 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle, 371 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 372 DMA_BIDIRECTIONAL); 373 374 re.d64 = p->rx_ring[p->rx_next]; 375 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE; 376 p->rx_current_fill--; 377 *pskb = __skb_dequeue(&p->rx_list); 378 379 dma_unmap_single(p->dev, re.s.addr, 380 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM, 381 DMA_FROM_DEVICE); 382 383 return re.d64; 384 } 385 386 387 static int octeon_mgmt_receive_one(struct octeon_mgmt *p) 388 { 389 struct net_device *netdev = p->netdev; 390 union cvmx_mixx_ircnt mix_ircnt; 391 union mgmt_port_ring_entry re; 392 struct sk_buff *skb; 393 struct sk_buff *skb2; 394 struct sk_buff *skb_new; 395 union mgmt_port_ring_entry re2; 396 int rc = 1; 397 398 399 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb); 400 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) { 401 /* A good packet, send it up. */ 402 skb_put(skb, re.s.len); 403 good: 404 /* Process the RX timestamp if it was recorded */ 405 if (p->has_rx_tstamp) { 406 /* The first 8 bytes are the timestamp */ 407 u64 ns = *(u64 *)skb->data; 408 struct skb_shared_hwtstamps *ts; 409 ts = skb_hwtstamps(skb); 410 ts->hwtstamp = ns_to_ktime(ns); 411 __skb_pull(skb, 8); 412 } 413 skb->protocol = eth_type_trans(skb, netdev); 414 netdev->stats.rx_packets++; 415 netdev->stats.rx_bytes += skb->len; 416 netif_receive_skb(skb); 417 rc = 0; 418 } else if (re.s.code == RING_ENTRY_CODE_MORE) { 419 /* Packet split across skbs. This can happen if we 420 * increase the MTU. Buffers that are already in the 421 * rx ring can then end up being too small. As the rx 422 * ring is refilled, buffers sized for the new MTU 423 * will be used and we should go back to the normal 424 * non-split case. 425 */ 426 skb_put(skb, re.s.len); 427 do { 428 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2); 429 if (re2.s.code != RING_ENTRY_CODE_MORE 430 && re2.s.code != RING_ENTRY_CODE_DONE) 431 goto split_error; 432 skb_put(skb2, re2.s.len); 433 skb_new = skb_copy_expand(skb, 0, skb2->len, 434 GFP_ATOMIC); 435 if (!skb_new) 436 goto split_error; 437 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new), 438 skb2->len)) 439 goto split_error; 440 skb_put(skb_new, skb2->len); 441 dev_kfree_skb_any(skb); 442 dev_kfree_skb_any(skb2); 443 skb = skb_new; 444 } while (re2.s.code == RING_ENTRY_CODE_MORE); 445 goto good; 446 } else { 447 /* Some other error, discard it. */ 448 dev_kfree_skb_any(skb); 449 /* Error statistics are accumulated in 450 * octeon_mgmt_update_rx_stats. 451 */ 452 } 453 goto done; 454 split_error: 455 /* Discard the whole mess. */ 456 dev_kfree_skb_any(skb); 457 dev_kfree_skb_any(skb2); 458 while (re2.s.code == RING_ENTRY_CODE_MORE) { 459 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2); 460 dev_kfree_skb_any(skb2); 461 } 462 netdev->stats.rx_errors++; 463 464 done: 465 /* Tell the hardware we processed a packet. */ 466 mix_ircnt.u64 = 0; 467 mix_ircnt.s.ircnt = 1; 468 cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); 469 return rc; 470 } 471 472 static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) 473 { 474 unsigned int work_done = 0; 475 union cvmx_mixx_ircnt mix_ircnt; 476 int rc; 477 478 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); 479 while (work_done < budget && mix_ircnt.s.ircnt) { 480 481 rc = octeon_mgmt_receive_one(p); 482 if (!rc) 483 work_done++; 484 485 /* Check for more packets. */ 486 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); 487 } 488 489 octeon_mgmt_rx_fill_ring(p->netdev); 490 491 return work_done; 492 } 493 494 static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget) 495 { 496 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi); 497 struct net_device *netdev = p->netdev; 498 unsigned int work_done = 0; 499 500 work_done = octeon_mgmt_receive_packets(p, budget); 501 502 if (work_done < budget) { 503 /* We stopped because no more packets were available. */ 504 napi_complete_done(napi, work_done); 505 octeon_mgmt_enable_rx_irq(p); 506 } 507 octeon_mgmt_update_rx_stats(netdev); 508 509 return work_done; 510 } 511 512 /* Reset the hardware to clean state. */ 513 static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) 514 { 515 union cvmx_mixx_ctl mix_ctl; 516 union cvmx_mixx_bist mix_bist; 517 union cvmx_agl_gmx_bist agl_gmx_bist; 518 519 mix_ctl.u64 = 0; 520 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 521 do { 522 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); 523 } while (mix_ctl.s.busy); 524 mix_ctl.s.reset = 1; 525 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 526 cvmx_read_csr(p->mix + MIX_CTL); 527 octeon_io_clk_delay(64); 528 529 mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); 530 if (mix_bist.u64) 531 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", 532 (unsigned long long)mix_bist.u64); 533 534 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST); 535 if (agl_gmx_bist.u64) 536 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n", 537 (unsigned long long)agl_gmx_bist.u64); 538 } 539 540 struct octeon_mgmt_cam_state { 541 u64 cam[6]; 542 u64 cam_mask; 543 int cam_index; 544 }; 545 546 static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, 547 unsigned char *addr) 548 { 549 int i; 550 551 for (i = 0; i < 6; i++) 552 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index)); 553 cs->cam_mask |= (1ULL << cs->cam_index); 554 cs->cam_index++; 555 } 556 557 static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) 558 { 559 struct octeon_mgmt *p = netdev_priv(netdev); 560 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; 561 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; 562 unsigned long flags; 563 unsigned int prev_packet_enable; 564 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */ 565 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */ 566 struct octeon_mgmt_cam_state cam_state; 567 struct netdev_hw_addr *ha; 568 int available_cam_entries; 569 570 memset(&cam_state, 0, sizeof(cam_state)); 571 572 if ((netdev->flags & IFF_PROMISC) || netdev->uc.count > 7) { 573 cam_mode = 0; 574 available_cam_entries = 8; 575 } else { 576 /* One CAM entry for the primary address, leaves seven 577 * for the secondary addresses. 578 */ 579 available_cam_entries = 7 - netdev->uc.count; 580 } 581 582 if (netdev->flags & IFF_MULTICAST) { 583 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI) || 584 netdev_mc_count(netdev) > available_cam_entries) 585 multicast_mode = 2; /* 2 - Accept all multicast. */ 586 else 587 multicast_mode = 0; /* 0 - Use CAM. */ 588 } 589 590 if (cam_mode == 1) { 591 /* Add primary address. */ 592 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr); 593 netdev_for_each_uc_addr(ha, netdev) 594 octeon_mgmt_cam_state_add(&cam_state, ha->addr); 595 } 596 if (multicast_mode == 0) { 597 netdev_for_each_mc_addr(ha, netdev) 598 octeon_mgmt_cam_state_add(&cam_state, ha->addr); 599 } 600 601 spin_lock_irqsave(&p->lock, flags); 602 603 /* Disable packet I/O. */ 604 agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 605 prev_packet_enable = agl_gmx_prtx.s.en; 606 agl_gmx_prtx.s.en = 0; 607 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); 608 609 adr_ctl.u64 = 0; 610 adr_ctl.s.cam_mode = cam_mode; 611 adr_ctl.s.mcst = multicast_mode; 612 adr_ctl.s.bcst = 1; /* Allow broadcast */ 613 614 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); 615 616 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); 617 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); 618 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); 619 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); 620 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); 621 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); 622 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); 623 624 /* Restore packet I/O. */ 625 agl_gmx_prtx.s.en = prev_packet_enable; 626 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); 627 628 spin_unlock_irqrestore(&p->lock, flags); 629 } 630 631 static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) 632 { 633 int r = eth_mac_addr(netdev, addr); 634 635 if (r) 636 return r; 637 638 octeon_mgmt_set_rx_filtering(netdev); 639 640 return 0; 641 } 642 643 static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) 644 { 645 struct octeon_mgmt *p = netdev_priv(netdev); 646 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; 647 648 netdev->mtu = new_mtu; 649 650 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs); 651 cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, 652 (size_without_fcs + 7) & 0xfff8); 653 654 return 0; 655 } 656 657 static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) 658 { 659 struct net_device *netdev = dev_id; 660 struct octeon_mgmt *p = netdev_priv(netdev); 661 union cvmx_mixx_isr mixx_isr; 662 663 mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); 664 665 /* Clear any pending interrupts */ 666 cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); 667 cvmx_read_csr(p->mix + MIX_ISR); 668 669 if (mixx_isr.s.irthresh) { 670 octeon_mgmt_disable_rx_irq(p); 671 napi_schedule(&p->napi); 672 } 673 if (mixx_isr.s.orthresh) { 674 octeon_mgmt_disable_tx_irq(p); 675 tasklet_schedule(&p->tx_clean_tasklet); 676 } 677 678 return IRQ_HANDLED; 679 } 680 681 static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev, 682 struct ifreq *rq, int cmd) 683 { 684 struct octeon_mgmt *p = netdev_priv(netdev); 685 struct hwtstamp_config config; 686 union cvmx_mio_ptp_clock_cfg ptp; 687 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; 688 bool have_hw_timestamps = false; 689 690 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 691 return -EFAULT; 692 693 if (config.flags) /* reserved for future extensions */ 694 return -EINVAL; 695 696 /* Check the status of hardware for tiemstamps */ 697 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 698 /* Get the current state of the PTP clock */ 699 ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG); 700 if (!ptp.s.ext_clk_en) { 701 /* The clock has not been configured to use an 702 * external source. Program it to use the main clock 703 * reference. 704 */ 705 u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate(); 706 if (!ptp.s.ptp_en) 707 cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp); 708 pr_info("PTP Clock: Using sclk reference at %lld Hz\n", 709 (NSEC_PER_SEC << 32) / clock_comp); 710 } else { 711 /* The clock is already programmed to use a GPIO */ 712 u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP); 713 pr_info("PTP Clock: Using GPIO %d at %lld Hz\n", 714 ptp.s.ext_clk_in, 715 (NSEC_PER_SEC << 32) / clock_comp); 716 } 717 718 /* Enable the clock if it wasn't done already */ 719 if (!ptp.s.ptp_en) { 720 ptp.s.ptp_en = 1; 721 cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64); 722 } 723 have_hw_timestamps = true; 724 } 725 726 if (!have_hw_timestamps) 727 return -EINVAL; 728 729 switch (config.tx_type) { 730 case HWTSTAMP_TX_OFF: 731 case HWTSTAMP_TX_ON: 732 break; 733 default: 734 return -ERANGE; 735 } 736 737 switch (config.rx_filter) { 738 case HWTSTAMP_FILTER_NONE: 739 p->has_rx_tstamp = false; 740 rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); 741 rxx_frm_ctl.s.ptp_mode = 0; 742 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); 743 break; 744 case HWTSTAMP_FILTER_ALL: 745 case HWTSTAMP_FILTER_SOME: 746 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 747 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 748 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 749 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 750 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 751 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 752 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 753 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 754 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 755 case HWTSTAMP_FILTER_PTP_V2_EVENT: 756 case HWTSTAMP_FILTER_PTP_V2_SYNC: 757 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 758 p->has_rx_tstamp = have_hw_timestamps; 759 config.rx_filter = HWTSTAMP_FILTER_ALL; 760 if (p->has_rx_tstamp) { 761 rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); 762 rxx_frm_ctl.s.ptp_mode = 1; 763 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); 764 } 765 break; 766 default: 767 return -ERANGE; 768 } 769 770 if (copy_to_user(rq->ifr_data, &config, sizeof(config))) 771 return -EFAULT; 772 773 return 0; 774 } 775 776 static int octeon_mgmt_ioctl(struct net_device *netdev, 777 struct ifreq *rq, int cmd) 778 { 779 switch (cmd) { 780 case SIOCSHWTSTAMP: 781 return octeon_mgmt_ioctl_hwtstamp(netdev, rq, cmd); 782 default: 783 if (netdev->phydev) 784 return phy_mii_ioctl(netdev->phydev, rq, cmd); 785 return -EINVAL; 786 } 787 } 788 789 static void octeon_mgmt_disable_link(struct octeon_mgmt *p) 790 { 791 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 792 793 /* Disable GMX before we make any changes. */ 794 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 795 prtx_cfg.s.en = 0; 796 prtx_cfg.s.tx_en = 0; 797 prtx_cfg.s.rx_en = 0; 798 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); 799 800 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 801 int i; 802 for (i = 0; i < 10; i++) { 803 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 804 if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1) 805 break; 806 mdelay(1); 807 i++; 808 } 809 } 810 } 811 812 static void octeon_mgmt_enable_link(struct octeon_mgmt *p) 813 { 814 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 815 816 /* Restore the GMX enable state only if link is set */ 817 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 818 prtx_cfg.s.tx_en = 1; 819 prtx_cfg.s.rx_en = 1; 820 prtx_cfg.s.en = 1; 821 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); 822 } 823 824 static void octeon_mgmt_update_link(struct octeon_mgmt *p) 825 { 826 struct net_device *ndev = p->netdev; 827 struct phy_device *phydev = ndev->phydev; 828 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 829 830 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 831 832 if (!phydev->link) 833 prtx_cfg.s.duplex = 1; 834 else 835 prtx_cfg.s.duplex = phydev->duplex; 836 837 switch (phydev->speed) { 838 case 10: 839 prtx_cfg.s.speed = 0; 840 prtx_cfg.s.slottime = 0; 841 842 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 843 prtx_cfg.s.burst = 1; 844 prtx_cfg.s.speed_msb = 1; 845 } 846 break; 847 case 100: 848 prtx_cfg.s.speed = 0; 849 prtx_cfg.s.slottime = 0; 850 851 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 852 prtx_cfg.s.burst = 1; 853 prtx_cfg.s.speed_msb = 0; 854 } 855 break; 856 case 1000: 857 /* 1000 MBits is only supported on 6XXX chips */ 858 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 859 prtx_cfg.s.speed = 1; 860 prtx_cfg.s.speed_msb = 0; 861 /* Only matters for half-duplex */ 862 prtx_cfg.s.slottime = 1; 863 prtx_cfg.s.burst = phydev->duplex; 864 } 865 break; 866 case 0: /* No link */ 867 default: 868 break; 869 } 870 871 /* Write the new GMX setting with the port still disabled. */ 872 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); 873 874 /* Read GMX CFG again to make sure the config is completed. */ 875 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 876 877 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 878 union cvmx_agl_gmx_txx_clk agl_clk; 879 union cvmx_agl_prtx_ctl prtx_ctl; 880 881 prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 882 agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK); 883 /* MII (both speeds) and RGMII 1000 speed. */ 884 agl_clk.s.clk_cnt = 1; 885 if (prtx_ctl.s.mode == 0) { /* RGMII mode */ 886 if (phydev->speed == 10) 887 agl_clk.s.clk_cnt = 50; 888 else if (phydev->speed == 100) 889 agl_clk.s.clk_cnt = 5; 890 } 891 cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64); 892 } 893 } 894 895 static void octeon_mgmt_adjust_link(struct net_device *netdev) 896 { 897 struct octeon_mgmt *p = netdev_priv(netdev); 898 struct phy_device *phydev = netdev->phydev; 899 unsigned long flags; 900 int link_changed = 0; 901 902 if (!phydev) 903 return; 904 905 spin_lock_irqsave(&p->lock, flags); 906 907 908 if (!phydev->link && p->last_link) 909 link_changed = -1; 910 911 if (phydev->link && 912 (p->last_duplex != phydev->duplex || 913 p->last_link != phydev->link || 914 p->last_speed != phydev->speed)) { 915 octeon_mgmt_disable_link(p); 916 link_changed = 1; 917 octeon_mgmt_update_link(p); 918 octeon_mgmt_enable_link(p); 919 } 920 921 p->last_link = phydev->link; 922 p->last_speed = phydev->speed; 923 p->last_duplex = phydev->duplex; 924 925 spin_unlock_irqrestore(&p->lock, flags); 926 927 if (link_changed != 0) { 928 if (link_changed > 0) { 929 pr_info("%s: Link is up - %d/%s\n", netdev->name, 930 phydev->speed, 931 phydev->duplex == DUPLEX_FULL ? 932 "Full" : "Half"); 933 } else { 934 pr_info("%s: Link is down\n", netdev->name); 935 } 936 } 937 } 938 939 static int octeon_mgmt_init_phy(struct net_device *netdev) 940 { 941 struct octeon_mgmt *p = netdev_priv(netdev); 942 struct phy_device *phydev = NULL; 943 944 if (octeon_is_simulation() || p->phy_np == NULL) { 945 /* No PHYs in the simulator. */ 946 netif_carrier_on(netdev); 947 return 0; 948 } 949 950 phydev = of_phy_connect(netdev, p->phy_np, 951 octeon_mgmt_adjust_link, 0, 952 PHY_INTERFACE_MODE_MII); 953 954 if (!phydev) 955 return -ENODEV; 956 957 return 0; 958 } 959 960 static int octeon_mgmt_open(struct net_device *netdev) 961 { 962 struct octeon_mgmt *p = netdev_priv(netdev); 963 union cvmx_mixx_ctl mix_ctl; 964 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode; 965 union cvmx_mixx_oring1 oring1; 966 union cvmx_mixx_iring1 iring1; 967 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; 968 union cvmx_mixx_irhwm mix_irhwm; 969 union cvmx_mixx_orhwm mix_orhwm; 970 union cvmx_mixx_intena mix_intena; 971 struct sockaddr sa; 972 973 /* Allocate ring buffers. */ 974 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 975 GFP_KERNEL); 976 if (!p->tx_ring) 977 return -ENOMEM; 978 p->tx_ring_handle = 979 dma_map_single(p->dev, p->tx_ring, 980 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 981 DMA_BIDIRECTIONAL); 982 p->tx_next = 0; 983 p->tx_next_clean = 0; 984 p->tx_current_fill = 0; 985 986 987 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 988 GFP_KERNEL); 989 if (!p->rx_ring) 990 goto err_nomem; 991 p->rx_ring_handle = 992 dma_map_single(p->dev, p->rx_ring, 993 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 994 DMA_BIDIRECTIONAL); 995 996 p->rx_next = 0; 997 p->rx_next_fill = 0; 998 p->rx_current_fill = 0; 999 1000 octeon_mgmt_reset_hw(p); 1001 1002 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); 1003 1004 /* Bring it out of reset if needed. */ 1005 if (mix_ctl.s.reset) { 1006 mix_ctl.s.reset = 0; 1007 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 1008 do { 1009 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); 1010 } while (mix_ctl.s.reset); 1011 } 1012 1013 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { 1014 agl_gmx_inf_mode.u64 = 0; 1015 agl_gmx_inf_mode.s.en = 1; 1016 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); 1017 } 1018 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 1019 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 1020 /* Force compensation values, as they are not 1021 * determined properly by HW 1022 */ 1023 union cvmx_agl_gmx_drv_ctl drv_ctl; 1024 1025 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); 1026 if (p->port) { 1027 drv_ctl.s.byp_en1 = 1; 1028 drv_ctl.s.nctl1 = 6; 1029 drv_ctl.s.pctl1 = 6; 1030 } else { 1031 drv_ctl.s.byp_en = 1; 1032 drv_ctl.s.nctl = 6; 1033 drv_ctl.s.pctl = 6; 1034 } 1035 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); 1036 } 1037 1038 oring1.u64 = 0; 1039 oring1.s.obase = p->tx_ring_handle >> 3; 1040 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; 1041 cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); 1042 1043 iring1.u64 = 0; 1044 iring1.s.ibase = p->rx_ring_handle >> 3; 1045 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; 1046 cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); 1047 1048 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); 1049 octeon_mgmt_set_mac_address(netdev, &sa); 1050 1051 octeon_mgmt_change_mtu(netdev, netdev->mtu); 1052 1053 /* Enable the port HW. Packets are not allowed until 1054 * cvmx_mgmt_port_enable() is called. 1055 */ 1056 mix_ctl.u64 = 0; 1057 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */ 1058 mix_ctl.s.en = 1; /* Enable the port */ 1059 mix_ctl.s.nbtarb = 0; /* Arbitration mode */ 1060 /* MII CB-request FIFO programmable high watermark */ 1061 mix_ctl.s.mrq_hwm = 1; 1062 #ifdef __LITTLE_ENDIAN 1063 mix_ctl.s.lendian = 1; 1064 #endif 1065 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 1066 1067 /* Read the PHY to find the mode of the interface. */ 1068 if (octeon_mgmt_init_phy(netdev)) { 1069 dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port); 1070 goto err_noirq; 1071 } 1072 1073 /* Set the mode of the interface, RGMII/MII. */ 1074 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && netdev->phydev) { 1075 union cvmx_agl_prtx_ctl agl_prtx_ctl; 1076 int rgmii_mode = (netdev->phydev->supported & 1077 (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) != 0; 1078 1079 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1080 agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1; 1081 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1082 1083 /* MII clocks counts are based on the 125Mhz 1084 * reference, which has an 8nS period. So our delays 1085 * need to be multiplied by this factor. 1086 */ 1087 #define NS_PER_PHY_CLK 8 1088 1089 /* Take the DLL and clock tree out of reset */ 1090 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1091 agl_prtx_ctl.s.clkrst = 0; 1092 if (rgmii_mode) { 1093 agl_prtx_ctl.s.dllrst = 0; 1094 agl_prtx_ctl.s.clktx_byp = 0; 1095 } 1096 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1097 cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */ 1098 1099 /* Wait for the DLL to lock. External 125 MHz 1100 * reference clock must be stable at this point. 1101 */ 1102 ndelay(256 * NS_PER_PHY_CLK); 1103 1104 /* Enable the interface */ 1105 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1106 agl_prtx_ctl.s.enable = 1; 1107 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1108 1109 /* Read the value back to force the previous write */ 1110 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1111 1112 /* Enable the compensation controller */ 1113 agl_prtx_ctl.s.comp = 1; 1114 agl_prtx_ctl.s.drv_byp = 0; 1115 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1116 /* Force write out before wait. */ 1117 cvmx_read_csr(p->agl_prt_ctl); 1118 1119 /* For compensation state to lock. */ 1120 ndelay(1040 * NS_PER_PHY_CLK); 1121 1122 /* Default Interframe Gaps are too small. Recommended 1123 * workaround is. 1124 * 1125 * AGL_GMX_TX_IFG[IFG1]=14 1126 * AGL_GMX_TX_IFG[IFG2]=10 1127 */ 1128 cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae); 1129 } 1130 1131 octeon_mgmt_rx_fill_ring(netdev); 1132 1133 /* Clear statistics. */ 1134 /* Clear on read. */ 1135 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); 1136 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); 1137 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); 1138 1139 cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); 1140 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); 1141 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); 1142 1143 /* Clear any pending interrupts */ 1144 cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); 1145 1146 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, 1147 netdev)) { 1148 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq); 1149 goto err_noirq; 1150 } 1151 1152 /* Interrupt every single RX packet */ 1153 mix_irhwm.u64 = 0; 1154 mix_irhwm.s.irhwm = 0; 1155 cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); 1156 1157 /* Interrupt when we have 1 or more packets to clean. */ 1158 mix_orhwm.u64 = 0; 1159 mix_orhwm.s.orhwm = 0; 1160 cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); 1161 1162 /* Enable receive and transmit interrupts */ 1163 mix_intena.u64 = 0; 1164 mix_intena.s.ithena = 1; 1165 mix_intena.s.othena = 1; 1166 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); 1167 1168 /* Enable packet I/O. */ 1169 1170 rxx_frm_ctl.u64 = 0; 1171 rxx_frm_ctl.s.ptp_mode = p->has_rx_tstamp ? 1 : 0; 1172 rxx_frm_ctl.s.pre_align = 1; 1173 /* When set, disables the length check for non-min sized pkts 1174 * with padding in the client data. 1175 */ 1176 rxx_frm_ctl.s.pad_len = 1; 1177 /* When set, disables the length check for VLAN pkts */ 1178 rxx_frm_ctl.s.vlan_len = 1; 1179 /* When set, PREAMBLE checking is less strict */ 1180 rxx_frm_ctl.s.pre_free = 1; 1181 /* Control Pause Frames can match station SMAC */ 1182 rxx_frm_ctl.s.ctl_smac = 0; 1183 /* Control Pause Frames can match globally assign Multicast address */ 1184 rxx_frm_ctl.s.ctl_mcst = 1; 1185 /* Forward pause information to TX block */ 1186 rxx_frm_ctl.s.ctl_bck = 1; 1187 /* Drop Control Pause Frames */ 1188 rxx_frm_ctl.s.ctl_drp = 1; 1189 /* Strip off the preamble */ 1190 rxx_frm_ctl.s.pre_strp = 1; 1191 /* This port is configured to send PREAMBLE+SFD to begin every 1192 * frame. GMX checks that the PREAMBLE is sent correctly. 1193 */ 1194 rxx_frm_ctl.s.pre_chk = 1; 1195 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); 1196 1197 /* Configure the port duplex, speed and enables */ 1198 octeon_mgmt_disable_link(p); 1199 if (netdev->phydev) 1200 octeon_mgmt_update_link(p); 1201 octeon_mgmt_enable_link(p); 1202 1203 p->last_link = 0; 1204 p->last_speed = 0; 1205 /* PHY is not present in simulator. The carrier is enabled 1206 * while initializing the phy for simulator, leave it enabled. 1207 */ 1208 if (netdev->phydev) { 1209 netif_carrier_off(netdev); 1210 phy_start_aneg(netdev->phydev); 1211 } 1212 1213 netif_wake_queue(netdev); 1214 napi_enable(&p->napi); 1215 1216 return 0; 1217 err_noirq: 1218 octeon_mgmt_reset_hw(p); 1219 dma_unmap_single(p->dev, p->rx_ring_handle, 1220 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 1221 DMA_BIDIRECTIONAL); 1222 kfree(p->rx_ring); 1223 err_nomem: 1224 dma_unmap_single(p->dev, p->tx_ring_handle, 1225 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 1226 DMA_BIDIRECTIONAL); 1227 kfree(p->tx_ring); 1228 return -ENOMEM; 1229 } 1230 1231 static int octeon_mgmt_stop(struct net_device *netdev) 1232 { 1233 struct octeon_mgmt *p = netdev_priv(netdev); 1234 1235 napi_disable(&p->napi); 1236 netif_stop_queue(netdev); 1237 1238 if (netdev->phydev) 1239 phy_disconnect(netdev->phydev); 1240 1241 netif_carrier_off(netdev); 1242 1243 octeon_mgmt_reset_hw(p); 1244 1245 free_irq(p->irq, netdev); 1246 1247 /* dma_unmap is a nop on Octeon, so just free everything. */ 1248 skb_queue_purge(&p->tx_list); 1249 skb_queue_purge(&p->rx_list); 1250 1251 dma_unmap_single(p->dev, p->rx_ring_handle, 1252 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 1253 DMA_BIDIRECTIONAL); 1254 kfree(p->rx_ring); 1255 1256 dma_unmap_single(p->dev, p->tx_ring_handle, 1257 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 1258 DMA_BIDIRECTIONAL); 1259 kfree(p->tx_ring); 1260 1261 return 0; 1262 } 1263 1264 static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) 1265 { 1266 struct octeon_mgmt *p = netdev_priv(netdev); 1267 union mgmt_port_ring_entry re; 1268 unsigned long flags; 1269 int rv = NETDEV_TX_BUSY; 1270 1271 re.d64 = 0; 1272 re.s.tstamp = ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) != 0); 1273 re.s.len = skb->len; 1274 re.s.addr = dma_map_single(p->dev, skb->data, 1275 skb->len, 1276 DMA_TO_DEVICE); 1277 1278 spin_lock_irqsave(&p->tx_list.lock, flags); 1279 1280 if (unlikely(p->tx_current_fill >= ring_max_fill(OCTEON_MGMT_TX_RING_SIZE) - 1)) { 1281 spin_unlock_irqrestore(&p->tx_list.lock, flags); 1282 netif_stop_queue(netdev); 1283 spin_lock_irqsave(&p->tx_list.lock, flags); 1284 } 1285 1286 if (unlikely(p->tx_current_fill >= 1287 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) { 1288 spin_unlock_irqrestore(&p->tx_list.lock, flags); 1289 dma_unmap_single(p->dev, re.s.addr, re.s.len, 1290 DMA_TO_DEVICE); 1291 goto out; 1292 } 1293 1294 __skb_queue_tail(&p->tx_list, skb); 1295 1296 /* Put it in the ring. */ 1297 p->tx_ring[p->tx_next] = re.d64; 1298 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE; 1299 p->tx_current_fill++; 1300 1301 spin_unlock_irqrestore(&p->tx_list.lock, flags); 1302 1303 dma_sync_single_for_device(p->dev, p->tx_ring_handle, 1304 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 1305 DMA_BIDIRECTIONAL); 1306 1307 netdev->stats.tx_packets++; 1308 netdev->stats.tx_bytes += skb->len; 1309 1310 /* Ring the bell. */ 1311 cvmx_write_csr(p->mix + MIX_ORING2, 1); 1312 1313 netif_trans_update(netdev); 1314 rv = NETDEV_TX_OK; 1315 out: 1316 octeon_mgmt_update_tx_stats(netdev); 1317 return rv; 1318 } 1319 1320 #ifdef CONFIG_NET_POLL_CONTROLLER 1321 static void octeon_mgmt_poll_controller(struct net_device *netdev) 1322 { 1323 struct octeon_mgmt *p = netdev_priv(netdev); 1324 1325 octeon_mgmt_receive_packets(p, 16); 1326 octeon_mgmt_update_rx_stats(netdev); 1327 } 1328 #endif 1329 1330 static void octeon_mgmt_get_drvinfo(struct net_device *netdev, 1331 struct ethtool_drvinfo *info) 1332 { 1333 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1334 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1335 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); 1336 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); 1337 } 1338 1339 static int octeon_mgmt_nway_reset(struct net_device *dev) 1340 { 1341 if (!capable(CAP_NET_ADMIN)) 1342 return -EPERM; 1343 1344 if (dev->phydev) 1345 return phy_start_aneg(dev->phydev); 1346 1347 return -EOPNOTSUPP; 1348 } 1349 1350 static const struct ethtool_ops octeon_mgmt_ethtool_ops = { 1351 .get_drvinfo = octeon_mgmt_get_drvinfo, 1352 .nway_reset = octeon_mgmt_nway_reset, 1353 .get_link = ethtool_op_get_link, 1354 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1355 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1356 }; 1357 1358 static const struct net_device_ops octeon_mgmt_ops = { 1359 .ndo_open = octeon_mgmt_open, 1360 .ndo_stop = octeon_mgmt_stop, 1361 .ndo_start_xmit = octeon_mgmt_xmit, 1362 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering, 1363 .ndo_set_mac_address = octeon_mgmt_set_mac_address, 1364 .ndo_do_ioctl = octeon_mgmt_ioctl, 1365 .ndo_change_mtu = octeon_mgmt_change_mtu, 1366 #ifdef CONFIG_NET_POLL_CONTROLLER 1367 .ndo_poll_controller = octeon_mgmt_poll_controller, 1368 #endif 1369 }; 1370 1371 static int octeon_mgmt_probe(struct platform_device *pdev) 1372 { 1373 struct net_device *netdev; 1374 struct octeon_mgmt *p; 1375 const __be32 *data; 1376 const u8 *mac; 1377 struct resource *res_mix; 1378 struct resource *res_agl; 1379 struct resource *res_agl_prt_ctl; 1380 int len; 1381 int result; 1382 1383 netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); 1384 if (netdev == NULL) 1385 return -ENOMEM; 1386 1387 SET_NETDEV_DEV(netdev, &pdev->dev); 1388 1389 platform_set_drvdata(pdev, netdev); 1390 p = netdev_priv(netdev); 1391 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll, 1392 OCTEON_MGMT_NAPI_WEIGHT); 1393 1394 p->netdev = netdev; 1395 p->dev = &pdev->dev; 1396 p->has_rx_tstamp = false; 1397 1398 data = of_get_property(pdev->dev.of_node, "cell-index", &len); 1399 if (data && len == sizeof(*data)) { 1400 p->port = be32_to_cpup(data); 1401 } else { 1402 dev_err(&pdev->dev, "no 'cell-index' property\n"); 1403 result = -ENXIO; 1404 goto err; 1405 } 1406 1407 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); 1408 1409 result = platform_get_irq(pdev, 0); 1410 if (result < 0) 1411 goto err; 1412 1413 p->irq = result; 1414 1415 res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1416 if (res_mix == NULL) { 1417 dev_err(&pdev->dev, "no 'reg' resource\n"); 1418 result = -ENXIO; 1419 goto err; 1420 } 1421 1422 res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1423 if (res_agl == NULL) { 1424 dev_err(&pdev->dev, "no 'reg' resource\n"); 1425 result = -ENXIO; 1426 goto err; 1427 } 1428 1429 res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1430 if (res_agl_prt_ctl == NULL) { 1431 dev_err(&pdev->dev, "no 'reg' resource\n"); 1432 result = -ENXIO; 1433 goto err; 1434 } 1435 1436 p->mix_phys = res_mix->start; 1437 p->mix_size = resource_size(res_mix); 1438 p->agl_phys = res_agl->start; 1439 p->agl_size = resource_size(res_agl); 1440 p->agl_prt_ctl_phys = res_agl_prt_ctl->start; 1441 p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl); 1442 1443 1444 if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, 1445 res_mix->name)) { 1446 dev_err(&pdev->dev, "request_mem_region (%s) failed\n", 1447 res_mix->name); 1448 result = -ENXIO; 1449 goto err; 1450 } 1451 1452 if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size, 1453 res_agl->name)) { 1454 result = -ENXIO; 1455 dev_err(&pdev->dev, "request_mem_region (%s) failed\n", 1456 res_agl->name); 1457 goto err; 1458 } 1459 1460 if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys, 1461 p->agl_prt_ctl_size, res_agl_prt_ctl->name)) { 1462 result = -ENXIO; 1463 dev_err(&pdev->dev, "request_mem_region (%s) failed\n", 1464 res_agl_prt_ctl->name); 1465 goto err; 1466 } 1467 1468 p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); 1469 p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); 1470 p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys, 1471 p->agl_prt_ctl_size); 1472 if (!p->mix || !p->agl || !p->agl_prt_ctl) { 1473 dev_err(&pdev->dev, "failed to map I/O memory\n"); 1474 result = -ENOMEM; 1475 goto err; 1476 } 1477 1478 spin_lock_init(&p->lock); 1479 1480 skb_queue_head_init(&p->tx_list); 1481 skb_queue_head_init(&p->rx_list); 1482 tasklet_init(&p->tx_clean_tasklet, 1483 octeon_mgmt_clean_tx_tasklet, (unsigned long)p); 1484 1485 netdev->priv_flags |= IFF_UNICAST_FLT; 1486 1487 netdev->netdev_ops = &octeon_mgmt_ops; 1488 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; 1489 1490 netdev->min_mtu = 64 - OCTEON_MGMT_RX_HEADROOM; 1491 netdev->max_mtu = 16383 - OCTEON_MGMT_RX_HEADROOM; 1492 1493 mac = of_get_mac_address(pdev->dev.of_node); 1494 1495 if (mac) 1496 memcpy(netdev->dev_addr, mac, ETH_ALEN); 1497 else 1498 eth_hw_addr_random(netdev); 1499 1500 p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1501 1502 result = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1503 if (result) 1504 goto err; 1505 1506 netif_carrier_off(netdev); 1507 result = register_netdev(netdev); 1508 if (result) 1509 goto err; 1510 1511 dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); 1512 return 0; 1513 1514 err: 1515 of_node_put(p->phy_np); 1516 free_netdev(netdev); 1517 return result; 1518 } 1519 1520 static int octeon_mgmt_remove(struct platform_device *pdev) 1521 { 1522 struct net_device *netdev = platform_get_drvdata(pdev); 1523 struct octeon_mgmt *p = netdev_priv(netdev); 1524 1525 unregister_netdev(netdev); 1526 of_node_put(p->phy_np); 1527 free_netdev(netdev); 1528 return 0; 1529 } 1530 1531 static const struct of_device_id octeon_mgmt_match[] = { 1532 { 1533 .compatible = "cavium,octeon-5750-mix", 1534 }, 1535 {}, 1536 }; 1537 MODULE_DEVICE_TABLE(of, octeon_mgmt_match); 1538 1539 static struct platform_driver octeon_mgmt_driver = { 1540 .driver = { 1541 .name = "octeon_mgmt", 1542 .of_match_table = octeon_mgmt_match, 1543 }, 1544 .probe = octeon_mgmt_probe, 1545 .remove = octeon_mgmt_remove, 1546 }; 1547 1548 extern void octeon_mdiobus_force_mod_depencency(void); 1549 1550 static int __init octeon_mgmt_mod_init(void) 1551 { 1552 /* Force our mdiobus driver module to be loaded first. */ 1553 octeon_mdiobus_force_mod_depencency(); 1554 return platform_driver_register(&octeon_mgmt_driver); 1555 } 1556 1557 static void __exit octeon_mgmt_mod_exit(void) 1558 { 1559 platform_driver_unregister(&octeon_mgmt_driver); 1560 } 1561 1562 module_init(octeon_mgmt_mod_init); 1563 module_exit(octeon_mgmt_mod_exit); 1564 1565 MODULE_DESCRIPTION(DRV_DESCRIPTION); 1566 MODULE_AUTHOR("David Daney"); 1567 MODULE_LICENSE("GPL"); 1568 MODULE_VERSION(DRV_VERSION); 1569