1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2009-2012 Cavium, Inc 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/etherdevice.h> 12 #include <linux/capability.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/interrupt.h> 15 #include <linux/netdevice.h> 16 #include <linux/spinlock.h> 17 #include <linux/if_vlan.h> 18 #include <linux/of_mdio.h> 19 #include <linux/module.h> 20 #include <linux/of_net.h> 21 #include <linux/init.h> 22 #include <linux/slab.h> 23 #include <linux/phy.h> 24 #include <linux/io.h> 25 26 #include <asm/octeon/octeon.h> 27 #include <asm/octeon/cvmx-mixx-defs.h> 28 #include <asm/octeon/cvmx-agl-defs.h> 29 30 #define DRV_NAME "octeon_mgmt" 31 #define DRV_DESCRIPTION \ 32 "Cavium Networks Octeon MII (management) port Network Driver" 33 34 #define OCTEON_MGMT_NAPI_WEIGHT 16 35 36 /* Ring sizes that are powers of two allow for more efficient modulo 37 * opertions. 38 */ 39 #define OCTEON_MGMT_RX_RING_SIZE 512 40 #define OCTEON_MGMT_TX_RING_SIZE 128 41 42 /* Allow 8 bytes for vlan and FCS. */ 43 #define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 44 45 union mgmt_port_ring_entry { 46 u64 d64; 47 struct { 48 #define RING_ENTRY_CODE_DONE 0xf 49 #define RING_ENTRY_CODE_MORE 0x10 50 #ifdef __BIG_ENDIAN_BITFIELD 51 u64 reserved_62_63:2; 52 /* Length of the buffer/packet in bytes */ 53 u64 len:14; 54 /* For TX, signals that the packet should be timestamped */ 55 u64 tstamp:1; 56 /* The RX error code */ 57 u64 code:7; 58 /* Physical address of the buffer */ 59 u64 addr:40; 60 #else 61 u64 addr:40; 62 u64 code:7; 63 u64 tstamp:1; 64 u64 len:14; 65 u64 reserved_62_63:2; 66 #endif 67 } s; 68 }; 69 70 #define MIX_ORING1 0x0 71 #define MIX_ORING2 0x8 72 #define MIX_IRING1 0x10 73 #define MIX_IRING2 0x18 74 #define MIX_CTL 0x20 75 #define MIX_IRHWM 0x28 76 #define MIX_IRCNT 0x30 77 #define MIX_ORHWM 0x38 78 #define MIX_ORCNT 0x40 79 #define MIX_ISR 0x48 80 #define MIX_INTENA 0x50 81 #define MIX_REMCNT 0x58 82 #define MIX_BIST 0x78 83 84 #define AGL_GMX_PRT_CFG 0x10 85 #define AGL_GMX_RX_FRM_CTL 0x18 86 #define AGL_GMX_RX_FRM_MAX 0x30 87 #define AGL_GMX_RX_JABBER 0x38 88 #define AGL_GMX_RX_STATS_CTL 0x50 89 90 #define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 91 #define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 92 #define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 93 94 #define AGL_GMX_RX_ADR_CTL 0x100 95 #define AGL_GMX_RX_ADR_CAM_EN 0x108 96 #define AGL_GMX_RX_ADR_CAM0 0x180 97 #define AGL_GMX_RX_ADR_CAM1 0x188 98 #define AGL_GMX_RX_ADR_CAM2 0x190 99 #define AGL_GMX_RX_ADR_CAM3 0x198 100 #define AGL_GMX_RX_ADR_CAM4 0x1a0 101 #define AGL_GMX_RX_ADR_CAM5 0x1a8 102 103 #define AGL_GMX_TX_CLK 0x208 104 #define AGL_GMX_TX_STATS_CTL 0x268 105 #define AGL_GMX_TX_CTL 0x270 106 #define AGL_GMX_TX_STAT0 0x280 107 #define AGL_GMX_TX_STAT1 0x288 108 #define AGL_GMX_TX_STAT2 0x290 109 #define AGL_GMX_TX_STAT3 0x298 110 #define AGL_GMX_TX_STAT4 0x2a0 111 #define AGL_GMX_TX_STAT5 0x2a8 112 #define AGL_GMX_TX_STAT6 0x2b0 113 #define AGL_GMX_TX_STAT7 0x2b8 114 #define AGL_GMX_TX_STAT8 0x2c0 115 #define AGL_GMX_TX_STAT9 0x2c8 116 117 struct octeon_mgmt { 118 struct net_device *netdev; 119 u64 mix; 120 u64 agl; 121 u64 agl_prt_ctl; 122 int port; 123 int irq; 124 bool has_rx_tstamp; 125 u64 *tx_ring; 126 dma_addr_t tx_ring_handle; 127 unsigned int tx_next; 128 unsigned int tx_next_clean; 129 unsigned int tx_current_fill; 130 /* The tx_list lock also protects the ring related variables */ 131 struct sk_buff_head tx_list; 132 133 /* RX variables only touched in napi_poll. No locking necessary. */ 134 u64 *rx_ring; 135 dma_addr_t rx_ring_handle; 136 unsigned int rx_next; 137 unsigned int rx_next_fill; 138 unsigned int rx_current_fill; 139 struct sk_buff_head rx_list; 140 141 spinlock_t lock; 142 unsigned int last_duplex; 143 unsigned int last_link; 144 unsigned int last_speed; 145 struct device *dev; 146 struct napi_struct napi; 147 struct tasklet_struct tx_clean_tasklet; 148 struct device_node *phy_np; 149 resource_size_t mix_phys; 150 resource_size_t mix_size; 151 resource_size_t agl_phys; 152 resource_size_t agl_size; 153 resource_size_t agl_prt_ctl_phys; 154 resource_size_t agl_prt_ctl_size; 155 }; 156 157 static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) 158 { 159 union cvmx_mixx_intena mix_intena; 160 unsigned long flags; 161 162 spin_lock_irqsave(&p->lock, flags); 163 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); 164 mix_intena.s.ithena = enable ? 1 : 0; 165 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); 166 spin_unlock_irqrestore(&p->lock, flags); 167 } 168 169 static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) 170 { 171 union cvmx_mixx_intena mix_intena; 172 unsigned long flags; 173 174 spin_lock_irqsave(&p->lock, flags); 175 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); 176 mix_intena.s.othena = enable ? 1 : 0; 177 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); 178 spin_unlock_irqrestore(&p->lock, flags); 179 } 180 181 static void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p) 182 { 183 octeon_mgmt_set_rx_irq(p, 1); 184 } 185 186 static void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p) 187 { 188 octeon_mgmt_set_rx_irq(p, 0); 189 } 190 191 static void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p) 192 { 193 octeon_mgmt_set_tx_irq(p, 1); 194 } 195 196 static void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p) 197 { 198 octeon_mgmt_set_tx_irq(p, 0); 199 } 200 201 static unsigned int ring_max_fill(unsigned int ring_size) 202 { 203 return ring_size - 8; 204 } 205 206 static unsigned int ring_size_to_bytes(unsigned int ring_size) 207 { 208 return ring_size * sizeof(union mgmt_port_ring_entry); 209 } 210 211 static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) 212 { 213 struct octeon_mgmt *p = netdev_priv(netdev); 214 215 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { 216 unsigned int size; 217 union mgmt_port_ring_entry re; 218 struct sk_buff *skb; 219 220 /* CN56XX pass 1 needs 8 bytes of padding. */ 221 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN; 222 223 skb = netdev_alloc_skb(netdev, size); 224 if (!skb) 225 break; 226 skb_reserve(skb, NET_IP_ALIGN); 227 __skb_queue_tail(&p->rx_list, skb); 228 229 re.d64 = 0; 230 re.s.len = size; 231 re.s.addr = dma_map_single(p->dev, skb->data, 232 size, 233 DMA_FROM_DEVICE); 234 235 /* Put it in the ring. */ 236 p->rx_ring[p->rx_next_fill] = re.d64; 237 dma_sync_single_for_device(p->dev, p->rx_ring_handle, 238 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 239 DMA_BIDIRECTIONAL); 240 p->rx_next_fill = 241 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; 242 p->rx_current_fill++; 243 /* Ring the bell. */ 244 cvmx_write_csr(p->mix + MIX_IRING2, 1); 245 } 246 } 247 248 static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) 249 { 250 union cvmx_mixx_orcnt mix_orcnt; 251 union mgmt_port_ring_entry re; 252 struct sk_buff *skb; 253 int cleaned = 0; 254 unsigned long flags; 255 256 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); 257 while (mix_orcnt.s.orcnt) { 258 spin_lock_irqsave(&p->tx_list.lock, flags); 259 260 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); 261 262 if (mix_orcnt.s.orcnt == 0) { 263 spin_unlock_irqrestore(&p->tx_list.lock, flags); 264 break; 265 } 266 267 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle, 268 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 269 DMA_BIDIRECTIONAL); 270 271 re.d64 = p->tx_ring[p->tx_next_clean]; 272 p->tx_next_clean = 273 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE; 274 skb = __skb_dequeue(&p->tx_list); 275 276 mix_orcnt.u64 = 0; 277 mix_orcnt.s.orcnt = 1; 278 279 /* Acknowledge to hardware that we have the buffer. */ 280 cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); 281 p->tx_current_fill--; 282 283 spin_unlock_irqrestore(&p->tx_list.lock, flags); 284 285 dma_unmap_single(p->dev, re.s.addr, re.s.len, 286 DMA_TO_DEVICE); 287 288 /* Read the hardware TX timestamp if one was recorded */ 289 if (unlikely(re.s.tstamp)) { 290 struct skb_shared_hwtstamps ts; 291 u64 ns; 292 293 memset(&ts, 0, sizeof(ts)); 294 /* Read the timestamp */ 295 ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port)); 296 /* Remove the timestamp from the FIFO */ 297 cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0); 298 /* Tell the kernel about the timestamp */ 299 ts.hwtstamp = ns_to_ktime(ns); 300 skb_tstamp_tx(skb, &ts); 301 } 302 303 dev_kfree_skb_any(skb); 304 cleaned++; 305 306 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); 307 } 308 309 if (cleaned && netif_queue_stopped(p->netdev)) 310 netif_wake_queue(p->netdev); 311 } 312 313 static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) 314 { 315 struct octeon_mgmt *p = (struct octeon_mgmt *)arg; 316 octeon_mgmt_clean_tx_buffers(p); 317 octeon_mgmt_enable_tx_irq(p); 318 } 319 320 static void octeon_mgmt_update_rx_stats(struct net_device *netdev) 321 { 322 struct octeon_mgmt *p = netdev_priv(netdev); 323 unsigned long flags; 324 u64 drop, bad; 325 326 /* These reads also clear the count registers. */ 327 drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); 328 bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); 329 330 if (drop || bad) { 331 /* Do an atomic update. */ 332 spin_lock_irqsave(&p->lock, flags); 333 netdev->stats.rx_errors += bad; 334 netdev->stats.rx_dropped += drop; 335 spin_unlock_irqrestore(&p->lock, flags); 336 } 337 } 338 339 static void octeon_mgmt_update_tx_stats(struct net_device *netdev) 340 { 341 struct octeon_mgmt *p = netdev_priv(netdev); 342 unsigned long flags; 343 344 union cvmx_agl_gmx_txx_stat0 s0; 345 union cvmx_agl_gmx_txx_stat1 s1; 346 347 /* These reads also clear the count registers. */ 348 s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); 349 s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); 350 351 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { 352 /* Do an atomic update. */ 353 spin_lock_irqsave(&p->lock, flags); 354 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol; 355 netdev->stats.collisions += s1.s.scol + s1.s.mcol; 356 spin_unlock_irqrestore(&p->lock, flags); 357 } 358 } 359 360 /* 361 * Dequeue a receive skb and its corresponding ring entry. The ring 362 * entry is returned, *pskb is updated to point to the skb. 363 */ 364 static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, 365 struct sk_buff **pskb) 366 { 367 union mgmt_port_ring_entry re; 368 369 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle, 370 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 371 DMA_BIDIRECTIONAL); 372 373 re.d64 = p->rx_ring[p->rx_next]; 374 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE; 375 p->rx_current_fill--; 376 *pskb = __skb_dequeue(&p->rx_list); 377 378 dma_unmap_single(p->dev, re.s.addr, 379 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM, 380 DMA_FROM_DEVICE); 381 382 return re.d64; 383 } 384 385 386 static int octeon_mgmt_receive_one(struct octeon_mgmt *p) 387 { 388 struct net_device *netdev = p->netdev; 389 union cvmx_mixx_ircnt mix_ircnt; 390 union mgmt_port_ring_entry re; 391 struct sk_buff *skb; 392 struct sk_buff *skb2; 393 struct sk_buff *skb_new; 394 union mgmt_port_ring_entry re2; 395 int rc = 1; 396 397 398 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb); 399 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) { 400 /* A good packet, send it up. */ 401 skb_put(skb, re.s.len); 402 good: 403 /* Process the RX timestamp if it was recorded */ 404 if (p->has_rx_tstamp) { 405 /* The first 8 bytes are the timestamp */ 406 u64 ns = *(u64 *)skb->data; 407 struct skb_shared_hwtstamps *ts; 408 ts = skb_hwtstamps(skb); 409 ts->hwtstamp = ns_to_ktime(ns); 410 __skb_pull(skb, 8); 411 } 412 skb->protocol = eth_type_trans(skb, netdev); 413 netdev->stats.rx_packets++; 414 netdev->stats.rx_bytes += skb->len; 415 netif_receive_skb(skb); 416 rc = 0; 417 } else if (re.s.code == RING_ENTRY_CODE_MORE) { 418 /* Packet split across skbs. This can happen if we 419 * increase the MTU. Buffers that are already in the 420 * rx ring can then end up being too small. As the rx 421 * ring is refilled, buffers sized for the new MTU 422 * will be used and we should go back to the normal 423 * non-split case. 424 */ 425 skb_put(skb, re.s.len); 426 do { 427 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2); 428 if (re2.s.code != RING_ENTRY_CODE_MORE 429 && re2.s.code != RING_ENTRY_CODE_DONE) 430 goto split_error; 431 skb_put(skb2, re2.s.len); 432 skb_new = skb_copy_expand(skb, 0, skb2->len, 433 GFP_ATOMIC); 434 if (!skb_new) 435 goto split_error; 436 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new), 437 skb2->len)) 438 goto split_error; 439 skb_put(skb_new, skb2->len); 440 dev_kfree_skb_any(skb); 441 dev_kfree_skb_any(skb2); 442 skb = skb_new; 443 } while (re2.s.code == RING_ENTRY_CODE_MORE); 444 goto good; 445 } else { 446 /* Some other error, discard it. */ 447 dev_kfree_skb_any(skb); 448 /* Error statistics are accumulated in 449 * octeon_mgmt_update_rx_stats. 450 */ 451 } 452 goto done; 453 split_error: 454 /* Discard the whole mess. */ 455 dev_kfree_skb_any(skb); 456 dev_kfree_skb_any(skb2); 457 while (re2.s.code == RING_ENTRY_CODE_MORE) { 458 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2); 459 dev_kfree_skb_any(skb2); 460 } 461 netdev->stats.rx_errors++; 462 463 done: 464 /* Tell the hardware we processed a packet. */ 465 mix_ircnt.u64 = 0; 466 mix_ircnt.s.ircnt = 1; 467 cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); 468 return rc; 469 } 470 471 static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) 472 { 473 unsigned int work_done = 0; 474 union cvmx_mixx_ircnt mix_ircnt; 475 int rc; 476 477 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); 478 while (work_done < budget && mix_ircnt.s.ircnt) { 479 480 rc = octeon_mgmt_receive_one(p); 481 if (!rc) 482 work_done++; 483 484 /* Check for more packets. */ 485 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); 486 } 487 488 octeon_mgmt_rx_fill_ring(p->netdev); 489 490 return work_done; 491 } 492 493 static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget) 494 { 495 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi); 496 struct net_device *netdev = p->netdev; 497 unsigned int work_done = 0; 498 499 work_done = octeon_mgmt_receive_packets(p, budget); 500 501 if (work_done < budget) { 502 /* We stopped because no more packets were available. */ 503 napi_complete_done(napi, work_done); 504 octeon_mgmt_enable_rx_irq(p); 505 } 506 octeon_mgmt_update_rx_stats(netdev); 507 508 return work_done; 509 } 510 511 /* Reset the hardware to clean state. */ 512 static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) 513 { 514 union cvmx_mixx_ctl mix_ctl; 515 union cvmx_mixx_bist mix_bist; 516 union cvmx_agl_gmx_bist agl_gmx_bist; 517 518 mix_ctl.u64 = 0; 519 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 520 do { 521 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); 522 } while (mix_ctl.s.busy); 523 mix_ctl.s.reset = 1; 524 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 525 cvmx_read_csr(p->mix + MIX_CTL); 526 octeon_io_clk_delay(64); 527 528 mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); 529 if (mix_bist.u64) 530 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", 531 (unsigned long long)mix_bist.u64); 532 533 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST); 534 if (agl_gmx_bist.u64) 535 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n", 536 (unsigned long long)agl_gmx_bist.u64); 537 } 538 539 struct octeon_mgmt_cam_state { 540 u64 cam[6]; 541 u64 cam_mask; 542 int cam_index; 543 }; 544 545 static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, 546 unsigned char *addr) 547 { 548 int i; 549 550 for (i = 0; i < 6; i++) 551 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index)); 552 cs->cam_mask |= (1ULL << cs->cam_index); 553 cs->cam_index++; 554 } 555 556 static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) 557 { 558 struct octeon_mgmt *p = netdev_priv(netdev); 559 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; 560 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; 561 unsigned long flags; 562 unsigned int prev_packet_enable; 563 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */ 564 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */ 565 struct octeon_mgmt_cam_state cam_state; 566 struct netdev_hw_addr *ha; 567 int available_cam_entries; 568 569 memset(&cam_state, 0, sizeof(cam_state)); 570 571 if ((netdev->flags & IFF_PROMISC) || netdev->uc.count > 7) { 572 cam_mode = 0; 573 available_cam_entries = 8; 574 } else { 575 /* One CAM entry for the primary address, leaves seven 576 * for the secondary addresses. 577 */ 578 available_cam_entries = 7 - netdev->uc.count; 579 } 580 581 if (netdev->flags & IFF_MULTICAST) { 582 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI) || 583 netdev_mc_count(netdev) > available_cam_entries) 584 multicast_mode = 2; /* 2 - Accept all multicast. */ 585 else 586 multicast_mode = 0; /* 0 - Use CAM. */ 587 } 588 589 if (cam_mode == 1) { 590 /* Add primary address. */ 591 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr); 592 netdev_for_each_uc_addr(ha, netdev) 593 octeon_mgmt_cam_state_add(&cam_state, ha->addr); 594 } 595 if (multicast_mode == 0) { 596 netdev_for_each_mc_addr(ha, netdev) 597 octeon_mgmt_cam_state_add(&cam_state, ha->addr); 598 } 599 600 spin_lock_irqsave(&p->lock, flags); 601 602 /* Disable packet I/O. */ 603 agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 604 prev_packet_enable = agl_gmx_prtx.s.en; 605 agl_gmx_prtx.s.en = 0; 606 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); 607 608 adr_ctl.u64 = 0; 609 adr_ctl.s.cam_mode = cam_mode; 610 adr_ctl.s.mcst = multicast_mode; 611 adr_ctl.s.bcst = 1; /* Allow broadcast */ 612 613 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); 614 615 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); 616 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); 617 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); 618 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); 619 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); 620 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); 621 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); 622 623 /* Restore packet I/O. */ 624 agl_gmx_prtx.s.en = prev_packet_enable; 625 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); 626 627 spin_unlock_irqrestore(&p->lock, flags); 628 } 629 630 static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) 631 { 632 int r = eth_mac_addr(netdev, addr); 633 634 if (r) 635 return r; 636 637 octeon_mgmt_set_rx_filtering(netdev); 638 639 return 0; 640 } 641 642 static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) 643 { 644 struct octeon_mgmt *p = netdev_priv(netdev); 645 int max_packet = new_mtu + ETH_HLEN + ETH_FCS_LEN; 646 647 netdev->mtu = new_mtu; 648 649 /* HW lifts the limit if the frame is VLAN tagged 650 * (+4 bytes per each tag, up to two tags) 651 */ 652 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, max_packet); 653 /* Set the hardware to truncate packets larger than the MTU. The jabber 654 * register must be set to a multiple of 8 bytes, so round up. JABBER is 655 * an unconditional limit, so we need to account for two possible VLAN 656 * tags. 657 */ 658 cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, 659 (max_packet + 7 + VLAN_HLEN * 2) & 0xfff8); 660 661 return 0; 662 } 663 664 static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) 665 { 666 struct net_device *netdev = dev_id; 667 struct octeon_mgmt *p = netdev_priv(netdev); 668 union cvmx_mixx_isr mixx_isr; 669 670 mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); 671 672 /* Clear any pending interrupts */ 673 cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); 674 cvmx_read_csr(p->mix + MIX_ISR); 675 676 if (mixx_isr.s.irthresh) { 677 octeon_mgmt_disable_rx_irq(p); 678 napi_schedule(&p->napi); 679 } 680 if (mixx_isr.s.orthresh) { 681 octeon_mgmt_disable_tx_irq(p); 682 tasklet_schedule(&p->tx_clean_tasklet); 683 } 684 685 return IRQ_HANDLED; 686 } 687 688 static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev, 689 struct ifreq *rq, int cmd) 690 { 691 struct octeon_mgmt *p = netdev_priv(netdev); 692 struct hwtstamp_config config; 693 union cvmx_mio_ptp_clock_cfg ptp; 694 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; 695 bool have_hw_timestamps = false; 696 697 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 698 return -EFAULT; 699 700 if (config.flags) /* reserved for future extensions */ 701 return -EINVAL; 702 703 /* Check the status of hardware for tiemstamps */ 704 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 705 /* Get the current state of the PTP clock */ 706 ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG); 707 if (!ptp.s.ext_clk_en) { 708 /* The clock has not been configured to use an 709 * external source. Program it to use the main clock 710 * reference. 711 */ 712 u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate(); 713 if (!ptp.s.ptp_en) 714 cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp); 715 netdev_info(netdev, 716 "PTP Clock using sclk reference @ %lldHz\n", 717 (NSEC_PER_SEC << 32) / clock_comp); 718 } else { 719 /* The clock is already programmed to use a GPIO */ 720 u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP); 721 netdev_info(netdev, 722 "PTP Clock using GPIO%d @ %lld Hz\n", 723 ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / clock_comp); 724 } 725 726 /* Enable the clock if it wasn't done already */ 727 if (!ptp.s.ptp_en) { 728 ptp.s.ptp_en = 1; 729 cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64); 730 } 731 have_hw_timestamps = true; 732 } 733 734 if (!have_hw_timestamps) 735 return -EINVAL; 736 737 switch (config.tx_type) { 738 case HWTSTAMP_TX_OFF: 739 case HWTSTAMP_TX_ON: 740 break; 741 default: 742 return -ERANGE; 743 } 744 745 switch (config.rx_filter) { 746 case HWTSTAMP_FILTER_NONE: 747 p->has_rx_tstamp = false; 748 rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); 749 rxx_frm_ctl.s.ptp_mode = 0; 750 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); 751 break; 752 case HWTSTAMP_FILTER_ALL: 753 case HWTSTAMP_FILTER_SOME: 754 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 755 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 756 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 757 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 758 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 759 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 760 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 761 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 762 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 763 case HWTSTAMP_FILTER_PTP_V2_EVENT: 764 case HWTSTAMP_FILTER_PTP_V2_SYNC: 765 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 766 case HWTSTAMP_FILTER_NTP_ALL: 767 p->has_rx_tstamp = have_hw_timestamps; 768 config.rx_filter = HWTSTAMP_FILTER_ALL; 769 if (p->has_rx_tstamp) { 770 rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); 771 rxx_frm_ctl.s.ptp_mode = 1; 772 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); 773 } 774 break; 775 default: 776 return -ERANGE; 777 } 778 779 if (copy_to_user(rq->ifr_data, &config, sizeof(config))) 780 return -EFAULT; 781 782 return 0; 783 } 784 785 static int octeon_mgmt_ioctl(struct net_device *netdev, 786 struct ifreq *rq, int cmd) 787 { 788 switch (cmd) { 789 case SIOCSHWTSTAMP: 790 return octeon_mgmt_ioctl_hwtstamp(netdev, rq, cmd); 791 default: 792 return phy_do_ioctl(netdev, rq, cmd); 793 } 794 } 795 796 static void octeon_mgmt_disable_link(struct octeon_mgmt *p) 797 { 798 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 799 800 /* Disable GMX before we make any changes. */ 801 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 802 prtx_cfg.s.en = 0; 803 prtx_cfg.s.tx_en = 0; 804 prtx_cfg.s.rx_en = 0; 805 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); 806 807 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 808 int i; 809 for (i = 0; i < 10; i++) { 810 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 811 if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1) 812 break; 813 mdelay(1); 814 i++; 815 } 816 } 817 } 818 819 static void octeon_mgmt_enable_link(struct octeon_mgmt *p) 820 { 821 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 822 823 /* Restore the GMX enable state only if link is set */ 824 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 825 prtx_cfg.s.tx_en = 1; 826 prtx_cfg.s.rx_en = 1; 827 prtx_cfg.s.en = 1; 828 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); 829 } 830 831 static void octeon_mgmt_update_link(struct octeon_mgmt *p) 832 { 833 struct net_device *ndev = p->netdev; 834 struct phy_device *phydev = ndev->phydev; 835 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 836 837 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 838 839 if (!phydev->link) 840 prtx_cfg.s.duplex = 1; 841 else 842 prtx_cfg.s.duplex = phydev->duplex; 843 844 switch (phydev->speed) { 845 case 10: 846 prtx_cfg.s.speed = 0; 847 prtx_cfg.s.slottime = 0; 848 849 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 850 prtx_cfg.s.burst = 1; 851 prtx_cfg.s.speed_msb = 1; 852 } 853 break; 854 case 100: 855 prtx_cfg.s.speed = 0; 856 prtx_cfg.s.slottime = 0; 857 858 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 859 prtx_cfg.s.burst = 1; 860 prtx_cfg.s.speed_msb = 0; 861 } 862 break; 863 case 1000: 864 /* 1000 MBits is only supported on 6XXX chips */ 865 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 866 prtx_cfg.s.speed = 1; 867 prtx_cfg.s.speed_msb = 0; 868 /* Only matters for half-duplex */ 869 prtx_cfg.s.slottime = 1; 870 prtx_cfg.s.burst = phydev->duplex; 871 } 872 break; 873 case 0: /* No link */ 874 default: 875 break; 876 } 877 878 /* Write the new GMX setting with the port still disabled. */ 879 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); 880 881 /* Read GMX CFG again to make sure the config is completed. */ 882 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); 883 884 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 885 union cvmx_agl_gmx_txx_clk agl_clk; 886 union cvmx_agl_prtx_ctl prtx_ctl; 887 888 prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 889 agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK); 890 /* MII (both speeds) and RGMII 1000 speed. */ 891 agl_clk.s.clk_cnt = 1; 892 if (prtx_ctl.s.mode == 0) { /* RGMII mode */ 893 if (phydev->speed == 10) 894 agl_clk.s.clk_cnt = 50; 895 else if (phydev->speed == 100) 896 agl_clk.s.clk_cnt = 5; 897 } 898 cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64); 899 } 900 } 901 902 static void octeon_mgmt_adjust_link(struct net_device *netdev) 903 { 904 struct octeon_mgmt *p = netdev_priv(netdev); 905 struct phy_device *phydev = netdev->phydev; 906 unsigned long flags; 907 int link_changed = 0; 908 909 if (!phydev) 910 return; 911 912 spin_lock_irqsave(&p->lock, flags); 913 914 915 if (!phydev->link && p->last_link) 916 link_changed = -1; 917 918 if (phydev->link && 919 (p->last_duplex != phydev->duplex || 920 p->last_link != phydev->link || 921 p->last_speed != phydev->speed)) { 922 octeon_mgmt_disable_link(p); 923 link_changed = 1; 924 octeon_mgmt_update_link(p); 925 octeon_mgmt_enable_link(p); 926 } 927 928 p->last_link = phydev->link; 929 p->last_speed = phydev->speed; 930 p->last_duplex = phydev->duplex; 931 932 spin_unlock_irqrestore(&p->lock, flags); 933 934 if (link_changed != 0) { 935 if (link_changed > 0) 936 netdev_info(netdev, "Link is up - %d/%s\n", 937 phydev->speed, phydev->duplex == DUPLEX_FULL ? "Full" : "Half"); 938 else 939 netdev_info(netdev, "Link is down\n"); 940 } 941 } 942 943 static int octeon_mgmt_init_phy(struct net_device *netdev) 944 { 945 struct octeon_mgmt *p = netdev_priv(netdev); 946 struct phy_device *phydev = NULL; 947 948 if (octeon_is_simulation() || p->phy_np == NULL) { 949 /* No PHYs in the simulator. */ 950 netif_carrier_on(netdev); 951 return 0; 952 } 953 954 phydev = of_phy_connect(netdev, p->phy_np, 955 octeon_mgmt_adjust_link, 0, 956 PHY_INTERFACE_MODE_MII); 957 958 if (!phydev) 959 return -ENODEV; 960 961 return 0; 962 } 963 964 static int octeon_mgmt_open(struct net_device *netdev) 965 { 966 struct octeon_mgmt *p = netdev_priv(netdev); 967 union cvmx_mixx_ctl mix_ctl; 968 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode; 969 union cvmx_mixx_oring1 oring1; 970 union cvmx_mixx_iring1 iring1; 971 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl; 972 union cvmx_mixx_irhwm mix_irhwm; 973 union cvmx_mixx_orhwm mix_orhwm; 974 union cvmx_mixx_intena mix_intena; 975 struct sockaddr sa; 976 977 /* Allocate ring buffers. */ 978 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 979 GFP_KERNEL); 980 if (!p->tx_ring) 981 return -ENOMEM; 982 p->tx_ring_handle = 983 dma_map_single(p->dev, p->tx_ring, 984 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 985 DMA_BIDIRECTIONAL); 986 p->tx_next = 0; 987 p->tx_next_clean = 0; 988 p->tx_current_fill = 0; 989 990 991 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 992 GFP_KERNEL); 993 if (!p->rx_ring) 994 goto err_nomem; 995 p->rx_ring_handle = 996 dma_map_single(p->dev, p->rx_ring, 997 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 998 DMA_BIDIRECTIONAL); 999 1000 p->rx_next = 0; 1001 p->rx_next_fill = 0; 1002 p->rx_current_fill = 0; 1003 1004 octeon_mgmt_reset_hw(p); 1005 1006 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); 1007 1008 /* Bring it out of reset if needed. */ 1009 if (mix_ctl.s.reset) { 1010 mix_ctl.s.reset = 0; 1011 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 1012 do { 1013 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); 1014 } while (mix_ctl.s.reset); 1015 } 1016 1017 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { 1018 agl_gmx_inf_mode.u64 = 0; 1019 agl_gmx_inf_mode.s.en = 1; 1020 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); 1021 } 1022 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 1023 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 1024 /* Force compensation values, as they are not 1025 * determined properly by HW 1026 */ 1027 union cvmx_agl_gmx_drv_ctl drv_ctl; 1028 1029 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); 1030 if (p->port) { 1031 drv_ctl.s.byp_en1 = 1; 1032 drv_ctl.s.nctl1 = 6; 1033 drv_ctl.s.pctl1 = 6; 1034 } else { 1035 drv_ctl.s.byp_en = 1; 1036 drv_ctl.s.nctl = 6; 1037 drv_ctl.s.pctl = 6; 1038 } 1039 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); 1040 } 1041 1042 oring1.u64 = 0; 1043 oring1.s.obase = p->tx_ring_handle >> 3; 1044 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; 1045 cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); 1046 1047 iring1.u64 = 0; 1048 iring1.s.ibase = p->rx_ring_handle >> 3; 1049 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; 1050 cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); 1051 1052 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); 1053 octeon_mgmt_set_mac_address(netdev, &sa); 1054 1055 octeon_mgmt_change_mtu(netdev, netdev->mtu); 1056 1057 /* Enable the port HW. Packets are not allowed until 1058 * cvmx_mgmt_port_enable() is called. 1059 */ 1060 mix_ctl.u64 = 0; 1061 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */ 1062 mix_ctl.s.en = 1; /* Enable the port */ 1063 mix_ctl.s.nbtarb = 0; /* Arbitration mode */ 1064 /* MII CB-request FIFO programmable high watermark */ 1065 mix_ctl.s.mrq_hwm = 1; 1066 #ifdef __LITTLE_ENDIAN 1067 mix_ctl.s.lendian = 1; 1068 #endif 1069 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); 1070 1071 /* Read the PHY to find the mode of the interface. */ 1072 if (octeon_mgmt_init_phy(netdev)) { 1073 dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port); 1074 goto err_noirq; 1075 } 1076 1077 /* Set the mode of the interface, RGMII/MII. */ 1078 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && netdev->phydev) { 1079 union cvmx_agl_prtx_ctl agl_prtx_ctl; 1080 int rgmii_mode = 1081 (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1082 netdev->phydev->supported) | 1083 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1084 netdev->phydev->supported)) != 0; 1085 1086 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1087 agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1; 1088 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1089 1090 /* MII clocks counts are based on the 125Mhz 1091 * reference, which has an 8nS period. So our delays 1092 * need to be multiplied by this factor. 1093 */ 1094 #define NS_PER_PHY_CLK 8 1095 1096 /* Take the DLL and clock tree out of reset */ 1097 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1098 agl_prtx_ctl.s.clkrst = 0; 1099 if (rgmii_mode) { 1100 agl_prtx_ctl.s.dllrst = 0; 1101 agl_prtx_ctl.s.clktx_byp = 0; 1102 } 1103 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1104 cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */ 1105 1106 /* Wait for the DLL to lock. External 125 MHz 1107 * reference clock must be stable at this point. 1108 */ 1109 ndelay(256 * NS_PER_PHY_CLK); 1110 1111 /* Enable the interface */ 1112 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1113 agl_prtx_ctl.s.enable = 1; 1114 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1115 1116 /* Read the value back to force the previous write */ 1117 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); 1118 1119 /* Enable the compensation controller */ 1120 agl_prtx_ctl.s.comp = 1; 1121 agl_prtx_ctl.s.drv_byp = 0; 1122 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); 1123 /* Force write out before wait. */ 1124 cvmx_read_csr(p->agl_prt_ctl); 1125 1126 /* For compensation state to lock. */ 1127 ndelay(1040 * NS_PER_PHY_CLK); 1128 1129 /* Default Interframe Gaps are too small. Recommended 1130 * workaround is. 1131 * 1132 * AGL_GMX_TX_IFG[IFG1]=14 1133 * AGL_GMX_TX_IFG[IFG2]=10 1134 */ 1135 cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae); 1136 } 1137 1138 octeon_mgmt_rx_fill_ring(netdev); 1139 1140 /* Clear statistics. */ 1141 /* Clear on read. */ 1142 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); 1143 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); 1144 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); 1145 1146 cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); 1147 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); 1148 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); 1149 1150 /* Clear any pending interrupts */ 1151 cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); 1152 1153 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, 1154 netdev)) { 1155 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq); 1156 goto err_noirq; 1157 } 1158 1159 /* Interrupt every single RX packet */ 1160 mix_irhwm.u64 = 0; 1161 mix_irhwm.s.irhwm = 0; 1162 cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); 1163 1164 /* Interrupt when we have 1 or more packets to clean. */ 1165 mix_orhwm.u64 = 0; 1166 mix_orhwm.s.orhwm = 0; 1167 cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); 1168 1169 /* Enable receive and transmit interrupts */ 1170 mix_intena.u64 = 0; 1171 mix_intena.s.ithena = 1; 1172 mix_intena.s.othena = 1; 1173 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); 1174 1175 /* Enable packet I/O. */ 1176 1177 rxx_frm_ctl.u64 = 0; 1178 rxx_frm_ctl.s.ptp_mode = p->has_rx_tstamp ? 1 : 0; 1179 rxx_frm_ctl.s.pre_align = 1; 1180 /* When set, disables the length check for non-min sized pkts 1181 * with padding in the client data. 1182 */ 1183 rxx_frm_ctl.s.pad_len = 1; 1184 /* When set, disables the length check for VLAN pkts */ 1185 rxx_frm_ctl.s.vlan_len = 1; 1186 /* When set, PREAMBLE checking is less strict */ 1187 rxx_frm_ctl.s.pre_free = 1; 1188 /* Control Pause Frames can match station SMAC */ 1189 rxx_frm_ctl.s.ctl_smac = 0; 1190 /* Control Pause Frames can match globally assign Multicast address */ 1191 rxx_frm_ctl.s.ctl_mcst = 1; 1192 /* Forward pause information to TX block */ 1193 rxx_frm_ctl.s.ctl_bck = 1; 1194 /* Drop Control Pause Frames */ 1195 rxx_frm_ctl.s.ctl_drp = 1; 1196 /* Strip off the preamble */ 1197 rxx_frm_ctl.s.pre_strp = 1; 1198 /* This port is configured to send PREAMBLE+SFD to begin every 1199 * frame. GMX checks that the PREAMBLE is sent correctly. 1200 */ 1201 rxx_frm_ctl.s.pre_chk = 1; 1202 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); 1203 1204 /* Configure the port duplex, speed and enables */ 1205 octeon_mgmt_disable_link(p); 1206 if (netdev->phydev) 1207 octeon_mgmt_update_link(p); 1208 octeon_mgmt_enable_link(p); 1209 1210 p->last_link = 0; 1211 p->last_speed = 0; 1212 /* PHY is not present in simulator. The carrier is enabled 1213 * while initializing the phy for simulator, leave it enabled. 1214 */ 1215 if (netdev->phydev) { 1216 netif_carrier_off(netdev); 1217 phy_start_aneg(netdev->phydev); 1218 } 1219 1220 netif_wake_queue(netdev); 1221 napi_enable(&p->napi); 1222 1223 return 0; 1224 err_noirq: 1225 octeon_mgmt_reset_hw(p); 1226 dma_unmap_single(p->dev, p->rx_ring_handle, 1227 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 1228 DMA_BIDIRECTIONAL); 1229 kfree(p->rx_ring); 1230 err_nomem: 1231 dma_unmap_single(p->dev, p->tx_ring_handle, 1232 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 1233 DMA_BIDIRECTIONAL); 1234 kfree(p->tx_ring); 1235 return -ENOMEM; 1236 } 1237 1238 static int octeon_mgmt_stop(struct net_device *netdev) 1239 { 1240 struct octeon_mgmt *p = netdev_priv(netdev); 1241 1242 napi_disable(&p->napi); 1243 netif_stop_queue(netdev); 1244 1245 if (netdev->phydev) 1246 phy_disconnect(netdev->phydev); 1247 1248 netif_carrier_off(netdev); 1249 1250 octeon_mgmt_reset_hw(p); 1251 1252 free_irq(p->irq, netdev); 1253 1254 /* dma_unmap is a nop on Octeon, so just free everything. */ 1255 skb_queue_purge(&p->tx_list); 1256 skb_queue_purge(&p->rx_list); 1257 1258 dma_unmap_single(p->dev, p->rx_ring_handle, 1259 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE), 1260 DMA_BIDIRECTIONAL); 1261 kfree(p->rx_ring); 1262 1263 dma_unmap_single(p->dev, p->tx_ring_handle, 1264 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 1265 DMA_BIDIRECTIONAL); 1266 kfree(p->tx_ring); 1267 1268 return 0; 1269 } 1270 1271 static netdev_tx_t 1272 octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) 1273 { 1274 struct octeon_mgmt *p = netdev_priv(netdev); 1275 union mgmt_port_ring_entry re; 1276 unsigned long flags; 1277 netdev_tx_t rv = NETDEV_TX_BUSY; 1278 1279 re.d64 = 0; 1280 re.s.tstamp = ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) != 0); 1281 re.s.len = skb->len; 1282 re.s.addr = dma_map_single(p->dev, skb->data, 1283 skb->len, 1284 DMA_TO_DEVICE); 1285 1286 spin_lock_irqsave(&p->tx_list.lock, flags); 1287 1288 if (unlikely(p->tx_current_fill >= ring_max_fill(OCTEON_MGMT_TX_RING_SIZE) - 1)) { 1289 spin_unlock_irqrestore(&p->tx_list.lock, flags); 1290 netif_stop_queue(netdev); 1291 spin_lock_irqsave(&p->tx_list.lock, flags); 1292 } 1293 1294 if (unlikely(p->tx_current_fill >= 1295 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) { 1296 spin_unlock_irqrestore(&p->tx_list.lock, flags); 1297 dma_unmap_single(p->dev, re.s.addr, re.s.len, 1298 DMA_TO_DEVICE); 1299 goto out; 1300 } 1301 1302 __skb_queue_tail(&p->tx_list, skb); 1303 1304 /* Put it in the ring. */ 1305 p->tx_ring[p->tx_next] = re.d64; 1306 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE; 1307 p->tx_current_fill++; 1308 1309 spin_unlock_irqrestore(&p->tx_list.lock, flags); 1310 1311 dma_sync_single_for_device(p->dev, p->tx_ring_handle, 1312 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE), 1313 DMA_BIDIRECTIONAL); 1314 1315 netdev->stats.tx_packets++; 1316 netdev->stats.tx_bytes += skb->len; 1317 1318 /* Ring the bell. */ 1319 cvmx_write_csr(p->mix + MIX_ORING2, 1); 1320 1321 netif_trans_update(netdev); 1322 rv = NETDEV_TX_OK; 1323 out: 1324 octeon_mgmt_update_tx_stats(netdev); 1325 return rv; 1326 } 1327 1328 #ifdef CONFIG_NET_POLL_CONTROLLER 1329 static void octeon_mgmt_poll_controller(struct net_device *netdev) 1330 { 1331 struct octeon_mgmt *p = netdev_priv(netdev); 1332 1333 octeon_mgmt_receive_packets(p, 16); 1334 octeon_mgmt_update_rx_stats(netdev); 1335 } 1336 #endif 1337 1338 static void octeon_mgmt_get_drvinfo(struct net_device *netdev, 1339 struct ethtool_drvinfo *info) 1340 { 1341 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1342 } 1343 1344 static int octeon_mgmt_nway_reset(struct net_device *dev) 1345 { 1346 if (!capable(CAP_NET_ADMIN)) 1347 return -EPERM; 1348 1349 if (dev->phydev) 1350 return phy_start_aneg(dev->phydev); 1351 1352 return -EOPNOTSUPP; 1353 } 1354 1355 static const struct ethtool_ops octeon_mgmt_ethtool_ops = { 1356 .get_drvinfo = octeon_mgmt_get_drvinfo, 1357 .nway_reset = octeon_mgmt_nway_reset, 1358 .get_link = ethtool_op_get_link, 1359 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1360 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1361 }; 1362 1363 static const struct net_device_ops octeon_mgmt_ops = { 1364 .ndo_open = octeon_mgmt_open, 1365 .ndo_stop = octeon_mgmt_stop, 1366 .ndo_start_xmit = octeon_mgmt_xmit, 1367 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering, 1368 .ndo_set_mac_address = octeon_mgmt_set_mac_address, 1369 .ndo_do_ioctl = octeon_mgmt_ioctl, 1370 .ndo_change_mtu = octeon_mgmt_change_mtu, 1371 #ifdef CONFIG_NET_POLL_CONTROLLER 1372 .ndo_poll_controller = octeon_mgmt_poll_controller, 1373 #endif 1374 }; 1375 1376 static int octeon_mgmt_probe(struct platform_device *pdev) 1377 { 1378 struct net_device *netdev; 1379 struct octeon_mgmt *p; 1380 const __be32 *data; 1381 const u8 *mac; 1382 struct resource *res_mix; 1383 struct resource *res_agl; 1384 struct resource *res_agl_prt_ctl; 1385 int len; 1386 int result; 1387 1388 netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); 1389 if (netdev == NULL) 1390 return -ENOMEM; 1391 1392 SET_NETDEV_DEV(netdev, &pdev->dev); 1393 1394 platform_set_drvdata(pdev, netdev); 1395 p = netdev_priv(netdev); 1396 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll, 1397 OCTEON_MGMT_NAPI_WEIGHT); 1398 1399 p->netdev = netdev; 1400 p->dev = &pdev->dev; 1401 p->has_rx_tstamp = false; 1402 1403 data = of_get_property(pdev->dev.of_node, "cell-index", &len); 1404 if (data && len == sizeof(*data)) { 1405 p->port = be32_to_cpup(data); 1406 } else { 1407 dev_err(&pdev->dev, "no 'cell-index' property\n"); 1408 result = -ENXIO; 1409 goto err; 1410 } 1411 1412 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); 1413 1414 result = platform_get_irq(pdev, 0); 1415 if (result < 0) 1416 goto err; 1417 1418 p->irq = result; 1419 1420 res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1421 if (res_mix == NULL) { 1422 dev_err(&pdev->dev, "no 'reg' resource\n"); 1423 result = -ENXIO; 1424 goto err; 1425 } 1426 1427 res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1428 if (res_agl == NULL) { 1429 dev_err(&pdev->dev, "no 'reg' resource\n"); 1430 result = -ENXIO; 1431 goto err; 1432 } 1433 1434 res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1435 if (res_agl_prt_ctl == NULL) { 1436 dev_err(&pdev->dev, "no 'reg' resource\n"); 1437 result = -ENXIO; 1438 goto err; 1439 } 1440 1441 p->mix_phys = res_mix->start; 1442 p->mix_size = resource_size(res_mix); 1443 p->agl_phys = res_agl->start; 1444 p->agl_size = resource_size(res_agl); 1445 p->agl_prt_ctl_phys = res_agl_prt_ctl->start; 1446 p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl); 1447 1448 1449 if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, 1450 res_mix->name)) { 1451 dev_err(&pdev->dev, "request_mem_region (%s) failed\n", 1452 res_mix->name); 1453 result = -ENXIO; 1454 goto err; 1455 } 1456 1457 if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size, 1458 res_agl->name)) { 1459 result = -ENXIO; 1460 dev_err(&pdev->dev, "request_mem_region (%s) failed\n", 1461 res_agl->name); 1462 goto err; 1463 } 1464 1465 if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys, 1466 p->agl_prt_ctl_size, res_agl_prt_ctl->name)) { 1467 result = -ENXIO; 1468 dev_err(&pdev->dev, "request_mem_region (%s) failed\n", 1469 res_agl_prt_ctl->name); 1470 goto err; 1471 } 1472 1473 p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); 1474 p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); 1475 p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys, 1476 p->agl_prt_ctl_size); 1477 if (!p->mix || !p->agl || !p->agl_prt_ctl) { 1478 dev_err(&pdev->dev, "failed to map I/O memory\n"); 1479 result = -ENOMEM; 1480 goto err; 1481 } 1482 1483 spin_lock_init(&p->lock); 1484 1485 skb_queue_head_init(&p->tx_list); 1486 skb_queue_head_init(&p->rx_list); 1487 tasklet_init(&p->tx_clean_tasklet, 1488 octeon_mgmt_clean_tx_tasklet, (unsigned long)p); 1489 1490 netdev->priv_flags |= IFF_UNICAST_FLT; 1491 1492 netdev->netdev_ops = &octeon_mgmt_ops; 1493 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; 1494 1495 netdev->min_mtu = 64 - OCTEON_MGMT_RX_HEADROOM; 1496 netdev->max_mtu = 16383 - OCTEON_MGMT_RX_HEADROOM - VLAN_HLEN; 1497 1498 mac = of_get_mac_address(pdev->dev.of_node); 1499 1500 if (!IS_ERR(mac)) 1501 ether_addr_copy(netdev->dev_addr, mac); 1502 else 1503 eth_hw_addr_random(netdev); 1504 1505 p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1506 1507 result = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1508 if (result) 1509 goto err; 1510 1511 netif_carrier_off(netdev); 1512 result = register_netdev(netdev); 1513 if (result) 1514 goto err; 1515 1516 return 0; 1517 1518 err: 1519 of_node_put(p->phy_np); 1520 free_netdev(netdev); 1521 return result; 1522 } 1523 1524 static int octeon_mgmt_remove(struct platform_device *pdev) 1525 { 1526 struct net_device *netdev = platform_get_drvdata(pdev); 1527 struct octeon_mgmt *p = netdev_priv(netdev); 1528 1529 unregister_netdev(netdev); 1530 of_node_put(p->phy_np); 1531 free_netdev(netdev); 1532 return 0; 1533 } 1534 1535 static const struct of_device_id octeon_mgmt_match[] = { 1536 { 1537 .compatible = "cavium,octeon-5750-mix", 1538 }, 1539 {}, 1540 }; 1541 MODULE_DEVICE_TABLE(of, octeon_mgmt_match); 1542 1543 static struct platform_driver octeon_mgmt_driver = { 1544 .driver = { 1545 .name = "octeon_mgmt", 1546 .of_match_table = octeon_mgmt_match, 1547 }, 1548 .probe = octeon_mgmt_probe, 1549 .remove = octeon_mgmt_remove, 1550 }; 1551 1552 extern void octeon_mdiobus_force_mod_depencency(void); 1553 1554 static int __init octeon_mgmt_mod_init(void) 1555 { 1556 /* Force our mdiobus driver module to be loaded first. */ 1557 octeon_mdiobus_force_mod_depencency(); 1558 return platform_driver_register(&octeon_mgmt_driver); 1559 } 1560 1561 static void __exit octeon_mgmt_mod_exit(void) 1562 { 1563 platform_driver_unregister(&octeon_mgmt_driver); 1564 } 1565 1566 module_init(octeon_mgmt_mod_init); 1567 module_exit(octeon_mgmt_mod_exit); 1568 1569 MODULE_DESCRIPTION(DRV_DESCRIPTION); 1570 MODULE_AUTHOR("David Daney"); 1571 MODULE_LICENSE("GPL"); 1572