1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 **********************************************************************/ 19 #include <linux/pci.h> 20 #include <linux/netdevice.h> 21 #include <linux/vmalloc.h> 22 #include "liquidio_common.h" 23 #include "octeon_droq.h" 24 #include "octeon_iq.h" 25 #include "response_manager.h" 26 #include "octeon_device.h" 27 #include "octeon_main.h" 28 #include "octeon_network.h" 29 #include "cn66xx_device.h" 30 #include "cn23xx_pf_device.h" 31 #include "cn23xx_vf_device.h" 32 33 struct iq_post_status { 34 int status; 35 int index; 36 }; 37 38 static void check_db_timeout(struct work_struct *work); 39 static void __check_db_timeout(struct octeon_device *oct, u64 iq_no); 40 41 static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *); 42 43 static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no) 44 { 45 struct octeon_instr_queue *iq = 46 (struct octeon_instr_queue *)oct->instr_queue[iq_no]; 47 return iq->iqcmd_64B; 48 } 49 50 #define IQ_INSTR_MODE_32B(oct, iq_no) (!IQ_INSTR_MODE_64B(oct, iq_no)) 51 52 /* Define this to return the request status comaptible to old code */ 53 /*#define OCTEON_USE_OLD_REQ_STATUS*/ 54 55 /* Return 0 on success, 1 on failure */ 56 int octeon_init_instr_queue(struct octeon_device *oct, 57 union oct_txpciq txpciq, 58 u32 num_descs) 59 { 60 struct octeon_instr_queue *iq; 61 struct octeon_iq_config *conf = NULL; 62 u32 iq_no = (u32)txpciq.s.q_no; 63 u32 q_size; 64 struct cavium_wq *db_wq; 65 int numa_node = dev_to_node(&oct->pci_dev->dev); 66 67 if (OCTEON_CN6XXX(oct)) 68 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx))); 69 else if (OCTEON_CN23XX_PF(oct)) 70 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf))); 71 else if (OCTEON_CN23XX_VF(oct)) 72 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_vf))); 73 74 if (!conf) { 75 dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n", 76 oct->chip_id); 77 return 1; 78 } 79 80 q_size = (u32)conf->instr_type * num_descs; 81 82 iq = oct->instr_queue[iq_no]; 83 84 iq->oct_dev = oct; 85 86 iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma); 87 if (!iq->base_addr) { 88 dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n", 89 iq_no); 90 return 1; 91 } 92 93 iq->max_count = num_descs; 94 95 /* Initialize a list to holds requests that have been posted to Octeon 96 * but has yet to be fetched by octeon 97 */ 98 iq->request_list = vmalloc_node((sizeof(*iq->request_list) * num_descs), 99 numa_node); 100 if (!iq->request_list) 101 iq->request_list = 102 vmalloc(array_size(num_descs, 103 sizeof(*iq->request_list))); 104 if (!iq->request_list) { 105 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma); 106 dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n", 107 iq_no); 108 return 1; 109 } 110 111 memset(iq->request_list, 0, sizeof(*iq->request_list) * num_descs); 112 113 dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %pad count: %d\n", 114 iq_no, iq->base_addr, &iq->base_addr_dma, iq->max_count); 115 116 iq->txpciq.u64 = txpciq.u64; 117 iq->fill_threshold = (u32)conf->db_min; 118 iq->fill_cnt = 0; 119 iq->host_write_index = 0; 120 iq->octeon_read_index = 0; 121 iq->flush_index = 0; 122 iq->last_db_time = 0; 123 iq->do_auto_flush = 1; 124 iq->db_timeout = (u32)conf->db_timeout; 125 atomic_set(&iq->instr_pending, 0); 126 iq->pkts_processed = 0; 127 128 /* Initialize the spinlock for this instruction queue */ 129 spin_lock_init(&iq->lock); 130 if (iq_no == 0) { 131 iq->allow_soft_cmds = true; 132 spin_lock_init(&iq->post_lock); 133 } else { 134 iq->allow_soft_cmds = false; 135 } 136 137 spin_lock_init(&iq->iq_flush_running_lock); 138 139 oct->io_qmask.iq |= BIT_ULL(iq_no); 140 141 /* Set the 32B/64B mode for each input queue */ 142 oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no); 143 iq->iqcmd_64B = (conf->instr_type == 64); 144 145 oct->fn_list.setup_iq_regs(oct, iq_no); 146 147 oct->check_db_wq[iq_no].wq = alloc_workqueue("check_iq_db", 148 WQ_MEM_RECLAIM, 149 0); 150 if (!oct->check_db_wq[iq_no].wq) { 151 vfree(iq->request_list); 152 iq->request_list = NULL; 153 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma); 154 dev_err(&oct->pci_dev->dev, "check db wq create failed for iq %d\n", 155 iq_no); 156 return 1; 157 } 158 159 db_wq = &oct->check_db_wq[iq_no]; 160 161 INIT_DELAYED_WORK(&db_wq->wk.work, check_db_timeout); 162 db_wq->wk.ctxptr = oct; 163 db_wq->wk.ctxul = iq_no; 164 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1)); 165 166 return 0; 167 } 168 169 int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no) 170 { 171 u64 desc_size = 0, q_size; 172 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; 173 174 cancel_delayed_work_sync(&oct->check_db_wq[iq_no].wk.work); 175 destroy_workqueue(oct->check_db_wq[iq_no].wq); 176 177 if (OCTEON_CN6XXX(oct)) 178 desc_size = 179 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn6xxx)); 180 else if (OCTEON_CN23XX_PF(oct)) 181 desc_size = 182 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf)); 183 else if (OCTEON_CN23XX_VF(oct)) 184 desc_size = 185 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_vf)); 186 187 vfree(iq->request_list); 188 189 if (iq->base_addr) { 190 q_size = iq->max_count * desc_size; 191 lio_dma_free(oct, (u32)q_size, iq->base_addr, 192 iq->base_addr_dma); 193 oct->io_qmask.iq &= ~(1ULL << iq_no); 194 vfree(oct->instr_queue[iq_no]); 195 oct->instr_queue[iq_no] = NULL; 196 oct->num_iqs--; 197 return 0; 198 } 199 return 1; 200 } 201 202 /* Return 0 on success, 1 on failure */ 203 int octeon_setup_iq(struct octeon_device *oct, 204 int ifidx, 205 int q_index, 206 union oct_txpciq txpciq, 207 u32 num_descs, 208 void *app_ctx) 209 { 210 u32 iq_no = (u32)txpciq.s.q_no; 211 int numa_node = dev_to_node(&oct->pci_dev->dev); 212 213 if (oct->instr_queue[iq_no]) { 214 dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n", 215 iq_no); 216 oct->instr_queue[iq_no]->txpciq.u64 = txpciq.u64; 217 oct->instr_queue[iq_no]->app_ctx = app_ctx; 218 return 0; 219 } 220 oct->instr_queue[iq_no] = 221 vzalloc_node(sizeof(struct octeon_instr_queue), numa_node); 222 if (!oct->instr_queue[iq_no]) 223 oct->instr_queue[iq_no] = 224 vzalloc(sizeof(struct octeon_instr_queue)); 225 if (!oct->instr_queue[iq_no]) 226 return 1; 227 228 229 oct->instr_queue[iq_no]->q_index = q_index; 230 oct->instr_queue[iq_no]->app_ctx = app_ctx; 231 oct->instr_queue[iq_no]->ifidx = ifidx; 232 233 if (octeon_init_instr_queue(oct, txpciq, num_descs)) { 234 vfree(oct->instr_queue[iq_no]); 235 oct->instr_queue[iq_no] = NULL; 236 return 1; 237 } 238 239 oct->num_iqs++; 240 if (oct->fn_list.enable_io_queues(oct)) 241 return 1; 242 243 return 0; 244 } 245 246 int lio_wait_for_instr_fetch(struct octeon_device *oct) 247 { 248 int i, retry = 1000, pending, instr_cnt = 0; 249 250 do { 251 instr_cnt = 0; 252 253 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 254 if (!(oct->io_qmask.iq & BIT_ULL(i))) 255 continue; 256 pending = 257 atomic_read(&oct->instr_queue[i]->instr_pending); 258 if (pending) 259 __check_db_timeout(oct, i); 260 instr_cnt += pending; 261 } 262 263 if (instr_cnt == 0) 264 break; 265 266 schedule_timeout_uninterruptible(1); 267 268 } while (retry-- && instr_cnt); 269 270 return instr_cnt; 271 } 272 273 static inline void 274 ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq) 275 { 276 if (atomic_read(&oct->status) == OCT_DEV_RUNNING) { 277 writel(iq->fill_cnt, iq->doorbell_reg); 278 /* make sure doorbell write goes through */ 279 iq->fill_cnt = 0; 280 iq->last_db_time = jiffies; 281 return; 282 } 283 } 284 285 void 286 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no) 287 { 288 struct octeon_instr_queue *iq; 289 290 iq = oct->instr_queue[iq_no]; 291 spin_lock(&iq->post_lock); 292 if (iq->fill_cnt) 293 ring_doorbell(oct, iq); 294 spin_unlock(&iq->post_lock); 295 } 296 297 static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq, 298 u8 *cmd) 299 { 300 u8 *iqptr, cmdsize; 301 302 cmdsize = ((iq->iqcmd_64B) ? 64 : 32); 303 iqptr = iq->base_addr + (cmdsize * iq->host_write_index); 304 305 memcpy(iqptr, cmd, cmdsize); 306 } 307 308 static inline struct iq_post_status 309 __post_command2(struct octeon_instr_queue *iq, u8 *cmd) 310 { 311 struct iq_post_status st; 312 313 st.status = IQ_SEND_OK; 314 315 /* This ensures that the read index does not wrap around to the same 316 * position if queue gets full before Octeon could fetch any instr. 317 */ 318 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1)) { 319 st.status = IQ_SEND_FAILED; 320 st.index = -1; 321 return st; 322 } 323 324 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 2)) 325 st.status = IQ_SEND_STOP; 326 327 __copy_cmd_into_iq(iq, cmd); 328 329 /* "index" is returned, host_write_index is modified. */ 330 st.index = iq->host_write_index; 331 iq->host_write_index = incr_index(iq->host_write_index, 1, 332 iq->max_count); 333 iq->fill_cnt++; 334 335 /* Flush the command into memory. We need to be sure the data is in 336 * memory before indicating that the instruction is pending. 337 */ 338 wmb(); 339 340 atomic_inc(&iq->instr_pending); 341 342 return st; 343 } 344 345 int 346 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 347 void (*fn)(void *)) 348 { 349 if (reqtype > REQTYPE_LAST) { 350 dev_err(&oct->pci_dev->dev, "%s: Invalid reqtype: %d\n", 351 __func__, reqtype); 352 return -EINVAL; 353 } 354 355 reqtype_free_fn[oct->octeon_id][reqtype] = fn; 356 357 return 0; 358 } 359 360 static inline void 361 __add_to_request_list(struct octeon_instr_queue *iq, 362 int idx, void *buf, int reqtype) 363 { 364 iq->request_list[idx].buf = buf; 365 iq->request_list[idx].reqtype = reqtype; 366 } 367 368 /* Can only run in process context */ 369 int 370 lio_process_iq_request_list(struct octeon_device *oct, 371 struct octeon_instr_queue *iq, u32 napi_budget) 372 { 373 struct cavium_wq *cwq = &oct->dma_comp_wq; 374 int reqtype; 375 void *buf; 376 u32 old = iq->flush_index; 377 u32 inst_count = 0; 378 unsigned int pkts_compl = 0, bytes_compl = 0; 379 struct octeon_soft_command *sc; 380 unsigned long flags; 381 382 while (old != iq->octeon_read_index) { 383 reqtype = iq->request_list[old].reqtype; 384 buf = iq->request_list[old].buf; 385 386 if (reqtype == REQTYPE_NONE) 387 goto skip_this; 388 389 octeon_update_tx_completion_counters(buf, reqtype, &pkts_compl, 390 &bytes_compl); 391 392 switch (reqtype) { 393 case REQTYPE_NORESP_NET: 394 case REQTYPE_NORESP_NET_SG: 395 case REQTYPE_RESP_NET_SG: 396 reqtype_free_fn[oct->octeon_id][reqtype](buf); 397 break; 398 case REQTYPE_RESP_NET: 399 case REQTYPE_SOFT_COMMAND: 400 sc = buf; 401 /* We're expecting a response from Octeon. 402 * It's up to lio_process_ordered_list() to 403 * process sc. Add sc to the ordered soft 404 * command response list because we expect 405 * a response from Octeon. 406 */ 407 spin_lock_irqsave(&oct->response_list 408 [OCTEON_ORDERED_SC_LIST].lock, flags); 409 atomic_inc(&oct->response_list 410 [OCTEON_ORDERED_SC_LIST].pending_req_count); 411 list_add_tail(&sc->node, &oct->response_list 412 [OCTEON_ORDERED_SC_LIST].head); 413 spin_unlock_irqrestore(&oct->response_list 414 [OCTEON_ORDERED_SC_LIST].lock, 415 flags); 416 break; 417 default: 418 dev_err(&oct->pci_dev->dev, 419 "%s Unknown reqtype: %d buf: %p at idx %d\n", 420 __func__, reqtype, buf, old); 421 } 422 423 iq->request_list[old].buf = NULL; 424 iq->request_list[old].reqtype = 0; 425 426 skip_this: 427 inst_count++; 428 old = incr_index(old, 1, iq->max_count); 429 430 if ((napi_budget) && (inst_count >= napi_budget)) 431 break; 432 } 433 if (bytes_compl) 434 octeon_report_tx_completion_to_bql(iq->app_ctx, pkts_compl, 435 bytes_compl); 436 iq->flush_index = old; 437 438 if (atomic_read(&oct->response_list 439 [OCTEON_ORDERED_SC_LIST].pending_req_count)) 440 queue_work(cwq->wq, &cwq->wk.work.work); 441 442 return inst_count; 443 } 444 445 /* Can only be called from process context */ 446 int 447 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, 448 u32 napi_budget) 449 { 450 u32 inst_processed = 0; 451 u32 tot_inst_processed = 0; 452 int tx_done = 1; 453 454 if (!spin_trylock(&iq->iq_flush_running_lock)) 455 return tx_done; 456 457 spin_lock_bh(&iq->lock); 458 459 iq->octeon_read_index = oct->fn_list.update_iq_read_idx(iq); 460 461 do { 462 /* Process any outstanding IQ packets. */ 463 if (iq->flush_index == iq->octeon_read_index) 464 break; 465 466 if (napi_budget) 467 inst_processed = 468 lio_process_iq_request_list(oct, iq, 469 napi_budget - 470 tot_inst_processed); 471 else 472 inst_processed = 473 lio_process_iq_request_list(oct, iq, 0); 474 475 if (inst_processed) { 476 iq->pkts_processed += inst_processed; 477 atomic_sub(inst_processed, &iq->instr_pending); 478 iq->stats.instr_processed += inst_processed; 479 } 480 481 tot_inst_processed += inst_processed; 482 } while (tot_inst_processed < napi_budget); 483 484 if (napi_budget && (tot_inst_processed >= napi_budget)) 485 tx_done = 0; 486 487 iq->last_db_time = jiffies; 488 489 spin_unlock_bh(&iq->lock); 490 491 spin_unlock(&iq->iq_flush_running_lock); 492 493 return tx_done; 494 } 495 496 /* Process instruction queue after timeout. 497 * This routine gets called from a workqueue or when removing the module. 498 */ 499 static void __check_db_timeout(struct octeon_device *oct, u64 iq_no) 500 { 501 struct octeon_instr_queue *iq; 502 u64 next_time; 503 504 if (!oct) 505 return; 506 507 iq = oct->instr_queue[iq_no]; 508 if (!iq) 509 return; 510 511 /* return immediately, if no work pending */ 512 if (!atomic_read(&iq->instr_pending)) 513 return; 514 /* If jiffies - last_db_time < db_timeout do nothing */ 515 next_time = iq->last_db_time + iq->db_timeout; 516 if (!time_after(jiffies, (unsigned long)next_time)) 517 return; 518 iq->last_db_time = jiffies; 519 520 /* Flush the instruction queue */ 521 octeon_flush_iq(oct, iq, 0); 522 523 lio_enable_irq(NULL, iq); 524 } 525 526 /* Called by the Poll thread at regular intervals to check the instruction 527 * queue for commands to be posted and for commands that were fetched by Octeon. 528 */ 529 static void check_db_timeout(struct work_struct *work) 530 { 531 struct cavium_wk *wk = (struct cavium_wk *)work; 532 struct octeon_device *oct = (struct octeon_device *)wk->ctxptr; 533 u64 iq_no = wk->ctxul; 534 struct cavium_wq *db_wq = &oct->check_db_wq[iq_no]; 535 u32 delay = 10; 536 537 __check_db_timeout(oct, iq_no); 538 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(delay)); 539 } 540 541 int 542 octeon_send_command(struct octeon_device *oct, u32 iq_no, 543 u32 force_db, void *cmd, void *buf, 544 u32 datasize, u32 reqtype) 545 { 546 int xmit_stopped; 547 struct iq_post_status st; 548 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; 549 550 /* Get the lock and prevent other tasks and tx interrupt handler from 551 * running. 552 */ 553 if (iq->allow_soft_cmds) 554 spin_lock_bh(&iq->post_lock); 555 556 st = __post_command2(iq, cmd); 557 558 if (st.status != IQ_SEND_FAILED) { 559 xmit_stopped = octeon_report_sent_bytes_to_bql(buf, reqtype); 560 __add_to_request_list(iq, st.index, buf, reqtype); 561 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize); 562 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1); 563 564 if (iq->fill_cnt >= MAX_OCTEON_FILL_COUNT || force_db || 565 xmit_stopped || st.status == IQ_SEND_STOP) 566 ring_doorbell(oct, iq); 567 } else { 568 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1); 569 } 570 571 if (iq->allow_soft_cmds) 572 spin_unlock_bh(&iq->post_lock); 573 574 /* This is only done here to expedite packets being flushed 575 * for cases where there are no IQ completion interrupts. 576 */ 577 578 return st.status; 579 } 580 581 void 582 octeon_prepare_soft_command(struct octeon_device *oct, 583 struct octeon_soft_command *sc, 584 u8 opcode, 585 u8 subcode, 586 u32 irh_ossp, 587 u64 ossp0, 588 u64 ossp1) 589 { 590 struct octeon_config *oct_cfg; 591 struct octeon_instr_ih2 *ih2; 592 struct octeon_instr_ih3 *ih3; 593 struct octeon_instr_pki_ih3 *pki_ih3; 594 struct octeon_instr_irh *irh; 595 struct octeon_instr_rdp *rdp; 596 597 WARN_ON(opcode > 15); 598 WARN_ON(subcode > 127); 599 600 oct_cfg = octeon_get_conf(oct); 601 602 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) { 603 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3; 604 605 ih3->pkind = oct->instr_queue[sc->iq_no]->txpciq.s.pkind; 606 607 pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3; 608 609 pki_ih3->w = 1; 610 pki_ih3->raw = 1; 611 pki_ih3->utag = 1; 612 pki_ih3->uqpg = 613 oct->instr_queue[sc->iq_no]->txpciq.s.use_qpg; 614 pki_ih3->utt = 1; 615 pki_ih3->tag = LIO_CONTROL; 616 pki_ih3->tagtype = ATOMIC_TAG; 617 pki_ih3->qpg = 618 oct->instr_queue[sc->iq_no]->txpciq.s.ctrl_qpg; 619 620 pki_ih3->pm = 0x7; 621 pki_ih3->sl = 8; 622 623 if (sc->datasize) 624 ih3->dlengsz = sc->datasize; 625 626 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh; 627 irh->opcode = opcode; 628 irh->subcode = subcode; 629 630 /* opcode/subcode specific parameters (ossp) */ 631 irh->ossp = irh_ossp; 632 sc->cmd.cmd3.ossp[0] = ossp0; 633 sc->cmd.cmd3.ossp[1] = ossp1; 634 635 if (sc->rdatasize) { 636 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp; 637 rdp->pcie_port = oct->pcie_port; 638 rdp->rlen = sc->rdatasize; 639 640 irh->rflag = 1; 641 /*PKI IH3*/ 642 /* pki_ih3 irh+ossp[0]+ossp[1]+rdp+rptr = 48 bytes */ 643 ih3->fsz = LIO_SOFTCMDRESP_IH3; 644 } else { 645 irh->rflag = 0; 646 /*PKI IH3*/ 647 /* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */ 648 ih3->fsz = LIO_PCICMD_O3; 649 } 650 651 } else { 652 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2; 653 ih2->tagtype = ATOMIC_TAG; 654 ih2->tag = LIO_CONTROL; 655 ih2->raw = 1; 656 ih2->grp = CFG_GET_CTRL_Q_GRP(oct_cfg); 657 658 if (sc->datasize) { 659 ih2->dlengsz = sc->datasize; 660 ih2->rs = 1; 661 } 662 663 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh; 664 irh->opcode = opcode; 665 irh->subcode = subcode; 666 667 /* opcode/subcode specific parameters (ossp) */ 668 irh->ossp = irh_ossp; 669 sc->cmd.cmd2.ossp[0] = ossp0; 670 sc->cmd.cmd2.ossp[1] = ossp1; 671 672 if (sc->rdatasize) { 673 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd2.rdp; 674 rdp->pcie_port = oct->pcie_port; 675 rdp->rlen = sc->rdatasize; 676 677 irh->rflag = 1; 678 /* irh+ossp[0]+ossp[1]+rdp+rptr = 40 bytes */ 679 ih2->fsz = LIO_SOFTCMDRESP_IH2; 680 } else { 681 irh->rflag = 0; 682 /* irh + ossp[0] + ossp[1] = 24 bytes */ 683 ih2->fsz = LIO_PCICMD_O2; 684 } 685 } 686 } 687 688 int octeon_send_soft_command(struct octeon_device *oct, 689 struct octeon_soft_command *sc) 690 { 691 struct octeon_instr_queue *iq; 692 struct octeon_instr_ih2 *ih2; 693 struct octeon_instr_ih3 *ih3; 694 struct octeon_instr_irh *irh; 695 u32 len; 696 697 iq = oct->instr_queue[sc->iq_no]; 698 if (!iq->allow_soft_cmds) { 699 dev_err(&oct->pci_dev->dev, "Soft commands are not allowed on Queue %d\n", 700 sc->iq_no); 701 INCR_INSTRQUEUE_PKT_COUNT(oct, sc->iq_no, instr_dropped, 1); 702 return IQ_SEND_FAILED; 703 } 704 705 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) { 706 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3; 707 if (ih3->dlengsz) { 708 WARN_ON(!sc->dmadptr); 709 sc->cmd.cmd3.dptr = sc->dmadptr; 710 } 711 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh; 712 if (irh->rflag) { 713 WARN_ON(!sc->dmarptr); 714 WARN_ON(!sc->status_word); 715 *sc->status_word = COMPLETION_WORD_INIT; 716 sc->cmd.cmd3.rptr = sc->dmarptr; 717 } 718 len = (u32)ih3->dlengsz; 719 } else { 720 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2; 721 if (ih2->dlengsz) { 722 WARN_ON(!sc->dmadptr); 723 sc->cmd.cmd2.dptr = sc->dmadptr; 724 } 725 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh; 726 if (irh->rflag) { 727 WARN_ON(!sc->dmarptr); 728 WARN_ON(!sc->status_word); 729 *sc->status_word = COMPLETION_WORD_INIT; 730 sc->cmd.cmd2.rptr = sc->dmarptr; 731 } 732 len = (u32)ih2->dlengsz; 733 } 734 735 sc->expiry_time = jiffies + msecs_to_jiffies(LIO_SC_MAX_TMO_MS); 736 737 return (octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc, 738 len, REQTYPE_SOFT_COMMAND)); 739 } 740 741 int octeon_setup_sc_buffer_pool(struct octeon_device *oct) 742 { 743 int i; 744 u64 dma_addr; 745 struct octeon_soft_command *sc; 746 747 INIT_LIST_HEAD(&oct->sc_buf_pool.head); 748 spin_lock_init(&oct->sc_buf_pool.lock); 749 atomic_set(&oct->sc_buf_pool.alloc_buf_count, 0); 750 751 for (i = 0; i < MAX_SOFT_COMMAND_BUFFERS; i++) { 752 sc = (struct octeon_soft_command *) 753 lio_dma_alloc(oct, 754 SOFT_COMMAND_BUFFER_SIZE, 755 (dma_addr_t *)&dma_addr); 756 if (!sc) { 757 octeon_free_sc_buffer_pool(oct); 758 return 1; 759 } 760 761 sc->dma_addr = dma_addr; 762 sc->size = SOFT_COMMAND_BUFFER_SIZE; 763 764 list_add_tail(&sc->node, &oct->sc_buf_pool.head); 765 } 766 767 return 0; 768 } 769 770 int octeon_free_sc_done_list(struct octeon_device *oct) 771 { 772 struct octeon_response_list *done_sc_list, *zombie_sc_list; 773 struct octeon_soft_command *sc; 774 struct list_head *tmp, *tmp2; 775 spinlock_t *sc_lists_lock; /* lock for response_list */ 776 777 done_sc_list = &oct->response_list[OCTEON_DONE_SC_LIST]; 778 zombie_sc_list = &oct->response_list[OCTEON_ZOMBIE_SC_LIST]; 779 780 if (!atomic_read(&done_sc_list->pending_req_count)) 781 return 0; 782 783 sc_lists_lock = &oct->response_list[OCTEON_ORDERED_SC_LIST].lock; 784 785 spin_lock_bh(sc_lists_lock); 786 787 list_for_each_safe(tmp, tmp2, &done_sc_list->head) { 788 sc = list_entry(tmp, struct octeon_soft_command, node); 789 790 if (READ_ONCE(sc->caller_is_done)) { 791 list_del(&sc->node); 792 atomic_dec(&done_sc_list->pending_req_count); 793 794 if (*sc->status_word == COMPLETION_WORD_INIT) { 795 /* timeout; move sc to zombie list */ 796 list_add_tail(&sc->node, &zombie_sc_list->head); 797 atomic_inc(&zombie_sc_list->pending_req_count); 798 } else { 799 octeon_free_soft_command(oct, sc); 800 } 801 } 802 } 803 804 spin_unlock_bh(sc_lists_lock); 805 806 return 0; 807 } 808 809 int octeon_free_sc_zombie_list(struct octeon_device *oct) 810 { 811 struct octeon_response_list *zombie_sc_list; 812 struct octeon_soft_command *sc; 813 struct list_head *tmp, *tmp2; 814 spinlock_t *sc_lists_lock; /* lock for response_list */ 815 816 zombie_sc_list = &oct->response_list[OCTEON_ZOMBIE_SC_LIST]; 817 sc_lists_lock = &oct->response_list[OCTEON_ORDERED_SC_LIST].lock; 818 819 spin_lock_bh(sc_lists_lock); 820 821 list_for_each_safe(tmp, tmp2, &zombie_sc_list->head) { 822 list_del(tmp); 823 atomic_dec(&zombie_sc_list->pending_req_count); 824 sc = list_entry(tmp, struct octeon_soft_command, node); 825 octeon_free_soft_command(oct, sc); 826 } 827 828 spin_unlock_bh(sc_lists_lock); 829 830 return 0; 831 } 832 833 int octeon_free_sc_buffer_pool(struct octeon_device *oct) 834 { 835 struct list_head *tmp, *tmp2; 836 struct octeon_soft_command *sc; 837 838 octeon_free_sc_zombie_list(oct); 839 840 spin_lock_bh(&oct->sc_buf_pool.lock); 841 842 list_for_each_safe(tmp, tmp2, &oct->sc_buf_pool.head) { 843 list_del(tmp); 844 845 sc = (struct octeon_soft_command *)tmp; 846 847 lio_dma_free(oct, sc->size, sc, sc->dma_addr); 848 } 849 850 INIT_LIST_HEAD(&oct->sc_buf_pool.head); 851 852 spin_unlock_bh(&oct->sc_buf_pool.lock); 853 854 return 0; 855 } 856 857 struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct, 858 u32 datasize, 859 u32 rdatasize, 860 u32 ctxsize) 861 { 862 u64 dma_addr; 863 u32 size; 864 u32 offset = sizeof(struct octeon_soft_command); 865 struct octeon_soft_command *sc = NULL; 866 struct list_head *tmp; 867 868 if (!rdatasize) 869 rdatasize = 16; 870 871 WARN_ON((offset + datasize + rdatasize + ctxsize) > 872 SOFT_COMMAND_BUFFER_SIZE); 873 874 spin_lock_bh(&oct->sc_buf_pool.lock); 875 876 if (list_empty(&oct->sc_buf_pool.head)) { 877 spin_unlock_bh(&oct->sc_buf_pool.lock); 878 return NULL; 879 } 880 881 list_for_each(tmp, &oct->sc_buf_pool.head) 882 break; 883 884 list_del(tmp); 885 886 atomic_inc(&oct->sc_buf_pool.alloc_buf_count); 887 888 spin_unlock_bh(&oct->sc_buf_pool.lock); 889 890 sc = (struct octeon_soft_command *)tmp; 891 892 dma_addr = sc->dma_addr; 893 size = sc->size; 894 895 memset(sc, 0, sc->size); 896 897 sc->dma_addr = dma_addr; 898 sc->size = size; 899 900 if (ctxsize) { 901 sc->ctxptr = (u8 *)sc + offset; 902 sc->ctxsize = ctxsize; 903 } 904 905 /* Start data at 128 byte boundary */ 906 offset = (offset + ctxsize + 127) & 0xffffff80; 907 908 if (datasize) { 909 sc->virtdptr = (u8 *)sc + offset; 910 sc->dmadptr = dma_addr + offset; 911 sc->datasize = datasize; 912 } 913 914 /* Start rdata at 128 byte boundary */ 915 offset = (offset + datasize + 127) & 0xffffff80; 916 917 if (rdatasize) { 918 WARN_ON(rdatasize < 16); 919 sc->virtrptr = (u8 *)sc + offset; 920 sc->dmarptr = dma_addr + offset; 921 sc->rdatasize = rdatasize; 922 sc->status_word = (u64 *)((u8 *)(sc->virtrptr) + rdatasize - 8); 923 } 924 925 return sc; 926 } 927 928 void octeon_free_soft_command(struct octeon_device *oct, 929 struct octeon_soft_command *sc) 930 { 931 spin_lock_bh(&oct->sc_buf_pool.lock); 932 933 list_add_tail(&sc->node, &oct->sc_buf_pool.head); 934 935 atomic_dec(&oct->sc_buf_pool.alloc_buf_count); 936 937 spin_unlock_bh(&oct->sc_buf_pool.lock); 938 } 939