1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 23 /*! \file octeon_mem_ops.h 24 * \brief Host Driver: Routines used to read/write Octeon memory. 25 */ 26 27 #ifndef __OCTEON_MEM_OPS_H__ 28 #define __OCTEON_MEM_OPS_H__ 29 30 /** Read a 64-bit value from a BAR1 mapped core memory address. 31 * @param oct - pointer to the octeon device. 32 * @param core_addr - the address to read from. 33 * 34 * The range_idx gives the BAR1 index register for the range of address 35 * in which core_addr is mapped. 36 * 37 * @return 64-bit value read from Core memory 38 */ 39 u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr); 40 41 /** Read a 32-bit value from a BAR1 mapped core memory address. 42 * @param oct - pointer to the octeon device. 43 * @param core_addr - the address to read from. 44 * 45 * @return 32-bit value read from Core memory 46 */ 47 u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr); 48 49 /** Write a 32-bit value to a BAR1 mapped core memory address. 50 * @param oct - pointer to the octeon device. 51 * @param core_addr - the address to write to. 52 * @param val - 32-bit value to write. 53 */ 54 void 55 octeon_write_device_mem32(struct octeon_device *oct, 56 u64 core_addr, 57 u32 val); 58 59 /** Read multiple bytes from Octeon memory. 60 */ 61 void 62 octeon_pci_read_core_mem(struct octeon_device *oct, 63 u64 coreaddr, 64 u8 *buf, 65 u32 len); 66 67 /** Write multiple bytes into Octeon memory. 68 */ 69 void 70 octeon_pci_write_core_mem(struct octeon_device *oct, 71 u64 coreaddr, 72 u8 *buf, 73 u32 len); 74 75 #endif 76