1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 **********************************************************************/ 19 #include <linux/netdevice.h> 20 #include "liquidio_common.h" 21 #include "octeon_droq.h" 22 #include "octeon_iq.h" 23 #include "response_manager.h" 24 #include "octeon_device.h" 25 26 #define MEMOPS_IDX MAX_BAR1_MAP_INDEX 27 28 #ifdef __BIG_ENDIAN_BITFIELD 29 static inline void 30 octeon_toggle_bar1_swapmode(struct octeon_device *oct, u32 idx) 31 { 32 u32 mask; 33 34 mask = oct->fn_list.bar1_idx_read(oct, idx); 35 mask = (mask & 0x2) ? (mask & ~2) : (mask | 2); 36 oct->fn_list.bar1_idx_write(oct, idx, mask); 37 } 38 #else 39 #define octeon_toggle_bar1_swapmode(oct, idx) 40 #endif 41 42 static void 43 octeon_pci_fastwrite(struct octeon_device *oct, u8 __iomem *mapped_addr, 44 u8 *hostbuf, u32 len) 45 { 46 while ((len) && ((unsigned long)mapped_addr) & 7) { 47 writeb(*(hostbuf++), mapped_addr++); 48 len--; 49 } 50 51 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX); 52 53 while (len >= 8) { 54 writeq(*((u64 *)hostbuf), mapped_addr); 55 mapped_addr += 8; 56 hostbuf += 8; 57 len -= 8; 58 } 59 60 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX); 61 62 while (len--) 63 writeb(*(hostbuf++), mapped_addr++); 64 } 65 66 static void 67 octeon_pci_fastread(struct octeon_device *oct, u8 __iomem *mapped_addr, 68 u8 *hostbuf, u32 len) 69 { 70 while ((len) && ((unsigned long)mapped_addr) & 7) { 71 *(hostbuf++) = readb(mapped_addr++); 72 len--; 73 } 74 75 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX); 76 77 while (len >= 8) { 78 *((u64 *)hostbuf) = readq(mapped_addr); 79 mapped_addr += 8; 80 hostbuf += 8; 81 len -= 8; 82 } 83 84 octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX); 85 86 while (len--) 87 *(hostbuf++) = readb(mapped_addr++); 88 } 89 90 /* Core mem read/write with temporary bar1 settings. */ 91 /* op = 1 to read, op = 0 to write. */ 92 static void 93 __octeon_pci_rw_core_mem(struct octeon_device *oct, u64 addr, 94 u8 *hostbuf, u32 len, u32 op) 95 { 96 u32 copy_len = 0, index_reg_val = 0; 97 unsigned long flags; 98 u8 __iomem *mapped_addr; 99 100 spin_lock_irqsave(&oct->mem_access_lock, flags); 101 102 /* Save the original index reg value. */ 103 index_reg_val = oct->fn_list.bar1_idx_read(oct, MEMOPS_IDX); 104 do { 105 oct->fn_list.bar1_idx_setup(oct, addr, MEMOPS_IDX, 1); 106 mapped_addr = oct->mmio[1].hw_addr 107 + (MEMOPS_IDX << 22) + (addr & 0x3fffff); 108 109 /* If operation crosses a 4MB boundary, split the transfer 110 * at the 4MB 111 * boundary. 112 */ 113 if (((addr + len - 1) & ~(0x3fffff)) != (addr & ~(0x3fffff))) { 114 copy_len = (u32)(((addr & ~(0x3fffff)) + 115 (MEMOPS_IDX << 22)) - addr); 116 } else { 117 copy_len = len; 118 } 119 120 if (op) { /* read from core */ 121 octeon_pci_fastread(oct, mapped_addr, hostbuf, 122 copy_len); 123 } else { 124 octeon_pci_fastwrite(oct, mapped_addr, hostbuf, 125 copy_len); 126 } 127 128 len -= copy_len; 129 addr += copy_len; 130 hostbuf += copy_len; 131 132 } while (len); 133 134 oct->fn_list.bar1_idx_write(oct, MEMOPS_IDX, index_reg_val); 135 136 spin_unlock_irqrestore(&oct->mem_access_lock, flags); 137 } 138 139 void 140 octeon_pci_read_core_mem(struct octeon_device *oct, 141 u64 coreaddr, 142 u8 *buf, 143 u32 len) 144 { 145 __octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 1); 146 } 147 148 void 149 octeon_pci_write_core_mem(struct octeon_device *oct, 150 u64 coreaddr, 151 u8 *buf, 152 u32 len) 153 { 154 __octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 0); 155 } 156 157 u64 octeon_read_device_mem64(struct octeon_device *oct, u64 coreaddr) 158 { 159 __be64 ret; 160 161 __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 8, 1); 162 163 return be64_to_cpu(ret); 164 } 165 166 u32 octeon_read_device_mem32(struct octeon_device *oct, u64 coreaddr) 167 { 168 __be32 ret; 169 170 __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 4, 1); 171 172 return be32_to_cpu(ret); 173 } 174 175 void octeon_write_device_mem32(struct octeon_device *oct, u64 coreaddr, 176 u32 val) 177 { 178 __be32 t = cpu_to_be32(val); 179 180 __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&t, 4, 0); 181 } 182