1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_iq.h 19 * \brief Host Driver: Implementation of Octeon input queues. "Input" is 20 * with respect to the Octeon device on the NIC. From this driver's 21 * point of view they are egress queues. 22 */ 23 24 #ifndef __OCTEON_IQ_H__ 25 #define __OCTEON_IQ_H__ 26 27 #define IQ_STATUS_RUNNING 1 28 29 #define IQ_SEND_OK 0 30 #define IQ_SEND_STOP 1 31 #define IQ_SEND_FAILED -1 32 33 /*------------------------- INSTRUCTION QUEUE --------------------------*/ 34 35 /* \cond */ 36 37 #define REQTYPE_NONE 0 38 #define REQTYPE_NORESP_NET 1 39 #define REQTYPE_NORESP_NET_SG 2 40 #define REQTYPE_RESP_NET 3 41 #define REQTYPE_RESP_NET_SG 4 42 #define REQTYPE_SOFT_COMMAND 5 43 #define REQTYPE_LAST 5 44 45 struct octeon_request_list { 46 u32 reqtype; 47 void *buf; 48 }; 49 50 /* \endcond */ 51 52 /** Input Queue statistics. Each input queue has four stats fields. */ 53 struct oct_iq_stats { 54 u64 instr_posted; /**< Instructions posted to this queue. */ 55 u64 instr_processed; /**< Instructions processed in this queue. */ 56 u64 instr_dropped; /**< Instructions that could not be processed */ 57 u64 bytes_sent; /**< Bytes sent through this queue. */ 58 u64 sgentry_sent;/**< Gather entries sent through this queue. */ 59 u64 tx_done;/**< Num of packets sent to network. */ 60 u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 61 u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 62 u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 63 u64 tx_gso; /* count of tso */ 64 u64 tx_vxlan; /* tunnel */ 65 u64 tx_dmamap_fail; /* Number of times dma mapping failed */ 66 u64 tx_restart; /* Number of times this queue restarted */ 67 }; 68 69 #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 70 71 /** The instruction (input) queue. 72 * The input queue is used to post raw (instruction) mode data or packet 73 * data to Octeon device from the host. Each input queue (upto 4) for 74 * a Octeon device has one such structure to represent it. 75 */ 76 struct octeon_instr_queue { 77 struct octeon_device *oct_dev; 78 79 /** A spinlock to protect access to the input ring. */ 80 spinlock_t lock; 81 82 /** A spinlock to protect while posting on the ring. */ 83 spinlock_t post_lock; 84 85 /** This flag indicates if the queue can be used for soft commands. 86 * If this flag is set, post_lock must be acquired before posting 87 * a command to the queue. 88 * If this flag is clear, post_lock is invalid for the queue. 89 * All control commands (soft commands) will go through only Queue 0 90 * (control and data queue). So only queue-0 needs post_lock, 91 * other queues are only data queues and does not need post_lock 92 */ 93 bool allow_soft_cmds; 94 95 u32 pkt_in_done; 96 97 /** A spinlock to protect access to the input ring.*/ 98 spinlock_t iq_flush_running_lock; 99 100 /** Flag that indicates if the queue uses 64 byte commands. */ 101 u32 iqcmd_64B:1; 102 103 /** Queue info. */ 104 union oct_txpciq txpciq; 105 106 u32 rsvd:17; 107 108 /* Controls whether extra flushing of IQ is done on Tx */ 109 u32 do_auto_flush:1; 110 111 u32 status:8; 112 113 /** Maximum no. of instructions in this queue. */ 114 u32 max_count; 115 116 /** Index in input ring where the driver should write the next packet */ 117 u32 host_write_index; 118 119 /** Index in input ring where Octeon is expected to read the next 120 * packet. 121 */ 122 u32 octeon_read_index; 123 124 /** This index aids in finding the window in the queue where Octeon 125 * has read the commands. 126 */ 127 u32 flush_index; 128 129 /** This field keeps track of the instructions pending in this queue. */ 130 atomic_t instr_pending; 131 132 u32 reset_instr_cnt; 133 134 /** Pointer to the Virtual Base addr of the input ring. */ 135 u8 *base_addr; 136 137 struct octeon_request_list *request_list; 138 139 /** Octeon doorbell register for the ring. */ 140 void __iomem *doorbell_reg; 141 142 /** Octeon instruction count register for this ring. */ 143 void __iomem *inst_cnt_reg; 144 145 /** Number of instructions pending to be posted to Octeon. */ 146 u32 fill_cnt; 147 148 /** The max. number of instructions that can be held pending by the 149 * driver. 150 */ 151 u32 fill_threshold; 152 153 /** The last time that the doorbell was rung. */ 154 u64 last_db_time; 155 156 /** The doorbell timeout. If the doorbell was not rung for this time and 157 * fill_cnt is non-zero, ring the doorbell again. 158 */ 159 u32 db_timeout; 160 161 /** Statistics for this input queue. */ 162 struct oct_iq_stats stats; 163 164 /** DMA mapped base address of the input descriptor ring. */ 165 dma_addr_t base_addr_dma; 166 167 /** Application context */ 168 void *app_ctx; 169 170 /* network stack queue index */ 171 int q_index; 172 173 /*os ifidx associated with this queue */ 174 int ifidx; 175 176 }; 177 178 /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 179 180 /** 32-byte instruction format. 181 * Format of instruction for a 32-byte mode input queue. 182 */ 183 struct octeon_instr_32B { 184 /** Pointer where the input data is available. */ 185 u64 dptr; 186 187 /** Instruction Header. */ 188 u64 ih; 189 190 /** Pointer where the response for a RAW mode packet will be written 191 * by Octeon. 192 */ 193 u64 rptr; 194 195 /** Input Request Header. Additional info about the input. */ 196 u64 irh; 197 198 }; 199 200 #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 201 202 /** 64-byte instruction format. 203 * Format of instruction for a 64-byte mode input queue. 204 */ 205 struct octeon_instr2_64B { 206 /** Pointer where the input data is available. */ 207 u64 dptr; 208 209 /** Instruction Header. */ 210 u64 ih2; 211 212 /** Input Request Header. */ 213 u64 irh; 214 215 /** opcode/subcode specific parameters */ 216 u64 ossp[2]; 217 218 /** Return Data Parameters */ 219 u64 rdp; 220 221 /** Pointer where the response for a RAW mode packet will be written 222 * by Octeon. 223 */ 224 u64 rptr; 225 226 u64 reserved; 227 }; 228 229 struct octeon_instr3_64B { 230 /** Pointer where the input data is available. */ 231 u64 dptr; 232 233 /** Instruction Header. */ 234 u64 ih3; 235 236 /** Instruction Header. */ 237 u64 pki_ih3; 238 239 /** Input Request Header. */ 240 u64 irh; 241 242 /** opcode/subcode specific parameters */ 243 u64 ossp[2]; 244 245 /** Return Data Parameters */ 246 u64 rdp; 247 248 /** Pointer where the response for a RAW mode packet will be written 249 * by Octeon. 250 */ 251 u64 rptr; 252 253 }; 254 255 union octeon_instr_64B { 256 struct octeon_instr2_64B cmd2; 257 struct octeon_instr3_64B cmd3; 258 }; 259 260 #define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B)) 261 262 /** The size of each buffer in soft command buffer pool 263 */ 264 #define SOFT_COMMAND_BUFFER_SIZE 2048 265 266 struct octeon_soft_command { 267 /** Soft command buffer info. */ 268 struct list_head node; 269 u64 dma_addr; 270 u32 size; 271 272 /** Command and return status */ 273 union octeon_instr_64B cmd; 274 275 #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 276 u64 *status_word; 277 278 /** Data buffer info */ 279 void *virtdptr; 280 u64 dmadptr; 281 u32 datasize; 282 283 /** Return buffer info */ 284 void *virtrptr; 285 u64 dmarptr; 286 u32 rdatasize; 287 288 /** Context buffer info */ 289 void *ctxptr; 290 u32 ctxsize; 291 292 /** Time out and callback */ 293 size_t wait_time; 294 size_t timeout; 295 u32 iq_no; 296 void (*callback)(struct octeon_device *, u32, void *); 297 void *callback_arg; 298 }; 299 300 /** Maximum number of buffers to allocate into soft command buffer pool 301 */ 302 #define MAX_SOFT_COMMAND_BUFFERS 256 303 304 /** Head of a soft command buffer pool. 305 */ 306 struct octeon_sc_buffer_pool { 307 /** List structure to add delete pending entries to */ 308 struct list_head head; 309 310 /** A lock for this response list */ 311 spinlock_t lock; 312 313 atomic_t alloc_buf_count; 314 }; 315 316 #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \ 317 (((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count) 318 319 int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 320 int octeon_free_sc_buffer_pool(struct octeon_device *oct); 321 struct octeon_soft_command * 322 octeon_alloc_soft_command(struct octeon_device *oct, 323 u32 datasize, u32 rdatasize, 324 u32 ctxsize); 325 void octeon_free_soft_command(struct octeon_device *oct, 326 struct octeon_soft_command *sc); 327 328 /** 329 * octeon_init_instr_queue() 330 * @param octeon_dev - pointer to the octeon device structure. 331 * @param txpciq - queue to be initialized (0 <= q_no <= 3). 332 * 333 * Called at driver init time for each input queue. iq_conf has the 334 * configuration parameters for the queue. 335 * 336 * @return Success: 0 Failure: 1 337 */ 338 int octeon_init_instr_queue(struct octeon_device *octeon_dev, 339 union oct_txpciq txpciq, 340 u32 num_descs); 341 342 /** 343 * octeon_delete_instr_queue() 344 * @param octeon_dev - pointer to the octeon device structure. 345 * @param iq_no - queue to be deleted (0 <= q_no <= 3). 346 * 347 * Called at driver unload time for each input queue. Deletes all 348 * allocated resources for the input queue. 349 * 350 * @return Success: 0 Failure: 1 351 */ 352 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 353 354 int lio_wait_for_instr_fetch(struct octeon_device *oct); 355 356 void 357 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no); 358 359 int 360 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 361 void (*fn)(void *)); 362 363 int 364 lio_process_iq_request_list(struct octeon_device *oct, 365 struct octeon_instr_queue *iq, u32 napi_budget); 366 367 int octeon_send_command(struct octeon_device *oct, u32 iq_no, 368 u32 force_db, void *cmd, void *buf, 369 u32 datasize, u32 reqtype); 370 371 void octeon_prepare_soft_command(struct octeon_device *oct, 372 struct octeon_soft_command *sc, 373 u8 opcode, u8 subcode, 374 u32 irh_ossp, u64 ossp0, 375 u64 ossp1); 376 377 int octeon_send_soft_command(struct octeon_device *oct, 378 struct octeon_soft_command *sc); 379 380 int octeon_setup_iq(struct octeon_device *oct, int ifidx, 381 int q_index, union oct_txpciq iq_no, u32 num_descs, 382 void *app_ctx); 383 int 384 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, 385 u32 napi_budget); 386 #endif /* __OCTEON_IQ_H__ */ 387