1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 23 /*! \file octeon_iq.h 24 * \brief Host Driver: Implementation of Octeon input queues. "Input" is 25 * with respect to the Octeon device on the NIC. From this driver's 26 * point of view they are egress queues. 27 */ 28 29 #ifndef __OCTEON_IQ_H__ 30 #define __OCTEON_IQ_H__ 31 32 #define IQ_STATUS_RUNNING 1 33 34 #define IQ_SEND_OK 0 35 #define IQ_SEND_STOP 1 36 #define IQ_SEND_FAILED -1 37 38 /*------------------------- INSTRUCTION QUEUE --------------------------*/ 39 40 /* \cond */ 41 42 #define REQTYPE_NONE 0 43 #define REQTYPE_NORESP_NET 1 44 #define REQTYPE_NORESP_NET_SG 2 45 #define REQTYPE_RESP_NET 3 46 #define REQTYPE_RESP_NET_SG 4 47 #define REQTYPE_SOFT_COMMAND 5 48 #define REQTYPE_LAST 5 49 50 struct octeon_request_list { 51 u32 reqtype; 52 void *buf; 53 }; 54 55 /* \endcond */ 56 57 /** Input Queue statistics. Each input queue has four stats fields. */ 58 struct oct_iq_stats { 59 u64 instr_posted; /**< Instructions posted to this queue. */ 60 u64 instr_processed; /**< Instructions processed in this queue. */ 61 u64 instr_dropped; /**< Instructions that could not be processed */ 62 u64 bytes_sent; /**< Bytes sent through this queue. */ 63 u64 sgentry_sent;/**< Gather entries sent through this queue. */ 64 u64 tx_done;/**< Num of packets sent to network. */ 65 u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 66 u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 67 u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 68 }; 69 70 #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 71 72 /** The instruction (input) queue. 73 * The input queue is used to post raw (instruction) mode data or packet 74 * data to Octeon device from the host. Each input queue (upto 4) for 75 * a Octeon device has one such structure to represent it. 76 */ 77 struct octeon_instr_queue { 78 /** A spinlock to protect access to the input ring. */ 79 spinlock_t lock; 80 81 /** Flag that indicates if the queue uses 64 byte commands. */ 82 u32 iqcmd_64B:1; 83 84 /** Queue Number. */ 85 u32 iq_no:5; 86 87 u32 rsvd:17; 88 89 /* Controls the periodic flushing of iq */ 90 u32 do_auto_flush:1; 91 92 u32 status:8; 93 94 /** Maximum no. of instructions in this queue. */ 95 u32 max_count; 96 97 /** Index in input ring where the driver should write the next packet */ 98 u32 host_write_index; 99 100 /** Index in input ring where Octeon is expected to read the next 101 * packet. 102 */ 103 u32 octeon_read_index; 104 105 /** This index aids in finding the window in the queue where Octeon 106 * has read the commands. 107 */ 108 u32 flush_index; 109 110 /** This field keeps track of the instructions pending in this queue. */ 111 atomic_t instr_pending; 112 113 u32 reset_instr_cnt; 114 115 /** Pointer to the Virtual Base addr of the input ring. */ 116 u8 *base_addr; 117 118 struct octeon_request_list *request_list; 119 120 /** Octeon doorbell register for the ring. */ 121 void __iomem *doorbell_reg; 122 123 /** Octeon instruction count register for this ring. */ 124 void __iomem *inst_cnt_reg; 125 126 /** Number of instructions pending to be posted to Octeon. */ 127 u32 fill_cnt; 128 129 /** The max. number of instructions that can be held pending by the 130 * driver. 131 */ 132 u32 fill_threshold; 133 134 /** The last time that the doorbell was rung. */ 135 u64 last_db_time; 136 137 /** The doorbell timeout. If the doorbell was not rung for this time and 138 * fill_cnt is non-zero, ring the doorbell again. 139 */ 140 u32 db_timeout; 141 142 /** Statistics for this input queue. */ 143 struct oct_iq_stats stats; 144 145 /** DMA mapped base address of the input descriptor ring. */ 146 u64 base_addr_dma; 147 148 /** Application context */ 149 void *app_ctx; 150 }; 151 152 /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 153 154 /** 32-byte instruction format. 155 * Format of instruction for a 32-byte mode input queue. 156 */ 157 struct octeon_instr_32B { 158 /** Pointer where the input data is available. */ 159 u64 dptr; 160 161 /** Instruction Header. */ 162 u64 ih; 163 164 /** Pointer where the response for a RAW mode packet will be written 165 * by Octeon. 166 */ 167 u64 rptr; 168 169 /** Input Request Header. Additional info about the input. */ 170 u64 irh; 171 172 }; 173 174 #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 175 176 /** 64-byte instruction format. 177 * Format of instruction for a 64-byte mode input queue. 178 */ 179 struct octeon_instr_64B { 180 /** Pointer where the input data is available. */ 181 u64 dptr; 182 183 /** Instruction Header. */ 184 u64 ih; 185 186 /** Input Request Header. */ 187 u64 irh; 188 189 /** opcode/subcode specific parameters */ 190 u64 ossp[2]; 191 192 /** Return Data Parameters */ 193 u64 rdp; 194 195 /** Pointer where the response for a RAW mode packet will be written 196 * by Octeon. 197 */ 198 u64 rptr; 199 200 u64 reserved; 201 202 }; 203 204 #define OCT_64B_INSTR_SIZE (sizeof(struct octeon_instr_64B)) 205 206 /** The size of each buffer in soft command buffer pool 207 */ 208 #define SOFT_COMMAND_BUFFER_SIZE 1024 209 210 struct octeon_soft_command { 211 /** Soft command buffer info. */ 212 struct list_head node; 213 u64 dma_addr; 214 u32 size; 215 216 /** Command and return status */ 217 struct octeon_instr_64B cmd; 218 #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 219 u64 *status_word; 220 221 /** Data buffer info */ 222 void *virtdptr; 223 u64 dmadptr; 224 u32 datasize; 225 226 /** Return buffer info */ 227 void *virtrptr; 228 u64 dmarptr; 229 u32 rdatasize; 230 231 /** Context buffer info */ 232 void *ctxptr; 233 u32 ctxsize; 234 235 /** Time out and callback */ 236 size_t wait_time; 237 size_t timeout; 238 u32 iq_no; 239 void (*callback)(struct octeon_device *, u32, void *); 240 void *callback_arg; 241 }; 242 243 /** Maximum number of buffers to allocate into soft command buffer pool 244 */ 245 #define MAX_SOFT_COMMAND_BUFFERS 16 246 247 /** Head of a soft command buffer pool. 248 */ 249 struct octeon_sc_buffer_pool { 250 /** List structure to add delete pending entries to */ 251 struct list_head head; 252 253 /** A lock for this response list */ 254 spinlock_t lock; 255 256 atomic_t alloc_buf_count; 257 }; 258 259 int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 260 int octeon_free_sc_buffer_pool(struct octeon_device *oct); 261 struct octeon_soft_command * 262 octeon_alloc_soft_command(struct octeon_device *oct, 263 u32 datasize, u32 rdatasize, 264 u32 ctxsize); 265 void octeon_free_soft_command(struct octeon_device *oct, 266 struct octeon_soft_command *sc); 267 268 /** 269 * octeon_init_instr_queue() 270 * @param octeon_dev - pointer to the octeon device structure. 271 * @param iq_no - queue to be initialized (0 <= q_no <= 3). 272 * 273 * Called at driver init time for each input queue. iq_conf has the 274 * configuration parameters for the queue. 275 * 276 * @return Success: 0 Failure: 1 277 */ 278 int octeon_init_instr_queue(struct octeon_device *octeon_dev, u32 iq_no, 279 u32 num_descs); 280 281 /** 282 * octeon_delete_instr_queue() 283 * @param octeon_dev - pointer to the octeon device structure. 284 * @param iq_no - queue to be deleted (0 <= q_no <= 3). 285 * 286 * Called at driver unload time for each input queue. Deletes all 287 * allocated resources for the input queue. 288 * 289 * @return Success: 0 Failure: 1 290 */ 291 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 292 293 int lio_wait_for_instr_fetch(struct octeon_device *oct); 294 295 int 296 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 297 void (*fn)(void *)); 298 299 int 300 lio_process_iq_request_list(struct octeon_device *oct, 301 struct octeon_instr_queue *iq); 302 303 int octeon_send_command(struct octeon_device *oct, u32 iq_no, 304 u32 force_db, void *cmd, void *buf, 305 u32 datasize, u32 reqtype); 306 307 void octeon_prepare_soft_command(struct octeon_device *oct, 308 struct octeon_soft_command *sc, 309 u8 opcode, u8 subcode, 310 u32 irh_ossp, u64 ossp0, 311 u64 ossp1); 312 313 int octeon_send_soft_command(struct octeon_device *oct, 314 struct octeon_soft_command *sc); 315 316 int octeon_setup_iq(struct octeon_device *oct, u32 iq_no, 317 u32 num_descs, void *app_ctx); 318 319 #endif /* __OCTEON_IQ_H__ */ 320