1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_iq.h 19 * \brief Host Driver: Implementation of Octeon input queues. "Input" is 20 * with respect to the Octeon device on the NIC. From this driver's 21 * point of view they are egress queues. 22 */ 23 24 #ifndef __OCTEON_IQ_H__ 25 #define __OCTEON_IQ_H__ 26 27 #define IQ_STATUS_RUNNING 1 28 29 #define IQ_SEND_OK 0 30 #define IQ_SEND_STOP 1 31 #define IQ_SEND_FAILED -1 32 33 /*------------------------- INSTRUCTION QUEUE --------------------------*/ 34 35 /* \cond */ 36 37 #define REQTYPE_NONE 0 38 #define REQTYPE_NORESP_NET 1 39 #define REQTYPE_NORESP_NET_SG 2 40 #define REQTYPE_RESP_NET 3 41 #define REQTYPE_RESP_NET_SG 4 42 #define REQTYPE_SOFT_COMMAND 5 43 #define REQTYPE_LAST 5 44 45 struct octeon_request_list { 46 u32 reqtype; 47 void *buf; 48 }; 49 50 /* \endcond */ 51 52 /** Input Queue statistics. Each input queue has four stats fields. */ 53 struct oct_iq_stats { 54 u64 instr_posted; /**< Instructions posted to this queue. */ 55 u64 instr_processed; /**< Instructions processed in this queue. */ 56 u64 instr_dropped; /**< Instructions that could not be processed */ 57 u64 bytes_sent; /**< Bytes sent through this queue. */ 58 u64 sgentry_sent;/**< Gather entries sent through this queue. */ 59 u64 tx_done;/**< Num of packets sent to network. */ 60 u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 61 u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 62 u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 63 u64 tx_gso; /* count of tso */ 64 u64 tx_vxlan; /* tunnel */ 65 u64 tx_dmamap_fail; 66 u64 tx_restart; 67 }; 68 69 #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 70 71 /** The instruction (input) queue. 72 * The input queue is used to post raw (instruction) mode data or packet 73 * data to Octeon device from the host. Each input queue (upto 4) for 74 * a Octeon device has one such structure to represent it. 75 */ 76 struct octeon_instr_queue { 77 struct octeon_device *oct_dev; 78 79 /** A spinlock to protect access to the input ring. */ 80 spinlock_t lock; 81 82 /** A spinlock to protect while posting on the ring. */ 83 spinlock_t post_lock; 84 85 u32 pkt_in_done; 86 87 /** A spinlock to protect access to the input ring.*/ 88 spinlock_t iq_flush_running_lock; 89 90 /** Flag that indicates if the queue uses 64 byte commands. */ 91 u32 iqcmd_64B:1; 92 93 /** Queue info. */ 94 union oct_txpciq txpciq; 95 96 u32 rsvd:17; 97 98 /* Controls whether extra flushing of IQ is done on Tx */ 99 u32 do_auto_flush:1; 100 101 u32 status:8; 102 103 /** Maximum no. of instructions in this queue. */ 104 u32 max_count; 105 106 /** Index in input ring where the driver should write the next packet */ 107 u32 host_write_index; 108 109 /** Index in input ring where Octeon is expected to read the next 110 * packet. 111 */ 112 u32 octeon_read_index; 113 114 /** This index aids in finding the window in the queue where Octeon 115 * has read the commands. 116 */ 117 u32 flush_index; 118 119 /** This field keeps track of the instructions pending in this queue. */ 120 atomic_t instr_pending; 121 122 u32 reset_instr_cnt; 123 124 /** Pointer to the Virtual Base addr of the input ring. */ 125 u8 *base_addr; 126 127 struct octeon_request_list *request_list; 128 129 /** Octeon doorbell register for the ring. */ 130 void __iomem *doorbell_reg; 131 132 /** Octeon instruction count register for this ring. */ 133 void __iomem *inst_cnt_reg; 134 135 /** Number of instructions pending to be posted to Octeon. */ 136 u32 fill_cnt; 137 138 /** The max. number of instructions that can be held pending by the 139 * driver. 140 */ 141 u32 fill_threshold; 142 143 /** The last time that the doorbell was rung. */ 144 u64 last_db_time; 145 146 /** The doorbell timeout. If the doorbell was not rung for this time and 147 * fill_cnt is non-zero, ring the doorbell again. 148 */ 149 u32 db_timeout; 150 151 /** Statistics for this input queue. */ 152 struct oct_iq_stats stats; 153 154 /** DMA mapped base address of the input descriptor ring. */ 155 u64 base_addr_dma; 156 157 /** Application context */ 158 void *app_ctx; 159 160 /* network stack queue index */ 161 int q_index; 162 163 /*os ifidx associated with this queue */ 164 int ifidx; 165 166 }; 167 168 /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 169 170 /** 32-byte instruction format. 171 * Format of instruction for a 32-byte mode input queue. 172 */ 173 struct octeon_instr_32B { 174 /** Pointer where the input data is available. */ 175 u64 dptr; 176 177 /** Instruction Header. */ 178 u64 ih; 179 180 /** Pointer where the response for a RAW mode packet will be written 181 * by Octeon. 182 */ 183 u64 rptr; 184 185 /** Input Request Header. Additional info about the input. */ 186 u64 irh; 187 188 }; 189 190 #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 191 192 /** 64-byte instruction format. 193 * Format of instruction for a 64-byte mode input queue. 194 */ 195 struct octeon_instr2_64B { 196 /** Pointer where the input data is available. */ 197 u64 dptr; 198 199 /** Instruction Header. */ 200 u64 ih2; 201 202 /** Input Request Header. */ 203 u64 irh; 204 205 /** opcode/subcode specific parameters */ 206 u64 ossp[2]; 207 208 /** Return Data Parameters */ 209 u64 rdp; 210 211 /** Pointer where the response for a RAW mode packet will be written 212 * by Octeon. 213 */ 214 u64 rptr; 215 216 u64 reserved; 217 }; 218 219 struct octeon_instr3_64B { 220 /** Pointer where the input data is available. */ 221 u64 dptr; 222 223 /** Instruction Header. */ 224 u64 ih3; 225 226 /** Instruction Header. */ 227 u64 pki_ih3; 228 229 /** Input Request Header. */ 230 u64 irh; 231 232 /** opcode/subcode specific parameters */ 233 u64 ossp[2]; 234 235 /** Return Data Parameters */ 236 u64 rdp; 237 238 /** Pointer where the response for a RAW mode packet will be written 239 * by Octeon. 240 */ 241 u64 rptr; 242 243 }; 244 245 union octeon_instr_64B { 246 struct octeon_instr2_64B cmd2; 247 struct octeon_instr3_64B cmd3; 248 }; 249 250 #define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B)) 251 252 /** The size of each buffer in soft command buffer pool 253 */ 254 #define SOFT_COMMAND_BUFFER_SIZE 1536 255 256 struct octeon_soft_command { 257 /** Soft command buffer info. */ 258 struct list_head node; 259 u64 dma_addr; 260 u32 size; 261 262 /** Command and return status */ 263 union octeon_instr_64B cmd; 264 265 #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 266 u64 *status_word; 267 268 /** Data buffer info */ 269 void *virtdptr; 270 u64 dmadptr; 271 u32 datasize; 272 273 /** Return buffer info */ 274 void *virtrptr; 275 u64 dmarptr; 276 u32 rdatasize; 277 278 /** Context buffer info */ 279 void *ctxptr; 280 u32 ctxsize; 281 282 /** Time out and callback */ 283 size_t wait_time; 284 size_t timeout; 285 u32 iq_no; 286 void (*callback)(struct octeon_device *, u32, void *); 287 void *callback_arg; 288 }; 289 290 /** Maximum number of buffers to allocate into soft command buffer pool 291 */ 292 #define MAX_SOFT_COMMAND_BUFFERS 256 293 294 /** Head of a soft command buffer pool. 295 */ 296 struct octeon_sc_buffer_pool { 297 /** List structure to add delete pending entries to */ 298 struct list_head head; 299 300 /** A lock for this response list */ 301 spinlock_t lock; 302 303 atomic_t alloc_buf_count; 304 }; 305 306 #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \ 307 (((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count) 308 309 int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 310 int octeon_free_sc_buffer_pool(struct octeon_device *oct); 311 struct octeon_soft_command * 312 octeon_alloc_soft_command(struct octeon_device *oct, 313 u32 datasize, u32 rdatasize, 314 u32 ctxsize); 315 void octeon_free_soft_command(struct octeon_device *oct, 316 struct octeon_soft_command *sc); 317 318 /** 319 * octeon_init_instr_queue() 320 * @param octeon_dev - pointer to the octeon device structure. 321 * @param txpciq - queue to be initialized (0 <= q_no <= 3). 322 * 323 * Called at driver init time for each input queue. iq_conf has the 324 * configuration parameters for the queue. 325 * 326 * @return Success: 0 Failure: 1 327 */ 328 int octeon_init_instr_queue(struct octeon_device *octeon_dev, 329 union oct_txpciq txpciq, 330 u32 num_descs); 331 332 /** 333 * octeon_delete_instr_queue() 334 * @param octeon_dev - pointer to the octeon device structure. 335 * @param iq_no - queue to be deleted (0 <= q_no <= 3). 336 * 337 * Called at driver unload time for each input queue. Deletes all 338 * allocated resources for the input queue. 339 * 340 * @return Success: 0 Failure: 1 341 */ 342 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 343 344 int lio_wait_for_instr_fetch(struct octeon_device *oct); 345 346 int 347 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 348 void (*fn)(void *)); 349 350 int 351 lio_process_iq_request_list(struct octeon_device *oct, 352 struct octeon_instr_queue *iq, u32 napi_budget); 353 354 int octeon_send_command(struct octeon_device *oct, u32 iq_no, 355 u32 force_db, void *cmd, void *buf, 356 u32 datasize, u32 reqtype); 357 358 void octeon_prepare_soft_command(struct octeon_device *oct, 359 struct octeon_soft_command *sc, 360 u8 opcode, u8 subcode, 361 u32 irh_ossp, u64 ossp0, 362 u64 ossp1); 363 364 int octeon_send_soft_command(struct octeon_device *oct, 365 struct octeon_soft_command *sc); 366 367 int octeon_setup_iq(struct octeon_device *oct, int ifidx, 368 int q_index, union oct_txpciq iq_no, u32 num_descs, 369 void *app_ctx); 370 int 371 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, 372 u32 napi_budget); 373 #endif /* __OCTEON_IQ_H__ */ 374