1f21fb3edSRaghu Vatsavayi /********************************************************************** 2f21fb3edSRaghu Vatsavayi * Author: Cavium, Inc. 3f21fb3edSRaghu Vatsavayi * 4f21fb3edSRaghu Vatsavayi * Contact: support@cavium.com 5f21fb3edSRaghu Vatsavayi * Please include "LiquidIO" in the subject. 6f21fb3edSRaghu Vatsavayi * 750579d3dSRaghu Vatsavayi * Copyright (c) 2003-2016 Cavium, Inc. 8f21fb3edSRaghu Vatsavayi * 9f21fb3edSRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify 10f21fb3edSRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as 11f21fb3edSRaghu Vatsavayi * published by the Free Software Foundation. 12f21fb3edSRaghu Vatsavayi * 13f21fb3edSRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but 14f21fb3edSRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15f21fb3edSRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 1650579d3dSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more details. 1750579d3dSRaghu Vatsavayi ***********************************************************************/ 18f21fb3edSRaghu Vatsavayi /*! \file octeon_iq.h 19f21fb3edSRaghu Vatsavayi * \brief Host Driver: Implementation of Octeon input queues. "Input" is 20f21fb3edSRaghu Vatsavayi * with respect to the Octeon device on the NIC. From this driver's 21f21fb3edSRaghu Vatsavayi * point of view they are egress queues. 22f21fb3edSRaghu Vatsavayi */ 23f21fb3edSRaghu Vatsavayi 24f21fb3edSRaghu Vatsavayi #ifndef __OCTEON_IQ_H__ 25f21fb3edSRaghu Vatsavayi #define __OCTEON_IQ_H__ 26f21fb3edSRaghu Vatsavayi 27f21fb3edSRaghu Vatsavayi #define IQ_STATUS_RUNNING 1 28f21fb3edSRaghu Vatsavayi 29f21fb3edSRaghu Vatsavayi #define IQ_SEND_OK 0 30f21fb3edSRaghu Vatsavayi #define IQ_SEND_STOP 1 31f21fb3edSRaghu Vatsavayi #define IQ_SEND_FAILED -1 32f21fb3edSRaghu Vatsavayi 33f21fb3edSRaghu Vatsavayi /*------------------------- INSTRUCTION QUEUE --------------------------*/ 34f21fb3edSRaghu Vatsavayi 35f21fb3edSRaghu Vatsavayi /* \cond */ 36f21fb3edSRaghu Vatsavayi 37f21fb3edSRaghu Vatsavayi #define REQTYPE_NONE 0 38f21fb3edSRaghu Vatsavayi #define REQTYPE_NORESP_NET 1 39f21fb3edSRaghu Vatsavayi #define REQTYPE_NORESP_NET_SG 2 40f21fb3edSRaghu Vatsavayi #define REQTYPE_RESP_NET 3 41f21fb3edSRaghu Vatsavayi #define REQTYPE_RESP_NET_SG 4 42f21fb3edSRaghu Vatsavayi #define REQTYPE_SOFT_COMMAND 5 43f21fb3edSRaghu Vatsavayi #define REQTYPE_LAST 5 44f21fb3edSRaghu Vatsavayi 45f21fb3edSRaghu Vatsavayi struct octeon_request_list { 46f21fb3edSRaghu Vatsavayi u32 reqtype; 47f21fb3edSRaghu Vatsavayi void *buf; 48f21fb3edSRaghu Vatsavayi }; 49f21fb3edSRaghu Vatsavayi 50f21fb3edSRaghu Vatsavayi /* \endcond */ 51f21fb3edSRaghu Vatsavayi 52f21fb3edSRaghu Vatsavayi /** Input Queue statistics. Each input queue has four stats fields. */ 53f21fb3edSRaghu Vatsavayi struct oct_iq_stats { 54f21fb3edSRaghu Vatsavayi u64 instr_posted; /**< Instructions posted to this queue. */ 55f21fb3edSRaghu Vatsavayi u64 instr_processed; /**< Instructions processed in this queue. */ 56f21fb3edSRaghu Vatsavayi u64 instr_dropped; /**< Instructions that could not be processed */ 57f21fb3edSRaghu Vatsavayi u64 bytes_sent; /**< Bytes sent through this queue. */ 58f21fb3edSRaghu Vatsavayi u64 sgentry_sent;/**< Gather entries sent through this queue. */ 59f21fb3edSRaghu Vatsavayi u64 tx_done;/**< Num of packets sent to network. */ 60f21fb3edSRaghu Vatsavayi u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 61f21fb3edSRaghu Vatsavayi u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 62f21fb3edSRaghu Vatsavayi u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 631f164717SRaghu Vatsavayi u64 tx_gso; /* count of tso */ 6401fb237aSRaghu Vatsavayi u64 tx_vxlan; /* tunnel */ 651f164717SRaghu Vatsavayi u64 tx_dmamap_fail; 661f164717SRaghu Vatsavayi u64 tx_restart; 67f21fb3edSRaghu Vatsavayi }; 68f21fb3edSRaghu Vatsavayi 69f21fb3edSRaghu Vatsavayi #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 70f21fb3edSRaghu Vatsavayi 71f21fb3edSRaghu Vatsavayi /** The instruction (input) queue. 72f21fb3edSRaghu Vatsavayi * The input queue is used to post raw (instruction) mode data or packet 73f21fb3edSRaghu Vatsavayi * data to Octeon device from the host. Each input queue (upto 4) for 74f21fb3edSRaghu Vatsavayi * a Octeon device has one such structure to represent it. 75f21fb3edSRaghu Vatsavayi */ 76f21fb3edSRaghu Vatsavayi struct octeon_instr_queue { 776a885b60SRaghu Vatsavayi struct octeon_device *oct_dev; 786a885b60SRaghu Vatsavayi 79f21fb3edSRaghu Vatsavayi /** A spinlock to protect access to the input ring. */ 80f21fb3edSRaghu Vatsavayi spinlock_t lock; 81f21fb3edSRaghu Vatsavayi 829a96bde4SRaghu Vatsavayi /** A spinlock to protect while posting on the ring. */ 839a96bde4SRaghu Vatsavayi spinlock_t post_lock; 849a96bde4SRaghu Vatsavayi 85cd8b1eb4SRaghu Vatsavayi u32 pkt_in_done; 86cd8b1eb4SRaghu Vatsavayi 879a96bde4SRaghu Vatsavayi /** A spinlock to protect access to the input ring.*/ 889a96bde4SRaghu Vatsavayi spinlock_t iq_flush_running_lock; 899a96bde4SRaghu Vatsavayi 90f21fb3edSRaghu Vatsavayi /** Flag that indicates if the queue uses 64 byte commands. */ 91f21fb3edSRaghu Vatsavayi u32 iqcmd_64B:1; 92f21fb3edSRaghu Vatsavayi 9326236fa9SRaghu Vatsavayi /** Queue info. */ 9426236fa9SRaghu Vatsavayi union oct_txpciq txpciq; 95f21fb3edSRaghu Vatsavayi 96f21fb3edSRaghu Vatsavayi u32 rsvd:17; 97f21fb3edSRaghu Vatsavayi 98a2c64b67SRaghu Vatsavayi /* Controls whether extra flushing of IQ is done on Tx */ 99f21fb3edSRaghu Vatsavayi u32 do_auto_flush:1; 100f21fb3edSRaghu Vatsavayi 101f21fb3edSRaghu Vatsavayi u32 status:8; 102f21fb3edSRaghu Vatsavayi 103f21fb3edSRaghu Vatsavayi /** Maximum no. of instructions in this queue. */ 104f21fb3edSRaghu Vatsavayi u32 max_count; 105f21fb3edSRaghu Vatsavayi 106f21fb3edSRaghu Vatsavayi /** Index in input ring where the driver should write the next packet */ 107f21fb3edSRaghu Vatsavayi u32 host_write_index; 108f21fb3edSRaghu Vatsavayi 109f21fb3edSRaghu Vatsavayi /** Index in input ring where Octeon is expected to read the next 110f21fb3edSRaghu Vatsavayi * packet. 111f21fb3edSRaghu Vatsavayi */ 112f21fb3edSRaghu Vatsavayi u32 octeon_read_index; 113f21fb3edSRaghu Vatsavayi 114f21fb3edSRaghu Vatsavayi /** This index aids in finding the window in the queue where Octeon 115f21fb3edSRaghu Vatsavayi * has read the commands. 116f21fb3edSRaghu Vatsavayi */ 117f21fb3edSRaghu Vatsavayi u32 flush_index; 118f21fb3edSRaghu Vatsavayi 119f21fb3edSRaghu Vatsavayi /** This field keeps track of the instructions pending in this queue. */ 120f21fb3edSRaghu Vatsavayi atomic_t instr_pending; 121f21fb3edSRaghu Vatsavayi 122f21fb3edSRaghu Vatsavayi u32 reset_instr_cnt; 123f21fb3edSRaghu Vatsavayi 124f21fb3edSRaghu Vatsavayi /** Pointer to the Virtual Base addr of the input ring. */ 125f21fb3edSRaghu Vatsavayi u8 *base_addr; 126f21fb3edSRaghu Vatsavayi 127f21fb3edSRaghu Vatsavayi struct octeon_request_list *request_list; 128f21fb3edSRaghu Vatsavayi 129f21fb3edSRaghu Vatsavayi /** Octeon doorbell register for the ring. */ 130f21fb3edSRaghu Vatsavayi void __iomem *doorbell_reg; 131f21fb3edSRaghu Vatsavayi 132f21fb3edSRaghu Vatsavayi /** Octeon instruction count register for this ring. */ 133f21fb3edSRaghu Vatsavayi void __iomem *inst_cnt_reg; 134f21fb3edSRaghu Vatsavayi 135f21fb3edSRaghu Vatsavayi /** Number of instructions pending to be posted to Octeon. */ 136f21fb3edSRaghu Vatsavayi u32 fill_cnt; 137f21fb3edSRaghu Vatsavayi 138f21fb3edSRaghu Vatsavayi /** The max. number of instructions that can be held pending by the 139f21fb3edSRaghu Vatsavayi * driver. 140f21fb3edSRaghu Vatsavayi */ 141f21fb3edSRaghu Vatsavayi u32 fill_threshold; 142f21fb3edSRaghu Vatsavayi 143f21fb3edSRaghu Vatsavayi /** The last time that the doorbell was rung. */ 144f21fb3edSRaghu Vatsavayi u64 last_db_time; 145f21fb3edSRaghu Vatsavayi 146f21fb3edSRaghu Vatsavayi /** The doorbell timeout. If the doorbell was not rung for this time and 147f21fb3edSRaghu Vatsavayi * fill_cnt is non-zero, ring the doorbell again. 148f21fb3edSRaghu Vatsavayi */ 149f21fb3edSRaghu Vatsavayi u32 db_timeout; 150f21fb3edSRaghu Vatsavayi 151f21fb3edSRaghu Vatsavayi /** Statistics for this input queue. */ 152f21fb3edSRaghu Vatsavayi struct oct_iq_stats stats; 153f21fb3edSRaghu Vatsavayi 154f21fb3edSRaghu Vatsavayi /** DMA mapped base address of the input descriptor ring. */ 155b3ca9af0SVSR Burru dma_addr_t base_addr_dma; 156f21fb3edSRaghu Vatsavayi 157f21fb3edSRaghu Vatsavayi /** Application context */ 158f21fb3edSRaghu Vatsavayi void *app_ctx; 1590cece6c5SRaghu Vatsavayi 1600cece6c5SRaghu Vatsavayi /* network stack queue index */ 1610cece6c5SRaghu Vatsavayi int q_index; 1620cece6c5SRaghu Vatsavayi 1630cece6c5SRaghu Vatsavayi /*os ifidx associated with this queue */ 1640cece6c5SRaghu Vatsavayi int ifidx; 1650cece6c5SRaghu Vatsavayi 166f21fb3edSRaghu Vatsavayi }; 167f21fb3edSRaghu Vatsavayi 168f21fb3edSRaghu Vatsavayi /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 169f21fb3edSRaghu Vatsavayi 170f21fb3edSRaghu Vatsavayi /** 32-byte instruction format. 171f21fb3edSRaghu Vatsavayi * Format of instruction for a 32-byte mode input queue. 172f21fb3edSRaghu Vatsavayi */ 173f21fb3edSRaghu Vatsavayi struct octeon_instr_32B { 174f21fb3edSRaghu Vatsavayi /** Pointer where the input data is available. */ 175f21fb3edSRaghu Vatsavayi u64 dptr; 176f21fb3edSRaghu Vatsavayi 177f21fb3edSRaghu Vatsavayi /** Instruction Header. */ 178f21fb3edSRaghu Vatsavayi u64 ih; 179f21fb3edSRaghu Vatsavayi 180f21fb3edSRaghu Vatsavayi /** Pointer where the response for a RAW mode packet will be written 181f21fb3edSRaghu Vatsavayi * by Octeon. 182f21fb3edSRaghu Vatsavayi */ 183f21fb3edSRaghu Vatsavayi u64 rptr; 184f21fb3edSRaghu Vatsavayi 185f21fb3edSRaghu Vatsavayi /** Input Request Header. Additional info about the input. */ 186f21fb3edSRaghu Vatsavayi u64 irh; 187f21fb3edSRaghu Vatsavayi 188f21fb3edSRaghu Vatsavayi }; 189f21fb3edSRaghu Vatsavayi 190f21fb3edSRaghu Vatsavayi #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 191f21fb3edSRaghu Vatsavayi 192f21fb3edSRaghu Vatsavayi /** 64-byte instruction format. 193f21fb3edSRaghu Vatsavayi * Format of instruction for a 64-byte mode input queue. 194f21fb3edSRaghu Vatsavayi */ 1956a885b60SRaghu Vatsavayi struct octeon_instr2_64B { 196f21fb3edSRaghu Vatsavayi /** Pointer where the input data is available. */ 197f21fb3edSRaghu Vatsavayi u64 dptr; 198f21fb3edSRaghu Vatsavayi 199f21fb3edSRaghu Vatsavayi /** Instruction Header. */ 2006a885b60SRaghu Vatsavayi u64 ih2; 201f21fb3edSRaghu Vatsavayi 202f21fb3edSRaghu Vatsavayi /** Input Request Header. */ 203f21fb3edSRaghu Vatsavayi u64 irh; 204f21fb3edSRaghu Vatsavayi 205f21fb3edSRaghu Vatsavayi /** opcode/subcode specific parameters */ 206f21fb3edSRaghu Vatsavayi u64 ossp[2]; 207f21fb3edSRaghu Vatsavayi 208f21fb3edSRaghu Vatsavayi /** Return Data Parameters */ 209f21fb3edSRaghu Vatsavayi u64 rdp; 210f21fb3edSRaghu Vatsavayi 211f21fb3edSRaghu Vatsavayi /** Pointer where the response for a RAW mode packet will be written 212f21fb3edSRaghu Vatsavayi * by Octeon. 213f21fb3edSRaghu Vatsavayi */ 214f21fb3edSRaghu Vatsavayi u64 rptr; 215f21fb3edSRaghu Vatsavayi 216f21fb3edSRaghu Vatsavayi u64 reserved; 2176a885b60SRaghu Vatsavayi }; 2186a885b60SRaghu Vatsavayi 2196a885b60SRaghu Vatsavayi struct octeon_instr3_64B { 2206a885b60SRaghu Vatsavayi /** Pointer where the input data is available. */ 2216a885b60SRaghu Vatsavayi u64 dptr; 2226a885b60SRaghu Vatsavayi 2236a885b60SRaghu Vatsavayi /** Instruction Header. */ 2246a885b60SRaghu Vatsavayi u64 ih3; 2256a885b60SRaghu Vatsavayi 2266a885b60SRaghu Vatsavayi /** Instruction Header. */ 2276a885b60SRaghu Vatsavayi u64 pki_ih3; 2286a885b60SRaghu Vatsavayi 2296a885b60SRaghu Vatsavayi /** Input Request Header. */ 2306a885b60SRaghu Vatsavayi u64 irh; 2316a885b60SRaghu Vatsavayi 2326a885b60SRaghu Vatsavayi /** opcode/subcode specific parameters */ 2336a885b60SRaghu Vatsavayi u64 ossp[2]; 2346a885b60SRaghu Vatsavayi 2356a885b60SRaghu Vatsavayi /** Return Data Parameters */ 2366a885b60SRaghu Vatsavayi u64 rdp; 2376a885b60SRaghu Vatsavayi 2386a885b60SRaghu Vatsavayi /** Pointer where the response for a RAW mode packet will be written 2396a885b60SRaghu Vatsavayi * by Octeon. 2406a885b60SRaghu Vatsavayi */ 2416a885b60SRaghu Vatsavayi u64 rptr; 242f21fb3edSRaghu Vatsavayi 243f21fb3edSRaghu Vatsavayi }; 244f21fb3edSRaghu Vatsavayi 2456a885b60SRaghu Vatsavayi union octeon_instr_64B { 2466a885b60SRaghu Vatsavayi struct octeon_instr2_64B cmd2; 2476a885b60SRaghu Vatsavayi struct octeon_instr3_64B cmd3; 2486a885b60SRaghu Vatsavayi }; 2496a885b60SRaghu Vatsavayi 2506a885b60SRaghu Vatsavayi #define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B)) 251f21fb3edSRaghu Vatsavayi 252f21fb3edSRaghu Vatsavayi /** The size of each buffer in soft command buffer pool 253f21fb3edSRaghu Vatsavayi */ 254a55667e6SPrasad Kanneganti #define SOFT_COMMAND_BUFFER_SIZE 2048 255f21fb3edSRaghu Vatsavayi 256f21fb3edSRaghu Vatsavayi struct octeon_soft_command { 257f21fb3edSRaghu Vatsavayi /** Soft command buffer info. */ 258f21fb3edSRaghu Vatsavayi struct list_head node; 259f21fb3edSRaghu Vatsavayi u64 dma_addr; 260f21fb3edSRaghu Vatsavayi u32 size; 261f21fb3edSRaghu Vatsavayi 262f21fb3edSRaghu Vatsavayi /** Command and return status */ 2636a885b60SRaghu Vatsavayi union octeon_instr_64B cmd; 2646a885b60SRaghu Vatsavayi 265f21fb3edSRaghu Vatsavayi #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 266f21fb3edSRaghu Vatsavayi u64 *status_word; 267f21fb3edSRaghu Vatsavayi 268f21fb3edSRaghu Vatsavayi /** Data buffer info */ 269f21fb3edSRaghu Vatsavayi void *virtdptr; 270f21fb3edSRaghu Vatsavayi u64 dmadptr; 271f21fb3edSRaghu Vatsavayi u32 datasize; 272f21fb3edSRaghu Vatsavayi 273f21fb3edSRaghu Vatsavayi /** Return buffer info */ 274f21fb3edSRaghu Vatsavayi void *virtrptr; 275f21fb3edSRaghu Vatsavayi u64 dmarptr; 276f21fb3edSRaghu Vatsavayi u32 rdatasize; 277f21fb3edSRaghu Vatsavayi 278f21fb3edSRaghu Vatsavayi /** Context buffer info */ 279f21fb3edSRaghu Vatsavayi void *ctxptr; 280f21fb3edSRaghu Vatsavayi u32 ctxsize; 281f21fb3edSRaghu Vatsavayi 282f21fb3edSRaghu Vatsavayi /** Time out and callback */ 283f21fb3edSRaghu Vatsavayi size_t wait_time; 284f21fb3edSRaghu Vatsavayi size_t timeout; 285f21fb3edSRaghu Vatsavayi u32 iq_no; 286f21fb3edSRaghu Vatsavayi void (*callback)(struct octeon_device *, u32, void *); 287f21fb3edSRaghu Vatsavayi void *callback_arg; 288f21fb3edSRaghu Vatsavayi }; 289f21fb3edSRaghu Vatsavayi 290f21fb3edSRaghu Vatsavayi /** Maximum number of buffers to allocate into soft command buffer pool 291f21fb3edSRaghu Vatsavayi */ 29263da8404SRaghu Vatsavayi #define MAX_SOFT_COMMAND_BUFFERS 256 293f21fb3edSRaghu Vatsavayi 294f21fb3edSRaghu Vatsavayi /** Head of a soft command buffer pool. 295f21fb3edSRaghu Vatsavayi */ 296f21fb3edSRaghu Vatsavayi struct octeon_sc_buffer_pool { 297f21fb3edSRaghu Vatsavayi /** List structure to add delete pending entries to */ 298f21fb3edSRaghu Vatsavayi struct list_head head; 299f21fb3edSRaghu Vatsavayi 300f21fb3edSRaghu Vatsavayi /** A lock for this response list */ 301f21fb3edSRaghu Vatsavayi spinlock_t lock; 302f21fb3edSRaghu Vatsavayi 303f21fb3edSRaghu Vatsavayi atomic_t alloc_buf_count; 304f21fb3edSRaghu Vatsavayi }; 305f21fb3edSRaghu Vatsavayi 30697a25326SRaghu Vatsavayi #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \ 30797a25326SRaghu Vatsavayi (((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count) 30897a25326SRaghu Vatsavayi 309f21fb3edSRaghu Vatsavayi int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 310f21fb3edSRaghu Vatsavayi int octeon_free_sc_buffer_pool(struct octeon_device *oct); 311f21fb3edSRaghu Vatsavayi struct octeon_soft_command * 312f21fb3edSRaghu Vatsavayi octeon_alloc_soft_command(struct octeon_device *oct, 313f21fb3edSRaghu Vatsavayi u32 datasize, u32 rdatasize, 314f21fb3edSRaghu Vatsavayi u32 ctxsize); 315f21fb3edSRaghu Vatsavayi void octeon_free_soft_command(struct octeon_device *oct, 316f21fb3edSRaghu Vatsavayi struct octeon_soft_command *sc); 317f21fb3edSRaghu Vatsavayi 318f21fb3edSRaghu Vatsavayi /** 319f21fb3edSRaghu Vatsavayi * octeon_init_instr_queue() 320f21fb3edSRaghu Vatsavayi * @param octeon_dev - pointer to the octeon device structure. 32126236fa9SRaghu Vatsavayi * @param txpciq - queue to be initialized (0 <= q_no <= 3). 322f21fb3edSRaghu Vatsavayi * 323f21fb3edSRaghu Vatsavayi * Called at driver init time for each input queue. iq_conf has the 324f21fb3edSRaghu Vatsavayi * configuration parameters for the queue. 325f21fb3edSRaghu Vatsavayi * 326f21fb3edSRaghu Vatsavayi * @return Success: 0 Failure: 1 327f21fb3edSRaghu Vatsavayi */ 32826236fa9SRaghu Vatsavayi int octeon_init_instr_queue(struct octeon_device *octeon_dev, 32926236fa9SRaghu Vatsavayi union oct_txpciq txpciq, 330f21fb3edSRaghu Vatsavayi u32 num_descs); 331f21fb3edSRaghu Vatsavayi 332f21fb3edSRaghu Vatsavayi /** 333f21fb3edSRaghu Vatsavayi * octeon_delete_instr_queue() 334f21fb3edSRaghu Vatsavayi * @param octeon_dev - pointer to the octeon device structure. 335f21fb3edSRaghu Vatsavayi * @param iq_no - queue to be deleted (0 <= q_no <= 3). 336f21fb3edSRaghu Vatsavayi * 337f21fb3edSRaghu Vatsavayi * Called at driver unload time for each input queue. Deletes all 338f21fb3edSRaghu Vatsavayi * allocated resources for the input queue. 339f21fb3edSRaghu Vatsavayi * 340f21fb3edSRaghu Vatsavayi * @return Success: 0 Failure: 1 341f21fb3edSRaghu Vatsavayi */ 342f21fb3edSRaghu Vatsavayi int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 343f21fb3edSRaghu Vatsavayi 344f21fb3edSRaghu Vatsavayi int lio_wait_for_instr_fetch(struct octeon_device *oct); 345f21fb3edSRaghu Vatsavayi 346f21fb3edSRaghu Vatsavayi int 347f21fb3edSRaghu Vatsavayi octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 348f21fb3edSRaghu Vatsavayi void (*fn)(void *)); 349f21fb3edSRaghu Vatsavayi 350f21fb3edSRaghu Vatsavayi int 351f21fb3edSRaghu Vatsavayi lio_process_iq_request_list(struct octeon_device *oct, 3529a96bde4SRaghu Vatsavayi struct octeon_instr_queue *iq, u32 napi_budget); 353f21fb3edSRaghu Vatsavayi 354f21fb3edSRaghu Vatsavayi int octeon_send_command(struct octeon_device *oct, u32 iq_no, 355f21fb3edSRaghu Vatsavayi u32 force_db, void *cmd, void *buf, 356f21fb3edSRaghu Vatsavayi u32 datasize, u32 reqtype); 357f21fb3edSRaghu Vatsavayi 358f21fb3edSRaghu Vatsavayi void octeon_prepare_soft_command(struct octeon_device *oct, 359f21fb3edSRaghu Vatsavayi struct octeon_soft_command *sc, 360f21fb3edSRaghu Vatsavayi u8 opcode, u8 subcode, 361f21fb3edSRaghu Vatsavayi u32 irh_ossp, u64 ossp0, 362f21fb3edSRaghu Vatsavayi u64 ossp1); 363f21fb3edSRaghu Vatsavayi 364f21fb3edSRaghu Vatsavayi int octeon_send_soft_command(struct octeon_device *oct, 365f21fb3edSRaghu Vatsavayi struct octeon_soft_command *sc); 366f21fb3edSRaghu Vatsavayi 3670cece6c5SRaghu Vatsavayi int octeon_setup_iq(struct octeon_device *oct, int ifidx, 3680cece6c5SRaghu Vatsavayi int q_index, union oct_txpciq iq_no, u32 num_descs, 3690cece6c5SRaghu Vatsavayi void *app_ctx); 3709a96bde4SRaghu Vatsavayi int 3719a96bde4SRaghu Vatsavayi octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, 37260889869SDerek Chickles u32 napi_budget); 373f21fb3edSRaghu Vatsavayi #endif /* __OCTEON_IQ_H__ */ 374