1f21fb3edSRaghu Vatsavayi /********************************************************************** 2f21fb3edSRaghu Vatsavayi * Author: Cavium, Inc. 3f21fb3edSRaghu Vatsavayi * 4f21fb3edSRaghu Vatsavayi * Contact: support@cavium.com 5f21fb3edSRaghu Vatsavayi * Please include "LiquidIO" in the subject. 6f21fb3edSRaghu Vatsavayi * 7f21fb3edSRaghu Vatsavayi * Copyright (c) 2003-2015 Cavium, Inc. 8f21fb3edSRaghu Vatsavayi * 9f21fb3edSRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify 10f21fb3edSRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as 11f21fb3edSRaghu Vatsavayi * published by the Free Software Foundation. 12f21fb3edSRaghu Vatsavayi * 13f21fb3edSRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but 14f21fb3edSRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15f21fb3edSRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16f21fb3edSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more 17f21fb3edSRaghu Vatsavayi * details. 18f21fb3edSRaghu Vatsavayi * 19f21fb3edSRaghu Vatsavayi * This file may also be available under a different license from Cavium. 20f21fb3edSRaghu Vatsavayi * Contact Cavium, Inc. for more information 21f21fb3edSRaghu Vatsavayi **********************************************************************/ 22f21fb3edSRaghu Vatsavayi 23f21fb3edSRaghu Vatsavayi /*! \file octeon_iq.h 24f21fb3edSRaghu Vatsavayi * \brief Host Driver: Implementation of Octeon input queues. "Input" is 25f21fb3edSRaghu Vatsavayi * with respect to the Octeon device on the NIC. From this driver's 26f21fb3edSRaghu Vatsavayi * point of view they are egress queues. 27f21fb3edSRaghu Vatsavayi */ 28f21fb3edSRaghu Vatsavayi 29f21fb3edSRaghu Vatsavayi #ifndef __OCTEON_IQ_H__ 30f21fb3edSRaghu Vatsavayi #define __OCTEON_IQ_H__ 31f21fb3edSRaghu Vatsavayi 32f21fb3edSRaghu Vatsavayi #define IQ_STATUS_RUNNING 1 33f21fb3edSRaghu Vatsavayi 34f21fb3edSRaghu Vatsavayi #define IQ_SEND_OK 0 35f21fb3edSRaghu Vatsavayi #define IQ_SEND_STOP 1 36f21fb3edSRaghu Vatsavayi #define IQ_SEND_FAILED -1 37f21fb3edSRaghu Vatsavayi 38f21fb3edSRaghu Vatsavayi /*------------------------- INSTRUCTION QUEUE --------------------------*/ 39f21fb3edSRaghu Vatsavayi 40f21fb3edSRaghu Vatsavayi /* \cond */ 41f21fb3edSRaghu Vatsavayi 42f21fb3edSRaghu Vatsavayi #define REQTYPE_NONE 0 43f21fb3edSRaghu Vatsavayi #define REQTYPE_NORESP_NET 1 44f21fb3edSRaghu Vatsavayi #define REQTYPE_NORESP_NET_SG 2 45f21fb3edSRaghu Vatsavayi #define REQTYPE_RESP_NET 3 46f21fb3edSRaghu Vatsavayi #define REQTYPE_RESP_NET_SG 4 47f21fb3edSRaghu Vatsavayi #define REQTYPE_SOFT_COMMAND 5 48f21fb3edSRaghu Vatsavayi #define REQTYPE_LAST 5 49f21fb3edSRaghu Vatsavayi 50f21fb3edSRaghu Vatsavayi struct octeon_request_list { 51f21fb3edSRaghu Vatsavayi u32 reqtype; 52f21fb3edSRaghu Vatsavayi void *buf; 53f21fb3edSRaghu Vatsavayi }; 54f21fb3edSRaghu Vatsavayi 55f21fb3edSRaghu Vatsavayi /* \endcond */ 56f21fb3edSRaghu Vatsavayi 57f21fb3edSRaghu Vatsavayi /** Input Queue statistics. Each input queue has four stats fields. */ 58f21fb3edSRaghu Vatsavayi struct oct_iq_stats { 59f21fb3edSRaghu Vatsavayi u64 instr_posted; /**< Instructions posted to this queue. */ 60f21fb3edSRaghu Vatsavayi u64 instr_processed; /**< Instructions processed in this queue. */ 61f21fb3edSRaghu Vatsavayi u64 instr_dropped; /**< Instructions that could not be processed */ 62f21fb3edSRaghu Vatsavayi u64 bytes_sent; /**< Bytes sent through this queue. */ 63f21fb3edSRaghu Vatsavayi u64 sgentry_sent;/**< Gather entries sent through this queue. */ 64f21fb3edSRaghu Vatsavayi u64 tx_done;/**< Num of packets sent to network. */ 65f21fb3edSRaghu Vatsavayi u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 66f21fb3edSRaghu Vatsavayi u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 67f21fb3edSRaghu Vatsavayi u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 68f21fb3edSRaghu Vatsavayi }; 69f21fb3edSRaghu Vatsavayi 70f21fb3edSRaghu Vatsavayi #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 71f21fb3edSRaghu Vatsavayi 72f21fb3edSRaghu Vatsavayi /** The instruction (input) queue. 73f21fb3edSRaghu Vatsavayi * The input queue is used to post raw (instruction) mode data or packet 74f21fb3edSRaghu Vatsavayi * data to Octeon device from the host. Each input queue (upto 4) for 75f21fb3edSRaghu Vatsavayi * a Octeon device has one such structure to represent it. 76f21fb3edSRaghu Vatsavayi */ 77f21fb3edSRaghu Vatsavayi struct octeon_instr_queue { 78f21fb3edSRaghu Vatsavayi /** A spinlock to protect access to the input ring. */ 79f21fb3edSRaghu Vatsavayi spinlock_t lock; 80f21fb3edSRaghu Vatsavayi 81f21fb3edSRaghu Vatsavayi /** Flag that indicates if the queue uses 64 byte commands. */ 82f21fb3edSRaghu Vatsavayi u32 iqcmd_64B:1; 83f21fb3edSRaghu Vatsavayi 8426236fa9SRaghu Vatsavayi /** Queue info. */ 8526236fa9SRaghu Vatsavayi union oct_txpciq txpciq; 86f21fb3edSRaghu Vatsavayi 87f21fb3edSRaghu Vatsavayi u32 rsvd:17; 88f21fb3edSRaghu Vatsavayi 89f21fb3edSRaghu Vatsavayi /* Controls the periodic flushing of iq */ 90f21fb3edSRaghu Vatsavayi u32 do_auto_flush:1; 91f21fb3edSRaghu Vatsavayi 92f21fb3edSRaghu Vatsavayi u32 status:8; 93f21fb3edSRaghu Vatsavayi 94f21fb3edSRaghu Vatsavayi /** Maximum no. of instructions in this queue. */ 95f21fb3edSRaghu Vatsavayi u32 max_count; 96f21fb3edSRaghu Vatsavayi 97f21fb3edSRaghu Vatsavayi /** Index in input ring where the driver should write the next packet */ 98f21fb3edSRaghu Vatsavayi u32 host_write_index; 99f21fb3edSRaghu Vatsavayi 100f21fb3edSRaghu Vatsavayi /** Index in input ring where Octeon is expected to read the next 101f21fb3edSRaghu Vatsavayi * packet. 102f21fb3edSRaghu Vatsavayi */ 103f21fb3edSRaghu Vatsavayi u32 octeon_read_index; 104f21fb3edSRaghu Vatsavayi 105f21fb3edSRaghu Vatsavayi /** This index aids in finding the window in the queue where Octeon 106f21fb3edSRaghu Vatsavayi * has read the commands. 107f21fb3edSRaghu Vatsavayi */ 108f21fb3edSRaghu Vatsavayi u32 flush_index; 109f21fb3edSRaghu Vatsavayi 110f21fb3edSRaghu Vatsavayi /** This field keeps track of the instructions pending in this queue. */ 111f21fb3edSRaghu Vatsavayi atomic_t instr_pending; 112f21fb3edSRaghu Vatsavayi 113f21fb3edSRaghu Vatsavayi u32 reset_instr_cnt; 114f21fb3edSRaghu Vatsavayi 115f21fb3edSRaghu Vatsavayi /** Pointer to the Virtual Base addr of the input ring. */ 116f21fb3edSRaghu Vatsavayi u8 *base_addr; 117f21fb3edSRaghu Vatsavayi 118f21fb3edSRaghu Vatsavayi struct octeon_request_list *request_list; 119f21fb3edSRaghu Vatsavayi 120f21fb3edSRaghu Vatsavayi /** Octeon doorbell register for the ring. */ 121f21fb3edSRaghu Vatsavayi void __iomem *doorbell_reg; 122f21fb3edSRaghu Vatsavayi 123f21fb3edSRaghu Vatsavayi /** Octeon instruction count register for this ring. */ 124f21fb3edSRaghu Vatsavayi void __iomem *inst_cnt_reg; 125f21fb3edSRaghu Vatsavayi 126f21fb3edSRaghu Vatsavayi /** Number of instructions pending to be posted to Octeon. */ 127f21fb3edSRaghu Vatsavayi u32 fill_cnt; 128f21fb3edSRaghu Vatsavayi 129f21fb3edSRaghu Vatsavayi /** The max. number of instructions that can be held pending by the 130f21fb3edSRaghu Vatsavayi * driver. 131f21fb3edSRaghu Vatsavayi */ 132f21fb3edSRaghu Vatsavayi u32 fill_threshold; 133f21fb3edSRaghu Vatsavayi 134f21fb3edSRaghu Vatsavayi /** The last time that the doorbell was rung. */ 135f21fb3edSRaghu Vatsavayi u64 last_db_time; 136f21fb3edSRaghu Vatsavayi 137f21fb3edSRaghu Vatsavayi /** The doorbell timeout. If the doorbell was not rung for this time and 138f21fb3edSRaghu Vatsavayi * fill_cnt is non-zero, ring the doorbell again. 139f21fb3edSRaghu Vatsavayi */ 140f21fb3edSRaghu Vatsavayi u32 db_timeout; 141f21fb3edSRaghu Vatsavayi 142f21fb3edSRaghu Vatsavayi /** Statistics for this input queue. */ 143f21fb3edSRaghu Vatsavayi struct oct_iq_stats stats; 144f21fb3edSRaghu Vatsavayi 145f21fb3edSRaghu Vatsavayi /** DMA mapped base address of the input descriptor ring. */ 146f21fb3edSRaghu Vatsavayi u64 base_addr_dma; 147f21fb3edSRaghu Vatsavayi 148f21fb3edSRaghu Vatsavayi /** Application context */ 149f21fb3edSRaghu Vatsavayi void *app_ctx; 150f21fb3edSRaghu Vatsavayi }; 151f21fb3edSRaghu Vatsavayi 152f21fb3edSRaghu Vatsavayi /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 153f21fb3edSRaghu Vatsavayi 154f21fb3edSRaghu Vatsavayi /** 32-byte instruction format. 155f21fb3edSRaghu Vatsavayi * Format of instruction for a 32-byte mode input queue. 156f21fb3edSRaghu Vatsavayi */ 157f21fb3edSRaghu Vatsavayi struct octeon_instr_32B { 158f21fb3edSRaghu Vatsavayi /** Pointer where the input data is available. */ 159f21fb3edSRaghu Vatsavayi u64 dptr; 160f21fb3edSRaghu Vatsavayi 161f21fb3edSRaghu Vatsavayi /** Instruction Header. */ 162f21fb3edSRaghu Vatsavayi u64 ih; 163f21fb3edSRaghu Vatsavayi 164f21fb3edSRaghu Vatsavayi /** Pointer where the response for a RAW mode packet will be written 165f21fb3edSRaghu Vatsavayi * by Octeon. 166f21fb3edSRaghu Vatsavayi */ 167f21fb3edSRaghu Vatsavayi u64 rptr; 168f21fb3edSRaghu Vatsavayi 169f21fb3edSRaghu Vatsavayi /** Input Request Header. Additional info about the input. */ 170f21fb3edSRaghu Vatsavayi u64 irh; 171f21fb3edSRaghu Vatsavayi 172f21fb3edSRaghu Vatsavayi }; 173f21fb3edSRaghu Vatsavayi 174f21fb3edSRaghu Vatsavayi #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 175f21fb3edSRaghu Vatsavayi 176f21fb3edSRaghu Vatsavayi /** 64-byte instruction format. 177f21fb3edSRaghu Vatsavayi * Format of instruction for a 64-byte mode input queue. 178f21fb3edSRaghu Vatsavayi */ 179f21fb3edSRaghu Vatsavayi struct octeon_instr_64B { 180f21fb3edSRaghu Vatsavayi /** Pointer where the input data is available. */ 181f21fb3edSRaghu Vatsavayi u64 dptr; 182f21fb3edSRaghu Vatsavayi 183f21fb3edSRaghu Vatsavayi /** Instruction Header. */ 184f21fb3edSRaghu Vatsavayi u64 ih; 185f21fb3edSRaghu Vatsavayi 186f21fb3edSRaghu Vatsavayi /** Input Request Header. */ 187f21fb3edSRaghu Vatsavayi u64 irh; 188f21fb3edSRaghu Vatsavayi 189f21fb3edSRaghu Vatsavayi /** opcode/subcode specific parameters */ 190f21fb3edSRaghu Vatsavayi u64 ossp[2]; 191f21fb3edSRaghu Vatsavayi 192f21fb3edSRaghu Vatsavayi /** Return Data Parameters */ 193f21fb3edSRaghu Vatsavayi u64 rdp; 194f21fb3edSRaghu Vatsavayi 195f21fb3edSRaghu Vatsavayi /** Pointer where the response for a RAW mode packet will be written 196f21fb3edSRaghu Vatsavayi * by Octeon. 197f21fb3edSRaghu Vatsavayi */ 198f21fb3edSRaghu Vatsavayi u64 rptr; 199f21fb3edSRaghu Vatsavayi 200f21fb3edSRaghu Vatsavayi u64 reserved; 201f21fb3edSRaghu Vatsavayi 202f21fb3edSRaghu Vatsavayi }; 203f21fb3edSRaghu Vatsavayi 204f21fb3edSRaghu Vatsavayi #define OCT_64B_INSTR_SIZE (sizeof(struct octeon_instr_64B)) 205f21fb3edSRaghu Vatsavayi 206f21fb3edSRaghu Vatsavayi /** The size of each buffer in soft command buffer pool 207f21fb3edSRaghu Vatsavayi */ 208f21fb3edSRaghu Vatsavayi #define SOFT_COMMAND_BUFFER_SIZE 1024 209f21fb3edSRaghu Vatsavayi 210f21fb3edSRaghu Vatsavayi struct octeon_soft_command { 211f21fb3edSRaghu Vatsavayi /** Soft command buffer info. */ 212f21fb3edSRaghu Vatsavayi struct list_head node; 213f21fb3edSRaghu Vatsavayi u64 dma_addr; 214f21fb3edSRaghu Vatsavayi u32 size; 215f21fb3edSRaghu Vatsavayi 216f21fb3edSRaghu Vatsavayi /** Command and return status */ 217f21fb3edSRaghu Vatsavayi struct octeon_instr_64B cmd; 218f21fb3edSRaghu Vatsavayi #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 219f21fb3edSRaghu Vatsavayi u64 *status_word; 220f21fb3edSRaghu Vatsavayi 221f21fb3edSRaghu Vatsavayi /** Data buffer info */ 222f21fb3edSRaghu Vatsavayi void *virtdptr; 223f21fb3edSRaghu Vatsavayi u64 dmadptr; 224f21fb3edSRaghu Vatsavayi u32 datasize; 225f21fb3edSRaghu Vatsavayi 226f21fb3edSRaghu Vatsavayi /** Return buffer info */ 227f21fb3edSRaghu Vatsavayi void *virtrptr; 228f21fb3edSRaghu Vatsavayi u64 dmarptr; 229f21fb3edSRaghu Vatsavayi u32 rdatasize; 230f21fb3edSRaghu Vatsavayi 231f21fb3edSRaghu Vatsavayi /** Context buffer info */ 232f21fb3edSRaghu Vatsavayi void *ctxptr; 233f21fb3edSRaghu Vatsavayi u32 ctxsize; 234f21fb3edSRaghu Vatsavayi 235f21fb3edSRaghu Vatsavayi /** Time out and callback */ 236f21fb3edSRaghu Vatsavayi size_t wait_time; 237f21fb3edSRaghu Vatsavayi size_t timeout; 238f21fb3edSRaghu Vatsavayi u32 iq_no; 239f21fb3edSRaghu Vatsavayi void (*callback)(struct octeon_device *, u32, void *); 240f21fb3edSRaghu Vatsavayi void *callback_arg; 241f21fb3edSRaghu Vatsavayi }; 242f21fb3edSRaghu Vatsavayi 243f21fb3edSRaghu Vatsavayi /** Maximum number of buffers to allocate into soft command buffer pool 244f21fb3edSRaghu Vatsavayi */ 245f21fb3edSRaghu Vatsavayi #define MAX_SOFT_COMMAND_BUFFERS 16 246f21fb3edSRaghu Vatsavayi 247f21fb3edSRaghu Vatsavayi /** Head of a soft command buffer pool. 248f21fb3edSRaghu Vatsavayi */ 249f21fb3edSRaghu Vatsavayi struct octeon_sc_buffer_pool { 250f21fb3edSRaghu Vatsavayi /** List structure to add delete pending entries to */ 251f21fb3edSRaghu Vatsavayi struct list_head head; 252f21fb3edSRaghu Vatsavayi 253f21fb3edSRaghu Vatsavayi /** A lock for this response list */ 254f21fb3edSRaghu Vatsavayi spinlock_t lock; 255f21fb3edSRaghu Vatsavayi 256f21fb3edSRaghu Vatsavayi atomic_t alloc_buf_count; 257f21fb3edSRaghu Vatsavayi }; 258f21fb3edSRaghu Vatsavayi 259f21fb3edSRaghu Vatsavayi int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 260f21fb3edSRaghu Vatsavayi int octeon_free_sc_buffer_pool(struct octeon_device *oct); 261f21fb3edSRaghu Vatsavayi struct octeon_soft_command * 262f21fb3edSRaghu Vatsavayi octeon_alloc_soft_command(struct octeon_device *oct, 263f21fb3edSRaghu Vatsavayi u32 datasize, u32 rdatasize, 264f21fb3edSRaghu Vatsavayi u32 ctxsize); 265f21fb3edSRaghu Vatsavayi void octeon_free_soft_command(struct octeon_device *oct, 266f21fb3edSRaghu Vatsavayi struct octeon_soft_command *sc); 267f21fb3edSRaghu Vatsavayi 268f21fb3edSRaghu Vatsavayi /** 269f21fb3edSRaghu Vatsavayi * octeon_init_instr_queue() 270f21fb3edSRaghu Vatsavayi * @param octeon_dev - pointer to the octeon device structure. 27126236fa9SRaghu Vatsavayi * @param txpciq - queue to be initialized (0 <= q_no <= 3). 272f21fb3edSRaghu Vatsavayi * 273f21fb3edSRaghu Vatsavayi * Called at driver init time for each input queue. iq_conf has the 274f21fb3edSRaghu Vatsavayi * configuration parameters for the queue. 275f21fb3edSRaghu Vatsavayi * 276f21fb3edSRaghu Vatsavayi * @return Success: 0 Failure: 1 277f21fb3edSRaghu Vatsavayi */ 27826236fa9SRaghu Vatsavayi int octeon_init_instr_queue(struct octeon_device *octeon_dev, 27926236fa9SRaghu Vatsavayi union oct_txpciq txpciq, 280f21fb3edSRaghu Vatsavayi u32 num_descs); 281f21fb3edSRaghu Vatsavayi 282f21fb3edSRaghu Vatsavayi /** 283f21fb3edSRaghu Vatsavayi * octeon_delete_instr_queue() 284f21fb3edSRaghu Vatsavayi * @param octeon_dev - pointer to the octeon device structure. 285f21fb3edSRaghu Vatsavayi * @param iq_no - queue to be deleted (0 <= q_no <= 3). 286f21fb3edSRaghu Vatsavayi * 287f21fb3edSRaghu Vatsavayi * Called at driver unload time for each input queue. Deletes all 288f21fb3edSRaghu Vatsavayi * allocated resources for the input queue. 289f21fb3edSRaghu Vatsavayi * 290f21fb3edSRaghu Vatsavayi * @return Success: 0 Failure: 1 291f21fb3edSRaghu Vatsavayi */ 292f21fb3edSRaghu Vatsavayi int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 293f21fb3edSRaghu Vatsavayi 294f21fb3edSRaghu Vatsavayi int lio_wait_for_instr_fetch(struct octeon_device *oct); 295f21fb3edSRaghu Vatsavayi 296f21fb3edSRaghu Vatsavayi int 297f21fb3edSRaghu Vatsavayi octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 298f21fb3edSRaghu Vatsavayi void (*fn)(void *)); 299f21fb3edSRaghu Vatsavayi 300f21fb3edSRaghu Vatsavayi int 301f21fb3edSRaghu Vatsavayi lio_process_iq_request_list(struct octeon_device *oct, 302f21fb3edSRaghu Vatsavayi struct octeon_instr_queue *iq); 303f21fb3edSRaghu Vatsavayi 304f21fb3edSRaghu Vatsavayi int octeon_send_command(struct octeon_device *oct, u32 iq_no, 305f21fb3edSRaghu Vatsavayi u32 force_db, void *cmd, void *buf, 306f21fb3edSRaghu Vatsavayi u32 datasize, u32 reqtype); 307f21fb3edSRaghu Vatsavayi 308f21fb3edSRaghu Vatsavayi void octeon_prepare_soft_command(struct octeon_device *oct, 309f21fb3edSRaghu Vatsavayi struct octeon_soft_command *sc, 310f21fb3edSRaghu Vatsavayi u8 opcode, u8 subcode, 311f21fb3edSRaghu Vatsavayi u32 irh_ossp, u64 ossp0, 312f21fb3edSRaghu Vatsavayi u64 ossp1); 313f21fb3edSRaghu Vatsavayi 314f21fb3edSRaghu Vatsavayi int octeon_send_soft_command(struct octeon_device *oct, 315f21fb3edSRaghu Vatsavayi struct octeon_soft_command *sc); 316f21fb3edSRaghu Vatsavayi 31726236fa9SRaghu Vatsavayi int octeon_setup_iq(struct octeon_device *oct, union oct_txpciq, 318f21fb3edSRaghu Vatsavayi u32 num_descs, void *app_ctx); 319f21fb3edSRaghu Vatsavayi 320f21fb3edSRaghu Vatsavayi #endif /* __OCTEON_IQ_H__ */ 321